 @@ -1,14 +1,14 @@
-/*	$NetBSD: cpu.c,v 1.149 2018/02/22 13:27:18 maxv Exp $	*/
+/*	$NetBSD: cpu.c,v 1.150 2018/03/11 13:38:02 maxv Exp $	*/
 /*
  * Copyright (c) 2000-2012 NetBSD Foundation, Inc.
  * All rights reserved.
+ *
  * This code is derived from software contributed to The NetBSD Foundation
  * by Bill Sommerfeld of RedBack Networks Inc, and by Andrew Doran.
+ *
  * Redistribution and use in source and binary forms, with or without
  * modification, are permitted provided that the following conditions
  * are met:
  * 1. Redistributions of source code must retain the above copyright
  *    notice, this list of conditions and the following disclaimer.
 @@ -52,27 +52,27 @@
  * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
  * ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR AND CONTRIBUTORS BE LIABLE
  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
  * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
  * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
  * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
  * SUCH DAMAGE.
  */
 #include <sys/cdefs.h>
-__KERNEL_RCSID(0, "$NetBSD: cpu.c,v 1.149 2018/02/22 13:27:18 maxv Exp $");
+__KERNEL_RCSID(0, "$NetBSD: cpu.c,v 1.150 2018/03/11 13:38:02 maxv Exp $");
 #include "opt_ddb.h"
 #include "opt_mpbios.h"		/* for MPDEBUG */
 #include "opt_mtrr.h"
 #include "opt_multiprocessor.h"
 #include "opt_svs.h"
 #include "lapic.h"
 #include "ioapic.h"
 #include <sys/param.h>
 #include <sys/proc.h>
 #include <sys/systm.h>
 @@ -664,27 +664,27 @@ cpu_init(struct cpu_info *ci)
 			if (CPUID_TO_MODEL(ci->ci_signature) > 8 ||
 			    (CPUID_TO_MODEL(ci->ci_signature) == 8 &&
 			     CPUID_TO_STEPPING(ci->ci_signature) >= 7)) {
 				mtrr_funcs = &k6_mtrr_funcs;
 				k6_mtrr_init_first();
 				mtrr_init_cpu(ci);
+			}
+		}
+	}
 #endif	/* i386 */
 #endif /* MTRR */
 	if (ci != &cpu_info_primary) {
-		/* Synchronize TSC again, and check for drift. */
+		/* Synchronize TSC */
 		wbinvd();
 		atomic_or_32(&ci->ci_flags, CPUF_RUNNING);
 		tsc_sync_ap(ci);
 	} else {
 		atomic_or_32(&ci->ci_flags, CPUF_RUNNING);
+	}
+}
 #ifdef MULTIPROCESSOR
 void
 cpu_boot_secondary_processors(void)
+{
 	struct cpu_info *ci;
 @@ -776,28 +776,29 @@ cpu_start_secondary(struct cpu_info *ci)
 	for (i = 100000; (!(ci->ci_flags & CPUF_PRESENT)) && i > 0; i--) {
 		i8254_delay(10);
+	}
 	if ((ci->ci_flags & CPUF_PRESENT) == 0) {
 		aprint_error_dev(ci->ci_dev, "failed to become ready\n");
 #if defined(MPDEBUG) && defined(DDB)
 		printf("dropping into debugger; continue from here to resume boot\n");
 		Debugger();
 #endif
 	} else {
 		/*
 		 * Synchronize time stamp counters. Invalidate cache and do
-		 * twice to try and minimize possible cache effects. Disable
+		 * twice (in tsc_sync_bp) to minimize possible cache effects.
-		 * interrupts to try and rule out any external interference.
+		 * Disable interrupts to try and rule out any external
 		 * interference.
 		 */
 		psl = x86_read_psl();
 		x86_disable_intr();
 		wbinvd();
 		tsc_sync_bp(ci);
 		x86_write_psl(psl);
+	}
 	CPU_START_CLEANUP(ci);
 	cpu_starting = NULL;
+}
 void
 @@ -844,39 +845,45 @@ cpu_hatch(void *v)
 	struct cpu_info *ci = (struct cpu_info *)v;
 	struct pcb *pcb;
 	int s, i;
 	cpu_init_msrs(ci, true);
 	cpu_probe(ci);
 	ci->ci_data.cpu_cc_freq = cpu_info_primary.ci_data.cpu_cc_freq;
 	/* cpu_get_tsc_freq(ci); */
 	KDASSERT((ci->ci_flags & CPUF_PRESENT) == 0);
 	/*
-	 * Synchronize time stamp counters.  Invalidate cache and do twice
+	 * Synchronize the TSC for the first time. Note that interrupts are
-	 * to try and minimize possible cache effects.  Note that interrupts
+	 * off at this point.
 	 * are off at this point.
 	 */
 	wbinvd();
 	atomic_or_32(&ci->ci_flags, CPUF_PRESENT);
 	tsc_sync_ap(ci);
 	/*
-	 * Wait to be brought online.  Use 'monitor/mwait' if available,
+	 * Wait to be brought online.
 	 * in order to make the TSC drift as much as possible. so that
-	 * we can detect it later.  If not available, try 'pause'.
+	 * Use MONITOR/MWAIT if available. These instructions put the CPU in
-	 * We'd like to use 'hlt', but we have interrupts off.
+	 * a low consumption mode (C-state), and if the TSC is not invariant,
 	 * this causes the TSC to drift. We want this to happen, so that we
 	 * can later detect (in tsc_tc_init) any abnormal drift with invariant
 	 * TSCs. That's just for safety; by definition such drifts should
 	 * never occur with invariant TSCs.
+	 *
 	 * If not available, try PAUSE. We'd like to use HLT, but we have
 	 * interrupts off.
 	 */
 	while ((ci->ci_flags & CPUF_GO) == 0) {
 		if ((cpu_feature[1] & CPUID2_MONITOR) != 0) {
 			x86_monitor(&ci->ci_flags, 0, 0);
 			if ((ci->ci_flags & CPUF_GO) != 0) {
 				continue;
+			}
 			x86_mwait(0, 0);
 		} else {
 	/*
 	 * XXX The loop repetition count could be a lot higher, but
 	 * XXX currently qemu emulator takes a _very_long_time_ to
 	 * XXX execute the pause instruction.  So for now, use a low
 @@ -912,26 +919,31 @@ cpu_hatch(void *v)
 	cpu_init_idt();
 	gdt_init_cpu(ci);
 #if NLAPIC > 0
 	lapic_enable();
 	lapic_set_lvt();
 	lapic_initclocks();
 #endif
 	fpuinit(ci);
 	lldt(GSYSSEL(GLDT_SEL, SEL_KPL));
 	ltr(ci->ci_tss_sel);
 	/*
 	 * cpu_init will re-synchronize the TSC, and will detect any abnormal
 	 * drift that would have been caused by the use of MONITOR/MWAIT
 	 * above.
 	 */
 	cpu_init(ci);
 	cpu_get_tsc_freq(ci);
 	s = splhigh();
 	lapic_write_tpri(0);
 	x86_enable_intr();
 	splx(s);
 	x86_errata();
 	aprint_debug_dev(ci->ci_dev, "running\n");
 	idle_loop(NULL);
 	KASSERT(false);