Mon Mar 12 06:20:33 2018 UTC ()
 Add 3way and 6way of L2 cache or TLB on AMD CPU.


(msaitoh)
diff -r1.24 -r1.25 src/sys/arch/x86/include/cacheinfo.h
cvs diff -r1.24 -r1.25 src/sys/arch/x86/include/cacheinfo.h (expand / switch to unified diff)

--- src/sys/arch/x86/include/cacheinfo.h 2018/03/09 08:49:32 1.24
+++ src/sys/arch/x86/include/cacheinfo.h 2018/03/12 06:20:33 1.25
@@ -1,14 +1,14 @@ @@ -1,14 +1,14 @@
1/* $NetBSD: cacheinfo.h,v 1.24 2018/03/09 08:49:32 msaitoh Exp $ */ 1/* $NetBSD: cacheinfo.h,v 1.25 2018/03/12 06:20:33 msaitoh Exp $ */
2 2
3#ifndef _X86_CACHEINFO_H_ 3#ifndef _X86_CACHEINFO_H_
4#define _X86_CACHEINFO_H_ 4#define _X86_CACHEINFO_H_
5 5
6struct x86_cache_info { 6struct x86_cache_info {
7 uint8_t cai_index; 7 uint8_t cai_index;
8 uint8_t cai_desc; 8 uint8_t cai_desc;
9 uint8_t cai_associativity; 9 uint8_t cai_associativity;
10 u_int cai_totalsize; /* #entries for TLB, bytes for cache */ 10 u_int cai_totalsize; /* #entries for TLB, bytes for cache */
11 u_int cai_linesize; /* 11 u_int cai_linesize; /*
12 * or page size for TLB, 12 * or page size for TLB,
13 * or prefetch size 13 * or prefetch size
14 */ 14 */
@@ -332,27 +332,29 @@ __CI_TBL(CAI_L3CACHE, 0xe4, 16, 8 * 1 @@ -332,27 +332,29 @@ __CI_TBL(CAI_L3CACHE, 0xe4, 16, 8 * 1
332__CI_TBL(CAI_L3CACHE, 0xea, 24,12 * 1024 * 1024, 64, NULL), \ 332__CI_TBL(CAI_L3CACHE, 0xea, 24,12 * 1024 * 1024, 64, NULL), \
333__CI_TBL(CAI_L3CACHE, 0xeb, 24,18 * 1024 * 1024, 64, NULL), \ 333__CI_TBL(CAI_L3CACHE, 0xeb, 24,18 * 1024 * 1024, 64, NULL), \
334__CI_TBL(CAI_L3CACHE, 0xec, 24,24 * 1024 * 1024, 64, NULL), \ 334__CI_TBL(CAI_L3CACHE, 0xec, 24,24 * 1024 * 1024, 64, NULL), \
335__CI_TBL(CAI_PREFETCH, 0xf0, 0, 0, 64, NULL), \ 335__CI_TBL(CAI_PREFETCH, 0xf0, 0, 0, 64, NULL), \
336__CI_TBL(CAI_PREFETCH, 0xf1, 0, 0,128, NULL), \ 336__CI_TBL(CAI_PREFETCH, 0xf1, 0, 0,128, NULL), \
337/* 0xfe means no TLB information in CPUID leaf 2 (and use leaf 0x18) */ \ 337/* 0xfe means no TLB information in CPUID leaf 2 (and use leaf 0x18) */ \
338/* 0xff means no cache information in CPUID leaf 2 (and use leaf 4) */ \ 338/* 0xff means no cache information in CPUID leaf 2 (and use leaf 4) */ \
339__CI_TBL(0, 0, 0, 0, 0, NULL) \ 339__CI_TBL(0, 0, 0, 0, 0, NULL) \
340} 340}
341 341
342#define AMD_L2CACHE_INFO { \ 342#define AMD_L2CACHE_INFO { \
343__CI_TBL(0, 0x01, 1, 0, 0, NULL), \ 343__CI_TBL(0, 0x01, 1, 0, 0, NULL), \
344__CI_TBL(0, 0x02, 2, 0, 0, NULL), \ 344__CI_TBL(0, 0x02, 2, 0, 0, NULL), \
 345__CI_TBL(0, 0x03, 3, 0, 0, NULL), \
345__CI_TBL(0, 0x04, 4, 0, 0, NULL), \ 346__CI_TBL(0, 0x04, 4, 0, 0, NULL), \
 347__CI_TBL(0, 0x05, 6, 0, 0, NULL), \
346__CI_TBL(0, 0x06, 8, 0, 0, NULL), \ 348__CI_TBL(0, 0x06, 8, 0, 0, NULL), \
347__CI_TBL(0, 0x08, 16, 0, 0, NULL), \ 349__CI_TBL(0, 0x08, 16, 0, 0, NULL), \
348__CI_TBL(0, 0x0a, 32, 0, 0, NULL), \ 350__CI_TBL(0, 0x0a, 32, 0, 0, NULL), \
349__CI_TBL(0, 0x0b, 48, 0, 0, NULL), \ 351__CI_TBL(0, 0x0b, 48, 0, 0, NULL), \
350__CI_TBL(0, 0x0c, 64, 0, 0, NULL), \ 352__CI_TBL(0, 0x0c, 64, 0, 0, NULL), \
351__CI_TBL(0, 0x0d, 96, 0, 0, NULL), \ 353__CI_TBL(0, 0x0d, 96, 0, 0, NULL), \
352__CI_TBL(0, 0x0e, 128, 0, 0, NULL), \ 354__CI_TBL(0, 0x0e, 128, 0, 0, NULL), \
353__CI_TBL(0, 0x0f, 0xff, 0, 0, NULL), \ 355__CI_TBL(0, 0x0f, 0xff, 0, 0, NULL), \
354__CI_TBL(0, 0x00, 0, 0, 0, NULL) \ 356__CI_TBL(0, 0x00, 0, 0, 0, NULL) \
355} 357}
356 358
357#define AMD_L3CACHE_INFO { \ 359#define AMD_L3CACHE_INFO { \
358__CI_TBL(0, 0x01, 1, 0, 0, NULL), \ 360__CI_TBL(0, 0x01, 1, 0, 0, NULL), \