 @@ -1,328 +1,379 @@
-/*	$NetBSD: timer.c,v 1.29 2011/07/17 23:18:23 mrg Exp $ */
+/*	$NetBSD: timer.c,v 1.29.8.1 2018/03/13 16:48:05 snj Exp $ */
 /*
  * Copyright (c) 1992, 1993
  *	The Regents of the University of California.  All rights reserved.
  * Copyright (c) 1994 Gordon W. Ross
  * Copyright (c) 1993 Adam Glass
  * Copyright (c) 1996 Paul Kranenburg
  * Copyright (c) 1996
  * 	The President and Fellows of Harvard College. All rights reserved.
+ *
  * This software was developed by the Computer Systems Engineering group
  * at Lawrence Berkeley Laboratory under DARPA contract BG 91-66 and
  * contributed to Berkeley.
+ *
  * All advertising materials mentioning features or use of this software
  * must display the following acknowledgement:
  *	This product includes software developed by Harvard University.
  *	This product includes software developed by the University of
  *	California, Lawrence Berkeley Laboratory.
+ *
  * Redistribution and use in source and binary forms, with or without
  * modification, are permitted provided that the following conditions
  * are met:
+ *
  * 1. Redistributions of source code must retain the above copyright
  *    notice, this list of conditions and the following disclaimer.
  * 2. Redistributions in binary form must reproduce the above copyright
  *    notice, this list of conditions and the following disclaimer in the
  *    documentation and/or other materials provided with the distribution.
  * 3. All advertising materials mentioning features or use of this software
  *    must display the following acknowledgement:
  *	This product includes software developed by the University of
  *	California, Berkeley and its contributors.
  *	This product includes software developed by Paul Kranenburg.
  *	This product includes software developed by Harvard University.
  * 4. Neither the name of the University nor the names of its contributors
  *    may be used to endorse or promote products derived from this software
  *    without specific prior written permission.
+ *
  * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
  * ARE DISCLAIMED.  IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
  * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
  * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
  * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
  * SUCH DAMAGE.
+ *
  *	@(#)clock.c	8.1 (Berkeley) 6/11/93
  */
 /*
  * Kernel clocks provided by "timer" device.  The hardclock is provided by
  * the timer register (aka system counter).  The statclock is provided by
  * per CPU counter register(s) (aka processor counter(s)).
  */
 #include <sys/cdefs.h>
-__KERNEL_RCSID(0, "$NetBSD: timer.c,v 1.29 2011/07/17 23:18:23 mrg Exp $");
+__KERNEL_RCSID(0, "$NetBSD: timer.c,v 1.29.8.1 2018/03/13 16:48:05 snj Exp $");
 #include <sys/param.h>
 #include <sys/kernel.h>
 #include <sys/device.h>
 #include <sys/systm.h>
 #include <sys/timetc.h>
 #include <machine/autoconf.h>
 #include <sys/bus.h>
 #include <sparc/sparc/timerreg.h>
 #include <sparc/sparc/timervar.h>
 static struct intrhand level10;
 static struct intrhand level14;
 static u_int timer_get_timecount(struct timecounter *);
 /*
  * timecounter local state
  */
 static struct counter {
-	volatile u_int *cntreg;	/* counter register */
+	__cpu_simple_lock_t lock; /* protects access to offset, reg, last* */
 	volatile u_int *cntreg;	/* counter register to read */
 	u_int limit;		/* limit we count up to */
 	u_int offset;		/* accumulated offet due to wraps */
 	u_int shift;		/* scaling for valid bits */
 	u_int mask;		/* valid bit mask */
-} cntr;
+	u_int lastcnt;		/* the last* values are used to notice */
 	u_int lastres;		/* and fix up cases where it would appear */
 	u_int lastoffset;	/* time went backwards. */
 } cntr __aligned(CACHE_LINE_SIZE);
 /*
  * define timecounter
  */
 static struct timecounter counter_timecounter = {
-	timer_get_timecount,	/* get_timecount */
+	.tc_get_timecount =	timer_get_timecount,
-,			/* no poll_pps */
+	.tc_poll_pps =		NULL,
-	~0u,			/* counter_mask */
+	.tc_counter_mask =	~0u,
-,                      /* frequency - set at initialisation */
+	.tc_frequency =		0,
-	"timer-counter",	/* name */
+	.tc_name =		"timer-counter",
-,			/* quality */
+	.tc_quality =		100,
-	&cntr			/* private reference */
+	.tc_priv =		&cntr,
 };
 /*
  * timer_get_timecount provide current counter value
  */
 __attribute__((__optimize__("Os")))
 static u_int
 timer_get_timecount(struct timecounter *tc)
+{
-	struct counter *ctr = (struct counter *)tc->tc_priv;
+	u_int cnt, res, fixup, offset;
 	u_int c, res, r;
 	int s;
 	/*
 	 * We use splhigh/__cpu_simple_lock here as we don't want
 	 * any mutex or lockdebug overhead.  The lock protects a
 	 * bunch of the members of cntr that are written here to
 	 * deal with the various minor races to be observed and
 	 * worked around.
 	 */
 	s = splhigh();
-	res = c = *ctr->cntreg;
+	__cpu_simple_lock(&cntr.lock);
 	res = cnt = *cntr.cntreg;
 	res  &= ~TMR_LIMIT;
 	offset = cntr.offset;
-	if (c != res) {
+	/*
-		r = ctr->limit;
+	 * There are 3 cases here:
 	 * - limit reached, interrupt not yet processed.
 	 * - count reset but offset the same, race between handling
 	 *   the interrupt and tickle_tc() updating the offset.
 	 * - normal case.
+	 *
 	 * For the first two cases, add the limit so that we avoid
 	 * time going backwards.
 	 */
 	if (cnt != res) {
 		fixup = cntr.limit;
 	} else if (res < cntr.lastcnt && offset == cntr.lastoffset) {
 		fixup = cntr.limit;
 	} else {
-		r = 0;
+		fixup = 0;
+	}
 	cntr.lastcnt = res;
 	cntr.lastoffset = offset;
-	res >>= ctr->shift;
+	res >>= cntr.shift;
-	res  &= ctr->mask;
+	res  &= cntr.mask;
-	res += r + ctr->offset;
+	res += fixup + offset;
 	/*
 	 * This handles early-boot cases where the counter resets twice
 	 * before the offset is updated, and we have a stupid check to
 	 * ensure overflow hasn't happened.
 	 */
 	if (res < cntr.lastres && res > (TMR_MASK+1) << 3)
 		res = cntr.lastres + 1;
 	cntr.lastres = res;
 	__cpu_simple_unlock(&cntr.lock);
 	splx(s);
 	return res;
+}
 void
 tickle_tc(void)
+{
 	if (timecounter->tc_get_timecount == timer_get_timecount) {
 		/*
 		 * This could be protected by cntr.lock/splhigh but the update
 		 * happens at IPL10 already and as a 32 bit value it should
 		 * never be seen as a partial update, so skip it here.  This
 		 * also probably slows down the actual offset update, making
 		 * one of the cases above more likely to need the workaround.
 		 */
 		cntr.offset += cntr.limit;
+	}
+}
 /*
  * sun4/sun4c/sun4m common timer attach code
  */
 void
 timerattach(volatile int *cntreg, volatile int *limreg)
+{
 	u_int prec = 0, t0;
 	void    (*sched_intr_fn)(void *);
 	/*
 	 * Calibrate delay() by tweaking the magic constant
 	 * until a delay(100) actually reads (at least) 100 us on the clock.
 	 * Note: sun4m clocks tick with 500ns periods.
 	 */
 	for (timerblurb = 1; ; timerblurb++) {
 		volatile int discard;
 		u_int t1;
 		/* Reset counter register by writing some large limit value */
 		discard = *limreg;
 		*limreg = tmr_ustolim(TMR_MASK-1);
 		t0 = *cntreg;
 		delay(100);
 		t1 = *cntreg;
 		prec |= (t0 ^ t1) | (*cntreg ^ *cntreg);
 		if (t1 & TMR_LIMIT)
 			panic("delay calibration");
 		t0 = (t0 >> TMR_SHIFT) & TMR_MASK;
 		t1 = (t1 >> TMR_SHIFT) & TMR_MASK;
 		if (t1 >= t0 + 100)
 			break;
+	}
 	/* find lowest active bit */
 	for (t0 = 0; t0 < TMR_SHIFT; t0++)
 		if ((1 << t0) & prec)
 			break;
 	__cpu_simple_lock_init(&cntr.lock);
 	cntr.shift = t0;
 	cntr.mask = (1 << (31-t0))-1;
 	counter_timecounter.tc_frequency = 1000000 * (TMR_SHIFT - t0 + 1);
 	printf(": delay constant %d, frequency = %" PRIu64 " Hz\n",
 	       timerblurb, counter_timecounter.tc_frequency);
 #if defined(SUN4) || defined(SUN4C)
 	if (CPU_ISSUN4 || CPU_ISSUN4C) {
 		timer_init = timer_init_4;
 		sched_intr_fn = schedintr;
 		level10.ih_fun = clockintr_4;
 		level14.ih_fun = statintr_4;
 		cntr.limit = tmr_ustolim(tick);
+	}
 #endif
 #if defined(SUN4M)
 	if (CPU_ISSUN4M) {
 		timer_init = timer_init_4m;
 #if defined(MULTIPROCESSOR)
 		if (sparc_ncpus > 1)
 			sched_intr_fn = schedintr_4m;
 		else
 #endif
 			sched_intr_fn = schedintr;
 		level10.ih_fun = clockintr_4m;
 		level14.ih_fun = statintr_4m;
 		cntr.limit = tmr_ustolim4m(tick);
+	}
 #endif
 	/* link interrupt handlers */
 	intr_establish(10, 0, &level10, NULL, true);
 	intr_establish(14, 0, &level14, NULL, true);
 	/* Establish a soft interrupt at a lower level for schedclock */
 	sched_cookie = sparc_softintr_establish(IPL_SCHED, sched_intr_fn, NULL);
 	if (sched_cookie == NULL)
 		panic("timerattach: cannot establish schedintr");
 	cntr.cntreg = cntreg;
 	cntr.limit >>= cntr.shift;
 	/* start at non-zero, so that cntr.oldoffset is less */
 	cntr.offset = cntr.limit;
 	tc_init(&counter_timecounter);
+}
 /*
  * Both sun4 and sun4m can attach a timer on obio.
  * The sun4m OPENPROM calls the timer the "counter".
  * The sun4 timer must be probed.
  */
 static int
 timermatch_obio(device_t parent, cfdata_t cf, void *aux)
+{
 #if defined(SUN4) || defined(SUN4M)
 	union obio_attach_args *uoba = aux;
 #endif
 #if defined(SUN4)
 	struct obio4_attach_args *oba;
 #endif
 #if defined(SUN4M)
 	if (uoba->uoba_isobio4 == 0)
 		return (strcmp("counter", uoba->uoba_sbus.sa_name) == 0);
 #endif /* SUN4M */
 	if (CPU_ISSUN4 == 0) {
 		printf("timermatch_obio: attach args mixed up\n");
 		return (0);
+	}
 #if defined(SUN4)
 	/* Only these sun4s have "timer" (others have "oclock") */
 	if (cpuinfo.cpu_type != CPUTYP_4_300 &&
 	    cpuinfo.cpu_type != CPUTYP_4_400)
 		return (0);
 	/* Make sure there is something there */
 	oba = &uoba->uoba_oba4;
 	return (bus_space_probe(oba->oba_bustag, oba->oba_paddr,
 ,	/* probe size */
 ,	/* offset */
 ,	/* flags */
 				NULL, NULL));
 #endif /* SUN4 */
 	panic("timermatch_obio: impossible");
+}
 static void
 timerattach_obio(device_t parent, device_t self, void *aux)
+{
 	union obio_attach_args *uoba = aux;
 	if (uoba->uoba_isobio4 == 0) {
 #if defined(SUN4M)
 		/* sun4m timer at obio */
 		timerattach_obio_4m(parent, self, aux);
 #endif /* SUN4M */
 		return;
+	}
 	if (uoba->uoba_isobio4 != 0) {
 #if defined(SUN4)
 		/* sun4 timer at obio */
 		timerattach_obio_4(parent, self, aux);
 #endif /* SUN4 */
+	}
+}
 CFATTACH_DECL_NEW(timer_obio, 0,
     timermatch_obio, timerattach_obio, NULL, NULL);
 /*
  * Only sun4c attaches a timer at mainbus
  */
 static int
 timermatch_mainbus(device_t parent, cfdata_t cf, void *aux)
+{
 #if defined(SUN4C)
 	struct mainbus_attach_args *ma = aux;
 	return (strcmp("counter-timer", ma->ma_name) == 0);
 #else
 	return (0);
 #endif
+}
 static void
 timerattach_mainbus(device_t parent, device_t self, void *aux)
+{
 #if defined(SUN4C)
 	timerattach_mainbus_4c(parent, self, aux);
 #endif /* SUN4C */
+}
 CFATTACH_DECL_NEW(timer_mainbus, 0,
     timermatch_mainbus, timerattach_mainbus, NULL, NULL);

 @@ -1,267 +1,271 @@
-/*	$NetBSD: timer_sun4m.c,v 1.28 2011/09/01 08:43:24 martin Exp $	*/
+/*	$NetBSD: timer_sun4m.c,v 1.28.8.1 2018/03/13 16:48:05 snj Exp $	*/
 /*
  * Copyright (c) 1992, 1993
  *	The Regents of the University of California.  All rights reserved.
  * Copyright (c) 1994 Gordon W. Ross
  * Copyright (c) 1993 Adam Glass
  * Copyright (c) 1996 Paul Kranenburg
  * Copyright (c) 1996
  * 	The President and Fellows of Harvard College. All rights reserved.
+ *
  * This software was developed by the Computer Systems Engineering group
  * at Lawrence Berkeley Laboratory under DARPA contract BG 91-66 and
  * contributed to Berkeley.
+ *
  * All advertising materials mentioning features or use of this software
  * must display the following acknowledgement:
  *	This product includes software developed by Harvard University.
  *	This product includes software developed by the University of
  *	California, Lawrence Berkeley Laboratory.
+ *
  * Redistribution and use in source and binary forms, with or without
  * modification, are permitted provided that the following conditions
  * are met:
+ *
  * 1. Redistributions of source code must retain the above copyright
  *    notice, this list of conditions and the following disclaimer.
  * 2. Redistributions in binary form must reproduce the above copyright
  *    notice, this list of conditions and the following disclaimer in the
  *    documentation and/or other materials provided with the distribution.
  * 3. All advertising materials mentioning features or use of this software
  *    must display the following acknowledgement:
  *	This product includes software developed by the University of
  *	California, Berkeley and its contributors.
  *	This product includes software developed by Paul Kranenburg.
  *	This product includes software developed by Harvard University.
  * 4. Neither the name of the University nor the names of its contributors
  *    may be used to endorse or promote products derived from this software
  *    without specific prior written permission.
+ *
  * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
  * ARE DISCLAIMED.  IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
  * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
  * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
  * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
  * SUCH DAMAGE.
+ *
  *	@(#)clock.c	8.1 (Berkeley) 6/11/93
  */
 /*
  * Sun4m timer support.
  */
 #include <sys/cdefs.h>
-__KERNEL_RCSID(0, "$NetBSD: timer_sun4m.c,v 1.28 2011/09/01 08:43:24 martin Exp $");
+__KERNEL_RCSID(0, "$NetBSD: timer_sun4m.c,v 1.28.8.1 2018/03/13 16:48:05 snj Exp $");
 #include <sys/param.h>
 #include <sys/kernel.h>
 #include <sys/device.h>
 #include <sys/systm.h>
 #include <sys/cpu.h>
 #include <machine/autoconf.h>
 #include <sys/bus.h>
 #include <sparc/sparc/vaddrs.h>
 #include <sparc/sparc/cpuvar.h>
 #include <sparc/sparc/timerreg.h>
 #include <sparc/sparc/timervar.h>
-struct timer_4m		*timerreg4m;
+static struct timer_4m		*timerreg4m;
 #define	counterreg4m	cpuinfo.counterreg_4m
 /*
  * Set up the real-time and statistics clocks.
  * Leave stathz 0 only if no alternative timer is available.
+ *
  * The frequencies of these clocks must be an even number of microseconds.
  */
 void
 timer_init_4m(void)
+{
 	struct cpu_info *cpi;
 	int n;
 	timerreg4m->t_limit = tmr_ustolim4m(tick);
 	for (CPU_INFO_FOREACH(n, cpi)) {
 		cpi->counterreg_4m->t_limit = tmr_ustolim4m(statint);
+	}
 	icr_si_bic(SINTR_T);
+}
 void
 schedintr_4m(void *v)
+{
 	kpreempt_disable();
 #ifdef MULTIPROCESSOR
 	/*
 	 * We call hardclock() here so that we make sure it is called on
 	 * all CPUs.  This function ends up being called on sun4m systems
 	 * every tick.
 	 */
 	if (!CPU_IS_PRIMARY(curcpu()))
 		hardclock(v);
 	/*
 	 * The factor 8 is only valid for stathz==100.
 	 * See also clock.c
 	 */
 	if ((++cpuinfo.ci_schedstate.spc_schedticks & 7) == 0 && schedhz != 0)
 #endif
 		schedclock(curlwp);
 	kpreempt_enable();
+}
 /*
  * Level 10 (clock) interrupts from system counter.
  */
 int
 clockintr_4m(void *cap)
+{
 	KASSERT(CPU_IS_PRIMARY(curcpu()));
 	/*
 	 * XXX this needs to be fixed in a more general way
 	 * problem is that the kernel enables interrupts and THEN
 	 * sets up clocks. In between there's an opportunity to catch
 	 * a timer interrupt - if we call hardclock() at that point we'll
 	 * panic
 	 * so for now just bail when cold
+	 *
 	 * For MP, we defer calling hardclock() to the schedintr so
 	 * that we call it on all cpus.
 	 */
 	if (cold)
 		return 0;
 	kpreempt_disable();
 	/* read the limit register to clear the interrupt */
 	/* Read the limit register to clear the interrupt. */
 	*((volatile int *)&timerreg4m->t_limit);
 	/* Update the timecounter offset. */
 	tickle_tc();
 	hardclock((struct clockframe *)cap);
 	kpreempt_enable();
 	return (1);
+}
 /*
  * Level 14 (stat clock) interrupts from processor counter.
  */
 int
 statintr_4m(void *cap)
+{
 	struct clockframe *frame = cap;
 	u_long newint;
 	kpreempt_disable();
 	/* read the limit register to clear the interrupt */
 	*((volatile int *)&counterreg4m->t_limit);
 	statclock(frame);
 	/*
 	 * Compute new randomized interval.
 	 */
 	newint = new_interval();
 	/*
 	 * Use the `non-resetting' limit register, so we don't
 	 * loose the counter ticks that happened since this
 	 * interrupt was raised.
 	 */
 	counterreg4m->t_limit_nr = tmr_ustolim4m(newint);
 	/*
 	 * The factor 8 is only valid for stathz==100.
 	 * See also clock.c
 	 */
 #if !defined(MULTIPROCESSOR)
 	if ((++cpuinfo.ci_schedstate.spc_schedticks & 7) == 0 && schedhz != 0) {
 #endif
 		if (CLKF_LOPRI(frame, IPL_SCHED)) {
 			/* No need to schedule a soft interrupt */
 			spllowerschedclock();
 			schedintr_4m(cap);
 		} else {
 			/*
 			 * We're interrupting a thread that may have the
 			 * scheduler lock; run schedintr_4m() on this CPU later.
 			 */
 			raise_ipi(&cpuinfo, IPL_SCHED); /* sched_cookie->pil */
+		}
 #if !defined(MULTIPROCESSOR)
+	}
 #endif
 	kpreempt_enable();
 	return (1);
+}
 void
 timerattach_obio_4m(device_t parent, device_t self, void *aux)
+{
 	union obio_attach_args *uoba = aux;
 	struct sbus_attach_args *sa = &uoba->uoba_sbus;
 	struct cpu_info *cpi;
 	bus_space_handle_t bh;
 	int i, n;
 	if (sa->sa_nreg < 2) {
 		printf(": only %d register sets\n", sa->sa_nreg);
 		return;
+	}
 	/* Map the system timer */
 	i = sa->sa_nreg - 1;
 	if (bus_space_map2(sa->sa_bustag,
 			   BUS_ADDR(sa->sa_reg[i].oa_space,
 				    sa->sa_reg[i].oa_base),
 			   sizeof(struct timer_4m),
 			   BUS_SPACE_MAP_LINEAR,
 			   TIMERREG_VA, &bh) != 0) {
 		printf(": can't map registers\n");
 		return;
+	}
 	timerreg4m = (struct timer_4m *)TIMERREG_VA;
 	/* Map each CPU's counter */
 	for (i = 0; i < sa->sa_nreg - 1; i++) {
 		/*
 		 * Check whether the CPU corresponding to this timer
 		 * register is installed.
 		 */
 		for (CPU_INFO_FOREACH(n, cpi)) {
 			if ((i == 0 && sparc_ncpus == 1) || cpi->mid == i + 8) {
 				/* We got a corresponding MID. */
 				break;
+			}
 			cpi = NULL;
+		}
 		if (cpi == NULL)
 			continue;
 		if (sbus_bus_map(sa->sa_bustag,
 				 sa->sa_reg[i].oa_space,
 				 sa->sa_reg[i].oa_base,
 				 sizeof(struct timer_4m),
 				 BUS_SPACE_MAP_LINEAR,
 				 &bh) != 0) {
 			printf(": can't map CPU counter %d\n", i);
 			return;
+		}
 		cpi->counterreg_4m = (struct counter_4m *)bh;
+	}
 	/* Put processor counter in "timer" mode */
 	timerreg4m->t_cfg = 0;
 	timerattach(&timerreg4m->t_counter, &timerreg4m->t_limit);
+}

 @@ -1,128 +1,131 @@
-/*	$NetBSD: timerreg.h,v 1.9 2005/11/16 03:00:23 uwe Exp $ */
+/*	$NetBSD: timerreg.h,v 1.9.118.1 2018/03/13 16:48:05 snj Exp $ */
 /*
  * Copyright (c) 1992, 1993
  *	The Regents of the University of California.  All rights reserved.
+ *
  * This software was developed by the Computer Systems Engineering group
  * at Lawrence Berkeley Laboratory under DARPA contract BG 91-66 and
  * contributed to Berkeley.
+ *
  * All advertising materials mentioning features or use of this software
  * must display the following acknowledgement:
  *	This product includes software developed by the University of
  *	California, Lawrence Berkeley Laboratory.
+ *
  * Redistribution and use in source and binary forms, with or without
  * modification, are permitted provided that the following conditions
  * are met:
  * 1. Redistributions of source code must retain the above copyright
  *    notice, this list of conditions and the following disclaimer.
  * 2. Redistributions in binary form must reproduce the above copyright
  *    notice, this list of conditions and the following disclaimer in the
  *    documentation and/or other materials provided with the distribution.
  * 3. Neither the name of the University nor the names of its contributors
  *    may be used to endorse or promote products derived from this software
  *    without specific prior written permission.
+ *
  * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
  * ARE DISCLAIMED.  IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
  * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
  * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
  * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
  * SUCH DAMAGE.
+ *
  *	@(#)timerreg.h	8.1 (Berkeley) 6/11/93
  */
 /*
  * Sun-4c counter/timer registers.  The timers are implemented within
  * the cache chip (!).  The counter and limit fields below could be
  * defined as:
+ *
  *	struct {
  *		u_int	t_limit:1,	// limit reached
  *			t_usec:21,	// counter value in microseconds
  *			t_mbz:10;	// always zero
  *	};
+ *
  * but this is more trouble than it is worth.
+ *
  * These timers work in a rather peculiar fashion.  Most clock counters
  * run to 0 (as, e.g., on the VAX, where the ICR counts up to 0 from a
  * large unsigned number).  On the Sun-4c, it counts up to a limit.  But
  * for some reason, when it reaches the limit, it resets to 1, not 0.
  * Thus, if the limit is set to 4, the counter counts like this:
+ *
  *	1, 2, 3, 1, 2, 3, ...
+ *
  * and if we want to divide by N we must set the limit register to N+1.
+ *
  * Sun-4m counters/timer registers are similar, with these exceptions:
+ *
  *	- the limit and counter registers have changed positions..
  *	- both limit and counter registers are 22 bits wide, but
  *	  they count in 500ns increments (bit 9 being the least
  *	  significant bit).
+ *
  */
 #ifndef _LOCORE
 struct timer_4 {
 	volatile int	t_counter;		/* counter reg */
 	volatile int	t_limit;		/* limit reg */
 };
 struct timerreg_4 {
 	struct	timer_4 t_c10;		/* counter that interrupts at ipl 10 */
 	struct	timer_4 t_c14;		/* counter that interrupts at ipl 14 */
 };
 struct timer_4m {		/* counter that interrupts at ipl 10 */
 	volatile int	t_limit;		/* limit register */
 	volatile int	t_counter;		/* counter register */
 	volatile int	t_limit_nr;		/* limit reg, non-resetting */
 	volatile int	t_reserved;
 	volatile int	t_cfg;			/* a configuration register */
 /*
  * Note: The SparcClassic manual only defines this one bit
  * I suspect there are more in multi-processor machines.
  */
 #define TMR_CFG_USER	1
 };
 struct counter_4m {		/* counter that interrupts at ipl 14 */
 	volatile int	t_limit;		/* limit register */
 	volatile int	t_counter;		/* counter register */
 	volatile int	t_limit_nr;		/* limit reg, non-resetting */
 	volatile int	t_ss;			/* Start/Stop register */
 #define TMR_USER_RUN	1
 };
 #endif /* _LOCORE */
 #define	TMR_LIMIT	0x80000000	/* counter reached its limit */
 #define	TMR_SHIFT	10		/* shift to obtain microseconds */
 #define	TMR_MASK	0x1fffff	/* 21 bits */
 /*
  * Compute a limit that causes the timer to fire every n microseconds.
  * The Sun4c requires that the timer register be initialized for n+1
  * microseconds, while the Sun4m requires it be initialized for n. Thus
  * the two versions of this function.
+ *
  * Note that the manual for the chipset used in the Sun4m suggests that
  * the timer be set at n+0.5 microseconds; in practice, this produces
  * a 50 ppm clock skew, which means that the 0.5 should not be there...
  */
 #define	tmr_ustolim(n)	(((n) + 1) << TMR_SHIFT)
-/*efine	TMR_SHIFT4M	9		-* shift to obtain microseconds */
+#define	TMR_SHIFT4M	9		/* shift to obtain microseconds */
-/*efine tmr_ustolim4m(n)	(((2*(n)) + 1) << TMR_SHIFT4M)*/
+#if 1
 #define tmr_ustolim4m(n)	(((2*(n)) + 1) << TMR_SHIFT4M)
 #else
 #define tmr_ustolim4m(n)	((n) << TMR_SHIFT)
 #endif
 /* The number of microseconds represented by a counter register value */
 #define tmr_cnttous(c)	((((c) >> TMR_SHIFT) & TMR_MASK) - 1)