Fri May 4 17:13:08 2018 UTC ()
when spinning up secondary CPUs, put them in bridge mode if the primary cpu is


(macallan)
diff -r1.55 -r1.56 src/sys/arch/powerpc/powerpc/locore_subr.S
cvs diff -r1.55 -r1.56 src/sys/arch/powerpc/powerpc/locore_subr.S (expand / switch to unified diff)

--- src/sys/arch/powerpc/powerpc/locore_subr.S 2017/02/28 17:35:29 1.55
+++ src/sys/arch/powerpc/powerpc/locore_subr.S 2018/05/04 17:13:08 1.56
@@ -1,14 +1,14 @@ @@ -1,14 +1,14 @@
1/* $NetBSD: locore_subr.S,v 1.55 2017/02/28 17:35:29 chs Exp $ */ 1/* $NetBSD: locore_subr.S,v 1.56 2018/05/04 17:13:08 macallan Exp $ */
2 2
3/* 3/*
4 * Copyright (c) 2001 Wasabi Systems, Inc. 4 * Copyright (c) 2001 Wasabi Systems, Inc.
5 * All rights reserved. 5 * All rights reserved.
6 * 6 *
7 * Written by Eduardo Horvath and Simon Burge for Wasabi Systems, Inc. 7 * Written by Eduardo Horvath and Simon Burge for Wasabi Systems, Inc.
8 * 8 *
9 * Redistribution and use in source and binary forms, with or without 9 * Redistribution and use in source and binary forms, with or without
10 * modification, are permitted provided that the following conditions 10 * modification, are permitted provided that the following conditions
11 * are met: 11 * are met:
12 * 1. Redistributions of source code must retain the above copyright 12 * 1. Redistributions of source code must retain the above copyright
13 * notice, this list of conditions and the following disclaimer. 13 * notice, this list of conditions and the following disclaimer.
14 * 2. Redistributions in binary form must reproduce the above copyright 14 * 2. Redistributions in binary form must reproduce the above copyright
@@ -516,26 +516,38 @@ _ENTRY(cpu_lwp_bootstrap) @@ -516,26 +516,38 @@ _ENTRY(cpu_lwp_bootstrap)
516 andis. %r0,%r31,PSL_CE@h 516 andis. %r0,%r31,PSL_CE@h
517 tweqi %r0,0 517 tweqi %r0,0
518 andi. %r0,%r31,PSL_DE@l 518 andi. %r0,%r31,PSL_DE@l
519 tweqi %r0,0 519 tweqi %r0,0
520#endif 520#endif
521 li %r4, 1 /* make sure userret gets called */ 521 li %r4, 1 /* make sure userret gets called */
522 stint %r4, L_MD_ASTPENDING(%r13) 522 stint %r4, L_MD_ASTPENDING(%r13)
523 b trapexit 523 b trapexit
524 524
525#if defined(MULTIPROCESSOR) && (defined(PPC_OEA) || defined (PPC_OEA64_BRIDGE)) 525#if defined(MULTIPROCESSOR) && (defined(PPC_OEA) || defined (PPC_OEA64_BRIDGE))
526ENTRY(cpu_spinup_trampoline) 526ENTRY(cpu_spinup_trampoline)
527 li %r0,0 527 li %r0,0
528 mtmsr %r0 528 mtmsr %r0
 529
 530 lis %r5,oeacpufeat@ha
 531 lwz %r5,oeacpufeat@l(%r5)
 532 andi. %r5,%r5,OEACPU_64_BRIDGE
 533 beq 6f
 534 sync
 535 slbia
 536 sync
 537 isync
 538 clrldi %r0,%r0,32
 539 mtmsrd %r0
 5406:
529 isync 541 isync
530 542
531 lis %r4,_C_LABEL(cpu_hatch_stack)@ha 543 lis %r4,_C_LABEL(cpu_hatch_stack)@ha
532 lwz %r1,_C_LABEL(cpu_hatch_stack)@l(%r4) 544 lwz %r1,_C_LABEL(cpu_hatch_stack)@l(%r4)
533 545
534 bl _C_LABEL(cpu_hatch) 546 bl _C_LABEL(cpu_hatch)
535 mr %r1,%r3 547 mr %r1,%r3
536 b _C_LABEL(idle_loop) 548 b _C_LABEL(idle_loop)
537 549
538ENTRY(cpu_spinstart) 550ENTRY(cpu_spinstart)
539 li %r0,0 551 li %r0,0
540 mtmsr %r0 552 mtmsr %r0
541 lis %r5,oeacpufeat@ha 553 lis %r5,oeacpufeat@ha