 @@ -1,14 +1,14 @@
-/*	$NetBSD: specialreg.h,v 1.120 2018/03/30 19:49:49 maxv Exp $	*/
+/*	$NetBSD: specialreg.h,v 1.121 2018/05/22 07:11:53 maxv Exp $	*/
 /*-
  * Copyright (c) 1991 The Regents of the University of California.
  * All rights reserved.
+ *
  * Redistribution and use in source and binary forms, with or without
  * modification, are permitted provided that the following conditions
  * are met:
  * 1. Redistributions of source code must retain the above copyright
  *    notice, this list of conditions and the following disclaimer.
  * 2. Redistributions in binary form must reproduce the above copyright
  *    notice, this list of conditions and the following disclaimer in the
  *    documentation and/or other materials provided with the distribution.
 @@ -395,31 +395,31 @@
 	"\1" "PREFETCHWT1" "\2" "AVX512_VBMI" "\3" "UMIP" "\4" "PKU"	\
 	"\5" "OSPKE"			"\7" "AVX512_VBMI2"		\
 	"\11" "GFNI"	"\12" "VAES"	"\13" "VPCLMULQDQ" "\14" "AVX512_VNNI"\
 	"\15" "AVX512_BITALG"		"\17" "AVX512_VPOPCNTDQ"	\
 					"\27" "RDPID"			\
 					"\37" "SGXLC"
 /* %edx */
 #define CPUID_SEF_AVX512_4VNNIW	__BIT(2)
 #define CPUID_SEF_AVX512_4FMAPS	__BIT(3)
 #define CPUID_SEF_IBRS		__BIT(26) /* IBRS / IBPB Speculation Control */
 #define CPUID_SEF_STIBP		__BIT(27) /* STIBP Speculation Control */
 #define CPUID_SEF_ARCH_CAP	__BIT(29) /* IA32_ARCH_CAPABILITIES */
 #define CPUID_SEF_SSBD		__BIT(31) /* Speculative Store Bypass Disable */
-#define CPUID_SEF_FLAGS2	"\20" \
+#define CPUID_SEF_FLAGS2	\
-				"\3" "AVX512_4VNNIW" "\4" "AVX512_4FMAPS" \
+	"\20" "\3" "AVX512_4VNNIW" "\4" "AVX512_4FMAPS" \
-					"\33" "IBRS"	"\34" "STIBP"	\
+	"\33" "IBRS" "\34" "STIBP" "\36" "ARCH_CAP" "\38" "SSBD"
 			"\36" "ARCH_CAP"
 /*
  * CPUID Processor extended state Enumeration Fn0000000d
+ *
  * %ecx == 0: supported features info:
  *	%eax: Valid bits of lower 32bits of XCR0
  *	%ebx: Maximum save area size for features enabled in XCR0
  *	%ecx: Maximum save area size for all cpu features
  *	%edx: Valid bits of upper 32bits of XCR0
+ *
  * %ecx == 1:
  *	%eax: Bit 0 => xsaveopt instruction available (sandy bridge onwards)
  *	%ebx: Save area size for features enabled by XCR0 | IA32_XSS
 @@ -633,43 +633,45 @@
 #define 	APICBASE_EN		0x00000800	/* software enable */
 /*
  * APICBASE_PHYSADDR is actually variable-sized on some CPUs. But we're
  * only interested in the initial value, which is guaranteed to fit the
  * first 32 bits. So this macro is fine.
  */
 #define 	APICBASE_PHYSADDR	0xfffff000	/* physical address */
 #define MSR_EBL_CR_POWERON	0x02a
 #define MSR_EBC_FREQUENCY_ID	0x02c	/* PIV only */
 #define MSR_TEST_CTL		0x033
 #define MSR_IA32_SPEC_CTRL	0x048
 #define 	IA32_SPEC_CTRL_IBRS	0x01
 #define 	IA32_SPEC_CTRL_STIBP	0x02
 #define 	IA32_SPEC_CTRL_SSBD	0x04
 #define MSR_IA32_PRED_CMD	0x049
 #define 	IA32_PRED_CMD_IBPB	0x01
 #define MSR_BIOS_UPDT_TRIG	0x079
 #define MSR_BBL_CR_D0		0x088	/* PII+ only */
 #define MSR_BBL_CR_D1		0x089	/* PII+ only */
 #define MSR_BBL_CR_D2		0x08a	/* PII+ only */
 #define MSR_BIOS_SIGN		0x08b
 #define MSR_PERFCTR0		0x0c1
 #define MSR_PERFCTR1		0x0c2
 #define MSR_FSB_FREQ		0x0cd	/* Core Duo/Solo only */
 #define MSR_MPERF		0x0e7
 #define MSR_APERF		0x0e8
 #define MSR_IA32_EXT_CONFIG	0x0ee	/* Undocumented. Core Solo/Duo only */
 #define MSR_MTRRcap		0x0fe
 #define MSR_IA32_ARCH_CAPABILITIES 0x10a
 #define 	IA32_ARCH_RDCL_NO	0x01
 #define 	IA32_ARCH_IBRS_ALL	0x02
 #define 	IA32_ARCH_SSB_NO	0x10
 #define MSR_BBL_CR_ADDR		0x116	/* PII+ only */
 #define MSR_BBL_CR_DECC		0x118	/* PII+ only */
 #define MSR_BBL_CR_CTL		0x119	/* PII+ only */
 #define MSR_BBL_CR_TRIG		0x11a	/* PII+ only */
 #define MSR_BBL_CR_BUSY		0x11b	/* PII+ only */
 #define MSR_BBL_CR_CTR3		0x11e	/* PII+ only */
 #define MSR_SYSENTER_CS		0x174	/* PII+ only */
 #define MSR_SYSENTER_ESP	0x175	/* PII+ only */
 #define MSR_SYSENTER_EIP	0x176	/* PII+ only */
 #define MSR_MCG_CAP		0x179
 #define MSR_MCG_STATUS		0x17a
 #define MSR_MCG_CTL		0x17b
 #define MSR_EVNTSEL0		0x186

 @@ -1,14 +1,14 @@
-/*	$NetBSD: spectre.c,v 1.11 2018/05/22 06:31:05 maxv Exp $	*/
+/*	$NetBSD: spectre.c,v 1.12 2018/05/22 07:11:53 maxv Exp $	*/
 /*
  * Copyright (c) 2018 NetBSD Foundation, Inc.
  * All rights reserved.
+ *
  * This code is derived from software contributed to The NetBSD Foundation
  * by Maxime Villard.
+ *
  * Redistribution and use in source and binary forms, with or without
  * modification, are permitted provided that the following conditions
  * are met:
  * 1. Redistributions of source code must retain the above copyright
  *    notice, this list of conditions and the following disclaimer.
 @@ -24,27 +24,27 @@
  * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
  * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
  * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
  * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
  * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
  * POSSIBILITY OF SUCH DAMAGE.
  */
 /*
  * Mitigations for the Spectre V2 CPU flaw.
  */
 #include <sys/cdefs.h>
-__KERNEL_RCSID(0, "$NetBSD: spectre.c,v 1.11 2018/05/22 06:31:05 maxv Exp $");
+__KERNEL_RCSID(0, "$NetBSD: spectre.c,v 1.12 2018/05/22 07:11:53 maxv Exp $");
 #include <sys/param.h>
 #include <sys/systm.h>
 #include <sys/cpu.h>
 #include <sys/sysctl.h>
 #include <sys/xcall.h>
 #include <machine/cpufunc.h>
 #include <machine/cpuvar.h>
 #include <machine/specialreg.h>
 #include <machine/frameasm.h>
 #include <x86/cputypes.h>
 @@ -337,26 +337,160 @@ sysctl_machdep_spectreV2_mitigated(SYSCT
 			error = mitigation_v2_change(false);
 	} else {
 		if (spec_v2_mitigation_enabled)
 			error = 0;
 		else
 			error = mitigation_v2_change(true);
+	}
 	return error;
+}
 /* -------------------------------------------------------------------------- */
 bool spec_v4_mitigation_enabled __read_mostly = false;
 bool spec_v4_affected __read_mostly = true;
 int sysctl_machdep_spectreV4_mitigated(SYSCTLFN_ARGS);
 static bool ssbd_needed(void)
+{
 	uint64_t msr;
 	if (cpu_info_primary.ci_feat_val[7] & CPUID_SEF_ARCH_CAP) {
 		msr = rdmsr(MSR_IA32_ARCH_CAPABILITIES);
 		if (msr & IA32_ARCH_SSB_NO) {
 			/*
 			 * The processor indicates it is not vulnerable to the
 			 * Speculative Store Bypass (SpectreV4) flaw.
 			 */
 			return false;
+		}
+	}
 	return true;
+}
 static bool ssbd_supported(void)
+{
 	u_int descs[4];
 	if (cpu_vendor == CPUVENDOR_INTEL) {
 		if (cpuid_level >= 7) {
 			x86_cpuid(7, descs);
 			if (descs[3] & CPUID_SEF_SSBD) {
 				/* descs[3] = %edx */
 				return true;
+			}
+		}
+	}
 	return false;
+}
 static void
 mitigation_v4_apply_cpu(bool enabled)
+{
 	uint64_t msr;
 	msr = rdmsr(MSR_IA32_SPEC_CTRL);
 	if (enabled) {
 		msr |= IA32_SPEC_CTRL_SSBD;
 	} else {
 		msr &= ~IA32_SPEC_CTRL_SSBD;
+	}
 	wrmsr(MSR_IA32_SPEC_CTRL, msr);
+}
 static void
 mitigation_v4_change_cpu(void *arg1, void *arg2)
+{
 	bool enabled = (bool)arg1;
 	mitigation_v4_apply_cpu(enabled);
+}
 static int mitigation_v4_change(bool enabled)
+{
 	struct cpu_info *ci = NULL;
 	CPU_INFO_ITERATOR cii;
 	uint64_t xc;
 	if (!ssbd_supported()) {
 			printf("[!] No mitigation available\n");
 			return EOPNOTSUPP;
+	}
 	mutex_enter(&cpu_lock);
 	/*
 	 * We expect all the CPUs to be online.
 	 */
 	for (CPU_INFO_FOREACH(cii, ci)) {
 		struct schedstate_percpu *spc = &ci->ci_schedstate;
 		if (spc->spc_flags & SPCF_OFFLINE) {
 			printf("[!] cpu%d offline, SpectreV4 not changed\n",
 			    cpu_index(ci));
 			mutex_exit(&cpu_lock);
 			return EOPNOTSUPP;
+		}
+	}
 	printf("[+] %s SpectreV4 Mitigation...",
 	    enabled ? "Enabling" : "Disabling");
 	xc = xc_broadcast(0, mitigation_v4_change_cpu,
 	    (void *)enabled, NULL);
 	xc_wait(xc);
 	printf(" done!\n");
 	spec_v4_mitigation_enabled = enabled;
 	mutex_exit(&cpu_lock);
 	return 0;
+}
 int
 sysctl_machdep_spectreV4_mitigated(SYSCTLFN_ARGS)
+{
 	struct sysctlnode node;
 	int error;
 	bool val;
 	val = *(bool *)rnode->sysctl_data;
 	node = *rnode;
 	node.sysctl_data = &val;
 	error = sysctl_lookup(SYSCTLFN_CALL(&node));
 	if (error != 0 || newp == NULL)
 		return error;
 	if (val == 0) {
 		if (!spec_v4_mitigation_enabled)
 			error = 0;
 		else
 			error = mitigation_v4_change(false);
 	} else {
 		if (spec_v4_mitigation_enabled)
 			error = 0;
 		else
 			error = mitigation_v4_change(true);
+	}
 	return error;
+}
 /* -------------------------------------------------------------------------- */
 void speculation_barrier(struct lwp *, struct lwp *);
 void
 speculation_barrier(struct lwp *oldlwp, struct lwp *newlwp)
+{
 	/*
 	 * Speculation barriers are applicable only to Spectre V2.
 	 */
 	if (!spec_v2_mitigation_enabled)
 		return;
 	/*
 	 * From kernel thread to kernel thread, no need for a barrier.
 @@ -383,14 +517,25 @@ cpu_speculation_init(struct cpu_info *ci
+	 *
 	 * cpu0 is the one that detects the method and sets the global
 	 * variable.
 	 */
 	if (ci == &cpu_info_primary) {
 		spec_v2_detect_method();
 		spec_v2_mitigation_enabled =
 		    (mitigation_v2_method != MITIGATION_NONE);
 		spec_v2_set_name();
+	}
 	if (mitigation_v2_method != MITIGATION_NONE) {
 		mitigation_v2_apply_cpu(ci, true);
+	}
 	/*
 	 * Spectre V4.
 	 */
 	if (ssbd_needed()) {
 		if (ci == &cpu_info_primary) {
 			spec_v4_affected = true;
+		}
 		/* mitigation_v4_apply_cpu(true); */
 		/* spec_v4_mitigation_enabled = true; */
+	}
+}

 @@ -1,14 +1,14 @@
-/*	$NetBSD: x86_machdep.c,v 1.112 2018/05/22 06:31:05 maxv Exp $	*/
+/*	$NetBSD: x86_machdep.c,v 1.113 2018/05/22 07:11:53 maxv Exp $	*/
 /*-
  * Copyright (c) 2002, 2006, 2007 YAMAMOTO Takashi,
  * Copyright (c) 2005, 2008, 2009 The NetBSD Foundation, Inc.
  * All rights reserved.
+ *
  * This code is derived from software contributed to The NetBSD Foundation
  * by Julio M. Merino Vidal.
+ *
  * Redistribution and use in source and binary forms, with or without
  * modification, are permitted provided that the following conditions
  * are met:
  * 1. Redistributions of source code must retain the above copyright
 @@ -21,27 +21,27 @@
  * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
  * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
  * PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
  * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
  * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
  * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
  * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
  * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
  * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
  * POSSIBILITY OF SUCH DAMAGE.
  */
 #include <sys/cdefs.h>
-__KERNEL_RCSID(0, "$NetBSD: x86_machdep.c,v 1.112 2018/05/22 06:31:05 maxv Exp $");
+__KERNEL_RCSID(0, "$NetBSD: x86_machdep.c,v 1.113 2018/05/22 07:11:53 maxv Exp $");
 #include "opt_modular.h"
 #include "opt_physmem.h"
 #include "opt_splash.h"
 #include "opt_kaslr.h"
 #include "opt_svs.h"
 #include <sys/types.h>
 #include <sys/param.h>
 #include <sys/systm.h>
 #include <sys/kcore.h>
 #include <sys/errno.h>
 #include <sys/kauth.h>
 @@ -1263,28 +1263,31 @@ SYSCTL_SETUP(sysctl_machdep_setup, "sysc
 		       CTLTYPE_NODE, "svs", NULL,
 		       NULL, 0, NULL, 0,
 		       CTL_MACHDEP, CTL_CREATE);
 	sysctl_createv(clog, 0, &svs_rnode, &svs_rnode,
 		       CTLFLAG_READWRITE,
 		       CTLTYPE_BOOL, "enabled",
 		       SYSCTL_DESCR("Whether the kernel uses SVS"),
 		       sysctl_machdep_svs_enabled, 0, &svs_enabled, 0,
 		       CTL_CREATE, CTL_EOL);
 #endif
 #ifndef XEN
 	int sysctl_machdep_spectreV2_mitigated(SYSCTLFN_ARGS);
 	int sysctl_machdep_spectreV4_mitigated(SYSCTLFN_ARGS);
 	extern bool spec_v2_mitigation_enabled;
 	extern bool spec_v4_mitigation_enabled;
 	extern char spec_v2_mitigation_name[];
 	extern bool spec_v4_affected;
 	const struct sysctlnode *spec_rnode;
 	/* SpectreV1 */
 	spec_rnode = NULL;
 	sysctl_createv(clog, 0, NULL, &spec_rnode,
 		       CTLFLAG_PERMANENT,
 		       CTLTYPE_NODE, "spectre_v1", NULL,
 		       NULL, 0, NULL, 0,
 		       CTL_MACHDEP, CTL_CREATE);
 	sysctl_createv(clog, 0, &spec_rnode, &spec_rnode,
 		       CTLFLAG_PERMANENT | CTLFLAG_IMMEDIATE,
 		       CTLTYPE_BOOL, "mitigated",
 		       SYSCTL_DESCR("Whether Spectre Variant 1 is mitigated"),
 @@ -1302,26 +1305,48 @@ SYSCTL_SETUP(sysctl_machdep_setup, "sysc
 		       CTLFLAG_READWRITE,
 		       CTLTYPE_BOOL, "mitigated",
 		       SYSCTL_DESCR("Whether Spectre Variant 2 is mitigated"),
 		       sysctl_machdep_spectreV2_mitigated, 0,
 		       &spec_v2_mitigation_enabled, 0,
 		       CTL_CREATE, CTL_EOL);
 	sysctl_createv(clog, 0, &spec_rnode, NULL,
 		       CTLFLAG_PERMANENT,
 		       CTLTYPE_STRING, "method",
 		       SYSCTL_DESCR("Mitigation method in use"),
 		       NULL, 0,
 		       spec_v2_mitigation_name, 0,
 		       CTL_CREATE, CTL_EOL);
 	/* SpectreV4 */
 	spec_rnode = NULL;
 	sysctl_createv(clog, 0, NULL, &spec_rnode,
 		       CTLFLAG_PERMANENT,
 		       CTLTYPE_NODE, "spectre_v4", NULL,
 		       NULL, 0, NULL, 0,
 		       CTL_MACHDEP, CTL_CREATE);
 	sysctl_createv(clog, 0, &spec_rnode, NULL,
 		       CTLFLAG_READWRITE,
 		       CTLTYPE_BOOL, "mitigated",
 		       SYSCTL_DESCR("Whether Spectre Variant 4 is mitigated"),
 		       sysctl_machdep_spectreV4_mitigated, 0,
 		       &spec_v4_mitigation_enabled, 0,
 		       CTL_CREATE, CTL_EOL);
 	sysctl_createv(clog, 0, &spec_rnode, NULL,
 		       CTLFLAG_PERMANENT,
 		       CTLTYPE_BOOL, "affected",
 		       SYSCTL_DESCR("Whether the CPU is affected by SpectreV4"),
 		       NULL, 0,
 	           &spec_v4_affected, 0,
 		       CTL_CREATE, CTL_EOL);
 #endif
 	/* None of these can ever change once the system has booted */
 	const_sysctl(clog, "fpu_present", CTLTYPE_INT, i386_fpu_present,
 	    CPU_FPU_PRESENT);
 	const_sysctl(clog, "osfxsr", CTLTYPE_INT, i386_use_fxsave,
 	    CPU_OSFXSR);
 	const_sysctl(clog, "sse", CTLTYPE_INT, i386_has_sse,
 	    CPU_SSE);
 	const_sysctl(clog, "sse2", CTLTYPE_INT, i386_has_sse2,
 	    CPU_SSE2);
 	const_sysctl(clog, "fpu_save", CTLTYPE_INT, x86_fpu_save,