Sat Jun 16 23:14:47 2018 UTC ()
Replace register numbers with defines, fixing a bunch of typos in the process.


(jmcneill)
diff -r1.1 -r1.2 src/sys/arch/arm/rockchip/rk3328_cru.c
cvs diff -r1.1 -r1.2 src/sys/arch/arm/rockchip/rk3328_cru.c (expand / switch to unified diff)

--- src/sys/arch/arm/rockchip/rk3328_cru.c 2018/06/16 00:19:04 1.1
+++ src/sys/arch/arm/rockchip/rk3328_cru.c 2018/06/16 23:14:47 1.2
@@ -1,14 +1,14 @@ @@ -1,14 +1,14 @@
1/* $NetBSD: rk3328_cru.c,v 1.1 2018/06/16 00:19:04 jmcneill Exp $ */ 1/* $NetBSD: rk3328_cru.c,v 1.2 2018/06/16 23:14:47 jmcneill Exp $ */
2 2
3/*- 3/*-
4 * Copyright (c) 2018 Jared McNeill <jmcneill@invisible.ca> 4 * Copyright (c) 2018 Jared McNeill <jmcneill@invisible.ca>
5 * All rights reserved. 5 * All rights reserved.
6 * 6 *
7 * Redistribution and use in source and binary forms, with or without 7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions 8 * modification, are permitted provided that the following conditions
9 * are met: 9 * are met:
10 * 1. Redistributions of source code must retain the above copyright 10 * 1. Redistributions of source code must retain the above copyright
11 * notice, this list of conditions and the following disclaimer. 11 * notice, this list of conditions and the following disclaimer.
12 * 2. Redistributions in binary form must reproduce the above copyright 12 * 2. Redistributions in binary form must reproduce the above copyright
13 * notice, this list of conditions and the following disclaimer in the 13 * notice, this list of conditions and the following disclaimer in the
14 * documentation and/or other materials provided with the distribution. 14 * documentation and/or other materials provided with the distribution.
@@ -18,38 +18,46 @@ @@ -18,38 +18,46 @@
18 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 18 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
19 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 19 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
20 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, 20 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
21 * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; 21 * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
22 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED 22 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
23 * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, 23 * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
24 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 24 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
25 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 25 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
26 * SUCH DAMAGE. 26 * SUCH DAMAGE.
27 */ 27 */
28 28
29#include <sys/cdefs.h> 29#include <sys/cdefs.h>
30 30
31__KERNEL_RCSID(1, "$NetBSD: rk3328_cru.c,v 1.1 2018/06/16 00:19:04 jmcneill Exp $"); 31__KERNEL_RCSID(1, "$NetBSD: rk3328_cru.c,v 1.2 2018/06/16 23:14:47 jmcneill Exp $");
32 32
33#include <sys/param.h> 33#include <sys/param.h>
34#include <sys/bus.h> 34#include <sys/bus.h>
35#include <sys/device.h> 35#include <sys/device.h>
36#include <sys/systm.h> 36#include <sys/systm.h>
37 37
38#include <dev/fdt/fdtvar.h> 38#include <dev/fdt/fdtvar.h>
39 39
40#include <arm/rockchip/rk_cru.h> 40#include <arm/rockchip/rk_cru.h>
41#include <arm/rockchip/rk3328_cru.h> 41#include <arm/rockchip/rk3328_cru.h>
42 42
 43#define PLL_CON(n) (0x0000 + (n) * 4)
 44#define MISC_CON 0x0084
 45#define CLKSEL_CON(n) (0x0100 + (n) * 4)
 46#define CLKGATE_CON(n) (0x0200 + (n) * 4)
 47
 48#define GRF_SOC_CON4 0x0410
 49#define GRF_MAC_CON1 0x0904
 50
43static int rk3328_cru_match(device_t, cfdata_t, void *); 51static int rk3328_cru_match(device_t, cfdata_t, void *);
44static void rk3328_cru_attach(device_t, device_t, void *); 52static void rk3328_cru_attach(device_t, device_t, void *);
45 53
46static const char * const compatible[] = { 54static const char * const compatible[] = {
47 "rockchip,rk3328-cru", 55 "rockchip,rk3328-cru",
48 NULL 56 NULL
49}; 57};
50 58
51CFATTACH_DECL_NEW(rk3328_cru, sizeof(struct rk_cru_softc), 59CFATTACH_DECL_NEW(rk3328_cru, sizeof(struct rk_cru_softc),
52 rk3328_cru_match, rk3328_cru_attach, NULL, NULL); 60 rk3328_cru_match, rk3328_cru_attach, NULL, NULL);
53 61
54static const struct rk_cru_pll_rate pll_rates[] = { 62static const struct rk_cru_pll_rate pll_rates[] = {
55 RK_PLL_RATE(1608000000, 1, 67, 1, 1, 1, 0), 63 RK_PLL_RATE(1608000000, 1, 67, 1, 1, 1, 0),
@@ -116,228 +124,235 @@ static const struct rk_cru_arm_rate armc @@ -116,228 +124,235 @@ static const struct rk_cru_arm_rate armc
116 RK_ARM_RATE( 912000000, 1), 124 RK_ARM_RATE( 912000000, 1),
117 RK_ARM_RATE( 816000000, 1), 125 RK_ARM_RATE( 816000000, 1),
118 RK_ARM_RATE( 696000000, 1), 126 RK_ARM_RATE( 696000000, 1),
119 RK_ARM_RATE( 600000000, 1), 127 RK_ARM_RATE( 600000000, 1),
120 RK_ARM_RATE( 408000000, 1), 128 RK_ARM_RATE( 408000000, 1),
121 RK_ARM_RATE( 312000000, 1), 129 RK_ARM_RATE( 312000000, 1),
122 RK_ARM_RATE( 216000000, 1), 130 RK_ARM_RATE( 216000000, 1),
123 RK_ARM_RATE( 96000000, 1), 131 RK_ARM_RATE( 96000000, 1),
124}; 132};
125 133
126static const char * armclk_parents[] = { "apll", "gpll", "dpll", "npll" }; 134static const char * armclk_parents[] = { "apll", "gpll", "dpll", "npll" };
127static const char * aclk_bus_pre_parents[] = { "cpll", "gpll", "hdmiphy" }; 135static const char * aclk_bus_pre_parents[] = { "cpll", "gpll", "hdmiphy" };
128static const char * hclk_bus_pre_parents[] = { "aclk_bus_pre" }; 136static const char * hclk_bus_pre_parents[] = { "aclk_bus_pre" };
129static const char * aclk_peri_pre_parents[] = { "cpll", "gpll", "hdmiphy" }; 137static const char * pclk_bus_pre_parents[] = { "aclk_bus_pre" };
 138static const char * aclk_peri_pre_parents[] = { "cpll", "gpll", "hdmiphy_peri" };
130static const char * mmc_parents[] = { "cpll", "gpll", "xin24m", "usb480m" }; 139static const char * mmc_parents[] = { "cpll", "gpll", "xin24m", "usb480m" };
131static const char * phclk_peri_parents[] = { "aclk_peri_pre" }; 140static const char * phclk_peri_parents[] = { "aclk_peri_pre" };
 141static const char * mux_hdmiphy_parents[] = { "hdmi_phy", "xin24m" };
132static const char * mux_usb480m_parents[] = { "usb480m_phy", "xin24m" }; 142static const char * mux_usb480m_parents[] = { "usb480m_phy", "xin24m" };
133static const char * mux_uart0_parents[] = { "clk_uart0_div", "clk_uart0_frac", "xin24m" }; 143static const char * mux_uart0_parents[] = { "clk_uart0_div", "clk_uart0_frac", "xin24m" };
134static const char * mux_uart1_parents[] = { "clk_uart1_div", "clk_uart1_frac", "xin24m" }; 144static const char * mux_uart1_parents[] = { "clk_uart1_div", "clk_uart1_frac", "xin24m" };
135static const char * mux_uart2_parents[] = { "clk_uart2_div", "clk_uart2_frac", "xin24m" }; 145static const char * mux_uart2_parents[] = { "clk_uart2_div", "clk_uart2_frac", "xin24m" };
136static const char * mux_mac2io_src_parents[] = { "clk_mac2io_src", "gmac_clkin" }; 146static const char * mux_mac2io_src_parents[] = { "clk_mac2io_src", "gmac_clkin" };
137static const char * mux_mac2io_ext_parents[] = { "clk_mac2io", "gmac_clkin" }; 147static const char * mux_mac2io_ext_parents[] = { "clk_mac2io", "gmac_clkin" };
138static const char * mux_2plls_parents[] = { "cpll", "gpll" }; 148static const char * mux_2plls_parents[] = { "cpll", "gpll" };
139static const char * mux_2plls_hdmiphy_parents[] = { "cpll", "gpll", "dummy_hdmiphy" }; 149static const char * mux_2plls_hdmiphy_parents[] = { "cpll", "gpll", "dummy_hdmiphy" };
140static const char * comp_uart_parents[] = { "cpll", "gpll", "usb480m" }; 150static const char * comp_uart_parents[] = { "cpll", "gpll", "usb480m" };
141static const char * pclk_gmac_parents[] = { "aclk_gmac" }; 151static const char * pclk_gmac_parents[] = { "aclk_gmac" };
142 152
143static struct rk_cru_clk rk3328_cru_clks[] = { 153static struct rk_cru_clk rk3328_cru_clks[] = {
144 RK_PLL(RK3328_PLL_APLL, "apll", "xin24m", 154 RK_PLL(RK3328_PLL_APLL, "apll", "xin24m",
145 0x0000, /* con_base */ 155 PLL_CON(0), /* con_base */
146 0x80, /* mode_reg */ 156 0x80, /* mode_reg */
147 __BIT(0), /* mode_mask */ 157 __BIT(0), /* mode_mask */
148 __BIT(4), /* lock_mask */ 158 __BIT(4), /* lock_mask */
149 pll_frac_rates), 159 pll_frac_rates),
150 RK_PLL(RK3328_PLL_DPLL, "dpll", "xin24m", 160 RK_PLL(RK3328_PLL_DPLL, "dpll", "xin24m",
151 0x0020, /* con_base */ 161 PLL_CON(8), /* con_base */
152 0x80, /* mode_reg */ 162 0x80, /* mode_reg */
153 __BIT(4), /* mode_mask */ 163 __BIT(4), /* mode_mask */
154 __BIT(3), /* lock_mask */ 164 __BIT(3), /* lock_mask */
155 pll_norates), 165 pll_norates),
156 RK_PLL(RK3328_PLL_CPLL, "cpll", "xin24m", 166 RK_PLL(RK3328_PLL_CPLL, "cpll", "xin24m",
157 0x0040, /* con_base */ 167 PLL_CON(16), /* con_base */
158 0x80, /* mode_reg */ 168 0x80, /* mode_reg */
159 __BIT(8), /* mode_mask */ 169 __BIT(8), /* mode_mask */
160 __BIT(2), /* lock_mask */ 170 __BIT(2), /* lock_mask */
161 pll_rates), 171 pll_rates),
162 RK_PLL(RK3328_PLL_GPLL, "gpll", "xin24m", 172 RK_PLL(RK3328_PLL_GPLL, "gpll", "xin24m",
163 0x0060, /* con_base */ 173 PLL_CON(24), /* con_base */
164 0x80, /* mode_reg */ 174 0x80, /* mode_reg */
165 __BIT(12), /* mode_mask */ 175 __BIT(12), /* mode_mask */
166 __BIT(1), /* lock_mask */ 176 __BIT(1), /* lock_mask */
167 pll_frac_rates), 177 pll_frac_rates),
168 RK_PLL(RK3328_PLL_NPLL, "npll", "xin24m", 178 RK_PLL(RK3328_PLL_NPLL, "npll", "xin24m",
169 0x00a0, /* con_base */ 179 PLL_CON(40), /* con_base */
170 0x80, /* mode_reg */ 180 0x80, /* mode_reg */
171 __BIT(1), /* mode_mask */ 181 __BIT(1), /* mode_mask */
172 __BIT(0), /* lock_mask */ 182 __BIT(0), /* lock_mask */
173 pll_rates), 183 pll_rates),
174 184
175 RK_ARM(RK3328_ARMCLK, "armclk", armclk_parents, 185 RK_ARM(RK3328_ARMCLK, "armclk", armclk_parents,
176 0x0100, /* reg */ 186 CLKSEL_CON(0), /* reg */
177 __BITS(7,6), 3, 0, /* mux_mask, mux_main, mux_alt */ 187 __BITS(7,6), 3, 1, /* mux_mask, mux_main, mux_alt */
178 __BITS(4,0), /* div_mask */ 188 __BITS(4,0), /* div_mask */
179 armclk_rates), 189 armclk_rates),
180 190
181 RK_COMPOSITE(RK3328_ACLK_BUS_PRE, "aclk_bus_pre", aclk_bus_pre_parents, 191 RK_COMPOSITE(RK3328_ACLK_BUS_PRE, "aclk_bus_pre", aclk_bus_pre_parents,
182 0x0100, /* muxdiv_reg */ 192 CLKSEL_CON(0), /* muxdiv_reg */
183 __BITS(14,13), /* mux_mask */ 193 __BITS(14,13), /* mux_mask */
184 __BITS(12,8), /* div_mask */ 194 __BITS(12,8), /* div_mask */
185 0x0220, /* gate_reg */ 195 CLKGATE_CON(8), /* gate_reg */
186 __BIT(0), /* gate_mask */ 196 __BIT(0), /* gate_mask */
187 0), 197 0),
188 RK_COMPOSITE(RK3328_HCLK_BUS_PRE, "hclk_bus_pre", hclk_bus_pre_parents, 198 RK_COMPOSITE(RK3328_HCLK_BUS_PRE, "hclk_bus_pre", hclk_bus_pre_parents,
189 0x0104, /* muxdiv_reg */ 199 CLKSEL_CON(1), /* muxdiv_reg */
190 0, /* mux_mask */ 200 0, /* mux_mask */
191 __BITS(9,8), /* div_mask */ 201 __BITS(9,8), /* div_mask */
192 0x0220, /* gate_reg */ 202 CLKGATE_CON(8), /* gate_reg */
193 __BIT(1), /* gate_mask */ 203 __BIT(1), /* gate_mask */
194 0), 204 0),
195 RK_COMPOSITE(RK3328_PCLK_BUS_PRE, "pclk_bus_pre", hclk_bus_pre_parents, 205 RK_COMPOSITE(RK3328_PCLK_BUS_PRE, "pclk_bus_pre", pclk_bus_pre_parents,
196 0x0104, /* muxdiv_reg */ 206 CLKSEL_CON(1), /* muxdiv_reg */
197 0, /* mux_mask */ 207 0, /* mux_mask */
198 __BITS(14,12), /* div_mask */ 208 __BITS(14,12), /* div_mask */
199 0x0220, /* gate_reg */ 209 CLKGATE_CON(8), /* gate_reg */
200 __BIT(2), /* gate_mask */ 210 __BIT(2), /* gate_mask */
201 0), 211 0),
202 RK_COMPOSITE(RK3328_ACLK_PERI_PRE, "aclk_peri_pre", aclk_peri_pre_parents, 212 RK_COMPOSITE(RK3328_ACLK_PERI_PRE, "aclk_peri_pre", aclk_peri_pre_parents,
203 0x0170, /* muxdiv_reg */ 213 CLKSEL_CON(28), /* muxdiv_reg */
204 __BITS(7,6), /* mux_mask */ 214 __BITS(7,6), /* mux_mask */
205 __BITS(4,0), /* div_mask */ 215 __BITS(4,0), /* div_mask */
206 0, 0, /* gate_reg, gate_mask */ 216 0, 0, /* gate_reg, gate_mask */
207 0), 217 0),
208 RK_COMPOSITE(RK3328_PCLK_PERI, "pclk_peri", phclk_peri_parents, 218 RK_COMPOSITE(RK3328_PCLK_PERI, "pclk_peri", phclk_peri_parents,
209 0x0174, /* muxdiv_reg */ 219 CLKSEL_CON(29), /* muxdiv_reg */
210 0, /* mux_mask */ 220 0, /* mux_mask */
211 __BITS(6,4), /* div_mask */ 221 __BITS(1,0), /* div_mask */
212 0x0228, /* gate_reg */ 222 CLKGATE_CON(10), /* gate_reg */
213 __BIT(2), /* gate_mask */ 223 __BIT(2), /* gate_mask */
214 0), 224 0),
215 RK_COMPOSITE(RK3328_HCLK_PERI, "hclk_peri", phclk_peri_parents, 225 RK_COMPOSITE(RK3328_HCLK_PERI, "hclk_peri", phclk_peri_parents,
216 0x0174, /* muxdiv_reg */ 226 CLKSEL_CON(29), /* muxdiv_reg */
217 0, /* mux_mask */ 227 0, /* mux_mask */
218 __BITS(1,0), /* div_mask */ 228 __BITS(6,4), /* div_mask */
219 0x0228, /* gate_reg */ 229 CLKGATE_CON(10), /* gate_reg */
220 __BIT(1), /* gate_mask */ 230 __BIT(1), /* gate_mask */
221 0), 231 0),
222 RK_COMPOSITE(RK3328_SCLK_SDMMC, "clk_sdmmc", mmc_parents, 232 RK_COMPOSITE(RK3328_SCLK_SDMMC, "clk_sdmmc", mmc_parents,
223 0x0178, /* muxdiv_reg */ 233 CLKSEL_CON(30), /* muxdiv_reg */
224 __BITS(9,8), /* mux_mask */ 234 __BITS(9,8), /* mux_mask */
225 __BITS(7,0), /* div_mask */ 235 __BITS(7,0), /* div_mask */
226 0x0210, /* gate_reg */ 236 CLKGATE_CON(4), /* gate_reg */
227 __BIT(3), /* gate_mask */ 237 __BIT(3), /* gate_mask */
228 RK_COMPOSITE_ROUND_DOWN), 238 RK_COMPOSITE_ROUND_DOWN),
229 RK_COMPOSITE(RK3328_SCLK_SDIO, "clk_sdio", mmc_parents, 239 RK_COMPOSITE(RK3328_SCLK_SDIO, "clk_sdio", mmc_parents,
230 0x0180, /* muxdiv_reg */ 240 CLKSEL_CON(31), /* muxdiv_reg */
231 __BITS(9,8), /* mux_mask */ 241 __BITS(9,8), /* mux_mask */
232 __BITS(7,0), /* div_mask */ 242 __BITS(7,0), /* div_mask */
233 0x0210, /* gate_reg */ 243 CLKGATE_CON(4), /* gate_reg */
234 __BIT(5), /* gate_mask */ 244 __BIT(4), /* gate_mask */
235 RK_COMPOSITE_ROUND_DOWN), 245 RK_COMPOSITE_ROUND_DOWN),
236 RK_COMPOSITE(RK3328_SCLK_EMMC, "clk_emmc", mmc_parents, 246 RK_COMPOSITE(RK3328_SCLK_EMMC, "clk_emmc", mmc_parents,
237 0x017c, /* muxdiv_reg */ 247 CLKSEL_CON(32), /* muxdiv_reg */
238 __BITS(9,8), /* mux_mask */ 248 __BITS(9,8), /* mux_mask */
239 __BITS(7,0), /* div_mask */ 249 __BITS(7,0), /* div_mask */
240 0x0210, /* gate_reg */ 250 CLKGATE_CON(4), /* gate_reg */
241 __BIT(4), /* gate_mask */ 251 __BIT(5), /* gate_mask */
242 RK_COMPOSITE_ROUND_DOWN), 252 RK_COMPOSITE_ROUND_DOWN),
243 RK_COMPOSITE(0, "clk_uart0_div", comp_uart_parents, 253 RK_COMPOSITE(0, "clk_uart0_div", comp_uart_parents,
244 0x0138, /* muxdiv_reg */ 254 CLKSEL_CON(14), /* muxdiv_reg */
245 __BITS(13,12), /* mux_mask */ 255 __BITS(13,12), /* mux_mask */
246 __BITS(6,0), /* div_mask */ 256 __BITS(6,0), /* div_mask */
247 0x0204, /* gate_reg */ 257 CLKGATE_CON(1), /* gate_reg */
248 __BIT(14), /* gate_mask */ 258 __BIT(14), /* gate_mask */
249 0), 259 0),
250 RK_COMPOSITE(0, "clk_uart1_div", comp_uart_parents, 260 RK_COMPOSITE(0, "clk_uart1_div", comp_uart_parents,
251 0x0140, /* muxdiv_reg */ 261 CLKSEL_CON(16), /* muxdiv_reg */
252 __BITS(13,12), /* mux_mask */ 262 __BITS(13,12), /* mux_mask */
253 __BITS(6,0), /* div_mask */ 263 __BITS(6,0), /* div_mask */
254 0x0208, /* gate_reg */ 264 CLKGATE_CON(2), /* gate_reg */
255 __BIT(0), /* gate_mask */ 265 __BIT(0), /* gate_mask */
256 0), 266 0),
257 RK_COMPOSITE(0, "clk_uart2_div", comp_uart_parents, 267 RK_COMPOSITE(0, "clk_uart2_div", comp_uart_parents,
258 0x0148, /* muxdiv_reg */ 268 CLKSEL_CON(18), /* muxdiv_reg */
259 __BITS(13,12), /* mux_mask */ 269 __BITS(13,12), /* mux_mask */
260 __BITS(6,0), /* div_mask */ 270 __BITS(6,0), /* div_mask */
261 0x0208, /* gate_reg */ 271 CLKGATE_CON(2), /* gate_reg */
262 __BIT(2), /* gate_mask */ 272 __BIT(2), /* gate_mask */
263 0), 273 0),
264 RK_COMPOSITE(RK3328_ACLK_GMAC, "aclk_gmac", mux_2plls_hdmiphy_parents, 274 RK_COMPOSITE(RK3328_ACLK_GMAC, "aclk_gmac", mux_2plls_hdmiphy_parents,
265 0x018c, /* muxdiv_reg */ 275 CLKSEL_CON(35), /* muxdiv_reg */
266 __BITS(7,6), /* mux_mask */ 276 __BITS(7,6), /* mux_mask */
267 __BITS(4,0), /* div_mask */ 277 __BITS(4,0), /* div_mask */
268 0x020c, /* gate_reg */ 278 CLKGATE_CON(3), /* gate_reg */
269 __BIT(2), /* gate_mask */ 279 __BIT(2), /* gate_mask */
270 0), 280 0),
271 RK_COMPOSITE(RK3328_PCLK_GMAC, "pclk_gmac", pclk_gmac_parents, 281 RK_COMPOSITE(RK3328_PCLK_GMAC, "pclk_gmac", pclk_gmac_parents,
272 0x0164, /* muxdiv_reg */ 282 CLKSEL_CON(25), /* muxdiv_reg */
273 0, /* mux_mask */ 283 0, /* mux_mask */
274 __BITS(10,8), /* div_mask */ 284 __BITS(10,8), /* div_mask */
275 0x0224, /* gate_reg */ 285 CLKGATE_CON(9), /* gate_reg */
276 __BIT(0), /* gate_mask */ 286 __BIT(0), /* gate_mask */
277 0), 287 0),
278 RK_COMPOSITE(RK3328_SCLK_MAC2IO_SRC, "clk_mac2io_src", mux_2plls_parents, 288 RK_COMPOSITE(RK3328_SCLK_MAC2IO_SRC, "clk_mac2io_src", mux_2plls_parents,
279 0x016c, /* muxdiv_reg */ 289 CLKSEL_CON(27), /* muxdiv_reg */
280 __BIT(7), /* mux_mask */ 290 __BIT(7), /* mux_mask */
281 __BITS(4,0), /* div_mask */ 291 __BITS(4,0), /* div_mask */
282 0x020c, /* gate_reg */ 292 CLKGATE_CON(3), /* gate_reg */
283 __BIT(1), /* gate_mask */ 293 __BIT(1), /* gate_mask */
284 0), 294 0),
285 RK_COMPOSITE(RK3328_SCLK_MAC2IO_OUT, "clk_mac2io_out", mux_2plls_parents, 295 RK_COMPOSITE(RK3328_SCLK_MAC2IO_OUT, "clk_mac2io_out", mux_2plls_parents,
286 0x016c, /* muxdiv_reg */ 296 CLKSEL_CON(27), /* muxdiv_reg */
287 __BIT(15), /* mux_mask */ 297 __BIT(15), /* mux_mask */
288 __BITS(12,8), /* div_mask */ 298 __BITS(12,8), /* div_mask */
289 0x020c, /* gate_reg */ 299 CLKGATE_CON(3), /* gate_reg */
290 __BIT(5), /* gate_mask */ 300 __BIT(5), /* gate_mask */
291 0), 301 0),
292 302
293 RK_GATE(0, "apll_core", "apll", 0x200, 0), 303 RK_GATE(0, "apll_core", "apll", CLKGATE_CON(0), 0),
294 RK_GATE(0, "dpll_core", "dpll", 0x200, 1), 304 RK_GATE(0, "dpll_core", "dpll", CLKGATE_CON(0), 1),
295 RK_GATE(0, "gpll_core", "gpll", 0x200, 2), 305 RK_GATE(0, "gpll_core", "gpll", CLKGATE_CON(0), 2),
296 RK_GATE(0, "npll_core", "npll", 0x200, 12), 306 RK_GATE(0, "npll_core", "npll", CLKGATE_CON(0), 12),
297 RK_GATE(0, "gpll_peri", "gpll", 0x210, 0), 307 RK_GATE(0, "gpll_peri", "gpll", CLKGATE_CON(4), 0),
298 RK_GATE(0, "cpll_peri", "cpll", 0x210, 1), 308 RK_GATE(0, "cpll_peri", "cpll", CLKGATE_CON(4), 1),
299 RK_GATE(0, "pclk_bus", "pclk_bus_pre", 0x220, 3), 309 RK_GATE(0, "hdmiphy_peri", "hdmiphy", CLKGATE_CON(4), 2),
300 RK_GATE(0, "pclk_phy_pre", "pclk_bus_pre", 0x220, 4), 310 RK_GATE(0, "pclk_bus", "pclk_bus_pre", CLKGATE_CON(8), 3),
301 RK_GATE(RK3328_ACLK_PERI, "aclk_peri", "aclk_peri_pre", 0x228, 0), 311 RK_GATE(0, "pclk_phy_pre", "pclk_bus_pre", CLKGATE_CON(8), 4),
302 RK_GATE(RK3328_PCLK_GPIO0, "pclk_gpio0", "pclk_bus", 0x240, 7), 312 RK_GATE(RK3328_ACLK_PERI, "aclk_peri", "aclk_peri_pre", CLKGATE_CON(10), 0),
303 RK_GATE(RK3328_PCLK_GPIO1, "pclk_gpio1", "pclk_bus", 0x240, 8), 313 RK_GATE(RK3328_PCLK_GPIO0, "pclk_gpio0", "pclk_bus", CLKGATE_CON(16), 7),
304 RK_GATE(RK3328_PCLK_GPIO2, "pclk_gpio2", "pclk_bus", 0x240, 9), 314 RK_GATE(RK3328_PCLK_GPIO1, "pclk_gpio1", "pclk_bus", CLKGATE_CON(16), 8),
305 RK_GATE(RK3328_PCLK_GPIO3, "pclk_gpio3", "pclk_bus", 0x240, 10), 315 RK_GATE(RK3328_PCLK_GPIO2, "pclk_gpio2", "pclk_bus", CLKGATE_CON(16), 9),
306 RK_GATE(RK3328_PCLK_UART0, "pclk_uart0", "pclk_bus", 0x240, 11), 316 RK_GATE(RK3328_PCLK_GPIO3, "pclk_gpio3", "pclk_bus", CLKGATE_CON(16), 10),
307 RK_GATE(RK3328_PCLK_UART1, "pclk_uart1", "pclk_bus", 0x240, 12), 317 RK_GATE(RK3328_PCLK_UART0, "pclk_uart0", "pclk_bus", CLKGATE_CON(16), 11),
308 RK_GATE(RK3328_PCLK_UART2, "pclk_uart2", "pclk_bus", 0x240, 13), 318 RK_GATE(RK3328_PCLK_UART1, "pclk_uart1", "pclk_bus", CLKGATE_CON(16), 12),
309 RK_GATE(RK3328_SCLK_MAC2IO_REF, "clk_mac2io_ref", "clk_mac2io", 0x224, 7), 319 RK_GATE(RK3328_PCLK_UART2, "pclk_uart2", "pclk_bus", CLKGATE_CON(16), 13),
310 RK_GATE(RK3328_SCLK_MAC2IO_RX, "clk_mac2io_rx", "clk_mac2io", 0x224, 4), 320 RK_GATE(RK3328_SCLK_MAC2IO_REF, "clk_mac2io_ref", "clk_mac2io", CLKGATE_CON(9), 7),
311 RK_GATE(RK3328_SCLK_MAC2IO_TX, "clk_mac2io_tx", "clk_mac2io", 0x224, 5), 321 RK_GATE(RK3328_SCLK_MAC2IO_RX, "clk_mac2io_rx", "clk_mac2io", CLKGATE_CON(9), 4),
312 RK_GATE(RK3328_SCLK_MAC2IO_REFOUT, "clk_mac2io_refout", "clk_mac2io", 0x224, 6), 322 RK_GATE(RK3328_SCLK_MAC2IO_TX, "clk_mac2io_tx", "clk_mac2io", CLKGATE_CON(9), 5),
313 RK_GATE(RK3328_ACLK_USB3OTG, "aclk_usb3otg", "aclk_peri", 0x24c, 4), 323 RK_GATE(RK3328_SCLK_MAC2IO_REFOUT, "clk_mac2io_refout", "clk_mac2io", CLKGATE_CON(9), 6),
314 RK_GATE(RK3328_HCLK_SDMMC, "hclk_sdmmc", "hclk_peri", 0x24c, 0), 324 RK_GATE(0, "pclk_phy_niu", "pclk_phy_pre", CLKGATE_CON(15), 15),
315 RK_GATE(RK3328_HCLK_SDIO, "hclk_sdio", "hclk_peri", 0x24c, 1), 325 RK_GATE(RK3328_ACLK_USB3OTG, "aclk_usb3otg", "aclk_peri", CLKGATE_CON(19), 4),
316 RK_GATE(RK3328_HCLK_EMMC, "hclk_emmc", "hclk_peri", 0x24c, 2), 326 RK_GATE(RK3328_HCLK_SDMMC, "hclk_sdmmc", "hclk_peri", CLKGATE_CON(19), 0),
317 RK_GATE(RK3328_HCLK_SDMMC_EXT, "hclk_sdmmc_ext", "hclk_peri", 0x24c, 15), 327 RK_GATE(RK3328_HCLK_SDIO, "hclk_sdio", "hclk_peri", CLKGATE_CON(19), 1),
318 RK_GATE(RK3328_HCLK_HOST0, "hclk_host0", "hclk_peri", 0x24c, 6), 328 RK_GATE(RK3328_HCLK_EMMC, "hclk_emmc", "hclk_peri", CLKGATE_CON(19), 2),
319 RK_GATE(RK3328_HCLK_HOST0_ARB, "hclk_host0_arb", "hclk_peri", 0x24c, 7), 329 RK_GATE(RK3328_HCLK_SDMMC_EXT, "hclk_sdmmc_ext", "hclk_peri", CLKGATE_CON(19), 15),
320 RK_GATE(RK3328_HCLK_OTG, "hclk_otg", "hclk_peri", 0x24c, 8), 330 RK_GATE(RK3328_HCLK_HOST0, "hclk_host0", "hclk_peri", CLKGATE_CON(19), 6),
321 RK_GATE(RK3328_HCLK_OTG_PMU, "hclk_otg_pmu", "hclk_peri", 0x24c, 9), 331 RK_GATE(RK3328_HCLK_HOST0_ARB, "hclk_host0_arb", "hclk_peri", CLKGATE_CON(19), 7),
322 RK_GATE(RK3328_ACLK_MAC2IO, "aclk_mac2io", "aclk_gmac", 0x268, 2), 332 RK_GATE(RK3328_HCLK_OTG, "hclk_otg", "hclk_peri", CLKGATE_CON(19), 8),
323 RK_GATE(RK3328_PCLK_MAC2IO, "pclk_mac2io", "pclk_gmac", 0x268, 3), 333 RK_GATE(RK3328_HCLK_OTG_PMU, "hclk_otg_pmu", "hclk_peri", CLKGATE_CON(19), 9),
324 334 RK_GATE(RK3328_ACLK_MAC2IO, "aclk_mac2io", "aclk_gmac", CLKGATE_CON(26), 2),
325 RK_MUX(RK3328_USB480M, "usb480m", mux_usb480m_parents, 0x0084, __BIT(13)), 335 RK_GATE(RK3328_PCLK_MAC2IO, "pclk_mac2io", "pclk_gmac", CLKGATE_CON(26), 3),
326 RK_MUX(RK3328_SCLK_UART0, "sclk_uart0", mux_uart0_parents, 0x0138, __BITS(9,8)), 336 RK_GATE(0, "aclk_gmac_niu", "aclk_gmac", CLKGATE_CON(26), 4),
327 RK_MUX(RK3328_SCLK_UART1, "sclk_uart1", mux_uart1_parents, 0x0140, __BITS(9,8)), 337 RK_GATE(0, "pclk_gmac_niu", "pclk_gmac", CLKGATE_CON(26), 5),
328 RK_MUX(RK3328_SCLK_UART2, "sclk_uart2", mux_uart2_parents, 0x0148, __BITS(9,8)), 338
329 RK_MUXGRF(RK3328_SCLK_MAC2IO, "clk_mac2io", mux_mac2io_src_parents, 0x0904, __BIT(10)), 339 RK_MUX(RK3328_HDMIPHY, "hdmiphy", mux_hdmiphy_parents, MISC_CON, __BIT(13)),
330 RK_MUXGRF(RK3328_SCLK_MAC2IO_EXT, "clk_mac2io_ext", mux_mac2io_ext_parents, 0x0410, __BIT(14)), 340 RK_MUX(RK3328_USB480M, "usb480m", mux_usb480m_parents, MISC_CON, __BIT(15)),
 341 RK_MUX(RK3328_SCLK_UART0, "sclk_uart0", mux_uart0_parents, CLKSEL_CON(14), __BITS(9,8)),
 342 RK_MUX(RK3328_SCLK_UART1, "sclk_uart1", mux_uart1_parents, CLKSEL_CON(16), __BITS(9,8)),
 343 RK_MUX(RK3328_SCLK_UART2, "sclk_uart2", mux_uart2_parents, CLKSEL_CON(18), __BITS(9,8)),
 344 RK_MUXGRF(RK3328_SCLK_MAC2IO, "clk_mac2io", mux_mac2io_src_parents, GRF_MAC_CON1, __BIT(10)),
 345 RK_MUXGRF(RK3328_SCLK_MAC2IO_EXT, "clk_mac2io_ext", mux_mac2io_ext_parents, GRF_SOC_CON4, __BIT(14)),
331}; 346};
332 347
333static int 348static int
334rk3328_cru_match(device_t parent, cfdata_t cf, void *aux) 349rk3328_cru_match(device_t parent, cfdata_t cf, void *aux)
335{ 350{
336 struct fdt_attach_args * const faa = aux; 351 struct fdt_attach_args * const faa = aux;
337 352
338 return of_match_compatible(faa->faa_phandle, compatible); 353 return of_match_compatible(faa->faa_phandle, compatible);
339} 354}
340 355
341static void 356static void
342rk3328_cru_attach(device_t parent, device_t self, void *aux) 357rk3328_cru_attach(device_t parent, device_t self, void *aux)
343{ 358{