 @@ -1,28 +1,28 @@
-/*	$NetBSD: fpu.h,v 1.11 2018/06/20 20:43:20 jdolecek Exp $	*/
+/*	$NetBSD: fpu.h,v 1.12 2018/06/22 06:22:37 maxv Exp $	*/
 #ifndef	_X86_FPU_H_
 #define	_X86_FPU_H_
 #include <x86/cpu_extended_state.h>
 #ifdef _KERNEL
 struct cpu_info;
 struct lwp;
 struct trapframe;
 void fpuinit(struct cpu_info *);
-void fpuinit_mxcsr_mask(bool);
+void fpuinit_mxcsr_mask(void);
 void fpusave_lwp(struct lwp *, bool);
 void fpusave_cpu(bool);
 void fpu_eagerswitch(struct lwp *, struct lwp *);
 void fpu_set_default_cw(struct lwp *, unsigned int);
 void fputrap(struct trapframe *);
 void fpudna(struct trapframe *);
 /* Set all to defaults (eg during exec) */
 void fpu_save_area_clear(struct lwp *, unsigned int);
 /* Reset control words only - for signal handlers */

 @@ -1,14 +1,14 @@
-/*	$NetBSD: cpu.c,v 1.157 2018/06/20 20:43:21 jdolecek Exp $	*/
+/*	$NetBSD: cpu.c,v 1.158 2018/06/22 06:22:37 maxv Exp $	*/
 /*
  * Copyright (c) 2000-2012 NetBSD Foundation, Inc.
  * All rights reserved.
+ *
  * This code is derived from software contributed to The NetBSD Foundation
  * by Bill Sommerfeld of RedBack Networks Inc, and by Andrew Doran.
+ *
  * Redistribution and use in source and binary forms, with or without
  * modification, are permitted provided that the following conditions
  * are met:
  * 1. Redistributions of source code must retain the above copyright
  *    notice, this list of conditions and the following disclaimer.
 @@ -52,27 +52,27 @@
  * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
  * ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR AND CONTRIBUTORS BE LIABLE
  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
  * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
  * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
  * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
  * SUCH DAMAGE.
  */
 #include <sys/cdefs.h>
-__KERNEL_RCSID(0, "$NetBSD: cpu.c,v 1.157 2018/06/20 20:43:21 jdolecek Exp $");
+__KERNEL_RCSID(0, "$NetBSD: cpu.c,v 1.158 2018/06/22 06:22:37 maxv Exp $");
 #include "opt_ddb.h"
 #include "opt_mpbios.h"		/* for MPDEBUG */
 #include "opt_mtrr.h"
 #include "opt_multiprocessor.h"
 #include "opt_svs.h"
 #include "lapic.h"
 #include "ioapic.h"
 #include <sys/param.h>
 #include <sys/proc.h>
 #include <sys/systm.h>
 @@ -628,27 +628,27 @@ cpu_init(struct cpu_info *ci)
 	 * Changing CR4 register may change cpuid values. For example, setting
 	 * CR4_OSXSAVE sets CPUID2_OSXSAVE. The CPUID2_OSXSAVE is in
 	 * ci_feat_val[1], so update it.
 	 * XXX Other than ci_feat_val[1] might be changed.
 	 */
 	if (cpuid_level >= 1) {
 		u_int descs[4];
 		x86_cpuid(1, descs);
 		ci->ci_feat_val[1] = descs[2];
+	}
 	if (x86_fpu_save >= FPU_SAVE_FXSAVE) {
-		fpuinit_mxcsr_mask(true);
+		fpuinit_mxcsr_mask();
+	}
 	/* If xsave is enabled, enable all fpu features */
 	if (cr4 & CR4_OSXSAVE)
 		wrxcr(0, x86_xsave_features & XCR0_FPU);
 #ifdef MTRR
 	/*
 	 * On a P6 or above, initialize MTRR's if the hardware supports them.
 	 */
 	if (cpu_feature[0] & CPUID_MTRR) {
 		if ((ci->ci_flags & CPUF_AP) == 0)
 			i686_mtrr_init_first();

 @@ -1,14 +1,14 @@
-/*	$NetBSD: fpu.c,v 1.41 2018/06/20 20:43:21 jdolecek Exp $	*/
+/*	$NetBSD: fpu.c,v 1.42 2018/06/22 06:22:37 maxv Exp $	*/
 /*
  * Copyright (c) 2008 The NetBSD Foundation, Inc.  All
  * rights reserved.
+ *
  * This code is derived from software developed for The NetBSD Foundation
  * by Andrew Doran.
+ *
  * Redistribution and use in source and binary forms, with or without
  * modification, are permitted provided that the following conditions
  * are met:
  * 1. Redistributions of source code must retain the above copyright
  *    notice, this list of conditions and the following disclaimer.
 @@ -86,27 +86,27 @@
  * ARE DISCLAIMED.  IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
  * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
  * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
  * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
  * SUCH DAMAGE.
+ *
  *	@(#)npx.c	7.2 (Berkeley) 5/12/91
  */
 #include <sys/cdefs.h>
-__KERNEL_RCSID(0, "$NetBSD: fpu.c,v 1.41 2018/06/20 20:43:21 jdolecek Exp $");
+__KERNEL_RCSID(0, "$NetBSD: fpu.c,v 1.42 2018/06/22 06:22:37 maxv Exp $");
 #include "opt_multiprocessor.h"
 #include <sys/param.h>
 #include <sys/systm.h>
 #include <sys/conf.h>
 #include <sys/cpu.h>
 #include <sys/file.h>
 #include <sys/proc.h>
 #include <sys/kernel.h>
 #include <sys/sysctl.h>
 #include <sys/xcall.h>
 @@ -227,56 +227,54 @@ static const uint8_t fpetable[128] = {
 void
 fpuinit(struct cpu_info *ci)
+{
 	clts();
 	fninit();
 	stts();
+}
 /*
  * Get the value of MXCSR_MASK supported by the CPU.
  */
 void
-fpuinit_mxcsr_mask(bool has_fxsave)
+fpuinit_mxcsr_mask(void)
+{
 #ifndef XEN
 	if (!has_fxsave) {
 		x86_fpu_mxcsr_mask = __INITIAL_MXCSR_MASK__;
 		return;
 	union savefpu fpusave __aligned(16);
 	u_long psl;
 	memset(&fpusave, 0, sizeof(fpusave));
 	/* Disable interrupts, and enable FPU */
 	psl = x86_read_psl();
 	x86_disable_intr();
 	clts();
 	/* Fill in the FPU area */
 	fxsave(&fpusave);
 	/* Restore previous state */
 	stts();
 	x86_write_psl(psl);
 	if (fpusave.sv_xmm.fx_mxcsr_mask == 0) {
 		x86_fpu_mxcsr_mask = __INITIAL_MXCSR_MASK__;
 	} else {
 		x86_fpu_mxcsr_mask = fpusave.sv_xmm.fx_mxcsr_mask;
+	}
 #else
 	x86_fpu_mxcsr_mask = __INITIAL_MXCSR_MASK__;
 #endif
+}
 static void
 fpu_clear_amd(void)
+{
 	/*
 	 * AMD FPUs do not restore FIP, FDP, and FOP on fxrstor and xrstor
 	 * when FSW.ES=0, leaking other threads' execution history.
+	 *
 	 * Clear them manually by loading a zero (fldummy). We do this
 	 * unconditionally, regardless of FSW.ES.
+	 *
 	 * Before that, clear the ES bit in the x87 status word if it is

 @@ -1,14 +1,14 @@
-/*	$NetBSD: cpu.c,v 1.119 2018/06/20 20:43:20 jdolecek Exp $	*/
+/*	$NetBSD: cpu.c,v 1.120 2018/06/22 06:22:37 maxv Exp $	*/
 /*-
  * Copyright (c) 2000 The NetBSD Foundation, Inc.
  * Copyright (c) 2002, 2006, 2007 YAMAMOTO Takashi,
  * All rights reserved.
+ *
  * This code is derived from software contributed to The NetBSD Foundation
  * by RedBack Networks Inc.
+ *
  * Author: Bill Sommerfeld
+ *
  * Redistribution and use in source and binary forms, with or without
  * modification, are permitted provided that the following conditions
 @@ -55,27 +55,27 @@
  * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
  * ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR AND CONTRIBUTORS BE LIABLE
  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
  * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
  * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
  * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
  * SUCH DAMAGE.
  */
 #include <sys/cdefs.h>
-__KERNEL_RCSID(0, "$NetBSD: cpu.c,v 1.119 2018/06/20 20:43:20 jdolecek Exp $");
+__KERNEL_RCSID(0, "$NetBSD: cpu.c,v 1.120 2018/06/22 06:22:37 maxv Exp $");
 #include "opt_ddb.h"
 #include "opt_multiprocessor.h"
 #include "opt_mpbios.h"		/* for MPDEBUG */
 #include "opt_mtrr.h"
 #include "opt_xen.h"
 #include "lapic.h"
 #include "ioapic.h"
 #include <sys/param.h>
 #include <sys/proc.h>
 #include <sys/systm.h>
 @@ -554,28 +554,27 @@ cpu_init(struct cpu_info *ci)
 	if (cpu_feature[1] & CPUID2_OSXSAVE)
 		cr4 |= CR4_OSXSAVE;
 	else {
 		x86_xsave_features = 0;
 		x86_fpu_save = FPU_SAVE_FXSAVE;
+	}
 	if (cr4) {
 		cr4 |= rcr4();
 		lcr4(cr4);
+	}
 	if (x86_fpu_save >= FPU_SAVE_FXSAVE) {
-		/* XXX fxsave() faults on Xen with no-xsave flag, why? */
+		fpuinit_mxcsr_mask();
 		fpuinit_mxcsr_mask((cr4 & CR4_OSXSAVE) != 0);
+	}
 	/*
 	 * Changing CR4 register may change cpuid values. For example, setting
 	 * CR4_OSXSAVE sets CPUID2_OSXSAVE. The CPUID2_OSXSAVE is in
 	 * ci_feat_val[1], so update it.
 	 * XXX Other than ci_feat_val[1] might be changed.
 	 */
 	if (cpuid_level >= 1) {
 		u_int descs[4];
 		x86_cpuid(1, descs);
 		ci->ci_feat_val[1] = descs[2];