Fri Aug 24 19:06:30 2018 UTC ()
set correctly TCR_EL1 for inner shareable when MULTIPROCESSOR


(ryo)
diff -r1.18 -r1.19 src/sys/arch/aarch64/aarch64/locore.S
cvs diff -r1.18 -r1.19 src/sys/arch/aarch64/aarch64/locore.S (expand / switch to unified diff)

--- src/sys/arch/aarch64/aarch64/locore.S 2018/08/10 21:06:42 1.18
+++ src/sys/arch/aarch64/aarch64/locore.S 2018/08/24 19:06:30 1.19
@@ -1,14 +1,14 @@ @@ -1,14 +1,14 @@
1/* $NetBSD: locore.S,v 1.18 2018/08/10 21:06:42 ryo Exp $ */ 1/* $NetBSD: locore.S,v 1.19 2018/08/24 19:06:30 ryo Exp $ */
2 2
3/* 3/*
4 * Copyright (c) 2017 Ryo Shimizu <ryo@nerv.org> 4 * Copyright (c) 2017 Ryo Shimizu <ryo@nerv.org>
5 * All rights reserved. 5 * All rights reserved.
6 * 6 *
7 * Redistribution and use in source and binary forms, with or without 7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions 8 * modification, are permitted provided that the following conditions
9 * are met: 9 * are met:
10 * 1. Redistributions of source code must retain the above copyright 10 * 1. Redistributions of source code must retain the above copyright
11 * notice, this list of conditions and the following disclaimer. 11 * notice, this list of conditions and the following disclaimer.
12 * 2. Redistributions in binary form must reproduce the above copyright 12 * 2. Redistributions in binary form must reproduce the above copyright
13 * notice, this list of conditions and the following disclaimer in the 13 * notice, this list of conditions and the following disclaimer in the
14 * documentation and/or other materials provided with the distribution. 14 * documentation and/or other materials provided with the distribution.
@@ -25,27 +25,27 @@ @@ -25,27 +25,27 @@
25 * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 25 * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
26 * POSSIBILITY OF SUCH DAMAGE. 26 * POSSIBILITY OF SUCH DAMAGE.
27 */ 27 */
28 28
29#include "opt_cpuoptions.h" 29#include "opt_cpuoptions.h"
30#include "opt_multiprocessor.h" 30#include "opt_multiprocessor.h"
31#include "opt_ddb.h" 31#include "opt_ddb.h"
32#include "opt_arm_debug.h" 32#include "opt_arm_debug.h"
33 33
34#include <aarch64/asm.h> 34#include <aarch64/asm.h>
35#include <aarch64/hypervisor.h> 35#include <aarch64/hypervisor.h>
36#include "assym.h" 36#include "assym.h"
37 37
38RCSID("$NetBSD: locore.S,v 1.18 2018/08/10 21:06:42 ryo Exp $") 38RCSID("$NetBSD: locore.S,v 1.19 2018/08/24 19:06:30 ryo Exp $")
39 39
40/* #define DEBUG_LOCORE */ 40/* #define DEBUG_LOCORE */
41/* #define DEBUG_MMU */ 41/* #define DEBUG_MMU */
42 42
43#if (defined(VERBOSE_INIT_ARM) || defined(DEBUG_LOCORE)) && defined(EARLYCONS) 43#if (defined(VERBOSE_INIT_ARM) || defined(DEBUG_LOCORE)) && defined(EARLYCONS)
44#define VERBOSE_LOCORE 44#define VERBOSE_LOCORE
45#endif 45#endif
46 46
47#define LOCORE_EL2 47#define LOCORE_EL2
48 48
49/* attributes are defined in MAIR_EL1 */ 49/* attributes are defined in MAIR_EL1 */
50#define L2_BLKPAG_ATTR_NORMAL_WB LX_BLKPAG_ATTR_INDX_0 50#define L2_BLKPAG_ATTR_NORMAL_WB LX_BLKPAG_ATTR_INDX_0
51#define L2_BLKPAG_ATTR_NORMAL_NC LX_BLKPAG_ATTR_INDX_1 51#define L2_BLKPAG_ATTR_NORMAL_NC LX_BLKPAG_ATTR_INDX_1
@@ -907,47 +907,47 @@ mmu_enable: @@ -907,47 +907,47 @@ mmu_enable:
907 tlbi vmalle1 907 tlbi vmalle1
908#endif 908#endif
909 dsb ish 909 dsb ish
910 isb 910 isb
911 911
912 ldr x0, mair_setting 912 ldr x0, mair_setting
913 msr mair_el1, x0 913 msr mair_el1, x0
914 914
915 915
916 /* TCR_EL1:IPS[34:32] = AA64MMFR0:PARange[3:0] */ 916 /* TCR_EL1:IPS[34:32] = AA64MMFR0:PARange[3:0] */
917 ldr x0, tcr_setting 917 ldr x0, tcr_setting
918 mrs x1, id_aa64mmfr0_el1 918 mrs x1, id_aa64mmfr0_el1
919 bfi x0, x1, #32, #3 919 bfi x0, x1, #32, #3
 920#ifdef MULTIPROCESSOR
 921 ldr x1, tcr_setting_inner_shareable
 922 orr x0, x0, x1
 923#endif
920 msr tcr_el1, x0 924 msr tcr_el1, x0
921 925
922 /* 926 /*
923 * configure SCTLR 927 * configure SCTLR
924 */ 928 */
925 mrs x0, sctlr_el1 929 mrs x0, sctlr_el1
926 ldr x1, sctlr_clear 930 ldr x1, sctlr_clear
927 bic x0, x0, x1 931 bic x0, x0, x1
928 ldr x1, sctlr_set 932 ldr x1, sctlr_set
929 orr x0, x0, x1 933 orr x0, x0, x1
930 934
931 ldr x1, sctlr_ee 935 ldr x1, sctlr_ee
932#ifdef __AARCH64EB__ 936#ifdef __AARCH64EB__
933 orr x0, x0, x1 /* set: BigEndian */ 937 orr x0, x0, x1 /* set: BigEndian */
934#else 938#else
935 bic x0, x0, x1 /* clear: LittleEndian */ 939 bic x0, x0, x1 /* clear: LittleEndian */
936#endif 940#endif
937#ifdef MULTIPROCESSOR 
938 ldr x1, tcr_setting_inner_shareable 
939 orr x0, x0, x1 
940#endif 
941 msr sctlr_el1, x0 /* enabling MMU! */ 941 msr sctlr_el1, x0 /* enabling MMU! */
942 isb 942 isb
943 943
944 ret 944 ret
945 945
946 .align 3 946 .align 3
947mair_setting: 947mair_setting:
948 .quad ( \ 948 .quad ( \
949 __SHIFTIN(MAIR_NORMAL_WB, MAIR_ATTR0) | \ 949 __SHIFTIN(MAIR_NORMAL_WB, MAIR_ATTR0) | \
950 __SHIFTIN(MAIR_NORMAL_NC, MAIR_ATTR1) | \ 950 __SHIFTIN(MAIR_NORMAL_NC, MAIR_ATTR1) | \
951 __SHIFTIN(MAIR_NORMAL_WT, MAIR_ATTR2) | \ 951 __SHIFTIN(MAIR_NORMAL_WT, MAIR_ATTR2) | \
952 __SHIFTIN(MAIR_DEVICE_nGnRnE, MAIR_ATTR3)) 952 __SHIFTIN(MAIR_DEVICE_nGnRnE, MAIR_ATTR3))
953 953