 @@ -1,3847 +1,3857 @@
-/*	$NetBSD: i915_gem_gtt.c,v 1.5 2018/08/27 04:58:23 riastradh Exp $	*/
+/*	$NetBSD: i915_gem_gtt.c,v 1.6 2018/08/27 06:08:25 riastradh Exp $	*/
 /*
  * Copyright © 2010 Daniel Vetter
  * Copyright © 2011-2014 Intel Corporation
+ *
  * Permission is hereby granted, free of charge, to any person obtaining a
  * copy of this software and associated documentation files (the "Software"),
  * to deal in the Software without restriction, including without limitation
  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
  * and/or sell copies of the Software, and to permit persons to whom the
  * Software is furnished to do so, subject to the following conditions:
+ *
  * The above copyright notice and this permission notice (including the next
  * paragraph) shall be included in all copies or substantial portions of the
  * Software.
+ *
  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
  * IN THE SOFTWARE.
+ *
  */
 #include <sys/cdefs.h>
-__KERNEL_RCSID(0, "$NetBSD: i915_gem_gtt.c,v 1.5 2018/08/27 04:58:23 riastradh Exp $");
+__KERNEL_RCSID(0, "$NetBSD: i915_gem_gtt.c,v 1.6 2018/08/27 06:08:25 riastradh Exp $");
 #include <linux/err.h>
 #include <linux/seq_file.h>
 #include <drm/drmP.h>
 #include <drm/i915_drm.h>
 #include "i915_drv.h"
 #include "i915_vgpu.h"
 #include "i915_trace.h"
 #include "intel_drv.h"
 #ifdef __NetBSD__
 #include <x86/machdep.h>
 #include <x86/pte.h>
 #define	_PAGE_PRESENT	PG_V	/* 0x01 PTE is present / valid */
 #define	_PAGE_RW	PG_RW	/* 0x02 read/write */
 #define	_PAGE_PWT	PG_WT	/* 0x08 write-through */
 #define	_PAGE_PCD	PG_N	/* 0x10 page cache disabled / non-cacheable */
 #define	_PAGE_PAT	PG_PAT	/* 0x80 page attribute table on PTE */
 #endif
 /**
  * DOC: Global GTT views
+ *
  * Background and previous state
+ *
  * Historically objects could exists (be bound) in global GTT space only as
  * singular instances with a view representing all of the object's backing pages
  * in a linear fashion. This view will be called a normal view.
+ *
  * To support multiple views of the same object, where the number of mapped
  * pages is not equal to the backing store, or where the layout of the pages
  * is not linear, concept of a GGTT view was added.
+ *
  * One example of an alternative view is a stereo display driven by a single
  * image. In this case we would have a framebuffer looking like this
  * (2x2 pages):
+ *
  *    12
  *    34
+ *
  * Above would represent a normal GGTT view as normally mapped for GPU or CPU
  * rendering. In contrast, fed to the display engine would be an alternative
  * view which could look something like this:
+ *
  *   1212
  *   3434
+ *
  * In this example both the size and layout of pages in the alternative view is
  * different from the normal view.
+ *
  * Implementation and usage
+ *
  * GGTT views are implemented using VMAs and are distinguished via enum
  * i915_ggtt_view_type and struct i915_ggtt_view.
+ *
  * A new flavour of core GEM functions which work with GGTT bound objects were
  * added with the _ggtt_ infix, and sometimes with _view postfix to avoid
  * renaming  in large amounts of code. They take the struct i915_ggtt_view
  * parameter encapsulating all metadata required to implement a view.
+ *
  * As a helper for callers which are only interested in the normal view,
  * globally const i915_ggtt_view_normal singleton instance exists. All old core
  * GEM API functions, the ones not taking the view parameter, are operating on,
  * or with the normal GGTT view.
+ *
  * Code wanting to add or use a new GGTT view needs to:
+ *
  * 1. Add a new enum with a suitable name.
  * 2. Extend the metadata in the i915_ggtt_view structure if required.
  * 3. Add support to i915_get_vma_pages().
+ *
  * New views are required to build a scatter-gather table from within the
  * i915_get_vma_pages function. This table is stored in the vma.ggtt_view and
  * exists for the lifetime of an VMA.
+ *
  * Core API is designed to have copy semantics which means that passed in
  * struct i915_ggtt_view does not need to be persistent (left around after
  * calling the core API functions).
+ *
  */
 static int
 i915_get_ggtt_vma_pages(struct i915_vma *vma);
 const struct i915_ggtt_view i915_ggtt_view_normal;
 const struct i915_ggtt_view i915_ggtt_view_rotated = {
         .type = I915_GGTT_VIEW_ROTATED
 };
 static int sanitize_enable_ppgtt(struct drm_device *dev, int enable_ppgtt)
+{
 	bool has_aliasing_ppgtt;
 	bool has_full_ppgtt;
 	has_aliasing_ppgtt = INTEL_INFO(dev)->gen >= 6;
 	has_full_ppgtt = INTEL_INFO(dev)->gen >= 7;
 	if (intel_vgpu_active(dev))
 		has_full_ppgtt = false; /* emulation is too hard */
 	/*
 	 * We don't allow disabling PPGTT for gen9+ as it's a requirement for
 	 * execlists, the sole mechanism available to submit work.
 	 */
 	if (INTEL_INFO(dev)->gen < 9 &&
 	    (enable_ppgtt == 0 || !has_aliasing_ppgtt))
 		return 0;
 	if (enable_ppgtt == 1)
 		return 1;
 	if (enable_ppgtt == 2 && has_full_ppgtt)
 		return 2;
 #ifdef CONFIG_INTEL_IOMMU
 	/* Disable ppgtt on SNB if VT-d is on. */
 	if (INTEL_INFO(dev)->gen == 6 && intel_iommu_gfx_mapped) {
 		DRM_INFO("Disabling PPGTT because VT-d is on\n");
 		return 0;
+	}
 #endif
 	/* Early VLV doesn't have this */
 	if (IS_VALLEYVIEW(dev) && !IS_CHERRYVIEW(dev) &&
 	    dev->pdev->revision < 0xb) {
 		DRM_DEBUG_DRIVER("disabling PPGTT on pre-B3 step VLV\n");
 		return 0;
+	}
 	if (INTEL_INFO(dev)->gen >= 8 && i915.enable_execlists)
 		return 2;
 	else
 		return has_aliasing_ppgtt ? 1 : 0;
+}
 static int ppgtt_bind_vma(struct i915_vma *vma,
 			  enum i915_cache_level cache_level,
 			  u32 unused)
+{
 	u32 pte_flags = 0;
 	/* Currently applicable only to VLV */
 	if (vma->obj->gt_ro)
 		pte_flags |= PTE_READ_ONLY;
 	vma->vm->insert_entries(vma->vm, vma->obj->pages, vma->node.start,
 				cache_level, pte_flags);
 	return 0;
+}
 static void ppgtt_unbind_vma(struct i915_vma *vma)
+{
 	vma->vm->clear_range(vma->vm,
 			     vma->node.start,
 			     vma->obj->base.size,
 			     true);
+}
 static gen8_pte_t gen8_pte_encode(dma_addr_t addr,
 				  enum i915_cache_level level,
 				  bool valid)
+{
 	gen8_pte_t pte = valid ? _PAGE_PRESENT | _PAGE_RW : 0;
 	pte |= addr;
 	switch (level) {
 	case I915_CACHE_NONE:
 		pte |= PPAT_UNCACHED_INDEX;
 		break;
 	case I915_CACHE_WT:
 		pte |= PPAT_DISPLAY_ELLC_INDEX;
 		break;
 	default:
 		pte |= PPAT_CACHED_INDEX;
 		break;
+	}
 	return pte;
+}
 static gen8_pde_t gen8_pde_encode(const dma_addr_t addr,
 				  const enum i915_cache_level level)
+{
 	gen8_pde_t pde = _PAGE_PRESENT | _PAGE_RW;
 	pde |= addr;
 	if (level != I915_CACHE_NONE)
 		pde |= PPAT_CACHED_PDE_INDEX;
 	else
 		pde |= PPAT_UNCACHED_INDEX;
 	return pde;
+}
 #define gen8_pdpe_encode gen8_pde_encode
 #define gen8_pml4e_encode gen8_pde_encode
 static gen6_pte_t snb_pte_encode(dma_addr_t addr,
 				 enum i915_cache_level level,
 				 bool valid, u32 unused)
+{
 	gen6_pte_t pte = valid ? GEN6_PTE_VALID : 0;
 	pte |= GEN6_PTE_ADDR_ENCODE(addr);
 	switch (level) {
 	case I915_CACHE_L3_LLC:
 	case I915_CACHE_LLC:
 		pte |= GEN6_PTE_CACHE_LLC;
 		break;
 	case I915_CACHE_NONE:
 		pte |= GEN6_PTE_UNCACHED;
 		break;
 	default:
 		MISSING_CASE(level);
+	}
 	return pte;
+}
 static gen6_pte_t ivb_pte_encode(dma_addr_t addr,
 				 enum i915_cache_level level,
 				 bool valid, u32 unused)
+{
 	gen6_pte_t pte = valid ? GEN6_PTE_VALID : 0;
 	pte |= GEN6_PTE_ADDR_ENCODE(addr);
 	switch (level) {
 	case I915_CACHE_L3_LLC:
 		pte |= GEN7_PTE_CACHE_L3_LLC;
 		break;
 	case I915_CACHE_LLC:
 		pte |= GEN6_PTE_CACHE_LLC;
 		break;
 	case I915_CACHE_NONE:
 		pte |= GEN6_PTE_UNCACHED;
 		break;
 	default:
 		MISSING_CASE(level);
+	}
 	return pte;
+}
 static gen6_pte_t byt_pte_encode(dma_addr_t addr,
 				 enum i915_cache_level level,
 				 bool valid, u32 flags)
+{
 	gen6_pte_t pte = valid ? GEN6_PTE_VALID : 0;
 	pte |= GEN6_PTE_ADDR_ENCODE(addr);
 	if (!(flags & PTE_READ_ONLY))
 		pte |= BYT_PTE_WRITEABLE;
 	if (level != I915_CACHE_NONE)
 		pte |= BYT_PTE_SNOOPED_BY_CPU_CACHES;
 	return pte;
+}
 static gen6_pte_t hsw_pte_encode(dma_addr_t addr,
 				 enum i915_cache_level level,
 				 bool valid, u32 unused)
+{
 	gen6_pte_t pte = valid ? GEN6_PTE_VALID : 0;
 	pte |= HSW_PTE_ADDR_ENCODE(addr);
 	if (level != I915_CACHE_NONE)
 		pte |= HSW_WB_LLC_AGE3;
 	return pte;
+}
 static gen6_pte_t iris_pte_encode(dma_addr_t addr,
 				  enum i915_cache_level level,
 				  bool valid, u32 unused)
+{
 	gen6_pte_t pte = valid ? GEN6_PTE_VALID : 0;
 	pte |= HSW_PTE_ADDR_ENCODE(addr);
 	switch (level) {
 	case I915_CACHE_NONE:
 		break;
 	case I915_CACHE_WT:
 		pte |= HSW_WT_ELLC_LLC_AGE3;
 		break;
 	default:
 		pte |= HSW_WB_ELLC_LLC_AGE3;
 		break;
+	}
 	return pte;
+}
 static int __setup_page_dma(struct drm_device *dev,
 			    struct i915_page_dma *p, gfp_t flags)
+{
 #ifdef __NetBSD__
 	int error;
 	int nseg = 1;
 	error = bus_dmamem_alloc(dev->dmat, PAGE_SIZE, PAGE_SIZE, PAGE_SIZE,
 	    &p->seg, nseg, &nseg, BUS_DMA_WAITOK);
 	if (error)
 fail0:		return -error;	/* XXX errno NetBSD->Linux */
 	KASSERT(nseg == 1);
 	error = bus_dmamap_create(dev->dmat, PAGE_SIZE, 1, PAGE_SIZE,
 	    PAGE_SIZE, BUS_DMA_WAITOK, &p->map);
 	if (error) {
 fail1:		bus_dmamem_free(dev->dmat, &p->seg, 1);
 		goto fail0;
+	}
 	error = bus_dmamap_load_raw(dev->dmat, p->map, &p->seg, 1, PAGE_SIZE,
 	    BUS_DMA_WAITOK);
 	if (error) {
 fail2: __unused
 		bus_dmamap_destroy(dev->dmat, p->map);
 		goto fail1;
+	}
 #else
 	struct device *device = &dev->pdev->dev;
 	p->page = alloc_page(flags);
 	if (!p->page)
 		return -ENOMEM;
 	p->daddr = dma_map_page(device,
 				p->page, 0, 4096, PCI_DMA_BIDIRECTIONAL);
 	if (dma_mapping_error(device, p->daddr)) {
 		__free_page(p->page);
 		return -EINVAL;
+	}
 #endif
 	return 0;
+}
 static int setup_page_dma(struct drm_device *dev, struct i915_page_dma *p)
+{
 	return __setup_page_dma(dev, p, GFP_KERNEL);
+}
 static void cleanup_page_dma(struct drm_device *dev, struct i915_page_dma *p)
+{
 #ifdef __NetBSD__
 	if (WARN_ON(!p->map))
 		return;
 	bus_dmamap_unload(dev->dmat, p->map);
 	bus_dmamap_destroy(dev->dmat, p->dmap);
 	bus_dmamem_free(dev->dmat, &p->seg, 1);
 #else
 	if (WARN_ON(!p->page))
 		return;
 	dma_unmap_page(&dev->pdev->dev, p->daddr, 4096, PCI_DMA_BIDIRECTIONAL);
 	__free_page(p->page);
 	memset(p, 0, sizeof(*p));
 #endif
+}
 static void *kmap_page_dma(struct i915_page_dma *p)
+{
 #ifdef __NetBSD__
 	return kmap_atomic(PHYS_TO_VM_PAGE(p->seg.ds_addr));
 #else
 	return kmap_atomic(p->page);
 #endif
+}
 /* We use the flushing unmap only with ppgtt structures:
  * page directories, page tables and scratch pages.
  */
 static void kunmap_page_dma(struct drm_device *dev, void *vaddr)
+{
 	/* There are only few exceptions for gen >=6. chv and bxt.
 	 * And we are not sure about the latter so play safe for now.
 	 */
 	if (IS_CHERRYVIEW(dev) || IS_BROXTON(dev))
 		drm_clflush_virt_range(vaddr, PAGE_SIZE);
 	kunmap_atomic(vaddr);
+}
 #define kmap_px(px) kmap_page_dma(px_base(px))
 #define kunmap_px(ppgtt, vaddr) kunmap_page_dma((ppgtt)->base.dev, (vaddr))
 #define setup_px(dev, px) setup_page_dma((dev), px_base(px))
 #define cleanup_px(dev, px) cleanup_page_dma((dev), px_base(px))
 #define fill_px(dev, px, v) fill_page_dma((dev), px_base(px), (v))
 #define fill32_px(dev, px, v) fill_page_dma_32((dev), px_base(px), (v))
 static void fill_page_dma(struct drm_device *dev, struct i915_page_dma *p,
 			  const uint64_t val)
+{
 	int i;
 	uint64_t * const vaddr = kmap_page_dma(p);
 	for (i = 0; i < 512; i++)
 		vaddr[i] = val;
 	kunmap_page_dma(dev, vaddr);
+}
 static void fill_page_dma_32(struct drm_device *dev, struct i915_page_dma *p,
 			     const uint32_t val32)
+{
 	uint64_t v = val32;
 	v = v << 32 | val32;
 	fill_page_dma(dev, p, v);
+}
 static struct i915_page_scratch *alloc_scratch_page(struct drm_device *dev)
+{
 	struct i915_page_scratch *sp;
 	int ret;
 	sp = kzalloc(sizeof(*sp), GFP_KERNEL);
 	if (sp == NULL)
 		return ERR_PTR(-ENOMEM);
 	ret = __setup_page_dma(dev, px_base(sp), GFP_DMA32 | __GFP_ZERO);
 	if (ret) {
 		kfree(sp);
 		return ERR_PTR(ret);
+	}
 	set_pages_uc(px_page(sp), 1);
 	return sp;
+}
 static void free_scratch_page(struct drm_device *dev,
 			      struct i915_page_scratch *sp)
+{
 	set_pages_wb(px_page(sp), 1);
 	cleanup_px(dev, sp);
 	kfree(sp);
+}
 static struct i915_page_table *alloc_pt(struct drm_device *dev)
+{
 	struct i915_page_table *pt;
 	const size_t count = INTEL_INFO(dev)->gen >= 8 ?
 		GEN8_PTES : GEN6_PTES;
 	int ret = -ENOMEM;
 	pt = kzalloc(sizeof(*pt), GFP_KERNEL);
 	if (!pt)
 		return ERR_PTR(-ENOMEM);
 	pt->used_ptes = kcalloc(BITS_TO_LONGS(count), sizeof(*pt->used_ptes),
 				GFP_KERNEL);
 	if (!pt->used_ptes)
 		goto fail_bitmap;
 	ret = setup_px(dev, pt);
 	if (ret)
 		goto fail_page_m;
 	return pt;
 fail_page_m:
 	kfree(pt->used_ptes);
 fail_bitmap:
 	kfree(pt);
 	return ERR_PTR(ret);
+}
 static void free_pt(struct drm_device *dev, struct i915_page_table *pt)
+{
 	cleanup_px(dev, pt);
 	kfree(pt->used_ptes);
 	kfree(pt);
+}
 static void gen8_initialize_pt(struct i915_address_space *vm,
 			       struct i915_page_table *pt)
+{
 	gen8_pte_t scratch_pte;
 	scratch_pte = gen8_pte_encode(px_dma(vm->scratch_page),
 				      I915_CACHE_LLC, true);
 	fill_px(vm->dev, pt, scratch_pte);
+}
 static void gen6_initialize_pt(struct i915_address_space *vm,
 			       struct i915_page_table *pt)
+{
 	gen6_pte_t scratch_pte;
 	WARN_ON(px_dma(vm->scratch_page) == 0);
 	scratch_pte = vm->pte_encode(px_dma(vm->scratch_page),
 				     I915_CACHE_LLC, true, 0);
 	fill32_px(vm->dev, pt, scratch_pte);
+}
 static struct i915_page_directory *alloc_pd(struct drm_device *dev)
+{
 	struct i915_page_directory *pd;
 	int ret = -ENOMEM;
 	pd = kzalloc(sizeof(*pd), GFP_KERNEL);
 	if (!pd)
 		return ERR_PTR(-ENOMEM);
 	pd->used_pdes = kcalloc(BITS_TO_LONGS(I915_PDES),
 				sizeof(*pd->used_pdes), GFP_KERNEL);
 	if (!pd->used_pdes)
 		goto fail_bitmap;
 	ret = setup_px(dev, pd);
 	if (ret)
 		goto fail_page_m;
 	return pd;
 fail_page_m:
 	kfree(pd->used_pdes);
 fail_bitmap:
 	kfree(pd);
 	return ERR_PTR(ret);
+}
 static void free_pd(struct drm_device *dev, struct i915_page_directory *pd)
+{
 	if (px_page(pd)) {
 		cleanup_px(dev, pd);
 		kfree(pd->used_pdes);
 		kfree(pd);
+	}
+}
 static void gen8_initialize_pd(struct i915_address_space *vm,
 			       struct i915_page_directory *pd)
+{
 	gen8_pde_t scratch_pde;
 	scratch_pde = gen8_pde_encode(px_dma(vm->scratch_pt), I915_CACHE_LLC);
 	fill_px(vm->dev, pd, scratch_pde);
+}
 static int __pdp_init(struct drm_device *dev,
 		      struct i915_page_directory_pointer *pdp)
+{
 	size_t pdpes = I915_PDPES_PER_PDP(dev);
 	pdp->used_pdpes = kcalloc(BITS_TO_LONGS(pdpes),
 				  sizeof(unsigned long),
 				  GFP_KERNEL);
 	if (!pdp->used_pdpes)
 		return -ENOMEM;
 	pdp->page_directory = kcalloc(pdpes, sizeof(*pdp->page_directory),
 				      GFP_KERNEL);
 	if (!pdp->page_directory) {
 		kfree(pdp->used_pdpes);
 		/* the PDP might be the statically allocated top level. Keep it
 		 * as clean as possible */
 		pdp->used_pdpes = NULL;
 		return -ENOMEM;
+	}
 	return 0;
+}
 static void __pdp_fini(struct i915_page_directory_pointer *pdp)
+{
 	kfree(pdp->used_pdpes);
 	kfree(pdp->page_directory);
 	pdp->page_directory = NULL;
+}
 static struct
 i915_page_directory_pointer *alloc_pdp(struct drm_device *dev)
+{
 	struct i915_page_directory_pointer *pdp;
 	int ret = -ENOMEM;
 	WARN_ON(!USES_FULL_48BIT_PPGTT(dev));
 	pdp = kzalloc(sizeof(*pdp), GFP_KERNEL);
 	if (!pdp)
 		return ERR_PTR(-ENOMEM);
 	ret = __pdp_init(dev, pdp);
 	if (ret)
 		goto fail_bitmap;
 	ret = setup_px(dev, pdp);
 	if (ret)
 		goto fail_page_m;
 	return pdp;
 fail_page_m:
 	__pdp_fini(pdp);
 fail_bitmap:
 	kfree(pdp);
 	return ERR_PTR(ret);
+}
 static void free_pdp(struct drm_device *dev,
 		     struct i915_page_directory_pointer *pdp)
+{
 	__pdp_fini(pdp);
 	if (USES_FULL_48BIT_PPGTT(dev)) {
 		cleanup_px(dev, pdp);
 		kfree(pdp);
+	}
+}
 static void gen8_initialize_pdp(struct i915_address_space *vm,
 				struct i915_page_directory_pointer *pdp)
+{
 	gen8_ppgtt_pdpe_t scratch_pdpe;
 	scratch_pdpe = gen8_pdpe_encode(px_dma(vm->scratch_pd), I915_CACHE_LLC);
 	fill_px(vm->dev, pdp, scratch_pdpe);
+}
 static void gen8_initialize_pml4(struct i915_address_space *vm,
 				 struct i915_pml4 *pml4)
+{
 	gen8_ppgtt_pml4e_t scratch_pml4e;
 	scratch_pml4e = gen8_pml4e_encode(px_dma(vm->scratch_pdp),
 					  I915_CACHE_LLC);
 	fill_px(vm->dev, pml4, scratch_pml4e);
+}
 static void
 gen8_setup_page_directory(struct i915_hw_ppgtt *ppgtt,
 			  struct i915_page_directory_pointer *pdp,
 			  struct i915_page_directory *pd,
 			  int index)
+{
 	gen8_ppgtt_pdpe_t *page_directorypo;
 	if (!USES_FULL_48BIT_PPGTT(ppgtt->base.dev))
 		return;
 	page_directorypo = kmap_px(pdp);
 	page_directorypo[index] = gen8_pdpe_encode(px_dma(pd), I915_CACHE_LLC);
 	kunmap_px(ppgtt, page_directorypo);
+}
 static void
 gen8_setup_page_directory_pointer(struct i915_hw_ppgtt *ppgtt,
 				  struct i915_pml4 *pml4,
 				  struct i915_page_directory_pointer *pdp,
 				  int index)
+{
 	gen8_ppgtt_pml4e_t *pagemap = kmap_px(pml4);
 	WARN_ON(!USES_FULL_48BIT_PPGTT(ppgtt->base.dev));
 	pagemap[index] = gen8_pml4e_encode(px_dma(pdp), I915_CACHE_LLC);
 	kunmap_px(ppgtt, pagemap);
+}
 /* Broadwell Page Directory Pointer Descriptors */
 static int gen8_write_pdp(struct drm_i915_gem_request *req,
 			  unsigned entry,
 			  dma_addr_t addr)
+{
 	struct intel_engine_cs *ring = req->ring;
 	int ret;
 	BUG_ON(entry >= 4);
 	ret = intel_ring_begin(req, 6);
 	if (ret)
 		return ret;
 	intel_ring_emit(ring, MI_LOAD_REGISTER_IMM(1));
 	intel_ring_emit(ring, GEN8_RING_PDP_UDW(ring, entry));
 	intel_ring_emit(ring, upper_32_bits(addr));
 	intel_ring_emit(ring, MI_LOAD_REGISTER_IMM(1));
 	intel_ring_emit(ring, GEN8_RING_PDP_LDW(ring, entry));
 	intel_ring_emit(ring, lower_32_bits(addr));
 	intel_ring_advance(ring);
 	return 0;
+}
 static int gen8_legacy_mm_switch(struct i915_hw_ppgtt *ppgtt,
 				 struct drm_i915_gem_request *req)
+{
 	int i, ret;
 	for (i = GEN8_LEGACY_PDPES - 1; i >= 0; i--) {
 		const dma_addr_t pd_daddr = i915_page_dir_dma_addr(ppgtt, i);
 		ret = gen8_write_pdp(req, i, pd_daddr);
 		if (ret)
 			return ret;
+	}
 	return 0;
+}
 static int gen8_48b_mm_switch(struct i915_hw_ppgtt *ppgtt,
 			      struct drm_i915_gem_request *req)
+{
 	return gen8_write_pdp(req, 0, px_dma(&ppgtt->pml4));
+}
 static void gen8_ppgtt_clear_pte_range(struct i915_address_space *vm,
 				       struct i915_page_directory_pointer *pdp,
 				       uint64_t start,
 				       uint64_t length,
 				       gen8_pte_t scratch_pte)
+{
 	struct i915_hw_ppgtt *ppgtt =
 		container_of(vm, struct i915_hw_ppgtt, base);
 	gen8_pte_t *pt_vaddr;
 	unsigned pdpe = gen8_pdpe_index(start);
 	unsigned pde = gen8_pde_index(start);
 	unsigned pte = gen8_pte_index(start);
 	unsigned num_entries = length >> PAGE_SHIFT;
 	unsigned last_pte, i;
 	if (WARN_ON(!pdp))
 		return;
 	while (num_entries) {
 		struct i915_page_directory *pd;
 		struct i915_page_table *pt;
 		if (WARN_ON(!pdp->page_directory[pdpe]))
 			break;
 		pd = pdp->page_directory[pdpe];
 		if (WARN_ON(!pd->page_table[pde]))
 			break;
 		pt = pd->page_table[pde];
 		if (WARN_ON(!px_page(pt)))
 			break;
 		last_pte = pte + num_entries;
 		if (last_pte > GEN8_PTES)
 			last_pte = GEN8_PTES;
 		pt_vaddr = kmap_px(pt);
 		for (i = pte; i < last_pte; i++) {
 			pt_vaddr[i] = scratch_pte;
 			num_entries--;
+		}
 		kunmap_px(ppgtt, pt);
 		pte = 0;
 		if (++pde == I915_PDES) {
 			if (++pdpe == I915_PDPES_PER_PDP(vm->dev))
 				break;
 			pde = 0;
+		}
+	}
+}
 static void gen8_ppgtt_clear_range(struct i915_address_space *vm,
 				   uint64_t start,
 				   uint64_t length,
 				   bool use_scratch)
+{
 	struct i915_hw_ppgtt *ppgtt =
 		container_of(vm, struct i915_hw_ppgtt, base);
 	gen8_pte_t scratch_pte = gen8_pte_encode(px_dma(vm->scratch_page),
 						 I915_CACHE_LLC, use_scratch);
 	if (!USES_FULL_48BIT_PPGTT(vm->dev)) {
 		gen8_ppgtt_clear_pte_range(vm, &ppgtt->pdp, start, length,
 					   scratch_pte);
 	} else {
 		uint64_t templ4, pml4e;
 		struct i915_page_directory_pointer *pdp;
 		gen8_for_each_pml4e(pdp, &ppgtt->pml4, start, length, templ4, pml4e) {
 			gen8_ppgtt_clear_pte_range(vm, pdp, start, length,
 						   scratch_pte);
+		}
+	}
+}
 static void
 gen8_ppgtt_insert_pte_entries(struct i915_address_space *vm,
 			      struct i915_page_directory_pointer *pdp,
 			      struct sg_page_iter *sg_iter,
 			      uint64_t start,
 			      enum i915_cache_level cache_level)
+{
 	struct i915_hw_ppgtt *ppgtt =
 		container_of(vm, struct i915_hw_ppgtt, base);
 	gen8_pte_t *pt_vaddr;
 	unsigned pdpe = gen8_pdpe_index(start);
 	unsigned pde = gen8_pde_index(start);
 	unsigned pte = gen8_pte_index(start);
 	pt_vaddr = NULL;
 	while (__sg_page_iter_next(sg_iter)) {
 		if (pt_vaddr == NULL) {
 			struct i915_page_directory *pd = pdp->page_directory[pdpe];
 			struct i915_page_table *pt = pd->page_table[pde];
 			pt_vaddr = kmap_px(pt);
+		}
 		pt_vaddr[pte] =
 			gen8_pte_encode(sg_page_iter_dma_address(sg_iter),
 					cache_level, true);
 		if (++pte == GEN8_PTES) {
 			kunmap_px(ppgtt, pt_vaddr);
 			pt_vaddr = NULL;
 			if (++pde == I915_PDES) {
 				if (++pdpe == I915_PDPES_PER_PDP(vm->dev))
 					break;
 				pde = 0;
+			}
 			pte = 0;
+		}
+	}
 	if (pt_vaddr)
 		kunmap_px(ppgtt, pt_vaddr);
+}
 static void gen8_ppgtt_insert_entries(struct i915_address_space *vm,
 				      struct sg_table *pages,
 				      uint64_t start,
 				      enum i915_cache_level cache_level,
 				      u32 unused)
+{
 	struct i915_hw_ppgtt *ppgtt =
 		container_of(vm, struct i915_hw_ppgtt, base);
 	struct sg_page_iter sg_iter;
 	__sg_page_iter_start(&sg_iter, pages->sgl, sg_nents(pages->sgl), 0);
 	if (!USES_FULL_48BIT_PPGTT(vm->dev)) {
 		gen8_ppgtt_insert_pte_entries(vm, &ppgtt->pdp, &sg_iter, start,
 					      cache_level);
 	} else {
 		struct i915_page_directory_pointer *pdp;
 		uint64_t templ4, pml4e;
 		uint64_t length = (uint64_t)pages->orig_nents << PAGE_SHIFT;
 		gen8_for_each_pml4e(pdp, &ppgtt->pml4, start, length, templ4, pml4e) {
 			gen8_ppgtt_insert_pte_entries(vm, pdp, &sg_iter,
 						      start, cache_level);
+		}
+	}
+}
 static void gen8_free_page_tables(struct drm_device *dev,
 				  struct i915_page_directory *pd)
+{
 	int i;
 	if (!px_page(pd))
 		return;
 	for_each_set_bit(i, pd->used_pdes, I915_PDES) {
 		if (WARN_ON(!pd->page_table[i]))
 			continue;
 		free_pt(dev, pd->page_table[i]);
 		pd->page_table[i] = NULL;
+	}
+}
 static int gen8_init_scratch(struct i915_address_space *vm)
+{
 	struct drm_device *dev = vm->dev;
 	vm->scratch_page = alloc_scratch_page(dev);
 	if (IS_ERR(vm->scratch_page))
 		return PTR_ERR(vm->scratch_page);
 	vm->scratch_pt = alloc_pt(dev);
 	if (IS_ERR(vm->scratch_pt)) {
 		free_scratch_page(dev, vm->scratch_page);
 		return PTR_ERR(vm->scratch_pt);
+	}
 	vm->scratch_pd = alloc_pd(dev);
 	if (IS_ERR(vm->scratch_pd)) {
 		free_pt(dev, vm->scratch_pt);
 		free_scratch_page(dev, vm->scratch_page);
 		return PTR_ERR(vm->scratch_pd);
+	}
 	if (USES_FULL_48BIT_PPGTT(dev)) {
 		vm->scratch_pdp = alloc_pdp(dev);
 		if (IS_ERR(vm->scratch_pdp)) {
 			free_pd(dev, vm->scratch_pd);
 			free_pt(dev, vm->scratch_pt);
 			free_scratch_page(dev, vm->scratch_page);
 			return PTR_ERR(vm->scratch_pdp);
+		}
+	}
 	gen8_initialize_pt(vm, vm->scratch_pt);
 	gen8_initialize_pd(vm, vm->scratch_pd);
 	if (USES_FULL_48BIT_PPGTT(dev))
 		gen8_initialize_pdp(vm, vm->scratch_pdp);
 	return 0;
+}
 static int gen8_ppgtt_notify_vgt(struct i915_hw_ppgtt *ppgtt, bool create)
+{
 	enum vgt_g2v_type msg;
 	struct drm_device *dev = ppgtt->base.dev;
 	struct drm_i915_private *dev_priv = dev->dev_private;
 	unsigned int offset = vgtif_reg(pdp0_lo);
 	int i;
 	if (USES_FULL_48BIT_PPGTT(dev)) {
 		u64 daddr = px_dma(&ppgtt->pml4);
 		I915_WRITE(offset, lower_32_bits(daddr));
 		I915_WRITE(offset + 4, upper_32_bits(daddr));
 		msg = (create ? VGT_G2V_PPGTT_L4_PAGE_TABLE_CREATE :
 				VGT_G2V_PPGTT_L4_PAGE_TABLE_DESTROY);
 	} else {
 		for (i = 0; i < GEN8_LEGACY_PDPES; i++) {
 			u64 daddr = i915_page_dir_dma_addr(ppgtt, i);
 			I915_WRITE(offset, lower_32_bits(daddr));
 			I915_WRITE(offset + 4, upper_32_bits(daddr));
 			offset += 8;
+		}
 		msg = (create ? VGT_G2V_PPGTT_L3_PAGE_TABLE_CREATE :
 				VGT_G2V_PPGTT_L3_PAGE_TABLE_DESTROY);
+	}
 	I915_WRITE(vgtif_reg(g2v_notify), msg);
 	return 0;
+}
 static void gen8_free_scratch(struct i915_address_space *vm)
+{
 	struct drm_device *dev = vm->dev;
 	if (USES_FULL_48BIT_PPGTT(dev))
 		free_pdp(dev, vm->scratch_pdp);
 	free_pd(dev, vm->scratch_pd);
 	free_pt(dev, vm->scratch_pt);
 	free_scratch_page(dev, vm->scratch_page);
+}
 static void gen8_ppgtt_cleanup_3lvl(struct drm_device *dev,
 				    struct i915_page_directory_pointer *pdp)
+{
 	int i;
 	for_each_set_bit(i, pdp->used_pdpes, I915_PDPES_PER_PDP(dev)) {
 		if (WARN_ON(!pdp->page_directory[i]))
 			continue;
 		gen8_free_page_tables(dev, pdp->page_directory[i]);
 		free_pd(dev, pdp->page_directory[i]);
+	}
 	free_pdp(dev, pdp);
+}
 static void gen8_ppgtt_cleanup_4lvl(struct i915_hw_ppgtt *ppgtt)
+{
 	int i;
 	for_each_set_bit(i, ppgtt->pml4.used_pml4es, GEN8_PML4ES_PER_PML4) {
 		if (WARN_ON(!ppgtt->pml4.pdps[i]))
 			continue;
 		gen8_ppgtt_cleanup_3lvl(ppgtt->base.dev, ppgtt->pml4.pdps[i]);
+	}
 	cleanup_px(ppgtt->base.dev, &ppgtt->pml4);
+}
 static void gen8_ppgtt_cleanup(struct i915_address_space *vm)
+{
 	struct i915_hw_ppgtt *ppgtt =
 		container_of(vm, struct i915_hw_ppgtt, base);
 	if (intel_vgpu_active(vm->dev))
 		gen8_ppgtt_notify_vgt(ppgtt, false);
 	if (!USES_FULL_48BIT_PPGTT(ppgtt->base.dev))
 		gen8_ppgtt_cleanup_3lvl(ppgtt->base.dev, &ppgtt->pdp);
 	else
 		gen8_ppgtt_cleanup_4lvl(ppgtt);
 	gen8_free_scratch(vm);
+}
 /**
  * gen8_ppgtt_alloc_pagetabs() - Allocate page tables for VA range.
  * @vm:	Master vm structure.
  * @pd:	Page directory for this address range.
  * @start:	Starting virtual address to begin allocations.
  * @length:	Size of the allocations.
  * @new_pts:	Bitmap set by function with new allocations. Likely used by the
  *		caller to free on error.
+ *
  * Allocate the required number of page tables. Extremely similar to
  * gen8_ppgtt_alloc_page_directories(). The main difference is here we are limited by
  * the page directory boundary (instead of the page directory pointer). That
  * boundary is 1GB virtual. Therefore, unlike gen8_ppgtt_alloc_page_directories(), it is
  * possible, and likely that the caller will need to use multiple calls of this
  * function to achieve the appropriate allocation.
+ *
  * Return: 0 if success; negative error code otherwise.
  */
 static int gen8_ppgtt_alloc_pagetabs(struct i915_address_space *vm,
 				     struct i915_page_directory *pd,
 				     uint64_t start,
 				     uint64_t length,
 				     unsigned long *new_pts)
+{
 	struct drm_device *dev = vm->dev;
 	struct i915_page_table *pt;
 	uint64_t temp;
 	uint32_t pde;
 	gen8_for_each_pde(pt, pd, start, length, temp, pde) {
 		/* Don't reallocate page tables */
 		if (test_bit(pde, pd->used_pdes)) {
 			/* Scratch is never allocated this way */
 			WARN_ON(pt == vm->scratch_pt);
 			continue;
+		}
 		pt = alloc_pt(dev);
 		if (IS_ERR(pt))
 			goto unwind_out;
 		gen8_initialize_pt(vm, pt);
 		pd->page_table[pde] = pt;
 		__set_bit(pde, new_pts);
 		trace_i915_page_table_entry_alloc(vm, pde, start, GEN8_PDE_SHIFT);
+	}
 	return 0;
 unwind_out:
 	for_each_set_bit(pde, new_pts, I915_PDES)
 		free_pt(dev, pd->page_table[pde]);
 	return -ENOMEM;
+}
 /**
  * gen8_ppgtt_alloc_page_directories() - Allocate page directories for VA range.
  * @vm:	Master vm structure.
  * @pdp:	Page directory pointer for this address range.
  * @start:	Starting virtual address to begin allocations.
  * @length:	Size of the allocations.
  * @new_pds:	Bitmap set by function with new allocations. Likely used by the
  *		caller to free on error.
+ *
  * Allocate the required number of page directories starting at the pde index of
  * @start, and ending at the pde index @start + @length. This function will skip
  * over already allocated page directories within the range, and only allocate
  * new ones, setting the appropriate pointer within the pdp as well as the
  * correct position in the bitmap @new_pds.
+ *
  * The function will only allocate the pages within the range for a give page
  * directory pointer. In other words, if @start + @length straddles a virtually
  * addressed PDP boundary (512GB for 4k pages), there will be more allocations
  * required by the caller, This is not currently possible, and the BUG in the
  * code will prevent it.
+ *
  * Return: 0 if success; negative error code otherwise.
  */
 static int
 gen8_ppgtt_alloc_page_directories(struct i915_address_space *vm,
 				  struct i915_page_directory_pointer *pdp,
 				  uint64_t start,
 				  uint64_t length,
 				  unsigned long *new_pds)
+{
 	struct drm_device *dev = vm->dev;
 	struct i915_page_directory *pd;
 	uint64_t temp;
 	uint32_t pdpe;
 	uint32_t pdpes = I915_PDPES_PER_PDP(dev);
 	WARN_ON(!bitmap_empty(new_pds, pdpes));
 	gen8_for_each_pdpe(pd, pdp, start, length, temp, pdpe) {
 		if (test_bit(pdpe, pdp->used_pdpes))
 			continue;
 		pd = alloc_pd(dev);
 		if (IS_ERR(pd))
 			goto unwind_out;
 		gen8_initialize_pd(vm, pd);
 		pdp->page_directory[pdpe] = pd;
 		__set_bit(pdpe, new_pds);
 		trace_i915_page_directory_entry_alloc(vm, pdpe, start, GEN8_PDPE_SHIFT);
+	}
 	return 0;
 unwind_out:
 	for_each_set_bit(pdpe, new_pds, pdpes)
 		free_pd(dev, pdp->page_directory[pdpe]);
 	return -ENOMEM;
+}
 /**
  * gen8_ppgtt_alloc_page_dirpointers() - Allocate pdps for VA range.
  * @vm:	Master vm structure.
  * @pml4:	Page map level 4 for this address range.
  * @start:	Starting virtual address to begin allocations.
  * @length:	Size of the allocations.
  * @new_pdps:	Bitmap set by function with new allocations. Likely used by the
  *		caller to free on error.
+ *
  * Allocate the required number of page directory pointers. Extremely similar to
  * gen8_ppgtt_alloc_page_directories() and gen8_ppgtt_alloc_pagetabs().
  * The main difference is here we are limited by the pml4 boundary (instead of
  * the page directory pointer).
+ *
  * Return: 0 if success; negative error code otherwise.
  */
 static int
 gen8_ppgtt_alloc_page_dirpointers(struct i915_address_space *vm,
 				  struct i915_pml4 *pml4,
 				  uint64_t start,
 				  uint64_t length,
 				  unsigned long *new_pdps)
+{
 	struct drm_device *dev = vm->dev;
 	struct i915_page_directory_pointer *pdp;
 	uint64_t temp;
 	uint32_t pml4e;
 	WARN_ON(!bitmap_empty(new_pdps, GEN8_PML4ES_PER_PML4));
 	gen8_for_each_pml4e(pdp, pml4, start, length, temp, pml4e) {
 		if (!test_bit(pml4e, pml4->used_pml4es)) {
 			pdp = alloc_pdp(dev);
 			if (IS_ERR(pdp))
 				goto unwind_out;
 			gen8_initialize_pdp(vm, pdp);
 			pml4->pdps[pml4e] = pdp;
 			__set_bit(pml4e, new_pdps);
 			trace_i915_page_directory_pointer_entry_alloc(vm,
 								      pml4e,
 								      start,
 								      GEN8_PML4E_SHIFT);
+		}
+	}
 	return 0;
 unwind_out:
 	for_each_set_bit(pml4e, new_pdps, GEN8_PML4ES_PER_PML4)
 		free_pdp(dev, pml4->pdps[pml4e]);
 	return -ENOMEM;
+}
 static void
 free_gen8_temp_bitmaps(unsigned long *new_pds, unsigned long *new_pts)
+{
 	kfree(new_pts);
 	kfree(new_pds);
+}
 /* Fills in the page directory bitmap, and the array of page tables bitmap. Both
  * of these are based on the number of PDPEs in the system.
  */
 static
 int __must_check alloc_gen8_temp_bitmaps(unsigned long **new_pds,
 					 unsigned long **new_pts,
 					 uint32_t pdpes)
+{
 	unsigned long *pds;
 	unsigned long *pts;
 	pds = kcalloc(BITS_TO_LONGS(pdpes), sizeof(unsigned long), GFP_TEMPORARY);
 	if (!pds)
 		return -ENOMEM;
 	pts = kcalloc(pdpes, BITS_TO_LONGS(I915_PDES) * sizeof(unsigned long),
 		      GFP_TEMPORARY);
 	if (!pts)
 		goto err_out;
 	*new_pds = pds;
 	*new_pts = pts;
 	return 0;
 err_out:
 	free_gen8_temp_bitmaps(pds, pts);
 	return -ENOMEM;
+}
 /* PDE TLBs are a pain to invalidate on GEN8+. When we modify
  * the page table structures, we mark them dirty so that
  * context switching/execlist queuing code takes extra steps
  * to ensure that tlbs are flushed.
  */
 static void mark_tlbs_dirty(struct i915_hw_ppgtt *ppgtt)
+{
 	ppgtt->pd_dirty_rings = INTEL_INFO(ppgtt->base.dev)->ring_mask;
+}
 static int gen8_alloc_va_range_3lvl(struct i915_address_space *vm,
 				    struct i915_page_directory_pointer *pdp,
 				    uint64_t start,
 				    uint64_t length)
+{
 	struct i915_hw_ppgtt *ppgtt =
 		container_of(vm, struct i915_hw_ppgtt, base);
 	unsigned long *new_page_dirs, *new_page_tables;
 	struct drm_device *dev = vm->dev;
 	struct i915_page_directory *pd;
 	const uint64_t orig_start = start;
 	const uint64_t orig_length = length;
 	uint64_t temp;
 	uint32_t pdpe;
 	uint32_t pdpes = I915_PDPES_PER_PDP(dev);
 	int ret;
 	/* Wrap is never okay since we can only represent 48b, and we don't
 	 * actually use the other side of the canonical address space.
 	 */
 	if (WARN_ON(start + length < start))
 		return -ENODEV;
 	if (WARN_ON(start + length > vm->total))
 		return -ENODEV;
 	ret = alloc_gen8_temp_bitmaps(&new_page_dirs, &new_page_tables, pdpes);
 	if (ret)
 		return ret;
 	/* Do the allocations first so we can easily bail out */
 	ret = gen8_ppgtt_alloc_page_directories(vm, pdp, start, length,
 						new_page_dirs);
 	if (ret) {
 		free_gen8_temp_bitmaps(new_page_dirs, new_page_tables);
 		return ret;
+	}
 	/* For every page directory referenced, allocate page tables */
 	gen8_for_each_pdpe(pd, pdp, start, length, temp, pdpe) {
 		ret = gen8_ppgtt_alloc_pagetabs(vm, pd, start, length,
 						new_page_tables + pdpe * BITS_TO_LONGS(I915_PDES));
 		if (ret)
 			goto err_out;
+	}
 	start = orig_start;
 	length = orig_length;
 	/* Allocations have completed successfully, so set the bitmaps, and do
 	 * the mappings. */
 	gen8_for_each_pdpe(pd, pdp, start, length, temp, pdpe) {
 		gen8_pde_t *const page_directory = kmap_px(pd);
 		struct i915_page_table *pt;
 		uint64_t pd_len = length;
 		uint64_t pd_start = start;
 		uint32_t pde;
 		/* Every pd should be allocated, we just did that above. */
 		WARN_ON(!pd);
 		gen8_for_each_pde(pt, pd, pd_start, pd_len, temp, pde) {
 			/* Same reasoning as pd */
 			WARN_ON(!pt);
 			WARN_ON(!pd_len);
 			WARN_ON(!gen8_pte_count(pd_start, pd_len));
 			/* Set our used ptes within the page table */
 			bitmap_set(pt->used_ptes,
 				   gen8_pte_index(pd_start),
 				   gen8_pte_count(pd_start, pd_len));
 			/* Our pde is now pointing to the pagetable, pt */
 			__set_bit(pde, pd->used_pdes);
 			/* Map the PDE to the page table */
 			page_directory[pde] = gen8_pde_encode(px_dma(pt),
 							      I915_CACHE_LLC);
 			trace_i915_page_table_entry_map(&ppgtt->base, pde, pt,
 							gen8_pte_index(start),
 							gen8_pte_count(start, length),
 							GEN8_PTES);
 			/* NB: We haven't yet mapped ptes to pages. At this
 			 * point we're still relying on insert_entries() */
+		}
 		kunmap_px(ppgtt, page_directory);
 		__set_bit(pdpe, pdp->used_pdpes);
 		gen8_setup_page_directory(ppgtt, pdp, pd, pdpe);
+	}
 	free_gen8_temp_bitmaps(new_page_dirs, new_page_tables);
 	mark_tlbs_dirty(ppgtt);
 	return 0;
 err_out:
 	while (pdpe--) {
 		for_each_set_bit(temp, new_page_tables + pdpe *
 				BITS_TO_LONGS(I915_PDES), I915_PDES)
 			free_pt(dev, pdp->page_directory[pdpe]->page_table[temp]);
+	}
 	for_each_set_bit(pdpe, new_page_dirs, pdpes)
 		free_pd(dev, pdp->page_directory[pdpe]);
 	free_gen8_temp_bitmaps(new_page_dirs, new_page_tables);
 	mark_tlbs_dirty(ppgtt);
 	return ret;
+}
 static int gen8_alloc_va_range_4lvl(struct i915_address_space *vm,
 				    struct i915_pml4 *pml4,
 				    uint64_t start,
 				    uint64_t length)
+{
 	DECLARE_BITMAP(new_pdps, GEN8_PML4ES_PER_PML4);
 	struct i915_hw_ppgtt *ppgtt =
 			container_of(vm, struct i915_hw_ppgtt, base);
 	struct i915_page_directory_pointer *pdp;
 	uint64_t temp, pml4e;
 	int ret = 0;
 	/* Do the pml4 allocations first, so we don't need to track the newly
 	 * allocated tables below the pdp */
 	bitmap_zero(new_pdps, GEN8_PML4ES_PER_PML4);
 	/* The pagedirectory and pagetable allocations are done in the shared 3
 	 * and 4 level code. Just allocate the pdps.
 	 */
 	ret = gen8_ppgtt_alloc_page_dirpointers(vm, pml4, start, length,
 						new_pdps);
 	if (ret)
 		return ret;
 	WARN(bitmap_weight(new_pdps, GEN8_PML4ES_PER_PML4) > 2,
 	     "The allocation has spanned more than 512GB. "
 	     "It is highly likely this is incorrect.");
 	gen8_for_each_pml4e(pdp, pml4, start, length, temp, pml4e) {
 		WARN_ON(!pdp);
 		ret = gen8_alloc_va_range_3lvl(vm, pdp, start, length);
 		if (ret)
 			goto err_out;
 		gen8_setup_page_directory_pointer(ppgtt, pml4, pdp, pml4e);
+	}
 	bitmap_or(pml4->used_pml4es, new_pdps, pml4->used_pml4es,
 		  GEN8_PML4ES_PER_PML4);
 	return 0;
 err_out:
 	for_each_set_bit(pml4e, new_pdps, GEN8_PML4ES_PER_PML4)
 		gen8_ppgtt_cleanup_3lvl(vm->dev, pml4->pdps[pml4e]);
 	return ret;
+}
 static int gen8_alloc_va_range(struct i915_address_space *vm,
 			       uint64_t start, uint64_t length)
+{
 	struct i915_hw_ppgtt *ppgtt =
 		container_of(vm, struct i915_hw_ppgtt, base);
 	if (USES_FULL_48BIT_PPGTT(vm->dev))
 		return gen8_alloc_va_range_4lvl(vm, &ppgtt->pml4, start, length);
 	else
 		return gen8_alloc_va_range_3lvl(vm, &ppgtt->pdp, start, length);
+}
 static void gen8_dump_pdp(struct i915_page_directory_pointer *pdp,
 			  uint64_t start, uint64_t length,
 			  gen8_pte_t scratch_pte,
 			  struct seq_file *m)
+{
 	struct i915_page_directory *pd;
 	uint64_t temp;
 	uint32_t pdpe;
 	gen8_for_each_pdpe(pd, pdp, start, length, temp, pdpe) {
 		struct i915_page_table *pt;
 		uint64_t pd_len = length;
 		uint64_t pd_start = start;
 		uint32_t pde;
 		if (!test_bit(pdpe, pdp->used_pdpes))
 			continue;
 		seq_printf(m, "\tPDPE #%d\n", pdpe);
 		gen8_for_each_pde(pt, pd, pd_start, pd_len, temp, pde) {
 			uint32_t  pte;
 			gen8_pte_t *pt_vaddr;
 			if (!test_bit(pde, pd->used_pdes))
 				continue;
 			pt_vaddr = kmap_px(pt);
 			for (pte = 0; pte < GEN8_PTES; pte += 4) {
 				uint64_t va =
 					(pdpe << GEN8_PDPE_SHIFT) |
 					(pde << GEN8_PDE_SHIFT) |
 					(pte << GEN8_PTE_SHIFT);
 				int i;
 				bool found = false;
 				for (i = 0; i < 4; i++)
 					if (pt_vaddr[pte + i] != scratch_pte)
 						found = true;
 				if (!found)
 					continue;
 				seq_printf(m, "\t\t0x%llx [%03d,%03d,%04d]: =", va, pdpe, pde, pte);
 				for (i = 0; i < 4; i++) {
 					if (pt_vaddr[pte + i] != scratch_pte)
 						seq_printf(m, " %llx", pt_vaddr[pte + i]);
 					else
 						seq_puts(m, "  SCRATCH ");
+				}
 				seq_puts(m, "\n");
+			}
 			/* don't use kunmap_px, it could trigger
 			 * an unnecessary flush.
 			 */
 			kunmap_atomic(pt_vaddr);
+		}
+	}
+}
 static void gen8_dump_ppgtt(struct i915_hw_ppgtt *ppgtt, struct seq_file *m)
+{
 	struct i915_address_space *vm = &ppgtt->base;
 	uint64_t start = ppgtt->base.start;
 	uint64_t length = ppgtt->base.total;
 	gen8_pte_t scratch_pte = gen8_pte_encode(px_dma(vm->scratch_page),
 						 I915_CACHE_LLC, true);
 	if (!USES_FULL_48BIT_PPGTT(vm->dev)) {
 		gen8_dump_pdp(&ppgtt->pdp, start, length, scratch_pte, m);
 	} else {
 		uint64_t templ4, pml4e;
 		struct i915_pml4 *pml4 = &ppgtt->pml4;
 		struct i915_page_directory_pointer *pdp;
 		gen8_for_each_pml4e(pdp, pml4, start, length, templ4, pml4e) {
 			if (!test_bit(pml4e, pml4->used_pml4es))
 				continue;
 			seq_printf(m, "    PML4E #%llu\n", pml4e);
 			gen8_dump_pdp(pdp, start, length, scratch_pte, m);
+		}
+	}
+}
 static int gen8_preallocate_top_level_pdps(struct i915_hw_ppgtt *ppgtt)
+{
 	unsigned long *new_page_dirs, *new_page_tables;
 	uint32_t pdpes = I915_PDPES_PER_PDP(dev);
 	int ret;
 	/* We allocate temp bitmap for page tables for no gain
 	 * but as this is for init only, lets keep the things simple
 	 */
 	ret = alloc_gen8_temp_bitmaps(&new_page_dirs, &new_page_tables, pdpes);
 	if (ret)
 		return ret;
 	/* Allocate for all pdps regardless of how the ppgtt
 	 * was defined.
 	 */
 	ret = gen8_ppgtt_alloc_page_directories(&ppgtt->base, &ppgtt->pdp,
 , 1ULL << 32,
 						new_page_dirs);
 	if (!ret)
 		*ppgtt->pdp.used_pdpes = *new_page_dirs;
 	free_gen8_temp_bitmaps(new_page_dirs, new_page_tables);
 	return ret;
+}
 /*
  * GEN8 legacy ppgtt programming is accomplished through a max 4 PDP registers
  * with a net effect resembling a 2-level page table in normal x86 terms. Each
  * PDP represents 1GB of memory 4 * 512 * 512 * 4096 = 4GB legacy 32b address
  * space.
+ *
  */
 static int gen8_ppgtt_init(struct i915_hw_ppgtt *ppgtt)
+{
 	int ret;
 	ret = gen8_init_scratch(&ppgtt->base);
 	if (ret)
 		return ret;
 	ppgtt->base.start = 0;
 	ppgtt->base.cleanup = gen8_ppgtt_cleanup;
 	ppgtt->base.allocate_va_range = gen8_alloc_va_range;
 	ppgtt->base.insert_entries = gen8_ppgtt_insert_entries;
 	ppgtt->base.clear_range = gen8_ppgtt_clear_range;
 	ppgtt->base.unbind_vma = ppgtt_unbind_vma;
 	ppgtt->base.bind_vma = ppgtt_bind_vma;
 	ppgtt->debug_dump = gen8_dump_ppgtt;
 	if (USES_FULL_48BIT_PPGTT(ppgtt->base.dev)) {
 		ret = setup_px(ppgtt->base.dev, &ppgtt->pml4);
 		if (ret)
 			goto free_scratch;
 		gen8_initialize_pml4(&ppgtt->base, &ppgtt->pml4);
 		ppgtt->base.total = 1ULL << 48;
 		ppgtt->switch_mm = gen8_48b_mm_switch;
 	} else {
 		ret = __pdp_init(ppgtt->base.dev, &ppgtt->pdp);
 		if (ret)
 			goto free_scratch;
 		ppgtt->base.total = 1ULL << 32;
 		ppgtt->switch_mm = gen8_legacy_mm_switch;
 		trace_i915_page_directory_pointer_entry_alloc(&ppgtt->base,
 , 0,
 							      GEN8_PML4E_SHIFT);
 		if (intel_vgpu_active(ppgtt->base.dev)) {
 			ret = gen8_preallocate_top_level_pdps(ppgtt);
 			if (ret)
 				goto free_scratch;
+		}
+	}
 	if (intel_vgpu_active(ppgtt->base.dev))
 		gen8_ppgtt_notify_vgt(ppgtt, true);
 	return 0;
 free_scratch:
 	gen8_free_scratch(&ppgtt->base);
 	return ret;
+}
 #endif
 #ifndef __NetBSD__
 static void gen6_dump_ppgtt(struct i915_hw_ppgtt *ppgtt, struct seq_file *m)
+{
 	struct i915_address_space *vm = &ppgtt->base;
 	struct i915_page_table *unused;
 	gen6_pte_t scratch_pte;
 	uint32_t pd_entry;
 	uint32_t  pte, pde, temp;
 	uint32_t start = ppgtt->base.start, length = ppgtt->base.total;
 	scratch_pte = vm->pte_encode(px_dma(vm->scratch_page),
 				     I915_CACHE_LLC, true, 0);
 	gen6_for_each_pde(unused, &ppgtt->pd, start, length, temp, pde) {
 		u32 expected;
 		gen6_pte_t *pt_vaddr;
 		const dma_addr_t pt_addr = px_dma(ppgtt->pd.page_table[pde]);
 		pd_entry = readl(ppgtt->pd_addr + pde);
 		expected = (GEN6_PDE_ADDR_ENCODE(pt_addr) | GEN6_PDE_VALID);
 		if (pd_entry != expected)
 			seq_printf(m, "\tPDE #%d mismatch: Actual PDE: %x Expected PDE: %x\n",
 				   pde,
 				   pd_entry,
 				   expected);
 		seq_printf(m, "\tPDE: %x\n", pd_entry);
 		pt_vaddr = kmap_px(ppgtt->pd.page_table[pde]);
 		for (pte = 0; pte < GEN6_PTES; pte+=4) {
 			unsigned long va =
 				(pde * PAGE_SIZE * GEN6_PTES) +
 				(pte * PAGE_SIZE);
 			int i;
 			bool found = false;
 			for (i = 0; i < 4; i++)
 				if (pt_vaddr[pte + i] != scratch_pte)
 					found = true;
 			if (!found)
 				continue;
 			seq_printf(m, "\t\t0x%lx [%03d,%04d]: =", va, pde, pte);
 			for (i = 0; i < 4; i++) {
 				if (pt_vaddr[pte + i] != scratch_pte)
 					seq_printf(m, " %08x", pt_vaddr[pte + i]);
 				else
 					seq_puts(m, "  SCRATCH ");
+			}
 			seq_puts(m, "\n");
+		}
 		kunmap_px(ppgtt, pt_vaddr);
+	}
+}
 #endif
 /* Write pde (index) from the page directory @pd to the page table @pt */
 static void gen6_write_pde(struct i915_page_directory *pd,
 			    const int pde, struct i915_page_table *pt)
+{
 	/* Caller needs to make sure the write completes if necessary */
 	struct i915_hw_ppgtt *ppgtt =
 		container_of(pd, struct i915_hw_ppgtt, pd);
 #ifdef __NetBSD__
 	struct drm_i915_private *dev_priv = ppgtt->base.dev->dev_private;
 	const bus_space_tag_t bst = dev_priv->gtt.bst;
 	const bus_space_handle_t bsh = dev_priv->gtt.bsh;
 	const bus_addr_t pd_base = ppgtt->pd.base.ggtt_offset;
 #endif
 	u32 pd_entry;
 	pd_entry = GEN6_PDE_ADDR_ENCODE(px_dma(pt));
 	pd_entry |= GEN6_PDE_VALID;
 #ifdef __NetBSD__
 	bus_space_write_4(bst, bsh, pd_base + pde, pd_entry);
 #else
 	writel(pd_entry, ppgtt->pd_addr + pde);
 #endif
+}
 /* Write all the page tables found in the ppgtt structure to incrementing page
  * directories. */
 static void gen6_write_page_range(struct drm_i915_private *dev_priv,
 				  struct i915_page_directory *pd,
 				  uint32_t start, uint32_t length)
+{
 	struct i915_page_table *pt;
 	uint32_t pde, temp;
 	gen6_for_each_pde(pt, pd, start, length, temp, pde)
 		gen6_write_pde(pd, pde, pt);
 	/* Make sure write is complete before other code can use this page
 	 * table. Also require for WC mapped PTEs */
 #ifdef __NetBSD__
 	bus_space_read_4(dev_priv->gtt.bst, dev_priv->gtt.bsh, 0);
 #else
 	readl(dev_priv->gtt.gsm);
 #endif
+}
 static uint32_t get_pd_offset(struct i915_hw_ppgtt *ppgtt)
+{
 	BUG_ON(ppgtt->pd.base.ggtt_offset & 0x3f);
 	return (ppgtt->pd.base.ggtt_offset / 64) << 16;
+}
 static int hsw_mm_switch(struct i915_hw_ppgtt *ppgtt,
 			 struct drm_i915_gem_request *req)
+{
 	struct intel_engine_cs *ring = req->ring;
 	int ret;
 	/* NB: TLBs must be flushed and invalidated before a switch */
 	ret = ring->flush(req, I915_GEM_GPU_DOMAINS, I915_GEM_GPU_DOMAINS);
 	if (ret)
 		return ret;
 	ret = intel_ring_begin(req, 6);
 	if (ret)
 		return ret;
 	intel_ring_emit(ring, MI_LOAD_REGISTER_IMM(2));
 	intel_ring_emit(ring, RING_PP_DIR_DCLV(ring));
 	intel_ring_emit(ring, PP_DIR_DCLV_2G);
 	intel_ring_emit(ring, RING_PP_DIR_BASE(ring));
 	intel_ring_emit(ring, get_pd_offset(ppgtt));
 	intel_ring_emit(ring, MI_NOOP);
 	intel_ring_advance(ring);
 	return 0;
+}
 static int vgpu_mm_switch(struct i915_hw_ppgtt *ppgtt,
 			  struct drm_i915_gem_request *req)
+{
 	struct intel_engine_cs *ring = req->ring;
 	struct drm_i915_private *dev_priv = to_i915(ppgtt->base.dev);
 	I915_WRITE(RING_PP_DIR_DCLV(ring), PP_DIR_DCLV_2G);
 	I915_WRITE(RING_PP_DIR_BASE(ring), get_pd_offset(ppgtt));
 	return 0;
+}
 static int gen7_mm_switch(struct i915_hw_ppgtt *ppgtt,
 			  struct drm_i915_gem_request *req)
+{
 	struct intel_engine_cs *ring = req->ring;
 	int ret;
 	/* NB: TLBs must be flushed and invalidated before a switch */
 	ret = ring->flush(req, I915_GEM_GPU_DOMAINS, I915_GEM_GPU_DOMAINS);
 	if (ret)
 		return ret;
 	ret = intel_ring_begin(req, 6);
 	if (ret)
 		return ret;
 	intel_ring_emit(ring, MI_LOAD_REGISTER_IMM(2));
 	intel_ring_emit(ring, RING_PP_DIR_DCLV(ring));
 	intel_ring_emit(ring, PP_DIR_DCLV_2G);
 	intel_ring_emit(ring, RING_PP_DIR_BASE(ring));
 	intel_ring_emit(ring, get_pd_offset(ppgtt));
 	intel_ring_emit(ring, MI_NOOP);
 	intel_ring_advance(ring);
 	/* XXX: RCS is the only one to auto invalidate the TLBs? */
 	if (ring->id != RCS) {
 		ret = ring->flush(req, I915_GEM_GPU_DOMAINS, I915_GEM_GPU_DOMAINS);
 		if (ret)
 			return ret;
+	}
 	return 0;
+}
 static int gen6_mm_switch(struct i915_hw_ppgtt *ppgtt,
 			  struct drm_i915_gem_request *req)
+{
 	struct intel_engine_cs *ring = req->ring;
 	struct drm_device *dev = ppgtt->base.dev;
 	struct drm_i915_private *dev_priv = dev->dev_private;
 	I915_WRITE(RING_PP_DIR_DCLV(ring), PP_DIR_DCLV_2G);
 	I915_WRITE(RING_PP_DIR_BASE(ring), get_pd_offset(ppgtt));
 	POSTING_READ(RING_PP_DIR_DCLV(ring));
 	return 0;
+}
 static void gen8_ppgtt_enable(struct drm_device *dev)
+{
 	struct drm_i915_private *dev_priv = dev->dev_private;
 	struct intel_engine_cs *ring;
 	int j;
 	for_each_ring(ring, dev_priv, j) {
 		u32 four_level = USES_FULL_48BIT_PPGTT(dev) ? GEN8_GFX_PPGTT_48B : 0;
 		I915_WRITE(RING_MODE_GEN7(ring),
 			   _MASKED_BIT_ENABLE(GFX_PPGTT_ENABLE | four_level));
+	}
+}
 static void gen7_ppgtt_enable(struct drm_device *dev)
+{
 	struct drm_i915_private *dev_priv = dev->dev_private;
 	struct intel_engine_cs *ring;
 	uint32_t ecochk, ecobits;
 	int i;
 	ecobits = I915_READ(GAC_ECO_BITS);
 	I915_WRITE(GAC_ECO_BITS, ecobits | ECOBITS_PPGTT_CACHE64B);
 	ecochk = I915_READ(GAM_ECOCHK);
 	if (IS_HASWELL(dev)) {
 		ecochk |= ECOCHK_PPGTT_WB_HSW;
 	} else {
 		ecochk |= ECOCHK_PPGTT_LLC_IVB;
 		ecochk &= ~ECOCHK_PPGTT_GFDT_IVB;
+	}
 	I915_WRITE(GAM_ECOCHK, ecochk);
 	for_each_ring(ring, dev_priv, i) {
 		/* GFX_MODE is per-ring on gen7+ */
 		I915_WRITE(RING_MODE_GEN7(ring),
 			   _MASKED_BIT_ENABLE(GFX_PPGTT_ENABLE));
+	}
+}
 static void gen6_ppgtt_enable(struct drm_device *dev)
+{
 	struct drm_i915_private *dev_priv = dev->dev_private;
 	uint32_t ecochk, gab_ctl, ecobits;
 	ecobits = I915_READ(GAC_ECO_BITS);
 	I915_WRITE(GAC_ECO_BITS, ecobits | ECOBITS_SNB_BIT |
 		   ECOBITS_PPGTT_CACHE64B);
 	gab_ctl = I915_READ(GAB_CTL);
 	I915_WRITE(GAB_CTL, gab_ctl | GAB_CTL_CONT_AFTER_PAGEFAULT);
 	ecochk = I915_READ(GAM_ECOCHK);
 	I915_WRITE(GAM_ECOCHK, ecochk | ECOCHK_SNB_BIT | ECOCHK_PPGTT_CACHE64B);
 	I915_WRITE(GFX_MODE, _MASKED_BIT_ENABLE(GFX_PPGTT_ENABLE));
+}
 /* PPGTT support for Sandybdrige/Gen6 and later */
 static void gen6_ppgtt_clear_range(struct i915_address_space *vm,
 				   uint64_t start,
 				   uint64_t length,
 				   bool use_scratch)
+{
 	struct i915_hw_ppgtt *ppgtt =
 		container_of(vm, struct i915_hw_ppgtt, base);
 	gen6_pte_t *pt_vaddr, scratch_pte;
 	unsigned first_entry = start >> PAGE_SHIFT;
 	unsigned num_entries = length >> PAGE_SHIFT;
 	unsigned act_pt = first_entry / GEN6_PTES;
 	unsigned first_pte = first_entry % GEN6_PTES;
 	unsigned last_pte, i;
 	scratch_pte = vm->pte_encode(px_dma(vm->scratch_page),
 				     I915_CACHE_LLC, true, 0);
 	while (num_entries) {
 		last_pte = first_pte + num_entries;
 		if (last_pte > GEN6_PTES)
 			last_pte = GEN6_PTES;
 		pt_vaddr = kmap_px(ppgtt->pd.page_table[act_pt]);
 		for (i = first_pte; i < last_pte; i++)
 			pt_vaddr[i] = scratch_pte;
 		kunmap_px(ppgtt, pt_vaddr);
 		num_entries -= last_pte - first_pte;
 		first_pte = 0;
 		act_pt++;
+	}
+}
 #ifdef __NetBSD__
 static void
 gen6_ppgtt_insert_entries(struct i915_address_space *vm, bus_dmamap_t dmamap,
     uint64_t start, enum i915_cache_level cache_level)
+{
 	struct i915_hw_ppgtt *ppgtt =
 		container_of(vm, struct i915_hw_ppgtt, base);
 	gen6_gtt_pte_t *pt_vaddr;
 	unsigned first_entry = start >> PAGE_SHIFT;
 	unsigned act_pt = first_entry / GEN6_PTES;
 	unsigned act_pte = first_entry % GEN6_PTES;
 	unsigned seg;
 	int ret;
 	pt_vaddr = NULL;
 	KASSERT(0 < dmamap->dm_nsegs);
 	for (seg = 0; seg < dmamap->dm_nsegs; seg++) {
 		KASSERT(dmamap->dm_segs[seg].ds_len == PAGE_SIZE);
 		if (pt_vaddr == NULL)
 			pt_vaddr = kmap_px(ppgtt->pd.page_table[act_pt]);
 		pt_vaddr[act_pte] =
 			vm->pte_encode(dmamap->dm_segs[seg].ds_addr,
 				       cache_level, true, flags);
 		if (++act_pte == GEN6_PTES) {
 			kunmap_px(ppgtt, pt_vaddr);
 			pt_vaddr = NULL;
 			act_pt++;
 			act_pte = 0;
+		}
+	}
 	if (pt_vaddr)
 		kunmap_px(ppgtt, pt_vaddr);
+}
 #else
 static void gen6_ppgtt_insert_entries(struct i915_address_space *vm,
 				      struct sg_table *pages,
 				      uint64_t start,
 				      enum i915_cache_level cache_level, u32 flags)
+{
 	struct i915_hw_ppgtt *ppgtt =
 		container_of(vm, struct i915_hw_ppgtt, base);
 	gen6_pte_t *pt_vaddr;
 	unsigned first_entry = start >> PAGE_SHIFT;
 	unsigned act_pt = first_entry / GEN6_PTES;
 	unsigned act_pte = first_entry % GEN6_PTES;
 	struct sg_page_iter sg_iter;
 	pt_vaddr = NULL;
 	for_each_sg_page(pages->sgl, &sg_iter, pages->nents, 0) {
 		if (pt_vaddr == NULL)
 			pt_vaddr = kmap_px(ppgtt->pd.page_table[act_pt]);
 		pt_vaddr[act_pte] =
 			vm->pte_encode(sg_page_iter_dma_address(&sg_iter),
 				       cache_level, true, flags);
 		if (++act_pte == GEN6_PTES) {
 			kunmap_px(ppgtt, pt_vaddr);
 			pt_vaddr = NULL;
 			act_pt++;
 			act_pte = 0;
+		}
+	}
 	if (pt_vaddr)
 		kunmap_px(ppgtt, pt_vaddr);
+}
 #endif
 static int gen6_alloc_va_range(struct i915_address_space *vm,
 			       uint64_t start_in, uint64_t length_in)
+{
 	DECLARE_BITMAP(new_page_tables, I915_PDES);
 	struct drm_device *dev = vm->dev;
 	struct drm_i915_private *dev_priv = dev->dev_private;
 	struct i915_hw_ppgtt *ppgtt =
 				container_of(vm, struct i915_hw_ppgtt, base);
 	struct i915_page_table *pt;
 	uint32_t start, length, start_save, length_save;
 	uint32_t pde, temp;
 	int ret;
 	if (WARN_ON(start_in + length_in > ppgtt->base.total))
 		return -ENODEV;
 	start = start_save = start_in;
 	length = length_save = length_in;
 	bitmap_zero(new_page_tables, I915_PDES);
 	/* The allocation is done in two stages so that we can bail out with
 	 * minimal amount of pain. The first stage finds new page tables that
 	 * need allocation. The second stage marks use ptes within the page
 	 * tables.
 	 */
 	gen6_for_each_pde(pt, &ppgtt->pd, start, length, temp, pde) {
 		if (pt != vm->scratch_pt) {
 			WARN_ON(bitmap_empty(pt->used_ptes, GEN6_PTES));
 			continue;
+		}
 		/* We've already allocated a page table */
 		WARN_ON(!bitmap_empty(pt->used_ptes, GEN6_PTES));
 		pt = alloc_pt(dev);
 		if (IS_ERR(pt)) {
 			ret = PTR_ERR(pt);
 			goto unwind_out;
+		}
 		gen6_initialize_pt(vm, pt);
 		ppgtt->pd.page_table[pde] = pt;
 		__set_bit(pde, new_page_tables);
 		trace_i915_page_table_entry_alloc(vm, pde, start, GEN6_PDE_SHIFT);
+	}
 	start = start_save;
 	length = length_save;
 	gen6_for_each_pde(pt, &ppgtt->pd, start, length, temp, pde) {
 		DECLARE_BITMAP(tmp_bitmap, GEN6_PTES);
 		bitmap_zero(tmp_bitmap, GEN6_PTES);
 		bitmap_set(tmp_bitmap, gen6_pte_index(start),
 			   gen6_pte_count(start, length));
 		if (__test_and_clear_bit(pde, new_page_tables))
 			gen6_write_pde(&ppgtt->pd, pde, pt);
 		trace_i915_page_table_entry_map(vm, pde, pt,
 					 gen6_pte_index(start),
 					 gen6_pte_count(start, length),
 					 GEN6_PTES);
 		bitmap_or(pt->used_ptes, tmp_bitmap, pt->used_ptes,
 				GEN6_PTES);
+	}
 	WARN_ON(!bitmap_empty(new_page_tables, I915_PDES));
 	/* Make sure write is complete before other code can use this page
 	 * table. Also require for WC mapped PTEs */
 #ifdef __NetBSD__
 	bus_space_read_4(dev_priv->gtt.bst, dev_priv->gtt.bsh, 0);
 #else
 	readl(dev_priv->gtt.gsm);
 #endif
 	mark_tlbs_dirty(ppgtt);
 	return 0;
 unwind_out:
 	for_each_set_bit(pde, new_page_tables, I915_PDES) {
 		struct i915_page_table *pt = ppgtt->pd.page_table[pde];
 		ppgtt->pd.page_table[pde] = vm->scratch_pt;
 		free_pt(vm->dev, pt);
+	}
 	mark_tlbs_dirty(ppgtt);
 	return ret;
+}
 static int gen6_init_scratch(struct i915_address_space *vm)
+{
 	struct drm_device *dev = vm->dev;
 	vm->scratch_page = alloc_scratch_page(dev);
 	if (IS_ERR(vm->scratch_page))
 		return PTR_ERR(vm->scratch_page);
 	vm->scratch_pt = alloc_pt(dev);
 	if (IS_ERR(vm->scratch_pt)) {
 		free_scratch_page(dev, vm->scratch_page);
 		return PTR_ERR(vm->scratch_pt);
+	}
 	gen6_initialize_pt(vm, vm->scratch_pt);
 	return 0;
+}
 static void gen6_free_scratch(struct i915_address_space *vm)
+{
 	struct drm_device *dev = vm->dev;
 	free_pt(dev, vm->scratch_pt);
 	free_scratch_page(dev, vm->scratch_page);
+}
 static void gen6_ppgtt_cleanup(struct i915_address_space *vm)
+{
 	struct i915_hw_ppgtt *ppgtt =
 		container_of(vm, struct i915_hw_ppgtt, base);
 	struct i915_page_table *pt;
 	uint32_t pde;
 	drm_mm_remove_node(&ppgtt->node);
 	gen6_for_all_pdes(pt, ppgtt, pde) {
 		if (pt != vm->scratch_pt)
 			free_pt(ppgtt->base.dev, pt);
+	}
 	gen6_free_scratch(vm);
+}
 static int gen6_ppgtt_allocate_page_directories(struct i915_hw_ppgtt *ppgtt)
+{
 	struct i915_address_space *vm = &ppgtt->base;
 	struct drm_device *dev = ppgtt->base.dev;
 	struct drm_i915_private *dev_priv = dev->dev_private;
 	bool retried = false;
 	int ret;
 	/* PPGTT PDEs reside in the GGTT and consists of 512 entries. The
 	 * allocator works in address space sizes, so it's multiplied by page
 	 * size. We allocate at the top of the GTT to avoid fragmentation.
 	 */
 	BUG_ON(!drm_mm_initialized(&dev_priv->gtt.base.mm));
 	ret = gen6_init_scratch(vm);
 	if (ret)
 		return ret;
 alloc:
 	ret = drm_mm_insert_node_in_range_generic(&dev_priv->gtt.base.mm,
 						  &ppgtt->node, GEN6_PD_SIZE,
 						  GEN6_PD_ALIGN, 0,
 , dev_priv->gtt.base.total,
 						  DRM_MM_TOPDOWN);
 	if (ret == -ENOSPC && !retried) {
 		ret = i915_gem_evict_something(dev, &dev_priv->gtt.base,
 					       GEN6_PD_SIZE, GEN6_PD_ALIGN,
 					       I915_CACHE_NONE,
 , dev_priv->gtt.base.total,
 );
 		if (ret)
 			goto err_out;
 		retried = true;
 		goto alloc;
+	}
 	if (ret)
 		goto err_out;
 	if (ppgtt->node.start < dev_priv->gtt.mappable_end)
 		DRM_DEBUG("Forced to use aperture for PDEs\n");
 	return 0;
 err_out:
 	gen6_free_scratch(vm);
 	return ret;
+}
 static int gen6_ppgtt_alloc(struct i915_hw_ppgtt *ppgtt)
+{
 	return gen6_ppgtt_allocate_page_directories(ppgtt);
+}
 static void gen6_scratch_va_range(struct i915_hw_ppgtt *ppgtt,
 				  uint64_t start, uint64_t length)
+{
 	struct i915_page_table *unused;
 	uint32_t pde, temp;
 	gen6_for_each_pde(unused, &ppgtt->pd, start, length, temp, pde)
 		ppgtt->pd.page_table[pde] = ppgtt->base.scratch_pt;
+}
 #endif
 static int gen6_ppgtt_init(struct i915_hw_ppgtt *ppgtt)
+{
 	struct drm_device *dev = ppgtt->base.dev;
 	struct drm_i915_private *dev_priv = dev->dev_private;
 	int ret;
 	ppgtt->base.pte_encode = dev_priv->gtt.base.pte_encode;
 	if (IS_GEN6(dev)) {
 		ppgtt->switch_mm = gen6_mm_switch;
 	} else if (IS_HASWELL(dev)) {
 		ppgtt->switch_mm = hsw_mm_switch;
 	} else if (IS_GEN7(dev)) {
 		ppgtt->switch_mm = gen7_mm_switch;
 	} else
 		BUG();
 	if (intel_vgpu_active(dev))
 		ppgtt->switch_mm = vgpu_mm_switch;
 	ret = gen6_ppgtt_alloc(ppgtt);
 	if (ret)
 		return ret;
 	ppgtt->base.allocate_va_range = gen6_alloc_va_range;
 	ppgtt->base.clear_range = gen6_ppgtt_clear_range;
 	ppgtt->base.insert_entries = gen6_ppgtt_insert_entries;
 	ppgtt->base.unbind_vma = ppgtt_unbind_vma;
 	ppgtt->base.bind_vma = ppgtt_bind_vma;
 	ppgtt->base.cleanup = gen6_ppgtt_cleanup;
 	ppgtt->base.start = 0;
 	ppgtt->base.total = I915_PDES * GEN6_PTES * PAGE_SIZE;
 #ifndef __NetBSD__
 	ppgtt->debug_dump = gen6_dump_ppgtt;
 #endif
 	ppgtt->pd.base.ggtt_offset =
 		ppgtt->node.start / PAGE_SIZE * sizeof(gen6_pte_t);
 	ppgtt->pd_addr = (gen6_pte_t __iomem *)dev_priv->gtt.gsm +
 		ppgtt->pd.base.ggtt_offset / sizeof(gen6_pte_t);
 	gen6_scratch_va_range(ppgtt, 0, ppgtt->base.total);
 	gen6_write_page_range(dev_priv, &ppgtt->pd, 0, ppgtt->base.total);
 	DRM_DEBUG_DRIVER("Allocated pde space (%lldM) at GTT entry: %llx\n",
 			 ppgtt->node.size >> 20,
 			 ppgtt->node.start / PAGE_SIZE);
 	DRM_DEBUG("Adding PPGTT at offset %x\n",
 		  ppgtt->pd.base.ggtt_offset << 10);
 	return 0;
+}
 static int __hw_ppgtt_init(struct drm_device *dev, struct i915_hw_ppgtt *ppgtt)
+{
 	ppgtt->base.dev = dev;
 	if (INTEL_INFO(dev)->gen < 8)
 		return gen6_ppgtt_init(ppgtt);
 	else
 		return gen8_ppgtt_init(ppgtt);
+}
 static void i915_address_space_init(struct i915_address_space *vm,
 				    struct drm_i915_private *dev_priv)
+{
 	drm_mm_init(&vm->mm, vm->start, vm->total);
 	vm->dev = dev_priv->dev;
 	INIT_LIST_HEAD(&vm->active_list);
 	INIT_LIST_HEAD(&vm->inactive_list);
 	list_add_tail(&vm->global_link, &dev_priv->vm_list);
+}
 int i915_ppgtt_init(struct drm_device *dev, struct i915_hw_ppgtt *ppgtt)
+{
 	struct drm_i915_private *dev_priv = dev->dev_private;
 	int ret = 0;
 	ret = __hw_ppgtt_init(dev, ppgtt);
 	if (ret == 0) {
 		kref_init(&ppgtt->ref);
 		i915_address_space_init(&ppgtt->base, dev_priv);
+	}
 	return ret;
+}
 int i915_ppgtt_init_hw(struct drm_device *dev)
+{
 	/* In the case of execlists, PPGTT is enabled by the context descriptor
 	 * and the PDPs are contained within the context itself.  We don't
 	 * need to do anything here. */
 	if (i915.enable_execlists)
 		return 0;
 	if (!USES_PPGTT(dev))
 		return 0;
 	if (IS_GEN6(dev))
 		gen6_ppgtt_enable(dev);
 	else if (IS_GEN7(dev))
 		gen7_ppgtt_enable(dev);
 	else if (INTEL_INFO(dev)->gen >= 8)
 		gen8_ppgtt_enable(dev);
 	else
 		MISSING_CASE(INTEL_INFO(dev)->gen);
 	return 0;
+}
 int i915_ppgtt_init_ring(struct drm_i915_gem_request *req)
+{
 	struct drm_i915_private *dev_priv = req->ring->dev->dev_private;
 	struct i915_hw_ppgtt *ppgtt = dev_priv->mm.aliasing_ppgtt;
 	if (i915.enable_execlists)
 		return 0;
 	if (!ppgtt)
 		return 0;
 	return ppgtt->switch_mm(ppgtt, req);
+}
 struct i915_hw_ppgtt *
 i915_ppgtt_create(struct drm_device *dev, struct drm_i915_file_private *fpriv)
+{
 	struct i915_hw_ppgtt *ppgtt;
 	int ret;
 	ppgtt = kzalloc(sizeof(*ppgtt), GFP_KERNEL);
 	if (!ppgtt)
 		return ERR_PTR(-ENOMEM);
 	ret = i915_ppgtt_init(dev, ppgtt);
 	if (ret) {
 		kfree(ppgtt);
 		return ERR_PTR(ret);
+	}
 	ppgtt->file_priv = fpriv;
 	trace_i915_ppgtt_create(&ppgtt->base);
 	return ppgtt;
+}
 void  i915_ppgtt_release(struct kref *kref)
+{
 	struct i915_hw_ppgtt *ppgtt =
 		container_of(kref, struct i915_hw_ppgtt, ref);
 	trace_i915_ppgtt_release(&ppgtt->base);
 	/* vmas should already be unbound */
 	WARN_ON(!list_empty(&ppgtt->base.active_list));
 	WARN_ON(!list_empty(&ppgtt->base.inactive_list));
 	list_del(&ppgtt->base.global_link);
 	drm_mm_takedown(&ppgtt->base.mm);
 	ppgtt->base.cleanup(&ppgtt->base);
 	kfree(ppgtt);
+}
 extern int intel_iommu_gfx_mapped;
 /* Certain Gen5 chipsets require require idling the GPU before
  * unmapping anything from the GTT when VT-d is enabled.
  */
 static bool needs_idle_maps(struct drm_device *dev)
+{
 #ifdef CONFIG_INTEL_IOMMU
 	/* Query intel_iommu to see if we need the workaround. Presumably that
 	 * was loaded first.
 	 */
 	if (IS_GEN5(dev) && IS_MOBILE(dev) && intel_iommu_gfx_mapped)
 		return true;
 #endif
 	return false;
+}
 static bool do_idling(struct drm_i915_private *dev_priv)
+{
 	bool ret = dev_priv->mm.interruptible;
 	if (unlikely(dev_priv->gtt.do_idle_maps)) {
 		dev_priv->mm.interruptible = false;
 		if (i915_gpu_idle(dev_priv->dev)) {
 			DRM_ERROR("Couldn't idle GPU\n");
 			/* Wait a bit, in hopes it avoids the hang */
 			udelay(10);
+		}
+	}
 	return ret;
+}
 static void undo_idling(struct drm_i915_private *dev_priv, bool interruptible)
+{
 	if (unlikely(dev_priv->gtt.do_idle_maps))
 		dev_priv->mm.interruptible = interruptible;
+}
 void i915_check_and_clear_faults(struct drm_device *dev)
+{
 	struct drm_i915_private *dev_priv = dev->dev_private;
 	struct intel_engine_cs *ring;
 	int i;
 	if (INTEL_INFO(dev)->gen < 6)
 		return;
 	for_each_ring(ring, dev_priv, i) {
 		u32 fault_reg;
 		fault_reg = I915_READ(RING_FAULT_REG(ring));
 		if (fault_reg & RING_FAULT_VALID) {
 			DRM_DEBUG_DRIVER("Unexpected fault\n"
 					 "\tAddr: 0x%08"PRIx32"\n"
 					 "\tAddress space: %s\n"
 					 "\tSource ID: %d\n"
 					 "\tType: %d\n",
 					 fault_reg & PAGE_MASK,
 					 fault_reg & RING_FAULT_GTTSEL_MASK ? "GGTT" : "PPGTT",
 					 RING_FAULT_SRCID(fault_reg),
 					 RING_FAULT_FAULT_TYPE(fault_reg));
 			I915_WRITE(RING_FAULT_REG(ring),
 				   fault_reg & ~RING_FAULT_VALID);
+		}
+	}
 	POSTING_READ(RING_FAULT_REG(&dev_priv->ring[RCS]));
+}
 static void i915_ggtt_flush(struct drm_i915_private *dev_priv)
+{
 	if (INTEL_INFO(dev_priv->dev)->gen < 6) {
 		intel_gtt_chipset_flush();
 	} else {
 		I915_WRITE(GFX_FLSH_CNTL_GEN6, GFX_FLSH_CNTL_EN);
 		POSTING_READ(GFX_FLSH_CNTL_GEN6);
+	}
+}
 void i915_gem_suspend_gtt_mappings(struct drm_device *dev)
+{
 	struct drm_i915_private *dev_priv = dev->dev_private;
 	/* Don't bother messing with faults pre GEN6 as we have little
 	 * documentation supporting that it's a good idea.
 	 */
 	if (INTEL_INFO(dev)->gen < 6)
 		return;
 	i915_check_and_clear_faults(dev);
 	dev_priv->gtt.base.clear_range(&dev_priv->gtt.base,
 				       dev_priv->gtt.base.start,
 				       dev_priv->gtt.base.total,
 				       true);
 	i915_ggtt_flush(dev_priv);
+}
 int i915_gem_gtt_prepare_object(struct drm_i915_gem_object *obj)
+{
 #ifdef __NetBSD__
 	KASSERT(0 < obj->base.size);
 	/* XXX errno NetBSD->Linux */
 	return -bus_dmamap_load_raw(obj->base.dev->dmat, obj->igo_dmamap,
 	    obj->pages, obj->igo_nsegs, obj->base.size, BUS_DMA_NOWAIT);
 #else
 	if (!dma_map_sg(&obj->base.dev->pdev->dev,
 			obj->pages->sgl, obj->pages->nents,
 			PCI_DMA_BIDIRECTIONAL))
 		return -ENOSPC;
 	return 0;
 #endif
+}
 #ifdef __NetBSD__
 static uint64_t
 gen8_get_pte(bus_space_tag_t bst, bus_space_handle_t bsh, unsigned i)
+{
 	CTASSERT(_BYTE_ORDER == _LITTLE_ENDIAN); /* x86 */
 	CTASSERT(sizeof(gen8_gtt_pte_t) == 8);
 #ifdef _LP64			/* XXX How to detect bus_space_read_8?  */
 	return bus_space_read_8(bst, bsh, 8*i);
 #else
 	/*
 	 * XXX I'm not sure this case can actually happen in practice:
 	 * 32-bit gen8 chipsets?
 	 */
 	return bus_space_read_4(bst, bsh, 8*i) |
 	    ((uint64_t)bus_space_read_4(bst, bsh, 8*i + 4) << 32);
 #endif
+}
 static inline void
 gen8_set_pte(bus_space_tag_t bst, bus_space_handle_t bsh, unsigned i,
     gen8_gtt_pte_t pte)
+{
 	CTASSERT(_BYTE_ORDER == _LITTLE_ENDIAN); /* x86 */
 	CTASSERT(sizeof(gen8_gtt_pte_t) == 8);
 #ifdef _LP64			/* XXX How to detect bus_space_write_8?  */
 	bus_space_write_8(bst, bsh, 8*i, pte);
 #else
 	bus_space_write_4(bst, bsh, 8*i, (uint32_t)pte);
 	bus_space_write_4(bst, bsh, 8*i + 4, (uint32_t)(pte >> 32));
 #endif
+}
 #else
 static void gen8_set_pte(void __iomem *addr, gen8_pte_t pte)
+{
 #ifdef writeq
 	writeq(pte, addr);
 #else
 	iowrite32((u32)pte, addr);
 	iowrite32(pte >> 32, addr + 4);
 #endif
+}
 #endif
 #ifdef __NetBSD__
 static void
 gen8_ggtt_insert_entries(struct i915_address_space *vm, bus_dmamap_t dmamap,
     uint64_t start, enum i915_cache_level level)
+{
 	struct drm_i915_private *dev_priv = vm->dev->dev_private;
 	unsigned first_entry = start >> PAGE_SHIFT;
 	const bus_space_tag_t bst = dev_priv->gtt.bst;
 	const bus_space_handle_t bsh = dev_priv->gtt.bsh;
 	unsigned i;
 	KASSERT(0 < dmamap->dm_nsegs);
 	for (i = 0; i < dmamap->dm_nsegs; i++) {
 		KASSERT(dmamap->dm_segs[i].ds_len == PAGE_SIZE);
 		gen8_set_pte(bst, bsh, first_entry + i,
 		    gen8_pte_encode(dmamap->dm_segs[i].ds_addr, level, true));
+	}
 	if (0 < i) {
 		/* Posting read.  */
 		WARN_ON(gen8_get_pte(bst, bsh, (first_entry + i - 1))
 		    != gen8_pte_encode(dmamap->dm_segs[i - 1].ds_addr, level,
 			true));
+	}
 	I915_WRITE(GFX_FLSH_CNTL_GEN6, GFX_FLSH_CNTL_EN);
 	POSTING_READ(GFX_FLSH_CNTL_GEN6);
+}
 #else
 static void gen8_ggtt_insert_entries(struct i915_address_space *vm,
 				     struct sg_table *st,
 				     uint64_t start,
 				     enum i915_cache_level level, u32 unused)
+{
 	struct drm_i915_private *dev_priv = vm->dev->dev_private;
 	unsigned first_entry = start >> PAGE_SHIFT;
 	gen8_pte_t __iomem *gtt_entries =
 		(gen8_pte_t __iomem *)dev_priv->gtt.gsm + first_entry;
 	int i = 0;
 	struct sg_page_iter sg_iter;
 	dma_addr_t addr = 0; /* shut up gcc */
 	for_each_sg_page(st->sgl, &sg_iter, st->nents, 0) {
 		addr = sg_dma_address(sg_iter.sg) +
 			(sg_iter.sg_pgoffset << PAGE_SHIFT);
 		gen8_set_pte(&gtt_entries[i],
 			     gen8_pte_encode(addr, level, true));
 		i++;
+	}
 	/*
 	 * XXX: This serves as a posting read to make sure that the PTE has
 	 * actually been updated. There is some concern that even though
 	 * registers and PTEs are within the same BAR that they are potentially
 	 * of NUMA access patterns. Therefore, even with the way we assume
 	 * hardware should work, we must keep this posting read for paranoia.
 	 */
 	if (i != 0)
 		WARN_ON(readq(&gtt_entries[i-1])
 			!= gen8_pte_encode(addr, level, true));
 	/* This next bit makes the above posting read even more important. We
 	 * want to flush the TLBs only after we're certain all the PTE updates
 	 * have finished.
 	 */
 	I915_WRITE(GFX_FLSH_CNTL_GEN6, GFX_FLSH_CNTL_EN);
 	POSTING_READ(GFX_FLSH_CNTL_GEN6);
+}
 #endif
 /*
  * Binds an object into the global gtt with the specified cache level. The object
  * will be accessible to the GPU via commands whose operands reference offsets
  * within the global GTT as well as accessible by the GPU through the GMADR
  * mapped BAR (dev_priv->mm.gtt->gtt).
  */
 #ifdef __NetBSD__
 static void
 gen6_ggtt_insert_entries(struct i915_address_space *vm, bus_dmamap_t dmamap,
     uint64_t start, enum i915_cache_level level)
+{
 	struct drm_i915_private *dev_priv = vm->dev->dev_private;
 	unsigned first_entry = start >> PAGE_SHIFT;
 	const bus_space_tag_t bst = dev_priv->gtt.bst;
 	const bus_space_handle_t bsh = dev_priv->gtt.bsh;
 	unsigned i;
 	KASSERT(0 < dmamap->dm_nsegs);
 	for (i = 0; i < dmamap->dm_nsegs; i++) {
 		KASSERT(dmamap->dm_segs[i].ds_len == PAGE_SIZE);
 		CTASSERT(sizeof(gen6_gtt_pte_t) == 4);
 		bus_space_write_4(bst, bsh, 4*(first_entry + i),
 		    vm->pte_encode(dmamap->dm_segs[i].ds_addr, level, true));
+	}
 	if (0 < i) {
 		/* Posting read.  */
 		WARN_ON(bus_space_read_4(bst, bsh, 4*(first_entry + i - 1))
 		    != vm->pte_encode(dmamap->dm_segs[i - 1].ds_addr, level,
 			true));
+	}
 	I915_WRITE(GFX_FLSH_CNTL_GEN6, GFX_FLSH_CNTL_EN);
 	POSTING_READ(GFX_FLSH_CNTL_GEN6);
+}
 #else
 static void gen6_ggtt_insert_entries(struct i915_address_space *vm,
 				     struct sg_table *st,
 				     uint64_t start,
 				     enum i915_cache_level level, u32 flags)
+{
 	struct drm_i915_private *dev_priv = vm->dev->dev_private;
 	unsigned first_entry = start >> PAGE_SHIFT;
 	gen6_pte_t __iomem *gtt_entries =
 		(gen6_pte_t __iomem *)dev_priv->gtt.gsm + first_entry;
 	int i = 0;
 	struct sg_page_iter sg_iter;
 	dma_addr_t addr = 0;
 	for_each_sg_page(st->sgl, &sg_iter, st->nents, 0) {
 		addr = sg_page_iter_dma_address(&sg_iter);
 		iowrite32(vm->pte_encode(addr, level, true, flags), &gtt_entries[i]);
 		i++;
+	}
 	/* XXX: This serves as a posting read to make sure that the PTE has
 	 * actually been updated. There is some concern that even though
 	 * registers and PTEs are within the same BAR that they are potentially
 	 * of NUMA access patterns. Therefore, even with the way we assume
 	 * hardware should work, we must keep this posting read for paranoia.
 	 */
 	if (i != 0) {
 		unsigned long gtt = readl(&gtt_entries[i-1]);
 		WARN_ON(gtt != vm->pte_encode(addr, level, true, flags));
+	}
 	/* This next bit makes the above posting read even more important. We
 	 * want to flush the TLBs only after we're certain all the PTE updates
 	 * have finished.
 	 */
 	I915_WRITE(GFX_FLSH_CNTL_GEN6, GFX_FLSH_CNTL_EN);
 	POSTING_READ(GFX_FLSH_CNTL_GEN6);
+}
 #endif
 static void gen8_ggtt_clear_range(struct i915_address_space *vm,
 				  uint64_t start,
 				  uint64_t length,
 				  bool use_scratch)
+{
 	struct drm_i915_private *dev_priv = vm->dev->dev_private;
 	unsigned first_entry = start >> PAGE_SHIFT;
 	unsigned num_entries = length >> PAGE_SHIFT;
 #ifdef __NetBSD__
 	const bus_space_tag_t bst = dev_priv->gtt.bst;
 	const bus_space_handle_t bsh = dev_priv->gtt.bsh;
 	gen8_pte_t scratch_pte;
 #else
 	gen8_pte_t scratch_pte, __iomem *gtt_base =
 		(gen8_pte_t __iomem *) dev_priv->gtt.gsm + first_entry;
 #endif
 	const int max_entries = gtt_total_entries(dev_priv->gtt) - first_entry;
 	int i;
 	if (WARN(num_entries > max_entries,
 		 "First entry = %d; Num entries = %d (max=%d)\n",
 		 first_entry, num_entries, max_entries))
 		num_entries = max_entries;
 	scratch_pte = gen8_pte_encode(px_dma(vm->scratch_page),
 				      I915_CACHE_LLC,
 				      use_scratch);
 #ifdef __NetBSD__
 	CTASSERT(sizeof(gen8_gtt_pte_t) == 8);
 	for (i = 0; i < num_entries; i++)
 		gen8_set_pte(bst, bsh, first_entry + i, scratch_pte);
 	(void)gen8_get_pte(bst, bsh, first_entry);
 #else
 	for (i = 0; i < num_entries; i++)
 		gen8_set_pte(&gtt_base[i], scratch_pte);
 	readl(gtt_base);
 #endif
+}
 static void gen6_ggtt_clear_range(struct i915_address_space *vm,
 				  uint64_t start,
 				  uint64_t length,
 				  bool use_scratch)
+{
 	struct drm_i915_private *dev_priv = vm->dev->dev_private;
 	unsigned first_entry = start >> PAGE_SHIFT;
 	unsigned num_entries = length >> PAGE_SHIFT;
 #ifdef __NetBSD__
 	const bus_space_tag_t bst = dev_priv->gtt.bst;
 	const bus_space_handle_t bsh = dev_priv->gtt.bsh;
 	gen8_pte_t scratch_pte;
 #else
 	gen6_pte_t scratch_pte, __iomem *gtt_base =
 		(gen6_pte_t __iomem *) dev_priv->gtt.gsm + first_entry;
 #endif
 	const int max_entries = gtt_total_entries(dev_priv->gtt) - first_entry;
 	int i;
 	if (WARN(num_entries > max_entries,
 		 "First entry = %d; Num entries = %d (max=%d)\n",
 		 first_entry, num_entries, max_entries))
 		num_entries = max_entries;
 	scratch_pte = vm->pte_encode(px_dma(vm->scratch_page),
 				     I915_CACHE_LLC, use_scratch, 0);
 #ifdef __NetBSD__
 	CTASSERT(sizeof(gen6_gtt_pte_t) == 4);
 	for (i = 0; i < num_entries; i++)
 		bus_space_write_4(bst, bsh, 4*(first_entry + i), scratch_pte);
 	(void)bus_space_read_4(bst, bsh, 4*first_entry);
 #else
 	for (i = 0; i < num_entries; i++)
 		iowrite32(scratch_pte, &gtt_base[i]);
 	readl(gtt_base);
 #endif
+}
 static void i915_ggtt_insert_entries(struct i915_address_space *vm,
 #ifdef __NetBSD__
 				     bus_dmamap_t pages,
 #else
 				     struct sg_table *pages,
 #endif
 				     uint64_t start,
 				     enum i915_cache_level cache_level, u32 unused)
+{
 	unsigned int flags = (cache_level == I915_CACHE_NONE) ?
 		AGP_USER_MEMORY : AGP_USER_CACHED_MEMORY;
 	intel_gtt_insert_sg_entries(pages, start >> PAGE_SHIFT, flags);
+}
 static void i915_ggtt_clear_range(struct i915_address_space *vm,
 				  uint64_t start,
 				  uint64_t length,
 				  bool unused)
+{
 	unsigned first_entry = start >> PAGE_SHIFT;
 	unsigned num_entries = length >> PAGE_SHIFT;
 	intel_gtt_clear_range(first_entry, num_entries);
+}
 static int ggtt_bind_vma(struct i915_vma *vma,
 			 enum i915_cache_level cache_level,
 			 u32 flags)
+{
 	struct drm_i915_gem_object *obj = vma->obj;
 	u32 pte_flags = 0;
 	int ret;
 	ret = i915_get_ggtt_vma_pages(vma);
 	if (ret)
 		return ret;
 	/* Currently applicable only to VLV */
 	if (obj->gt_ro)
 		pte_flags |= PTE_READ_ONLY;
 	vma->vm->insert_entries(vma->vm, vma->ggtt_view.pages,
 				vma->node.start,
 				cache_level, pte_flags);
 	/*
 	 * Without aliasing PPGTT there's no difference between
 	 * GLOBAL/LOCAL_BIND, it's all the same ptes. Hence unconditionally
 	 * upgrade to both bound if we bind either to avoid double-binding.
 	 */
 	vma->bound |= GLOBAL_BIND | LOCAL_BIND;
 	return 0;
+}
 static int aliasing_gtt_bind_vma(struct i915_vma *vma,
 				 enum i915_cache_level cache_level,
 				 u32 flags)
+{
 	struct drm_device *dev = vma->vm->dev;
 	struct drm_i915_private *dev_priv = dev->dev_private;
 	struct drm_i915_gem_object *obj = vma->obj;
 #ifdef __NetBSD__
 	bus_dmamap_t pages = obj->pages;
 #else
 	struct sg_table *pages = obj->pages;
 #endif
 	u32 pte_flags = 0;
 	int ret;
 	ret = i915_get_ggtt_vma_pages(vma);
 	if (ret)
 		return ret;
 	pages = vma->ggtt_view.pages;
 	/* Currently applicable only to VLV */
 	if (obj->gt_ro)
 		pte_flags |= PTE_READ_ONLY;
 	if (flags & GLOBAL_BIND) {
 		vma->vm->insert_entries(vma->vm, pages,
 					vma->node.start,
 					cache_level, pte_flags);
+	}
 	if (flags & LOCAL_BIND) {
 		struct i915_hw_ppgtt *appgtt = dev_priv->mm.aliasing_ppgtt;
 		appgtt->base.insert_entries(&appgtt->base, pages,
 					    vma->node.start,
 					    cache_level, pte_flags);
+	}
 	return 0;
+}
 static void ggtt_unbind_vma(struct i915_vma *vma)
+{
 	struct drm_device *dev = vma->vm->dev;
 	struct drm_i915_private *dev_priv = dev->dev_private;
 	struct drm_i915_gem_object *obj = vma->obj;
 	const uint64_t size = min_t(uint64_t,
 				    obj->base.size,
 				    vma->node.size);
 	if (vma->bound & GLOBAL_BIND) {
 		vma->vm->clear_range(vma->vm,
 				     vma->node.start,
 				     size,
 				     true);
+	}
 	if (dev_priv->mm.aliasing_ppgtt && vma->bound & LOCAL_BIND) {
 		struct i915_hw_ppgtt *appgtt = dev_priv->mm.aliasing_ppgtt;
 		appgtt->base.clear_range(&appgtt->base,
 					 vma->node.start,
 					 size,
 					 true);
+	}
+}
 void i915_gem_gtt_finish_object(struct drm_i915_gem_object *obj)
+{
 	struct drm_device *dev = obj->base.dev;
 	struct drm_i915_private *dev_priv = dev->dev_private;
 	bool interruptible;
 	interruptible = do_idling(dev_priv);
 #ifdef __NetBSD__
 	bus_dmamap_unload(dev->dmat, obj->igo_dmamap);
 #else
 	dma_unmap_sg(&dev->pdev->dev, obj->pages->sgl, obj->pages->nents,
 		     PCI_DMA_BIDIRECTIONAL);
 #endif
 	undo_idling(dev_priv, interruptible);
+}
 static void i915_gtt_color_adjust(struct drm_mm_node *node,
 				  unsigned long color,
 				  u64 *start,
 				  u64 *end)
+{
 	if (node->color != color)
 		*start += 4096;
 	if (!list_empty(&node->node_list)) {
 		node = list_entry(node->node_list.next,
 				  struct drm_mm_node,
 				  node_list);
 		if (node->allocated && node->color != color)
 			*end -= 4096;
+	}
+}
 static int i915_gem_setup_global_gtt(struct drm_device *dev,
 				     u64 start,
 				     u64 mappable_end,
 				     u64 end)
+{
 	/* Let GEM Manage all of the aperture.
+	 *
 	 * However, leave one page at the end still bound to the scratch page.
 	 * There are a number of places where the hardware apparently prefetches
 	 * past the end of the object, and we've seen multiple hangs with the
 	 * GPU head pointer stuck in a batchbuffer bound at the last page of the
 	 * aperture.  One page should be enough to keep any prefetching inside
 	 * of the aperture.
 	 */
 	struct drm_i915_private *dev_priv = dev->dev_private;
 	struct i915_address_space *ggtt_vm = &dev_priv->gtt.base;
 	struct drm_mm_node *entry;
 	struct drm_i915_gem_object *obj;
 	unsigned long hole_start, hole_end;
 	int ret;
 	BUG_ON(mappable_end > end);
 	ggtt_vm->start = start;
 	/* Subtract the guard page before address space initialization to
 	 * shrink the range used by drm_mm */
 	ggtt_vm->total = end - start - PAGE_SIZE;
 	i915_address_space_init(ggtt_vm, dev_priv);
 	ggtt_vm->total += PAGE_SIZE;
 	if (intel_vgpu_active(dev)) {
 		ret = intel_vgt_balloon(dev);
 		if (ret)
 			return ret;
+	}
 	if (!HAS_LLC(dev))
 		ggtt_vm->mm.color_adjust = i915_gtt_color_adjust;
 	/* Mark any preallocated objects as occupied */
 	list_for_each_entry(obj, &dev_priv->mm.bound_list, global_list) {
 		struct i915_vma *vma = i915_gem_obj_to_vma(obj, ggtt_vm);
 		DRM_DEBUG_KMS("reserving preallocated space: %llx + %zx\n",
 			      i915_gem_obj_ggtt_offset(obj), obj->base.size);
 		WARN_ON(i915_gem_obj_ggtt_bound(obj));
 		ret = drm_mm_reserve_node(&ggtt_vm->mm, &vma->node);
 		if (ret) {
 			DRM_DEBUG_KMS("Reservation failed: %i\n", ret);
 			return ret;
+		}
 		vma->bound |= GLOBAL_BIND;
 		__i915_vma_set_map_and_fenceable(vma);
 		list_add_tail(&vma->mm_list, &ggtt_vm->inactive_list);
+	}
 	/* Clear any non-preallocated blocks */
 	drm_mm_for_each_hole(entry, &ggtt_vm->mm, hole_start, hole_end) {
 		DRM_DEBUG_KMS("clearing unused GTT space: [%lx, %lx]\n",
 			      hole_start, hole_end);
 		ggtt_vm->clear_range(ggtt_vm, hole_start,
 				     hole_end - hole_start, true);
+	}
 	/* And finally clear the reserved guard page */
 	ggtt_vm->clear_range(ggtt_vm, end - PAGE_SIZE, PAGE_SIZE, true);
 	if (USES_PPGTT(dev) && !USES_FULL_PPGTT(dev)) {
 		struct i915_hw_ppgtt *ppgtt;
 		ppgtt = kzalloc(sizeof(*ppgtt), GFP_KERNEL);
 		if (!ppgtt)
 			return -ENOMEM;
 		ret = __hw_ppgtt_init(dev, ppgtt);
 		if (ret) {
 			ppgtt->base.cleanup(&ppgtt->base);
 			kfree(ppgtt);
 			return ret;
+		}
 		if (ppgtt->base.allocate_va_range)
 			ret = ppgtt->base.allocate_va_range(&ppgtt->base, 0,
 							    ppgtt->base.total);
 		if (ret) {
 			ppgtt->base.cleanup(&ppgtt->base);
 			kfree(ppgtt);
 			return ret;
+		}
 		ppgtt->base.clear_range(&ppgtt->base,
 					ppgtt->base.start,
 					ppgtt->base.total,
 					true);
 		dev_priv->mm.aliasing_ppgtt = ppgtt;
 		WARN_ON(dev_priv->gtt.base.bind_vma != ggtt_bind_vma);
 		dev_priv->gtt.base.bind_vma = aliasing_gtt_bind_vma;
+	}
 	return 0;
+}
 void i915_gem_init_global_gtt(struct drm_device *dev)
+{
 	struct drm_i915_private *dev_priv = dev->dev_private;
 	u64 gtt_size, mappable_size;
 	gtt_size = dev_priv->gtt.base.total;
 	mappable_size = dev_priv->gtt.mappable_end;
 	i915_gem_setup_global_gtt(dev, 0, mappable_size, gtt_size);
+}
 void i915_global_gtt_cleanup(struct drm_device *dev)
+{
 	struct drm_i915_private *dev_priv = dev->dev_private;
 	struct i915_address_space *vm = &dev_priv->gtt.base;
 	if (dev_priv->mm.aliasing_ppgtt) {
 		struct i915_hw_ppgtt *ppgtt = dev_priv->mm.aliasing_ppgtt;
 		ppgtt->base.cleanup(&ppgtt->base);
 		kfree(ppgtt);
+	}
 	if (drm_mm_initialized(&vm->mm)) {
 		if (intel_vgpu_active(dev))
 			intel_vgt_deballoon();
 		drm_mm_takedown(&vm->mm);
 		list_del(&vm->global_link);
+	}
 	vm->cleanup(vm);
+}
 static unsigned int gen6_get_total_gtt_size(u16 snb_gmch_ctl)
+{
 	snb_gmch_ctl >>= SNB_GMCH_GGMS_SHIFT;
 	snb_gmch_ctl &= SNB_GMCH_GGMS_MASK;
 	return snb_gmch_ctl << 20;
+}
 static unsigned int gen8_get_total_gtt_size(u16 bdw_gmch_ctl)
+{
 	bdw_gmch_ctl >>= BDW_GMCH_GGMS_SHIFT;
 	bdw_gmch_ctl &= BDW_GMCH_GGMS_MASK;
 	if (bdw_gmch_ctl)
 		bdw_gmch_ctl = 1 << bdw_gmch_ctl;
 #ifdef CONFIG_X86_32
 	/* Limit 32b platforms to a 2GB GGTT: 4 << 20 / pte size * PAGE_SIZE */
 	if (bdw_gmch_ctl > 4)
 		bdw_gmch_ctl = 4;
 #endif
 	return bdw_gmch_ctl << 20;
+}
 static unsigned int chv_get_total_gtt_size(u16 gmch_ctrl)
+{
 	gmch_ctrl >>= SNB_GMCH_GGMS_SHIFT;
 	gmch_ctrl &= SNB_GMCH_GGMS_MASK;
 	if (gmch_ctrl)
 		return 1 << (20 + gmch_ctrl);
 	return 0;
+}
 static size_t gen6_get_stolen_size(u16 snb_gmch_ctl)
+{
 	snb_gmch_ctl >>= SNB_GMCH_GMS_SHIFT;
 	snb_gmch_ctl &= SNB_GMCH_GMS_MASK;
 	return snb_gmch_ctl << 25; /* 32 MB units */
+}
 static size_t gen8_get_stolen_size(u16 bdw_gmch_ctl)
+{
 	bdw_gmch_ctl >>= BDW_GMCH_GMS_SHIFT;
 	bdw_gmch_ctl &= BDW_GMCH_GMS_MASK;
 	return bdw_gmch_ctl << 25; /* 32 MB units */
+}
 static size_t chv_get_stolen_size(u16 gmch_ctrl)
+{
 	gmch_ctrl >>= SNB_GMCH_GMS_SHIFT;
 	gmch_ctrl &= SNB_GMCH_GMS_MASK;
 	/*
 	 * 0x0  to 0x10: 32MB increments starting at 0MB
 	 * 0x11 to 0x16: 4MB increments starting at 8MB
 	 * 0x17 to 0x1d: 4MB increments start at 36MB
 	 */
 	if (gmch_ctrl < 0x11)
 		return gmch_ctrl << 25;
 	else if (gmch_ctrl < 0x17)
 		return (gmch_ctrl - 0x11 + 2) << 22;
 	else
 		return (gmch_ctrl - 0x17 + 9) << 22;
+}
 static size_t gen9_get_stolen_size(u16 gen9_gmch_ctl)
+{
 	gen9_gmch_ctl >>= BDW_GMCH_GMS_SHIFT;
 	gen9_gmch_ctl &= BDW_GMCH_GMS_MASK;
 	if (gen9_gmch_ctl < 0xf0)
 		return gen9_gmch_ctl << 25; /* 32 MB units */
 	else
 		/* 4MB increments starting at 0xf0 for 4MB */
 		return (gen9_gmch_ctl - 0xf0 + 1) << 22;
+}
 static int ggtt_probe_common(struct drm_device *dev,
 			     size_t gtt_size)
+{
 	struct drm_i915_private *dev_priv = dev->dev_private;
 	struct i915_page_scratch *scratch_page;
 	phys_addr_t gtt_phys_addr;
 	/* For Modern GENs the PTEs and register space are split in the BAR */
 	gtt_phys_addr = pci_resource_start(dev->pdev, 0) +
 		(pci_resource_len(dev->pdev, 0) / 2);
 #ifdef __NetBSD__
 	dev_priv->gtt.bst = dev->pdev->pd_pa.pa_memt;
 	/* XXX errno NetBSD->Linux */
 	ret = -bus_space_map(dev_priv->gtt.bst, gtt_phys_addr, gtt_size,
 	    IS_PROXTON(dev) ? 0 : BUS_SPACE_MAP_PREFETCHABLE,
 	    &dev_priv->gtt.bsh);
 	if (ret) {
 		DRM_ERROR("Failed to map the graphics translation table: %d\n",
 		    ret);
 		return ret;
+	}
 	dev_priv->gtt.size = gtt_size;
 #else
 	/*
 	 * On BXT writes larger than 64 bit to the GTT pagetable range will be
 	 * dropped. For WC mappings in general we have 64 byte burst writes
 	 * when the WC buffer is flushed, so we can't use it, but have to
 	 * resort to an uncached mapping. The WC issue is easily caught by the
 	 * readback check when writing GTT PTE entries.
 	 */
 	if (IS_BROXTON(dev))
 		dev_priv->gtt.gsm = ioremap_nocache(gtt_phys_addr, gtt_size);
 	else
 		dev_priv->gtt.gsm = ioremap_wc(gtt_phys_addr, gtt_size);
 	if (!dev_priv->gtt.gsm) {
 		DRM_ERROR("Failed to map the gtt page table\n");
 		return -ENOMEM;
+	}
 #endif
 	scratch_page = alloc_scratch_page(dev);
 	if (IS_ERR(scratch_page)) {
 		DRM_ERROR("Scratch setup failed\n");
 		/* iounmap will also get called at remove, but meh */
 #ifdef __NetBSD__
 		bus_space_unmap(dev_priv->gtt.bst, dev_priv->gtt.bsh,
 		    dev_priv->gtt.size);
 #else
 		iounmap(dev_priv->gtt.gsm);
 #endif
 		return PTR_ERR(scratch_page);
+	}
 	dev_priv->gtt.base.scratch_page = scratch_page;
 	return 0;
+}
 /* The GGTT and PPGTT need a private PPAT setup in order to handle cacheability
  * bits. When using advanced contexts each context stores its own PAT, but
  * writing this data shouldn't be harmful even in those cases. */
 static void bdw_setup_private_ppat(struct drm_i915_private *dev_priv)
+{
 	uint64_t pat;
 	pat = GEN8_PPAT(0, GEN8_PPAT_WB | GEN8_PPAT_LLC)     | /* for normal objects, no eLLC */
 	      GEN8_PPAT(1, GEN8_PPAT_WC | GEN8_PPAT_LLCELLC) | /* for something pointing to ptes? */
 	      GEN8_PPAT(2, GEN8_PPAT_WT | GEN8_PPAT_LLCELLC) | /* for scanout with eLLC */
 	      GEN8_PPAT(3, GEN8_PPAT_UC)                     | /* Uncached objects, mostly for scanout */
 	      GEN8_PPAT(4, GEN8_PPAT_WB | GEN8_PPAT_LLCELLC | GEN8_PPAT_AGE(0)) |
 	      GEN8_PPAT(5, GEN8_PPAT_WB | GEN8_PPAT_LLCELLC | GEN8_PPAT_AGE(1)) |
 	      GEN8_PPAT(6, GEN8_PPAT_WB | GEN8_PPAT_LLCELLC | GEN8_PPAT_AGE(2)) |
 	      GEN8_PPAT(7, GEN8_PPAT_WB | GEN8_PPAT_LLCELLC | GEN8_PPAT_AGE(3));
 	if (!USES_PPGTT(dev_priv->dev))
 		/* Spec: "For GGTT, there is NO pat_sel[2:0] from the entry,
 		 * so RTL will always use the value corresponding to
 		 * pat_sel = 000".
 		 * So let's disable cache for GGTT to avoid screen corruptions.
 		 * MOCS still can be used though.
 		 * - System agent ggtt writes (i.e. cpu gtt mmaps) already work
 		 * before this patch, i.e. the same uncached + snooping access
 		 * like on gen6/7 seems to be in effect.
 		 * - So this just fixes blitter/render access. Again it looks
 		 * like it's not just uncached access, but uncached + snooping.
 		 * So we can still hold onto all our assumptions wrt cpu
 		 * clflushing on LLC machines.
 		 */
 		pat = GEN8_PPAT(0, GEN8_PPAT_UC);
 	/* XXX: spec defines this as 2 distinct registers. It's unclear if a 64b
 	 * write would work. */
 	I915_WRITE(GEN8_PRIVATE_PAT_LO, pat);
 	I915_WRITE(GEN8_PRIVATE_PAT_HI, pat >> 32);
+}
 static void chv_setup_private_ppat(struct drm_i915_private *dev_priv)
+{
 	uint64_t pat;
 	/*
 	 * Map WB on BDW to snooped on CHV.
+	 *
 	 * Only the snoop bit has meaning for CHV, the rest is
 	 * ignored.
+	 *
 	 * The hardware will never snoop for certain types of accesses:
 	 * - CPU GTT (GMADR->GGTT->no snoop->memory)
 	 * - PPGTT page tables
 	 * - some other special cycles
+	 *
 	 * As with BDW, we also need to consider the following for GT accesses:
 	 * "For GGTT, there is NO pat_sel[2:0] from the entry,
 	 * so RTL will always use the value corresponding to
 	 * pat_sel = 000".
 	 * Which means we must set the snoop bit in PAT entry 0
 	 * in order to keep the global status page working.
 	 */
 	pat = GEN8_PPAT(0, CHV_PPAT_SNOOP) |
 	      GEN8_PPAT(1, 0) |
 	      GEN8_PPAT(2, 0) |
 	      GEN8_PPAT(3, 0) |
 	      GEN8_PPAT(4, CHV_PPAT_SNOOP) |
 	      GEN8_PPAT(5, CHV_PPAT_SNOOP) |
 	      GEN8_PPAT(6, CHV_PPAT_SNOOP) |
 	      GEN8_PPAT(7, CHV_PPAT_SNOOP);
 	I915_WRITE(GEN8_PRIVATE_PAT_LO, pat);
 	I915_WRITE(GEN8_PRIVATE_PAT_HI, pat >> 32);
+}
 static int gen8_gmch_probe(struct drm_device *dev,
 			   u64 *gtt_total,
 			   size_t *stolen,
 			   phys_addr_t *mappable_base,
 			   u64 *mappable_end)
+{
 	struct drm_i915_private *dev_priv = dev->dev_private;
 	u64 gtt_size;
 	u16 snb_gmch_ctl;
 	int ret;
 	/* TODO: We're not aware of mappable constraints on gen8 yet */
 	*mappable_base = pci_resource_start(dev->pdev, 2);
 	*mappable_end = pci_resource_len(dev->pdev, 2);
 #ifndef __NetBSD__
 	if (!pci_set_dma_mask(dev->pdev, DMA_BIT_MASK(39)))
 		pci_set_consistent_dma_mask(dev->pdev, DMA_BIT_MASK(39));
 #endif
 	pci_read_config_word(dev->pdev, SNB_GMCH_CTRL, &snb_gmch_ctl);
 	if (INTEL_INFO(dev)->gen >= 9) {
 		*stolen = gen9_get_stolen_size(snb_gmch_ctl);
 		gtt_size = gen8_get_total_gtt_size(snb_gmch_ctl);
 	} else if (IS_CHERRYVIEW(dev)) {
 		*stolen = chv_get_stolen_size(snb_gmch_ctl);
 		gtt_size = chv_get_total_gtt_size(snb_gmch_ctl);
 	} else {
 		*stolen = gen8_get_stolen_size(snb_gmch_ctl);
 		gtt_size = gen8_get_total_gtt_size(snb_gmch_ctl);
+	}
 	*gtt_total = (gtt_size / sizeof(gen8_pte_t)) << PAGE_SHIFT;
 	if (IS_CHERRYVIEW(dev) || IS_BROXTON(dev))
 		chv_setup_private_ppat(dev_priv);
 	else
 		bdw_setup_private_ppat(dev_priv);
 	ret = ggtt_probe_common(dev, gtt_size);
 	dev_priv->gtt.base.clear_range = gen8_ggtt_clear_range;
 	dev_priv->gtt.base.insert_entries = gen8_ggtt_insert_entries;
 	dev_priv->gtt.base.bind_vma = ggtt_bind_vma;
 	dev_priv->gtt.base.unbind_vma = ggtt_unbind_vma;
 	/* XXX 39-bit addresses?  Really?  See pci_set_dma_mask above...  */
 	dev_priv->gtt.max_paddr = __BITS(38, 0);
 	return ret;
+}
 static int gen6_gmch_probe(struct drm_device *dev,
 			   u64 *gtt_total,
 			   size_t *stolen,
 			   phys_addr_t *mappable_base,
 			   u64 *mappable_end)
+{
 	struct drm_i915_private *dev_priv = dev->dev_private;
 	unsigned int gtt_size;
 	u16 snb_gmch_ctl;
 	int ret;
 	*mappable_base = pci_resource_start(dev->pdev, 2);
 	*mappable_end = pci_resource_len(dev->pdev, 2);
 	/* 64/512MB is the current min/max we actually know of, but this is just
 	 * a coarse sanity check.
 	 */
 	if ((*mappable_end < (64<<20) || (*mappable_end > (512<<20)))) {
 		DRM_ERROR("Unknown GMADR size (%llx)\n",
 			  dev_priv->gtt.mappable_end);
 		return -ENXIO;
+	}
 #ifndef __NetBSD__
 	if (!pci_set_dma_mask(dev->pdev, DMA_BIT_MASK(40)))
 		pci_set_consistent_dma_mask(dev->pdev, DMA_BIT_MASK(40));
 #endif
 	pci_read_config_word(dev->pdev, SNB_GMCH_CTRL, &snb_gmch_ctl);
 	*stolen = gen6_get_stolen_size(snb_gmch_ctl);
 	gtt_size = gen6_get_total_gtt_size(snb_gmch_ctl);
 	*gtt_total = (gtt_size / sizeof(gen6_pte_t)) << PAGE_SHIFT;
 	ret = ggtt_probe_common(dev, gtt_size);
 	dev_priv->gtt.base.clear_range = gen6_ggtt_clear_range;
 	dev_priv->gtt.base.insert_entries = gen6_ggtt_insert_entries;
 	dev_priv->gtt.base.bind_vma = ggtt_bind_vma;
 	dev_priv->gtt.base.unbind_vma = ggtt_unbind_vma;
 	dev_priv->gtt.max_paddr = __BITS(39, 0);
 	return ret;
+}
 static void gen6_gmch_remove(struct i915_address_space *vm)
+{
 	struct i915_gtt *gtt = container_of(vm, struct i915_gtt, base);
 #ifdef __NetBSD__
 	bus_space_unmap(gtt->bst, gtt->bsh, gtt->size);
 #else
 	iounmap(gtt->gsm);
 #endif
 	free_scratch_page(vm->dev, vm->scratch_page);
+}
 static int i915_gmch_probe(struct drm_device *dev,
 			   u64 *gtt_total,
 			   size_t *stolen,
 			   phys_addr_t *mappable_base,
 			   u64 *mappable_end)
+{
 	struct drm_i915_private *dev_priv = dev->dev_private;
 	int ret;
 	ret = intel_gmch_probe(dev_priv->bridge_dev, dev_priv->dev->pdev, NULL);
 	if (!ret) {
 		DRM_ERROR("failed to set up gmch\n");
 		return -EIO;
+	}
 	intel_gtt_get(gtt_total, stolen, mappable_base, mappable_end);
 	dev_priv->gtt.do_idle_maps = needs_idle_maps(dev_priv->dev);
 	dev_priv->gtt.base.insert_entries = i915_ggtt_insert_entries;
 	dev_priv->gtt.base.clear_range = i915_ggtt_clear_range;
 	dev_priv->gtt.base.bind_vma = ggtt_bind_vma;
 	dev_priv->gtt.base.unbind_vma = ggtt_unbind_vma;
 	if (unlikely(dev_priv->gtt.do_idle_maps))
 		DRM_INFO("applying Ironlake quirks for intel_iommu\n");
 	if (INTEL_INFO(dev)->gen <= 2)
 		dev_priv->gtt.max_paddr = __BITS(29, 0);
 	else if ((INTEL_INFO(dev)->gen <= 3) ||
 	    IS_BROADWATER(dev) || IS_CRESTLINE(dev))
 		dev_priv->gtt.max_paddr = __BITS(31, 0);
 	else if (INTEL_INFO(dev)->gen <= 5)
 		dev_priv->gtt.max_paddr = __BITS(35, 0);
 	else
 		dev_priv->gtt.max_paddr = __BITS(39, 0);
 	return 0;
+}
 static void i915_gmch_remove(struct i915_address_space *vm)
+{
 	intel_gmch_remove();
+}
 int i915_gem_gtt_init(struct drm_device *dev)
+{
 	struct drm_i915_private *dev_priv = dev->dev_private;
 	struct i915_gtt *gtt = &dev_priv->gtt;
 	int ret;
 	if (INTEL_INFO(dev)->gen <= 5) {
 		gtt->gtt_probe = i915_gmch_probe;
 		gtt->base.cleanup = i915_gmch_remove;
 	} else if (INTEL_INFO(dev)->gen < 8) {
 		gtt->gtt_probe = gen6_gmch_probe;
 		gtt->base.cleanup = gen6_gmch_remove;
 		if (IS_HASWELL(dev) && dev_priv->ellc_size)
 			gtt->base.pte_encode = iris_pte_encode;
 		else if (IS_HASWELL(dev))
 			gtt->base.pte_encode = hsw_pte_encode;
 		else if (IS_VALLEYVIEW(dev))
 			gtt->base.pte_encode = byt_pte_encode;
 		else if (INTEL_INFO(dev)->gen >= 7)
 			gtt->base.pte_encode = ivb_pte_encode;
 		else
 			gtt->base.pte_encode = snb_pte_encode;
 	} else {
 		dev_priv->gtt.gtt_probe = gen8_gmch_probe;
 		dev_priv->gtt.base.cleanup = gen6_gmch_remove;
+	}
 	gtt->base.dev = dev;
 	ret = gtt->gtt_probe(dev, &gtt->base.total, &gtt->stolen_size,
 			     &gtt->mappable_base, &gtt->mappable_end);
 	if (ret)
 		return ret;
 #ifdef __NetBSD__
 	dev_priv->gtt.pgfl = x86_select_freelist(dev_priv->gtt.max_paddr);
 	ret = drm_limit_dma_space(dev, 0, dev_priv->gtt.max_paddr);
 	if (ret) {
 		DRM_ERROR("Unable to limit DMA paddr allocations: %d!\n", ret);
 		gtt->base.cleanup(&gtt->base);
 		return ret;
+	}
 #endif
 	/* GMADR is the PCI mmio aperture into the global GTT. */
 	DRM_INFO("Memory usable by graphics device = %lluM\n",
 		 gtt->base.total >> 20);
 	DRM_DEBUG_DRIVER("GMADR size = %lldM\n", gtt->mappable_end >> 20);
 	DRM_DEBUG_DRIVER("GTT stolen size = %zdM\n", gtt->stolen_size >> 20);
 #ifdef CONFIG_INTEL_IOMMU
 	if (intel_iommu_gfx_mapped)
 		DRM_INFO("VT-d active for gfx access\n");
 #endif
 	/*
 	 * i915.enable_ppgtt is read-only, so do an early pass to validate the
 	 * user's requested state against the hardware/driver capabilities.  We
 	 * do this now so that we can print out any log messages once rather
 	 * than every time we check intel_enable_ppgtt().
 	 */
 	i915.enable_ppgtt = sanitize_enable_ppgtt(dev, i915.enable_ppgtt);
 	DRM_DEBUG_DRIVER("ppgtt mode: %i\n", i915.enable_ppgtt);
 	return 0;
+}
 void i915_gem_restore_gtt_mappings(struct drm_device *dev)
+{
 	struct drm_i915_private *dev_priv = dev->dev_private;
 	struct drm_i915_gem_object *obj;
 	struct i915_address_space *vm;
 	struct i915_vma *vma;
 	bool flush;
 	i915_check_and_clear_faults(dev);
 	/* First fill our portion of the GTT with scratch pages */
 	dev_priv->gtt.base.clear_range(&dev_priv->gtt.base,
 				       dev_priv->gtt.base.start,
 				       dev_priv->gtt.base.total,
 				       true);
 	/* Cache flush objects bound into GGTT and rebind them. */
 	vm = &dev_priv->gtt.base;
 	list_for_each_entry(obj, &dev_priv->mm.bound_list, global_list) {
 		flush = false;
 		list_for_each_entry(vma, &obj->vma_list, vma_link) {
 			if (vma->vm != vm)
 				continue;
 			WARN_ON(i915_vma_bind(vma, obj->cache_level,
 					      PIN_UPDATE));
 			flush = true;
+		}
 		if (flush)
 			i915_gem_clflush_object(obj, obj->pin_display);
+	}
 	if (INTEL_INFO(dev)->gen >= 8) {
 		if (IS_CHERRYVIEW(dev) || IS_BROXTON(dev))
 			chv_setup_private_ppat(dev_priv);
 		else
 			bdw_setup_private_ppat(dev_priv);
 		return;
+	}
 	if (USES_PPGTT(dev)) {
 		list_for_each_entry(vm, &dev_priv->vm_list, global_link) {
 			/* TODO: Perhaps it shouldn't be gen6 specific */
 			struct i915_hw_ppgtt *ppgtt =
 					container_of(vm, struct i915_hw_ppgtt,
 						     base);
 			if (i915_is_ggtt(vm))
 				ppgtt = dev_priv->mm.aliasing_ppgtt;
 			gen6_write_page_range(dev_priv, &ppgtt->pd,
 , ppgtt->base.total);
+		}
+	}
 	i915_ggtt_flush(dev_priv);
+}
 static struct i915_vma *
 __i915_gem_vma_create(struct drm_i915_gem_object *obj,
 		      struct i915_address_space *vm,
 		      const struct i915_ggtt_view *ggtt_view)
+{
 	struct i915_vma *vma;
 	if (WARN_ON(i915_is_ggtt(vm) != !!ggtt_view))
 		return ERR_PTR(-EINVAL);
 	vma = kmem_cache_zalloc(to_i915(obj->base.dev)->vmas, GFP_KERNEL);
 	if (vma == NULL)
 		return ERR_PTR(-ENOMEM);
 	INIT_LIST_HEAD(&vma->vma_link);
 	INIT_LIST_HEAD(&vma->mm_list);
 	INIT_LIST_HEAD(&vma->exec_list);
 	vma->vm = vm;
 	vma->obj = obj;
 	if (i915_is_ggtt(vm))
 		vma->ggtt_view = *ggtt_view;
 	list_add_tail(&vma->vma_link, &obj->vma_list);
 	if (!i915_is_ggtt(vm))
 		i915_ppgtt_get(i915_vm_to_ppgtt(vm));
 	return vma;
+}
 struct i915_vma *
 i915_gem_obj_lookup_or_create_vma(struct drm_i915_gem_object *obj,
 				  struct i915_address_space *vm)
+{
 	struct i915_vma *vma;
 	vma = i915_gem_obj_to_vma(obj, vm);
 	if (!vma)
 		vma = __i915_gem_vma_create(obj, vm,
 					    i915_is_ggtt(vm) ? &i915_ggtt_view_normal : NULL);
 	return vma;
+}
 struct i915_vma *
 i915_gem_obj_lookup_or_create_ggtt_vma(struct drm_i915_gem_object *obj,
 				       const struct i915_ggtt_view *view)
+{
 	struct i915_address_space *ggtt = i915_obj_to_ggtt(obj);
 	struct i915_vma *vma;
 	if (WARN_ON(!view))
 		return ERR_PTR(-EINVAL);
 	vma = i915_gem_obj_to_ggtt_view(obj, view);
 	if (IS_ERR(vma))
 		return vma;
 	if (!vma)
 		vma = __i915_gem_vma_create(obj, ggtt, view);
 	return vma;
+}
 static struct scatterlist *
 rotate_pages(dma_addr_t *in, unsigned int offset,
 	     unsigned int width, unsigned int height,
 	     struct sg_table *st, struct scatterlist *sg)
+{
 #ifdef __NetBSD__
 	panic("XXX");
 #else
 	unsigned int column, row;
 	unsigned int src_idx;
 	if (!sg) {
 		st->nents = 0;
 		sg = st->sgl;
+	}
 	for (column = 0; column < width; column++) {
 		src_idx = width * (height - 1) + column;
 		for (row = 0; row < height; row++) {
 			st->nents++;
 			/* We don't need the pages, but need to initialize
 			 * the entries so the sg list can be happily traversed.
 			 * The only thing we need are DMA addresses.
 			 */
 			sg_set_page(sg, NULL, PAGE_SIZE, 0);
 			sg_dma_address(sg) = in[offset + src_idx];
 			sg_dma_len(sg) = PAGE_SIZE;
 			sg = sg_next(sg);
 			src_idx -= width;
+		}
+	}
 	return sg;
 #endif
+}
 static struct sg_table *
 intel_rotate_fb_obj_pages(struct i915_ggtt_view *ggtt_view,
 			  struct drm_i915_gem_object *obj)
+{
 #ifdef __NetBSD__
 	panic("XXX");
 #else
 	struct intel_rotation_info *rot_info = &ggtt_view->rotation_info;
 	unsigned int size_pages = rot_info->size >> PAGE_SHIFT;
 	unsigned int size_pages_uv;
 	struct sg_page_iter sg_iter;
 	unsigned long i;
 	dma_addr_t *page_addr_list;
 	struct sg_table *st;
 	unsigned int uv_start_page;
 	struct scatterlist *sg;
 	int ret = -ENOMEM;
 	/* Allocate a temporary list of source pages for random access. */
 	page_addr_list = drm_malloc_ab(obj->base.size / PAGE_SIZE,
 				       sizeof(dma_addr_t));
 	if (!page_addr_list)
 		return ERR_PTR(ret);
 	/* Account for UV plane with NV12. */
 	if (rot_info->pixel_format == DRM_FORMAT_NV12)
 		size_pages_uv = rot_info->size_uv >> PAGE_SHIFT;
 	else
 		size_pages_uv = 0;
 	/* Allocate target SG list. */
 	st = kmalloc(sizeof(*st), GFP_KERNEL);
 	if (!st)
 		goto err_st_alloc;
 	ret = sg_alloc_table(st, size_pages + size_pages_uv, GFP_KERNEL);
 	if (ret)
 		goto err_sg_alloc;
 	/* Populate source page list from the object. */
 	i = 0;
 	for_each_sg_page(obj->pages->sgl, &sg_iter, obj->pages->nents, 0) {
 		page_addr_list[i] = sg_page_iter_dma_address(&sg_iter);
 		i++;
+	}
 	/* Rotate the pages. */
 	sg = rotate_pages(page_addr_list, 0,
 		     rot_info->width_pages, rot_info->height_pages,
 		     st, NULL);
 	/* Append the UV plane if NV12. */
 	if (rot_info->pixel_format == DRM_FORMAT_NV12) {
 		uv_start_page = size_pages;
 		/* Check for tile-row un-alignment. */
 		if (offset_in_page(rot_info->uv_offset))
 			uv_start_page--;
 		rot_info->uv_start_page = uv_start_page;
 		rotate_pages(page_addr_list, uv_start_page,
 			     rot_info->width_pages_uv,
 			     rot_info->height_pages_uv,
 			     st, sg);
+	}
 	DRM_DEBUG_KMS(
 		      "Created rotated page mapping for object size %zu (pitch=%u, height=%u, pixel_format=0x%x, %ux%u tiles, %u pages (%u plane 0)).\n",
 		      obj->base.size, rot_info->pitch, rot_info->height,
 		      rot_info->pixel_format, rot_info->width_pages,
 		      rot_info->height_pages, size_pages + size_pages_uv,
 		      size_pages);
 	drm_free_large(page_addr_list);
 	return st;
 err_sg_alloc:
 	kfree(st);
 err_st_alloc:
 	drm_free_large(page_addr_list);
 	DRM_DEBUG_KMS(
 		      "Failed to create rotated mapping for object size %zu! (%d) (pitch=%u, height=%u, pixel_format=0x%x, %ux%u tiles, %u pages (%u plane 0))\n",
 		      obj->base.size, ret, rot_info->pitch, rot_info->height,
 		      rot_info->pixel_format, rot_info->width_pages,
 		      rot_info->height_pages, size_pages + size_pages_uv,
 		      size_pages);
 	return ERR_PTR(ret);
 #endif
+}
 static struct sg_table *
 intel_partial_pages(const struct i915_ggtt_view *view,
 		    struct drm_i915_gem_object *obj)
+{
 #ifdef __NetBSD__
 	panic("XXX");
 #else
 	struct sg_table *st;
 	struct scatterlist *sg;
 	struct sg_page_iter obj_sg_iter;
 	int ret = -ENOMEM;
 	st = kmalloc(sizeof(*st), GFP_KERNEL);
 	if (!st)
 		goto err_st_alloc;
 	ret = sg_alloc_table(st, view->params.partial.size, GFP_KERNEL);
 	if (ret)
 		goto err_sg_alloc;
 	sg = st->sgl;
 	st->nents = 0;
 	for_each_sg_page(obj->pages->sgl, &obj_sg_iter, obj->pages->nents,
 		view->params.partial.offset)
+	{
 		if (st->nents >= view->params.partial.size)
 			break;
 		sg_set_page(sg, NULL, PAGE_SIZE, 0);
 		sg_dma_address(sg) = sg_page_iter_dma_address(&obj_sg_iter);
 		sg_dma_len(sg) = PAGE_SIZE;
 		sg = sg_next(sg);
 		st->nents++;
+	}
 	return st;
 err_sg_alloc:
 	kfree(st);
 err_st_alloc:
 	return ERR_PTR(ret);
 #endif
+}
 static int
 i915_get_ggtt_vma_pages(struct i915_vma *vma)
+{
 	int ret = 0;
 	if (vma->ggtt_view.pages)
 		return 0;
 	if (vma->ggtt_view.type == I915_GGTT_VIEW_NORMAL)
 		vma->ggtt_view.pages = vma->obj->pages;
 	else if (vma->ggtt_view.type == I915_GGTT_VIEW_ROTATED)
 		vma->ggtt_view.pages =
 			intel_rotate_fb_obj_pages(&vma->ggtt_view, vma->obj);
 	else if (vma->ggtt_view.type == I915_GGTT_VIEW_PARTIAL)
 		vma->ggtt_view.pages =
 			intel_partial_pages(&vma->ggtt_view, vma->obj);
 	else
 		WARN_ONCE(1, "GGTT view %u not implemented!\n",
 			  vma->ggtt_view.type);
 	if (!vma->ggtt_view.pages) {
 		DRM_ERROR("Failed to get pages for GGTT view type %u!\n",
 			  vma->ggtt_view.type);
 		ret = -EINVAL;
 	} else if (IS_ERR(vma->ggtt_view.pages)) {
 		ret = PTR_ERR(vma->ggtt_view.pages);
 		vma->ggtt_view.pages = NULL;
 		DRM_ERROR("Failed to get pages for VMA view type %u (%d)!\n",
 			  vma->ggtt_view.type, ret);
+	}
 	return ret;
+}
 /**
  * i915_vma_bind - Sets up PTEs for an VMA in it's corresponding address space.
  * @vma: VMA to map
  * @cache_level: mapping cache level
  * @flags: flags like global or local mapping
+ *
  * DMA addresses are taken from the scatter-gather table of this object (or of
  * this VMA in case of non-default GGTT views) and PTE entries set up.
  * Note that DMA addresses are also the only part of the SG table we care about.
  */
 int i915_vma_bind(struct i915_vma *vma, enum i915_cache_level cache_level,
 		  u32 flags)
+{
 	int ret;
 	u32 bind_flags;
 	if (WARN_ON(flags == 0))
 		return -EINVAL;
 	bind_flags = 0;
 	if (flags & PIN_GLOBAL)
 		bind_flags |= GLOBAL_BIND;
 	if (flags & PIN_USER)
 		bind_flags |= LOCAL_BIND;
 	if (flags & PIN_UPDATE)
 		bind_flags |= vma->bound;
 	else
 		bind_flags &= ~vma->bound;
 	if (bind_flags == 0)
 		return 0;
 	if (vma->bound == 0 && vma->vm->allocate_va_range) {
 		trace_i915_va_alloc(vma->vm,
 				    vma->node.start,
 				    vma->node.size,
 				    VM_TO_TRACE_NAME(vma->vm));
 		/* XXX: i915_vma_pin() will fix this +- hack */
 		vma->pin_count++;
 		ret = vma->vm->allocate_va_range(vma->vm,
 						 vma->node.start,
 						 vma->node.size);
 		vma->pin_count--;
 		if (ret)
 			return ret;
+	}
 	ret = vma->vm->bind_vma(vma, cache_level, bind_flags);
 	if (ret)
 		return ret;
 	vma->bound |= bind_flags;
 	return 0;
+}
 /**
  * i915_ggtt_view_size - Get the size of a GGTT view.
  * @obj: Object the view is of.
  * @view: The view in question.
+ *
  * @return The size of the GGTT view in bytes.
  */
 size_t
 i915_ggtt_view_size(struct drm_i915_gem_object *obj,
 		    const struct i915_ggtt_view *view)
+{
 	if (view->type == I915_GGTT_VIEW_NORMAL) {
 		return obj->base.size;
 	} else if (view->type == I915_GGTT_VIEW_ROTATED) {
 		return view->rotation_info.size;
 	} else if (view->type == I915_GGTT_VIEW_PARTIAL) {
 		return view->params.partial.size << PAGE_SHIFT;
 	} else {
 		WARN_ONCE(1, "GGTT view %u not implemented!\n", view->type);
 		return obj->base.size;
+	}
+}

 @@ -1,776 +1,784 @@
-/*	$NetBSD: i915_gem_stolen.c,v 1.5 2018/08/27 04:58:23 riastradh Exp $	*/
+/*	$NetBSD: i915_gem_stolen.c,v 1.6 2018/08/27 06:08:25 riastradh Exp $	*/
 /*
  * Copyright © 2008-2012 Intel Corporation
+ *
  * Permission is hereby granted, free of charge, to any person obtaining a
  * copy of this software and associated documentation files (the "Software"),
  * to deal in the Software without restriction, including without limitation
  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
  * and/or sell copies of the Software, and to permit persons to whom the
  * Software is furnished to do so, subject to the following conditions:
+ *
  * The above copyright notice and this permission notice (including the next
  * paragraph) shall be included in all copies or substantial portions of the
  * Software.
+ *
  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
  * IN THE SOFTWARE.
+ *
  * Authors:
  *    Eric Anholt <eric@anholt.net>
  *    Chris Wilson <chris@chris-wilson.co.uk>
+ *
  */
 #include <sys/cdefs.h>
-__KERNEL_RCSID(0, "$NetBSD: i915_gem_stolen.c,v 1.5 2018/08/27 04:58:23 riastradh Exp $");
+__KERNEL_RCSID(0, "$NetBSD: i915_gem_stolen.c,v 1.6 2018/08/27 06:08:25 riastradh Exp $");
 #include <linux/printk.h>
 #include <linux/err.h>
 #include <drm/drmP.h>
 #include <drm/i915_drm.h>
 #include "i915_drv.h"
 #define KB(x) ((x) * 1024)
 #define MB(x) (KB(x) * 1024)
 /*
  * The BIOS typically reserves some of the system's memory for the exclusive
  * use of the integrated graphics. This memory is no longer available for
  * use by the OS and so the user finds that his system has less memory
  * available than he put in. We refer to this memory as stolen.
+ *
  * The BIOS will allocate its framebuffer from the stolen memory. Our
  * goal is try to reuse that object for our own fbcon which must always
  * be available for panics. Anything else we can reuse the stolen memory
  * for is a boon.
  */
 int i915_gem_stolen_insert_node_in_range(struct drm_i915_private *dev_priv,
 					 struct drm_mm_node *node, u64 size,
 					 unsigned alignment, u64 start, u64 end)
+{
 	int ret;
 	if (!drm_mm_initialized(&dev_priv->mm.stolen))
 		return -ENODEV;
 	/* See the comment at the drm_mm_init() call for more about this check.
 	 * WaSkipStolenMemoryFirstPage:bdw,chv (incomplete) */
 	if (INTEL_INFO(dev_priv)->gen == 8 && start < 4096)
 		start = 4096;
 	mutex_lock(&dev_priv->mm.stolen_lock);
 	ret = drm_mm_insert_node_in_range(&dev_priv->mm.stolen, node, size,
 					  alignment, start, end,
 					  DRM_MM_SEARCH_DEFAULT);
 	mutex_unlock(&dev_priv->mm.stolen_lock);
 	return ret;
+}
 int i915_gem_stolen_insert_node(struct drm_i915_private *dev_priv,
 				struct drm_mm_node *node, u64 size,
 				unsigned alignment)
+{
 	return i915_gem_stolen_insert_node_in_range(dev_priv, node, size,
 					alignment, 0,
 					dev_priv->gtt.stolen_usable_size);
+}
 void i915_gem_stolen_remove_node(struct drm_i915_private *dev_priv,
 				 struct drm_mm_node *node)
+{
 	mutex_lock(&dev_priv->mm.stolen_lock);
 	drm_mm_remove_node(node);
 	mutex_unlock(&dev_priv->mm.stolen_lock);
+}
 static unsigned long i915_stolen_to_physical(struct drm_device *dev)
+{
 #ifndef __NetBSD__
 	struct drm_i915_private *dev_priv = dev->dev_private;
 	struct resource *r;
 #endif
 	u32 base;
 	/* Almost universally we can find the Graphics Base of Stolen Memory
 	 * at offset 0x5c in the igfx configuration space. On a few (desktop)
 	 * machines this is also mirrored in the bridge device at different
 	 * locations, or in the MCHBAR.
+	 *
 	 * On 865 we just check the TOUD register.
+	 *
 	 * On 830/845/85x the stolen memory base isn't available in any
 	 * register. We need to calculate it as TOM-TSEG_SIZE-stolen_size.
+	 *
 	 */
 	base = 0;
 	if (INTEL_INFO(dev)->gen >= 3) {
 #ifndef __NetBSD__		/* XXX disable this for now */
 		/* Read Graphics Base of Stolen Memory directly */
 		pci_read_config_dword(dev->pdev, 0x5c, &base);
 		base &= ~((1<<20) - 1);
 #endif
 	} else if (IS_I865G(dev)) {
 		u32 tseg_size = 0;
 		u16 toud = 0;
 		u8 tmp;
 		pci_bus_read_config_byte(dev->pdev->bus, PCI_DEVFN(0, 0),
 					 I845_ESMRAMC, &tmp);
 		if (tmp & TSEG_ENABLE) {
 			switch (tmp & I845_TSEG_SIZE_MASK) {
 			case I845_TSEG_SIZE_512K:
 				tseg_size = KB(512);
 				break;
 			case I845_TSEG_SIZE_1M:
 				tseg_size = MB(1);
 				break;
+			}
+		}
 		pci_bus_read_config_word(dev->pdev->bus, PCI_DEVFN(0, 0),
 					 I865_TOUD, &toud);
 		base = (toud << 16) + tseg_size;
 	} else if (IS_I85X(dev)) {
 		u32 tseg_size = 0;
 		u32 tom;
 		u8 tmp;
 		pci_bus_read_config_byte(dev->pdev->bus, PCI_DEVFN(0, 0),
 					 I85X_ESMRAMC, &tmp);
 		if (tmp & TSEG_ENABLE)
 			tseg_size = MB(1);
 		pci_bus_read_config_byte(dev->pdev->bus, PCI_DEVFN(0, 1),
 					 I85X_DRB3, &tmp);
 		tom = tmp * MB(32);
 		base = tom - tseg_size - dev_priv->gtt.stolen_size;
 	} else if (IS_845G(dev)) {
 		u32 tseg_size = 0;
 		u32 tom;
 		u8 tmp;
 		pci_bus_read_config_byte(dev->pdev->bus, PCI_DEVFN(0, 0),
 					 I845_ESMRAMC, &tmp);
 		if (tmp & TSEG_ENABLE) {
 			switch (tmp & I845_TSEG_SIZE_MASK) {
 			case I845_TSEG_SIZE_512K:
 				tseg_size = KB(512);
 				break;
 			case I845_TSEG_SIZE_1M:
 				tseg_size = MB(1);
 				break;
+			}
+		}
 		pci_bus_read_config_byte(dev->pdev->bus, PCI_DEVFN(0, 0),
 					 I830_DRB3, &tmp);
 		tom = tmp * MB(32);
 		base = tom - tseg_size - dev_priv->gtt.stolen_size;
 	} else if (IS_I830(dev)) {
 		u32 tseg_size = 0;
 		u32 tom;
 		u8 tmp;
 		pci_bus_read_config_byte(dev->pdev->bus, PCI_DEVFN(0, 0),
 					 I830_ESMRAMC, &tmp);
 		if (tmp & TSEG_ENABLE) {
 			if (tmp & I830_TSEG_SIZE_1M)
 				tseg_size = MB(1);
 			else
 				tseg_size = KB(512);
+		}
 		pci_bus_read_config_byte(dev->pdev->bus, PCI_DEVFN(0, 0),
 					 I830_DRB3, &tmp);
 		tom = tmp * MB(32);
 		base = tom - tseg_size - dev_priv->gtt.stolen_size;
+	}
 	if (base == 0)
 		return 0;
 	/* make sure we don't clobber the GTT if it's within stolen memory */
 	if (INTEL_INFO(dev)->gen <= 4 && !IS_G33(dev) && !IS_G4X(dev)) {
 		struct {
 			u32 start, end;
 		} stolen[2] = {
 			{ .start = base, .end = base + dev_priv->gtt.stolen_size, },
 			{ .start = base, .end = base + dev_priv->gtt.stolen_size, },
 		};
 		u64 gtt_start, gtt_end;
 		gtt_start = I915_READ(PGTBL_CTL);
 		if (IS_GEN4(dev))
 			gtt_start = (gtt_start & PGTBL_ADDRESS_LO_MASK) |
 				(gtt_start & PGTBL_ADDRESS_HI_MASK) << 28;
 		else
 			gtt_start &= PGTBL_ADDRESS_LO_MASK;
 		gtt_end = gtt_start + gtt_total_entries(dev_priv->gtt) * 4;
 		if (gtt_start >= stolen[0].start && gtt_start < stolen[0].end)
 			stolen[0].end = gtt_start;
 		if (gtt_end > stolen[1].start && gtt_end <= stolen[1].end)
 			stolen[1].start = gtt_end;
 		/* pick the larger of the two chunks */
 		if (stolen[0].end - stolen[0].start >
 		    stolen[1].end - stolen[1].start) {
 			base = stolen[0].start;
 			dev_priv->gtt.stolen_size = stolen[0].end - stolen[0].start;
 		} else {
 			base = stolen[1].start;
 			dev_priv->gtt.stolen_size = stolen[1].end - stolen[1].start;
+		}
 		if (stolen[0].start != stolen[1].start ||
 		    stolen[0].end != stolen[1].end) {
 			DRM_DEBUG_KMS("GTT within stolen memory at 0x%llx-0x%llx\n",
 				      (unsigned long long) gtt_start,
 				      (unsigned long long) gtt_end - 1);
 			DRM_DEBUG_KMS("Stolen memory adjusted to 0x%x-0x%x\n",
 				      base, base + (u32) dev_priv->gtt.stolen_size - 1);
+		}
+	}
 #ifndef __NetBSD__		/* XXX */
 	/* Verify that nothing else uses this physical address. Stolen
 	 * memory should be reserved by the BIOS and hidden from the
 	 * kernel. So if the region is already marked as busy, something
 	 * is seriously wrong.
 	 */
 	r = devm_request_mem_region(dev->dev, base, dev_priv->gtt.stolen_size,
 				    "Graphics Stolen Memory");
 	if (r == NULL) {
 		/*
 		 * One more attempt but this time requesting region from
 		 * base + 1, as we have seen that this resolves the region
 		 * conflict with the PCI Bus.
 		 * This is a BIOS w/a: Some BIOS wrap stolen in the root
 		 * PCI bus, but have an off-by-one error. Hence retry the
 		 * reservation starting from 1 instead of 0.
 		 */
 		r = devm_request_mem_region(dev->dev, base + 1,
 					    dev_priv->gtt.stolen_size - 1,
 					    "Graphics Stolen Memory");
 		/*
 		 * GEN3 firmware likes to smash pci bridges into the stolen
 		 * range. Apparently this works.
 		 */
 		if (r == NULL && !IS_GEN3(dev)) {
 			DRM_ERROR("conflict detected with stolen region: [0x%08x - 0x%08x]\n",
 				  base, base + (uint32_t)dev_priv->gtt.stolen_size);
 			base = 0;
+		}
+	}
 #endif
 	return base;
+}
 void i915_gem_cleanup_stolen(struct drm_device *dev)
+{
 	struct drm_i915_private *dev_priv = dev->dev_private;
 	if (!drm_mm_initialized(&dev_priv->mm.stolen))
 		return;
 	drm_mm_takedown(&dev_priv->mm.stolen);
+}
 static void g4x_get_stolen_reserved(struct drm_i915_private *dev_priv,
 				    unsigned long *base, unsigned long *size)
+{
 	uint32_t reg_val = I915_READ(IS_GM45(dev_priv) ?
 				     CTG_STOLEN_RESERVED :
 				     ELK_STOLEN_RESERVED);
 	unsigned long stolen_top = dev_priv->mm.stolen_base +
 		dev_priv->gtt.stolen_size;
 	*base = (reg_val & G4X_STOLEN_RESERVED_ADDR2_MASK) << 16;
 	WARN_ON((reg_val & G4X_STOLEN_RESERVED_ADDR1_MASK) < *base);
 	/* On these platforms, the register doesn't have a size field, so the
 	 * size is the distance between the base and the top of the stolen
 	 * memory. We also have the genuine case where base is zero and there's
 	 * nothing reserved. */
 	if (*base == 0)
 		*size = 0;
 	else
 		*size = stolen_top - *base;
+}
 static void gen6_get_stolen_reserved(struct drm_i915_private *dev_priv,
 				     unsigned long *base, unsigned long *size)
+{
 	uint32_t reg_val = I915_READ(GEN6_STOLEN_RESERVED);
 	*base = reg_val & GEN6_STOLEN_RESERVED_ADDR_MASK;
 	switch (reg_val & GEN6_STOLEN_RESERVED_SIZE_MASK) {
 	case GEN6_STOLEN_RESERVED_1M:
 		*size = 1024 * 1024;
 		break;
 	case GEN6_STOLEN_RESERVED_512K:
 		*size = 512 * 1024;
 		break;
 	case GEN6_STOLEN_RESERVED_256K:
 		*size = 256 * 1024;
 		break;
 	case GEN6_STOLEN_RESERVED_128K:
 		*size = 128 * 1024;
 		break;
 	default:
 		*size = 1024 * 1024;
 		MISSING_CASE(reg_val & GEN6_STOLEN_RESERVED_SIZE_MASK);
+	}
+}
 static void gen7_get_stolen_reserved(struct drm_i915_private *dev_priv,
 				     unsigned long *base, unsigned long *size)
+{
 	uint32_t reg_val = I915_READ(GEN6_STOLEN_RESERVED);
 	*base = reg_val & GEN7_STOLEN_RESERVED_ADDR_MASK;
 	switch (reg_val & GEN7_STOLEN_RESERVED_SIZE_MASK) {
 	case GEN7_STOLEN_RESERVED_1M:
 		*size = 1024 * 1024;
 		break;
 	case GEN7_STOLEN_RESERVED_256K:
 		*size = 256 * 1024;
 		break;
 	default:
 		*size = 1024 * 1024;
 		MISSING_CASE(reg_val & GEN7_STOLEN_RESERVED_SIZE_MASK);
+	}
+}
 static void gen8_get_stolen_reserved(struct drm_i915_private *dev_priv,
 				     unsigned long *base, unsigned long *size)
+{
 	uint32_t reg_val = I915_READ(GEN6_STOLEN_RESERVED);
 	*base = reg_val & GEN6_STOLEN_RESERVED_ADDR_MASK;
 	switch (reg_val & GEN8_STOLEN_RESERVED_SIZE_MASK) {
 	case GEN8_STOLEN_RESERVED_1M:
 		*size = 1024 * 1024;
 		break;
 	case GEN8_STOLEN_RESERVED_2M:
 		*size = 2 * 1024 * 1024;
 		break;
 	case GEN8_STOLEN_RESERVED_4M:
 		*size = 4 * 1024 * 1024;
 		break;
 	case GEN8_STOLEN_RESERVED_8M:
 		*size = 8 * 1024 * 1024;
 		break;
 	default:
 		*size = 8 * 1024 * 1024;
 		MISSING_CASE(reg_val & GEN8_STOLEN_RESERVED_SIZE_MASK);
+	}
+}
 static void bdw_get_stolen_reserved(struct drm_i915_private *dev_priv,
 				    unsigned long *base, unsigned long *size)
+{
 	uint32_t reg_val = I915_READ(GEN6_STOLEN_RESERVED);
 	unsigned long stolen_top;
 	stolen_top = dev_priv->mm.stolen_base + dev_priv->gtt.stolen_size;
 	*base = reg_val & GEN6_STOLEN_RESERVED_ADDR_MASK;
 	/* On these platforms, the register doesn't have a size field, so the
 	 * size is the distance between the base and the top of the stolen
 	 * memory. We also have the genuine case where base is zero and there's
 	 * nothing reserved. */
 	if (*base == 0)
 		*size = 0;
 	else
 		*size = stolen_top - *base;
+}
 int i915_gem_init_stolen(struct drm_device *dev)
+{
 	struct drm_i915_private *dev_priv = dev->dev_private;
 	unsigned long reserved_total, reserved_base = 0, reserved_size;
 	unsigned long stolen_top;
 #ifdef __NetBSD__
 	linux_mutex_init(&dev_priv->mm.stolen_lock);
 #else
 	mutex_init(&dev_priv->mm.stolen_lock);
 #endif
 #ifdef CONFIG_INTEL_IOMMU
 	if (intel_iommu_gfx_mapped && INTEL_INFO(dev)->gen < 8) {
 		DRM_INFO("DMAR active, disabling use of stolen memory\n");
 		return 0;
+	}
 #endif
 	if (dev_priv->gtt.stolen_size == 0)
 		return 0;
 	dev_priv->mm.stolen_base = i915_stolen_to_physical(dev);
 	if (dev_priv->mm.stolen_base == 0)
 		return 0;
 	stolen_top = dev_priv->mm.stolen_base + dev_priv->gtt.stolen_size;
 	switch (INTEL_INFO(dev_priv)->gen) {
 	case 2:
 	case 3:
 		break;
 	case 4:
 		if (IS_G4X(dev))
 			g4x_get_stolen_reserved(dev_priv, &reserved_base,
 						&reserved_size);
 		break;
 	case 5:
 		/* Assume the gen6 maximum for the older platforms. */
 		reserved_size = 1024 * 1024;
 		reserved_base = stolen_top - reserved_size;
 		break;
 	case 6:
 		gen6_get_stolen_reserved(dev_priv, &reserved_base,
 					 &reserved_size);
 		break;
 	case 7:
 		gen7_get_stolen_reserved(dev_priv, &reserved_base,
 					 &reserved_size);
 		break;
 	default:
 		if (IS_BROADWELL(dev_priv) || IS_SKYLAKE(dev_priv))
 			bdw_get_stolen_reserved(dev_priv, &reserved_base,
 						&reserved_size);
 		else
 			gen8_get_stolen_reserved(dev_priv, &reserved_base,
 						 &reserved_size);
 		break;
+	}
 	/* It is possible for the reserved base to be zero, but the register
 	 * field for size doesn't have a zero option. */
 	if (reserved_base == 0) {
 		reserved_size = 0;
 		reserved_base = stolen_top;
+	}
 	if (reserved_base < dev_priv->mm.stolen_base ||
 	    reserved_base + reserved_size > stolen_top) {
 		DRM_DEBUG_KMS("Stolen reserved area [0x%08lx - 0x%08lx] outside stolen memory [0x%08lx - 0x%08lx]\n",
 			      reserved_base, reserved_base + reserved_size,
 			      dev_priv->mm.stolen_base, stolen_top);
 		return 0;
+	}
 	/* It is possible for the reserved area to end before the end of stolen
 	 * memory, so just consider the start. */
 	reserved_total = stolen_top - reserved_base;
 	DRM_DEBUG_KMS("Memory reserved for graphics device: %zuK, usable: %luK\n",
 		      dev_priv->gtt.stolen_size >> 10,
 		      (dev_priv->gtt.stolen_size - reserved_total) >> 10);
 	dev_priv->gtt.stolen_usable_size = dev_priv->gtt.stolen_size -
 					   reserved_total;
 	/*
 	 * Basic memrange allocator for stolen space.
+	 *
 	 * TODO: Notice that some platforms require us to not use the first page
 	 * of the stolen memory but their BIOSes may still put the framebuffer
 	 * on the first page. So we don't reserve this page for now because of
 	 * that. Our current solution is to just prevent new nodes from being
 	 * inserted on the first page - see the check we have at
 	 * i915_gem_stolen_insert_node_in_range(). We may want to fix the fbcon
 	 * problem later.
 	 */
 	drm_mm_init(&dev_priv->mm.stolen, 0, dev_priv->gtt.stolen_usable_size);
 	return 0;
+}
 #ifndef __NetBSD__
 static struct sg_table *
 i915_pages_create_for_stolen(struct drm_device *dev,
 			     u32 offset, u32 size)
+{
 #ifdef __NetBSD__
 	panic("XXX");
 #else
 	struct drm_i915_private *dev_priv = dev->dev_private;
 	struct sg_table *st;
 	struct scatterlist *sg;
 	DRM_DEBUG_DRIVER("offset=0x%x, size=%d\n", offset, size);
 	BUG_ON(offset > dev_priv->gtt.stolen_size - size);
 	/* We hide that we have no struct page backing our stolen object
 	 * by wrapping the contiguous physical allocation with a fake
 	 * dma mapping in a single scatterlist.
 	 */
 	st = kmalloc(sizeof(*st), GFP_KERNEL);
 	if (st == NULL)
 		return NULL;
 	if (sg_alloc_table(st, 1, GFP_KERNEL)) {
 		kfree(st);
 		return NULL;
+	}
 	sg = st->sgl;
 	sg->offset = 0;
 	sg->length = size;
 	sg_dma_address(sg) = (dma_addr_t)dev_priv->mm.stolen_base + offset;
 	sg_dma_len(sg) = size;
 	return st;
 #endif
+}
 #endif
 static int i915_gem_object_get_pages_stolen(struct drm_i915_gem_object *obj)
+{
 	BUG();
 	return -EINVAL;
+}
 static void i915_gem_object_put_pages_stolen(struct drm_i915_gem_object *obj)
+{
 	/* Should only be called during free */
 #ifdef __NetBSD__
 	bus_dmamap_unload(obj->base.dev->dmat, obj->igo_dmamap);
 	bus_dmamap_destroy(obj->base.dev->dmat, obj->igo_dmamap);
 	kmem_free(obj->pages, (obj->igo_nsegs * sizeof(obj->pages[0])));
 #else
 	sg_free_table(obj->pages);
 	kfree(obj->pages);
 #endif
+}
 static void
 i915_gem_object_release_stolen(struct drm_i915_gem_object *obj)
+{
 	struct drm_i915_private *dev_priv = obj->base.dev->dev_private;
 	if (obj->stolen) {
 		i915_gem_stolen_remove_node(dev_priv, obj->stolen);
 		kfree(obj->stolen);
 		obj->stolen = NULL;
+	}
+}
 static const struct drm_i915_gem_object_ops i915_gem_object_stolen_ops = {
 	.get_pages = i915_gem_object_get_pages_stolen,
 	.put_pages = i915_gem_object_put_pages_stolen,
 	.release = i915_gem_object_release_stolen,
 };
 static struct drm_i915_gem_object *
 _i915_gem_object_create_stolen(struct drm_device *dev,
 			       struct drm_mm_node *stolen)
+{
 	struct drm_i915_gem_object *obj;
 #ifdef __NetBSD__
 	struct drm_i915_private *const dev_priv = dev->dev_private;
 	unsigned i;
 	int error;
 #endif
 	obj = i915_gem_object_alloc(dev);
 	if (obj == NULL)
 		return NULL;
 	drm_gem_private_object_init(dev, &obj->base, stolen->size);
 	i915_gem_object_init(obj, &i915_gem_object_stolen_ops);
 #ifdef __NetBSD__
 	TAILQ_INIT(&obj->igo_pageq); /* XXX Need to fill this...  */
 	KASSERT((stolen->size % PAGE_SIZE) == 0);
 	obj->igo_nsegs = (stolen->size / PAGE_SIZE);
 	obj->pages = kmem_alloc((obj->igo_nsegs * sizeof(obj->pages[0])),
 	    KM_SLEEP);
 	/*
 	 * x86 bus_dmamap_load_raw fails to respect the maxsegsz we
 	 * pass to bus_dmamap_create, so we have to create page-sized
 	 * segments to begin with.
 	 */
 	for (i = 0; i < obj->igo_nsegs; i++) {
 		obj->pages[i].ds_addr = (bus_addr_t)dev_priv->mm.stolen_base +
 		    stolen->start + (i*PAGE_SIZE);
 		obj->pages[i].ds_len = PAGE_SIZE;
+	}
 	error = bus_dmamap_create(dev->dmat, obj->base.size, obj->igo_nsegs,
 	    PAGE_SIZE, 0, BUS_DMA_WAITOK, &obj->igo_dmamap);
 	if (error) {
 		DRM_ERROR("failed to create DMA map for stolen object: %d\n",
 		    error);
 		kmem_free(obj->pages, sizeof(obj->pages[0]));
 		obj->pages = NULL;
 		goto cleanup;
+	}
 	error = bus_dmamap_load_raw(dev->dmat, obj->igo_dmamap, obj->pages,
 	    obj->igo_nsegs, stolen->size, BUS_DMA_WAITOK);
 	if (error) {
 		DRM_ERROR("failed to load DMA map for stolen object: %d\n",
 		    error);
 		bus_dmamap_destroy(dev->dmat, obj->igo_dmamap);
 		kmem_free(obj->pages, sizeof(obj->pages[0]));
 		obj->pages = NULL;
 		goto cleanup;
+	}
 #else
 	obj->pages = i915_pages_create_for_stolen(dev,
 						  stolen->start, stolen->size);
 	if (obj->pages == NULL)
 		goto cleanup;
 #endif
 	i915_gem_object_pin_pages(obj);
 	obj->stolen = stolen;
 	obj->base.read_domains = I915_GEM_DOMAIN_CPU | I915_GEM_DOMAIN_GTT;
 	obj->cache_level = HAS_LLC(dev) ? I915_CACHE_LLC : I915_CACHE_NONE;
 	return obj;
 cleanup:
 	i915_gem_object_free(obj);
 	return NULL;
+}
 struct drm_i915_gem_object *
 i915_gem_object_create_stolen(struct drm_device *dev, u32 size)
+{
 	struct drm_i915_private *dev_priv = dev->dev_private;
 	struct drm_i915_gem_object *obj;
 	struct drm_mm_node *stolen;
 	int ret;
 	if (!drm_mm_initialized(&dev_priv->mm.stolen))
 		return NULL;
 	DRM_DEBUG_KMS("creating stolen object: size=%x\n", size);
 	if (size == 0)
 		return NULL;
 	stolen = kzalloc(sizeof(*stolen), GFP_KERNEL);
 	if (!stolen)
 		return NULL;
 	ret = i915_gem_stolen_insert_node(dev_priv, stolen, size, 4096);
 	if (ret) {
 		kfree(stolen);
 		return NULL;
+	}
 	obj = _i915_gem_object_create_stolen(dev, stolen);
 	if (obj)
 		return obj;
 	i915_gem_stolen_remove_node(dev_priv, stolen);
 	kfree(stolen);
 	return NULL;
+}
 struct drm_i915_gem_object *
 i915_gem_object_create_stolen_for_preallocated(struct drm_device *dev,
 					       u32 stolen_offset,
 					       u32 gtt_offset,
 					       u32 size)
+{
 	struct drm_i915_private *dev_priv = dev->dev_private;
 	struct i915_address_space *ggtt = &dev_priv->gtt.base;
 	struct drm_i915_gem_object *obj;
 	struct drm_mm_node *stolen;
 	struct i915_vma *vma;
 	int ret;
 	if (!drm_mm_initialized(&dev_priv->mm.stolen))
 		return NULL;
 	DRM_DEBUG_KMS("creating preallocated stolen object: stolen_offset=%x, gtt_offset=%x, size=%x\n",
 			stolen_offset, gtt_offset, size);
 	/* KISS and expect everything to be page-aligned */
 	if (WARN_ON(size == 0) || WARN_ON(size & 4095) ||
 	    WARN_ON(stolen_offset & 4095))
 		return NULL;
 	stolen = kzalloc(sizeof(*stolen), GFP_KERNEL);
 	if (!stolen)
 		return NULL;
 	stolen->start = stolen_offset;
 	stolen->size = size;
 	mutex_lock(&dev_priv->mm.stolen_lock);
 	ret = drm_mm_reserve_node(&dev_priv->mm.stolen, stolen);
 	mutex_unlock(&dev_priv->mm.stolen_lock);
 	if (ret) {
 		DRM_DEBUG_KMS("failed to allocate stolen space\n");
 		kfree(stolen);
 		return NULL;
+	}
 	obj = _i915_gem_object_create_stolen(dev, stolen);
 	if (obj == NULL) {
 		DRM_DEBUG_KMS("failed to allocate stolen object\n");
 		i915_gem_stolen_remove_node(dev_priv, stolen);
 		kfree(stolen);
 		return NULL;
+	}
 	/* Some objects just need physical mem from stolen space */
 	if (gtt_offset == I915_GTT_OFFSET_NONE)
 		return obj;
 	vma = i915_gem_obj_lookup_or_create_vma(obj, ggtt);
 	if (IS_ERR(vma)) {
 		ret = PTR_ERR(vma);
 		goto err;
+	}
 	/* To simplify the initialisation sequence between KMS and GTT,
 	 * we allow construction of the stolen object prior to
 	 * setting up the GTT space. The actual reservation will occur
 	 * later.
 	 */
 	vma->node.start = gtt_offset;
 	vma->node.size = size;
 	if (drm_mm_initialized(&ggtt->mm)) {
 		ret = drm_mm_reserve_node(&ggtt->mm, &vma->node);
 		if (ret) {
 			DRM_DEBUG_KMS("failed to allocate stolen GTT space\n");
 			goto err;
+		}
 		vma->bound |= GLOBAL_BIND;
 		__i915_vma_set_map_and_fenceable(vma);
 		list_add_tail(&vma->mm_list, &ggtt->inactive_list);
+	}
 	list_add_tail(&obj->global_list, &dev_priv->mm.bound_list);
 	i915_gem_object_pin_pages(obj);
 	return obj;
 err:
 	drm_gem_object_unreference(&obj->base);
 	return NULL;
+}

 @@ -1,1357 +1,1357 @@
-/*	$NetBSD: i915_gpu_error.c,v 1.6 2018/08/27 05:57:29 riastradh Exp $	*/
+/*	$NetBSD: i915_gpu_error.c,v 1.7 2018/08/27 06:08:25 riastradh Exp $	*/
 /*
  * Copyright (c) 2008 Intel Corporation
+ *
  * Permission is hereby granted, free of charge, to any person obtaining a
  * copy of this software and associated documentation files (the "Software"),
  * to deal in the Software without restriction, including without limitation
  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
  * and/or sell copies of the Software, and to permit persons to whom the
  * Software is furnished to do so, subject to the following conditions:
+ *
  * The above copyright notice and this permission notice (including the next
  * paragraph) shall be included in all copies or substantial portions of the
  * Software.
+ *
  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
  * IN THE SOFTWARE.
+ *
  * Authors:
  *    Eric Anholt <eric@anholt.net>
  *    Keith Packard <keithp@keithp.com>
  *    Mika Kuoppala <mika.kuoppala@intel.com>
+ *
  */
 #include <sys/cdefs.h>
-__KERNEL_RCSID(0, "$NetBSD: i915_gpu_error.c,v 1.6 2018/08/27 05:57:29 riastradh Exp $");
+__KERNEL_RCSID(0, "$NetBSD: i915_gpu_error.c,v 1.7 2018/08/27 06:08:25 riastradh Exp $");
 #include <sys/param.h>
 #include <asm/io.h>
 #include <linux/irqflags.h>
 #include "i915_drv.h"
 static const char *ring_str(int ring)
+{
 	switch (ring) {
 	case RCS: return "render";
 	case VCS: return "bsd";
 	case BCS: return "blt";
 	case VECS: return "vebox";
 	case VCS2: return "bsd2";
 	default: return "";
+	}
+}
 static const char *pin_flag(int pinned)
+{
 	if (pinned > 0)
 		return " P";
 	else if (pinned < 0)
 		return " p";
 	else
 		return "";
+}
 static const char *tiling_flag(int tiling)
+{
 	switch (tiling) {
 	default:
 	case I915_TILING_NONE: return "";
 	case I915_TILING_X: return " X";
 	case I915_TILING_Y: return " Y";
+	}
+}
 static const char *dirty_flag(int dirty)
+{
 	return dirty ? " dirty" : "";
+}
 static const char *purgeable_flag(int purgeable)
+{
 	return purgeable ? " purgeable" : "";
+}
 static bool __i915_error_ok(struct drm_i915_error_state_buf *e)
+{
 	if (!e->err && WARN(e->bytes > (e->size - 1), "overflow")) {
 		e->err = -ENOSPC;
 		return false;
+	}
 	if (e->bytes == e->size - 1 || e->err)
 		return false;
 	return true;
+}
 static bool __i915_error_seek(struct drm_i915_error_state_buf *e,
 			      unsigned len)
+{
 	if (e->pos + len <= e->start) {
 		e->pos += len;
 		return false;
+	}
 	/* First vsnprintf needs to fit in its entirety for memmove */
 	if (len >= e->size) {
 		e->err = -EIO;
 		return false;
+	}
 	return true;
+}
 static void __i915_error_advance(struct drm_i915_error_state_buf *e,
 				 unsigned len)
+{
 	/* If this is first printf in this window, adjust it so that
 	 * start position matches start of the buffer
 	 */
 	if (e->pos < e->start) {
 		const size_t off = e->start - e->pos;
 		/* Should not happen but be paranoid */
 		if (off > len || e->bytes) {
 			e->err = -EIO;
 			return;
+		}
 		memmove(e->buf, e->buf + off, len - off);
 		e->bytes = len - off;
 		e->pos = e->start;
 		return;
+	}
 	e->bytes += len;
 	e->pos += len;
+}
 static void i915_error_vprintf(struct drm_i915_error_state_buf *e,
 			       const char *f, va_list args)
+{
 	unsigned len;
 	if (!__i915_error_ok(e))
 		return;
 	/* Seek the first printf which is hits start position */
 	if (e->pos < e->start) {
 		va_list tmp;
 		va_copy(tmp, args);
 		len = vsnprintf(NULL, 0, f, tmp);
 		va_end(tmp);
 		if (!__i915_error_seek(e, len))
 			return;
+	}
 	len = vsnprintf(e->buf + e->bytes, e->size - e->bytes, f, args);
 	if (len >= e->size - e->bytes)
 		len = e->size - e->bytes - 1;
 	__i915_error_advance(e, len);
+}
 static void i915_error_puts(struct drm_i915_error_state_buf *e,
 			    const char *str)
+{
 	unsigned len;
 	if (!__i915_error_ok(e))
 		return;
 	len = strlen(str);
 	/* Seek the first printf which is hits start position */
 	if (e->pos < e->start) {
 		if (!__i915_error_seek(e, len))
 			return;
+	}
 	if (len >= e->size - e->bytes)
 		len = e->size - e->bytes - 1;
 	memcpy(e->buf + e->bytes, str, len);
 	__i915_error_advance(e, len);
+}
 #define err_printf(e, ...) i915_error_printf(e, __VA_ARGS__)
 #define err_puts(e, s) i915_error_puts(e, s)
 static void print_error_buffers(struct drm_i915_error_state_buf *m,
 				const char *name,
 				struct drm_i915_error_buffer *err,
 				int count)
+{
 	int i;
 	err_printf(m, "  %s [%d]:\n", name, count);
 	while (count--) {
 		err_printf(m, "    %08x_%08x %8u %02x %02x [ ",
 			   upper_32_bits(err->gtt_offset),
 			   lower_32_bits(err->gtt_offset),
 			   err->size,
 			   err->read_domains,
 			   err->write_domain);
 		for (i = 0; i < I915_NUM_RINGS; i++)
 			err_printf(m, "%02x ", err->rseqno[i]);
 		err_printf(m, "] %02x", err->wseqno);
 		err_puts(m, pin_flag(err->pinned));
 		err_puts(m, tiling_flag(err->tiling));
 		err_puts(m, dirty_flag(err->dirty));
 		err_puts(m, purgeable_flag(err->purgeable));
 		err_puts(m, err->userptr ? " userptr" : "");
 		err_puts(m, err->ring != -1 ? " " : "");
 		err_puts(m, ring_str(err->ring));
 		err_puts(m, i915_cache_level_str(m->i915, err->cache_level));
 		if (err->name)
 			err_printf(m, " (name: %d)", err->name);
 		if (err->fence_reg != I915_FENCE_REG_NONE)
 			err_printf(m, " (fence: %d)", err->fence_reg);
 		err_puts(m, "\n");
 		err++;
+	}
+}
 static const char *hangcheck_action_to_str(enum intel_ring_hangcheck_action a)
+{
 	switch (a) {
 	case HANGCHECK_IDLE:
 		return "idle";
 	case HANGCHECK_WAIT:
 		return "wait";
 	case HANGCHECK_ACTIVE:
 		return "active";
 	case HANGCHECK_ACTIVE_LOOP:
 		return "active (loop)";
 	case HANGCHECK_KICK:
 		return "kick";
 	case HANGCHECK_HUNG:
 		return "hung";
+	}
 	return "unknown";
+}
 static void i915_ring_error_state(struct drm_i915_error_state_buf *m,
 				  struct drm_device *dev,
 				  struct drm_i915_error_state *error,
 				  int ring_idx)
+{
 	struct drm_i915_error_ring *ring = &error->ring[ring_idx];
 	if (!ring->valid)
 		return;
 	err_printf(m, "%s command stream:\n", ring_str(ring_idx));
 	err_printf(m, "  START: 0x%08x\n", ring->start);
 	err_printf(m, "  HEAD:  0x%08x\n", ring->head);
 	err_printf(m, "  TAIL:  0x%08x\n", ring->tail);
 	err_printf(m, "  CTL:   0x%08x\n", ring->ctl);
 	err_printf(m, "  HWS:   0x%08x\n", ring->hws);
 	err_printf(m, "  ACTHD: 0x%08x %08x\n", (u32)(ring->acthd>>32), (u32)ring->acthd);
 	err_printf(m, "  IPEIR: 0x%08x\n", ring->ipeir);
 	err_printf(m, "  IPEHR: 0x%08x\n", ring->ipehr);
 	err_printf(m, "  INSTDONE: 0x%08x\n", ring->instdone);
 	if (INTEL_INFO(dev)->gen >= 4) {
 		err_printf(m, "  BBADDR: 0x%08x %08x\n", (u32)(ring->bbaddr>>32), (u32)ring->bbaddr);
 		err_printf(m, "  BB_STATE: 0x%08x\n", ring->bbstate);
 		err_printf(m, "  INSTPS: 0x%08x\n", ring->instps);
+	}
 	err_printf(m, "  INSTPM: 0x%08x\n", ring->instpm);
 	err_printf(m, "  FADDR: 0x%08x %08x\n", upper_32_bits(ring->faddr),
 		   lower_32_bits(ring->faddr));
 	if (INTEL_INFO(dev)->gen >= 6) {
 		err_printf(m, "  RC PSMI: 0x%08x\n", ring->rc_psmi);
 		err_printf(m, "  FAULT_REG: 0x%08x\n", ring->fault_reg);
 		err_printf(m, "  SYNC_0: 0x%08x [last synced 0x%08x]\n",
 			   ring->semaphore_mboxes[0],
 			   ring->semaphore_seqno[0]);
 		err_printf(m, "  SYNC_1: 0x%08x [last synced 0x%08x]\n",
 			   ring->semaphore_mboxes[1],
 			   ring->semaphore_seqno[1]);
 		if (HAS_VEBOX(dev)) {
 			err_printf(m, "  SYNC_2: 0x%08x [last synced 0x%08x]\n",
 				   ring->semaphore_mboxes[2],
 				   ring->semaphore_seqno[2]);
+		}
+	}
 	if (USES_PPGTT(dev)) {
 		err_printf(m, "  GFX_MODE: 0x%08x\n", ring->vm_info.gfx_mode);
 		if (INTEL_INFO(dev)->gen >= 8) {
 			int i;
 			for (i = 0; i < 4; i++)
 				err_printf(m, "  PDP%d: 0x%016"PRIx64"\n",
 					   i, ring->vm_info.pdp[i]);
 		} else {
 			err_printf(m, "  PP_DIR_BASE: 0x%08x\n",
 				   ring->vm_info.pp_dir_base);
+		}
+	}
 	err_printf(m, "  seqno: 0x%08x\n", ring->seqno);
 	err_printf(m, "  waiting: %s\n", yesno(ring->waiting));
 	err_printf(m, "  ring->head: 0x%08x\n", ring->cpu_ring_head);
 	err_printf(m, "  ring->tail: 0x%08x\n", ring->cpu_ring_tail);
 	err_printf(m, "  hangcheck: %s [%d]\n",
 		   hangcheck_action_to_str(ring->hangcheck_action),
 		   ring->hangcheck_score);
+}
 void i915_error_printf(struct drm_i915_error_state_buf *e, const char *f, ...)
+{
 	va_list args;
 	va_start(args, f);
 	i915_error_vprintf(e, f, args);
 	va_end(args);
+}
 static void print_error_obj(struct drm_i915_error_state_buf *m,
 			    struct drm_i915_error_object *obj)
+{
 	int page, offset, elt;
 	for (page = offset = 0; page < obj->page_count; page++) {
 		for (elt = 0; elt < PAGE_SIZE/4; elt++) {
 			err_printf(m, "%08x :  %08x\n", offset,
 				   obj->pages[page][elt]);
 			offset += 4;
+		}
+	}
+}
 int i915_error_state_to_str(struct drm_i915_error_state_buf *m,
 			    const struct i915_error_state_file_priv *error_priv)
+{
 	struct drm_device *dev = error_priv->dev;
 	struct drm_i915_private *dev_priv = dev->dev_private;
 	struct drm_i915_error_state *error = error_priv->error;
 	struct drm_i915_error_object *obj;
 	int i, j, offset, elt;
 	int max_hangcheck_score;
 	if (!error) {
 		err_printf(m, "no error state collected\n");
 		goto out;
+	}
 	err_printf(m, "%s\n", error->error_msg);
 	err_printf(m, "Time: %"PRIdMAX" s %ld us\n", (intmax_t)error->time.tv_sec,
 		   (long)error->time.tv_usec);
-	err_printf(m, "Kernel: " __NetBSD_Version__ "\n");
+	err_printf(m, "Kernel: %d\n", __NetBSD_Version__);
 	err_printf(m, "Time: %ld s %ld us\n", error->time.tv_sec,
 		   error->time.tv_usec);
 	max_hangcheck_score = 0;
 	for (i = 0; i < ARRAY_SIZE(error->ring); i++) {
 		if (error->ring[i].hangcheck_score > max_hangcheck_score)
 			max_hangcheck_score = error->ring[i].hangcheck_score;
+	}
 	for (i = 0; i < ARRAY_SIZE(error->ring); i++) {
 		if (error->ring[i].hangcheck_score == max_hangcheck_score &&
 		    error->ring[i].pid != -1) {
 			err_printf(m, "Active process (on ring %s): %s [%d]\n",
 				   ring_str(i),
 				   error->ring[i].comm,
 				   error->ring[i].pid);
+		}
+	}
 	err_printf(m, "Reset count: %u\n", error->reset_count);
 	err_printf(m, "Suspend count: %u\n", error->suspend_count);
 	err_printf(m, "PCI ID: 0x%04x\n", dev->pdev->device);
 	err_printf(m, "IOMMU enabled?: %d\n", error->iommu);
 	err_printf(m, "EIR: 0x%08x\n", error->eir);
 	err_printf(m, "IER: 0x%08x\n", error->ier);
 	if (INTEL_INFO(dev)->gen >= 8) {
 		for (i = 0; i < 4; i++)
 			err_printf(m, "GTIER gt %d: 0x%08x\n", i,
 				   error->gtier[i]);
 	} else if (HAS_PCH_SPLIT(dev) || IS_VALLEYVIEW(dev))
 		err_printf(m, "GTIER: 0x%08x\n", error->gtier[0]);
 	err_printf(m, "PGTBL_ER: 0x%08x\n", error->pgtbl_er);
 	err_printf(m, "FORCEWAKE: 0x%08x\n", error->forcewake);
 	err_printf(m, "DERRMR: 0x%08x\n", error->derrmr);
 	err_printf(m, "CCID: 0x%08x\n", error->ccid);
 	err_printf(m, "Missed interrupts: 0x%08lx\n", dev_priv->gpu_error.missed_irq_rings);
 	for (i = 0; i < dev_priv->num_fence_regs; i++)
 		err_printf(m, "  fence[%d] = %08"PRIx64"\n", i, error->fence[i]);
 	for (i = 0; i < ARRAY_SIZE(error->extra_instdone); i++)
 		err_printf(m, "  INSTDONE_%d: 0x%08x\n", i,
 			   error->extra_instdone[i]);
 	if (INTEL_INFO(dev)->gen >= 6) {
 		err_printf(m, "ERROR: 0x%08x\n", error->error);
 		if (INTEL_INFO(dev)->gen >= 8)
 			err_printf(m, "FAULT_TLB_DATA: 0x%08x 0x%08x\n",
 				   error->fault_data1, error->fault_data0);
 		err_printf(m, "DONE_REG: 0x%08x\n", error->done_reg);
+	}
 	if (INTEL_INFO(dev)->gen == 7)
 		err_printf(m, "ERR_INT: 0x%08x\n", error->err_int);
 	for (i = 0; i < ARRAY_SIZE(error->ring); i++)
 		i915_ring_error_state(m, dev, error, i);
 	for (i = 0; i < error->vm_count; i++) {
 		err_printf(m, "vm[%d]\n", i);
 		print_error_buffers(m, "Active",
 				    error->active_bo[i],
 				    error->active_bo_count[i]);
 		print_error_buffers(m, "Pinned",
 				    error->pinned_bo[i],
 				    error->pinned_bo_count[i]);
+	}
 	for (i = 0; i < ARRAY_SIZE(error->ring); i++) {
 		obj = error->ring[i].batchbuffer;
 		if (obj) {
 			err_puts(m, dev_priv->ring[i].name);
 			if (error->ring[i].pid != -1)
 				err_printf(m, " (submitted by %s [%d])",
 					   error->ring[i].comm,
 					   error->ring[i].pid);
 			err_printf(m, " --- gtt_offset = 0x%08x %08x\n",
 				   upper_32_bits(obj->gtt_offset),
 				   lower_32_bits(obj->gtt_offset));
 			print_error_obj(m, obj);
+		}
 		obj = error->ring[i].wa_batchbuffer;
 		if (obj) {
 			err_printf(m, "%s (w/a) --- gtt_offset = 0x%08x\n",
 				   dev_priv->ring[i].name,
 				   lower_32_bits(obj->gtt_offset));
 			print_error_obj(m, obj);
+		}
 		if (error->ring[i].num_requests) {
 			err_printf(m, "%s --- %d requests\n",
 				   dev_priv->ring[i].name,
 				   error->ring[i].num_requests);
 			for (j = 0; j < error->ring[i].num_requests; j++) {
 				err_printf(m, "  seqno 0x%08x, emitted %ld, tail 0x%08x\n",
 					   error->ring[i].requests[j].seqno,
 					   error->ring[i].requests[j].jiffies,
 					   error->ring[i].requests[j].tail);
+			}
+		}
 		if ((obj = error->ring[i].ringbuffer)) {
 			err_printf(m, "%s --- ringbuffer = 0x%08x\n",
 				   dev_priv->ring[i].name,
 				   lower_32_bits(obj->gtt_offset));
 			print_error_obj(m, obj);
+		}
 		if ((obj = error->ring[i].hws_page)) {
 			u64 hws_offset = obj->gtt_offset;
 			u32 *hws_page = &obj->pages[0][0];
 			if (i915.enable_execlists) {
 				hws_offset += LRC_PPHWSP_PN * PAGE_SIZE;
 				hws_page = &obj->pages[LRC_PPHWSP_PN][0];
+			}
 			err_printf(m, "%s --- HW Status = 0x%08llx\n",
 				   dev_priv->ring[i].name, hws_offset);
 			offset = 0;
 			for (elt = 0; elt < PAGE_SIZE/16; elt += 4) {
 				err_printf(m, "[%04x] %08x %08x %08x %08x\n",
 					   offset,
 					   hws_page[elt],
 					   hws_page[elt+1],
 					   hws_page[elt+2],
 					   hws_page[elt+3]);
 					offset += 16;
+			}
+		}
 		if ((obj = error->ring[i].ctx)) {
 			err_printf(m, "%s --- HW Context = 0x%08x\n",
 				   dev_priv->ring[i].name,
 				   lower_32_bits(obj->gtt_offset));
 			print_error_obj(m, obj);
+		}
+	}
 	if ((obj = error->semaphore_obj)) {
 		err_printf(m, "Semaphore page = 0x%08x\n",
 			   lower_32_bits(obj->gtt_offset));
 		for (elt = 0; elt < PAGE_SIZE/16; elt += 4) {
 			err_printf(m, "[%04x] %08x %08x %08x %08x\n",
 				   elt * 4,
 				   obj->pages[0][elt],
 				   obj->pages[0][elt+1],
 				   obj->pages[0][elt+2],
 				   obj->pages[0][elt+3]);
+		}
+	}
 	if (error->overlay)
 		intel_overlay_print_error_state(m, error->overlay);
 	if (error->display)
 		intel_display_print_error_state(m, dev, error->display);
 out:
 	if (m->bytes == 0 && m->err)
 		return m->err;
 	return 0;
+}
 int i915_error_state_buf_init(struct drm_i915_error_state_buf *ebuf,
 			      struct drm_i915_private *i915,
 			      size_t count, loff_t pos)
+{
 	memset(ebuf, 0, sizeof(*ebuf));
 	ebuf->i915 = i915;
 	/* We need to have enough room to store any i915_error_state printf
 	 * so that we can move it to start position.
 	 */
 	ebuf->size = count + 1 > PAGE_SIZE ? count + 1 : PAGE_SIZE;
 	ebuf->buf = kmalloc(ebuf->size,
 				GFP_TEMPORARY | __GFP_NORETRY | __GFP_NOWARN);
 	if (ebuf->buf == NULL) {
 		ebuf->size = PAGE_SIZE;
 		ebuf->buf = kmalloc(ebuf->size, GFP_TEMPORARY);
+	}
 	if (ebuf->buf == NULL) {
 		ebuf->size = 128;
 		ebuf->buf = kmalloc(ebuf->size, GFP_TEMPORARY);
+	}
 	if (ebuf->buf == NULL)
 		return -ENOMEM;
 	ebuf->start = pos;
 	return 0;
+}
 static void i915_error_object_free(struct drm_i915_error_object *obj)
+{
 	int page;
 	if (obj == NULL)
 		return;
 	for (page = 0; page < obj->page_count; page++)
 		kfree(obj->pages[page]);
 	kfree(obj);
+}
 static void i915_error_state_free(struct kref *error_ref)
+{
 	struct drm_i915_error_state *error = container_of(error_ref,
 							  typeof(*error), ref);
 	int i;
 	for (i = 0; i < ARRAY_SIZE(error->ring); i++) {
 		i915_error_object_free(error->ring[i].batchbuffer);
 		i915_error_object_free(error->ring[i].wa_batchbuffer);
 		i915_error_object_free(error->ring[i].ringbuffer);
 		i915_error_object_free(error->ring[i].hws_page);
 		i915_error_object_free(error->ring[i].ctx);
 		kfree(error->ring[i].requests);
+	}
 	i915_error_object_free(error->semaphore_obj);
 	for (i = 0; i < error->vm_count; i++)
 		kfree(error->active_bo[i]);
 	kfree(error->active_bo);
 	kfree(error->active_bo_count);
 	kfree(error->pinned_bo);
 	kfree(error->pinned_bo_count);
 	kfree(error->overlay);
 	kfree(error->display);
 	kfree(error);
+}
 #ifdef __NetBSD__
 #  define	__aperture_iomem
 #  define	__iomem __aperture_iomem
 #endif
 static struct drm_i915_error_object *
 i915_error_object_create(struct drm_i915_private *dev_priv,
 			 struct drm_i915_gem_object *src,
 			 struct i915_address_space *vm)
+{
 	struct drm_i915_error_object *dst;
 	struct i915_vma *vma = NULL;
 	int num_pages;
 	bool use_ggtt;
 	int i = 0;
 	u64 reloc_offset;
 	if (src == NULL || src->pages == NULL)
 		return NULL;
 	num_pages = src->base.size >> PAGE_SHIFT;
 	dst = kmalloc(sizeof(*dst) + num_pages * sizeof(u32 *), GFP_ATOMIC);
 	if (dst == NULL)
 		return NULL;
 	if (i915_gem_obj_bound(src, vm))
 		dst->gtt_offset = i915_gem_obj_offset(src, vm);
 	else
 		dst->gtt_offset = -1;
 	reloc_offset = dst->gtt_offset;
 	if (i915_is_ggtt(vm))
 		vma = i915_gem_obj_to_ggtt(src);
 	use_ggtt = (src->cache_level == I915_CACHE_NONE &&
 		   vma && (vma->bound & GLOBAL_BIND) &&
 		   reloc_offset + num_pages * PAGE_SIZE <= dev_priv->gtt.mappable_end);
 	/* Cannot access stolen address directly, try to use the aperture */
 	if (src->stolen) {
 		use_ggtt = true;
 		if (!(vma && vma->bound & GLOBAL_BIND))
 			goto unwind;
 		reloc_offset = i915_gem_obj_ggtt_offset(src);
 		if (reloc_offset + num_pages * PAGE_SIZE > dev_priv->gtt.mappable_end)
 			goto unwind;
+	}
 	/* Cannot access snooped pages through the aperture */
 	if (use_ggtt && src->cache_level != I915_CACHE_NONE && !HAS_LLC(dev_priv->dev))
 		goto unwind;
 	dst->page_count = num_pages;
 	while (num_pages--) {
 		unsigned long flags;
 		void *d;
 		d = kmalloc(PAGE_SIZE, GFP_ATOMIC);
 		if (d == NULL)
 			goto unwind;
 		local_irq_save(flags);
 		if (use_ggtt) {
 			void __iomem *s;
 			/* Simply ignore tiling or any overlapping fence.
 			 * It's part of the error state, and this hopefully
 			 * captures what the GPU read.
 			 */
 			s = io_mapping_map_atomic_wc(dev_priv->gtt.mappable,
 						     reloc_offset);
 			memcpy_fromio(d, s, PAGE_SIZE);
 #ifdef __NetBSD__
 			io_mapping_unmap_atomic(dev_priv->gtt.mappable, s);
 #else
 			io_mapping_unmap_atomic(s);
 #endif
 		} else {
 			if (cpu_intr_p() || cpu_softintr_p() ||
 			    (curlwp->l_pflag & LP_INTR) != 0) {
 				/*
 				 * We can't take locks during interrupts
 				 * and finding the page from uvm requires
 				 * taking a lock. Checking for an interrupt
 				 * context is bogus, but this is the least
 				 * intrusive change. Zero the result, doesn't
 				 * matter much, because this is only used
 				 * for diagnostics.
 				 */
 				memset(d, 0, PAGE_SIZE);
 			} else {
 				struct page *page;
 				void *s;
 				page = i915_gem_object_get_page(src, i);
 				drm_clflush_pages(&page, 1);
 				s = kmap_atomic(page);
 				memcpy(d, s, PAGE_SIZE);
 				kunmap_atomic(s);
 				drm_clflush_pages(&page, 1);
+			}
+		}
 		local_irq_restore(flags);
 		dst->pages[i++] = d;
 		reloc_offset += PAGE_SIZE;
+	}
 	return dst;
 unwind:
 	while (i--)
 		kfree(dst->pages[i]);
 	kfree(dst);
 	return NULL;
+}
 #define i915_error_ggtt_object_create(dev_priv, src) \
 	i915_error_object_create((dev_priv), (src), &(dev_priv)->gtt.base)
 #ifdef __NetBSD__
 #  undef	__iomem
 #  undef	__aperture_iomem
 #endif
 static void capture_bo(struct drm_i915_error_buffer *err,
 		       struct i915_vma *vma)
+{
 	struct drm_i915_gem_object *obj = vma->obj;
 	int i;
 	err->size = obj->base.size;
 	err->name = obj->base.name;
 	for (i = 0; i < I915_NUM_RINGS; i++)
 		err->rseqno[i] = i915_gem_request_get_seqno(obj->last_read_req[i]);
 	err->wseqno = i915_gem_request_get_seqno(obj->last_write_req);
 	err->gtt_offset = vma->node.start;
 	err->read_domains = obj->base.read_domains;
 	err->write_domain = obj->base.write_domain;
 	err->fence_reg = obj->fence_reg;
 	err->pinned = 0;
 	if (i915_gem_obj_is_pinned(obj))
 		err->pinned = 1;
 	err->tiling = obj->tiling_mode;
 	err->dirty = obj->dirty;
 	err->purgeable = obj->madv != I915_MADV_WILLNEED;
 	err->userptr = obj->userptr.mm != NULL;
 	err->ring = obj->last_write_req ?
 			i915_gem_request_get_ring(obj->last_write_req)->id : -1;
 	err->cache_level = obj->cache_level;
+}
 static u32 capture_active_bo(struct drm_i915_error_buffer *err,
 			     int count, struct list_head *head)
+{
 	struct i915_vma *vma;
 	int i = 0;
 	list_for_each_entry(vma, head, mm_list) {
 		capture_bo(err++, vma);
 		if (++i == count)
 			break;
+	}
 	return i;
+}
 static u32 capture_pinned_bo(struct drm_i915_error_buffer *err,
 			     int count, struct list_head *head,
 			     struct i915_address_space *vm)
+{
 	struct drm_i915_gem_object *obj;
 	struct drm_i915_error_buffer * const first = err;
 	struct drm_i915_error_buffer * const last = err + count;
 	list_for_each_entry(obj, head, global_list) {
 		struct i915_vma *vma;
 		if (err == last)
 			break;
 		list_for_each_entry(vma, &obj->vma_list, vma_link)
 			if (vma->vm == vm && vma->pin_count > 0)
 				capture_bo(err++, vma);
+	}
 	return err - first;
+}
 /* Generate a semi-unique error code. The code is not meant to have meaning, The
  * code's only purpose is to try to prevent false duplicated bug reports by
  * grossly estimating a GPU error state.
+ *
  * TODO Ideally, hashing the batchbuffer would be a very nice way to determine
  * the hang if we could strip the GTT offset information from it.
+ *
  * It's only a small step better than a random number in its current form.
  */
 static uint32_t i915_error_generate_code(struct drm_i915_private *dev_priv,
 					 struct drm_i915_error_state *error,
 					 int *ring_id)
+{
 	uint32_t error_code = 0;
 	int i;
 	/* IPEHR would be an ideal way to detect errors, as it's the gross
 	 * measure of "the command that hung." However, has some very common
 	 * synchronization commands which almost always appear in the case
 	 * strictly a client bug. Use instdone to differentiate those some.
 	 */
 	for (i = 0; i < I915_NUM_RINGS; i++) {
 		if (error->ring[i].hangcheck_action == HANGCHECK_HUNG) {
 			if (ring_id)
 				*ring_id = i;
 			return error->ring[i].ipehr ^ error->ring[i].instdone;
+		}
+	}
 	return error_code;
+}
 static void i915_gem_record_fences(struct drm_device *dev,
 				   struct drm_i915_error_state *error)
+{
 	struct drm_i915_private *dev_priv = dev->dev_private;
 	int i;
 	if (IS_GEN3(dev) || IS_GEN2(dev)) {
 		for (i = 0; i < dev_priv->num_fence_regs; i++)
 			error->fence[i] = I915_READ(FENCE_REG(i));
 	} else if (IS_GEN5(dev) || IS_GEN4(dev)) {
 		for (i = 0; i < dev_priv->num_fence_regs; i++)
 			error->fence[i] = I915_READ64(FENCE_REG_965_LO(i));
 	} else if (INTEL_INFO(dev)->gen >= 6) {
 		for (i = 0; i < dev_priv->num_fence_regs; i++)
 			error->fence[i] = I915_READ64(FENCE_REG_GEN6_LO(i));
+	}
+}
 static void gen8_record_semaphore_state(struct drm_i915_private *dev_priv,
 					struct drm_i915_error_state *error,
 					struct intel_engine_cs *ring,
 					struct drm_i915_error_ring *ering)
+{
 	struct intel_engine_cs *to;
 	int i;
 	if (!i915_semaphore_is_enabled(dev_priv->dev))
 		return;
 	if (!error->semaphore_obj)
 		error->semaphore_obj =
 			i915_error_ggtt_object_create(dev_priv,
 						      dev_priv->semaphore_obj);
 	for_each_ring(to, dev_priv, i) {
 		int idx;
 		u16 signal_offset;
 		u32 *tmp;
 		if (ring == to)
 			continue;
 		signal_offset = (GEN8_SIGNAL_OFFSET(ring, i) & (PAGE_SIZE - 1))
 				/ 4;
 		tmp = error->semaphore_obj->pages[0];
 		idx = intel_ring_sync_index(ring, to);
 		ering->semaphore_mboxes[idx] = tmp[signal_offset];
 		ering->semaphore_seqno[idx] = ring->semaphore.sync_seqno[idx];
+	}
+}
 static void gen6_record_semaphore_state(struct drm_i915_private *dev_priv,
 					struct intel_engine_cs *ring,
 					struct drm_i915_error_ring *ering)
+{
 	ering->semaphore_mboxes[0] = I915_READ(RING_SYNC_0(ring->mmio_base));
 	ering->semaphore_mboxes[1] = I915_READ(RING_SYNC_1(ring->mmio_base));
 	ering->semaphore_seqno[0] = ring->semaphore.sync_seqno[0];
 	ering->semaphore_seqno[1] = ring->semaphore.sync_seqno[1];
 	if (HAS_VEBOX(dev_priv->dev)) {
 		ering->semaphore_mboxes[2] =
 			I915_READ(RING_SYNC_2(ring->mmio_base));
 		ering->semaphore_seqno[2] = ring->semaphore.sync_seqno[2];
+	}
+}
 static void i915_record_ring_state(struct drm_device *dev,
 				   struct drm_i915_error_state *error,
 				   struct intel_engine_cs *ring,
 				   struct drm_i915_error_ring *ering)
+{
 	struct drm_i915_private *dev_priv = dev->dev_private;
 	if (INTEL_INFO(dev)->gen >= 6) {
 		ering->rc_psmi = I915_READ(ring->mmio_base + 0x50);
 		ering->fault_reg = I915_READ(RING_FAULT_REG(ring));
 		if (INTEL_INFO(dev)->gen >= 8)
 			gen8_record_semaphore_state(dev_priv, error, ring, ering);
 		else
 			gen6_record_semaphore_state(dev_priv, ring, ering);
+	}
 	if (INTEL_INFO(dev)->gen >= 4) {
 		ering->faddr = I915_READ(RING_DMA_FADD(ring->mmio_base));
 		ering->ipeir = I915_READ(RING_IPEIR(ring->mmio_base));
 		ering->ipehr = I915_READ(RING_IPEHR(ring->mmio_base));
 		ering->instdone = I915_READ(RING_INSTDONE(ring->mmio_base));
 		ering->instps = I915_READ(RING_INSTPS(ring->mmio_base));
 		ering->bbaddr = I915_READ(RING_BBADDR(ring->mmio_base));
 		if (INTEL_INFO(dev)->gen >= 8) {
 			ering->faddr |= (u64) I915_READ(RING_DMA_FADD_UDW(ring->mmio_base)) << 32;
 			ering->bbaddr |= (u64) I915_READ(RING_BBADDR_UDW(ring->mmio_base)) << 32;
+		}
 		ering->bbstate = I915_READ(RING_BBSTATE(ring->mmio_base));
 	} else {
 		ering->faddr = I915_READ(DMA_FADD_I8XX);
 		ering->ipeir = I915_READ(IPEIR);
 		ering->ipehr = I915_READ(IPEHR);
 		ering->instdone = I915_READ(GEN2_INSTDONE);
+	}
 #ifdef __NetBSD__
 	ering->waiting = DRM_SPIN_WAITERS_P(&ring->irq_queue,
 	    &dev_priv->irq_lock);
 #else
 	ering->waiting = waitqueue_active(&ring->irq_queue);
 #endif
 	ering->instpm = I915_READ(RING_INSTPM(ring->mmio_base));
 	ering->seqno = ring->get_seqno(ring, false);
 	ering->acthd = intel_ring_get_active_head(ring);
 	ering->start = I915_READ_START(ring);
 	ering->head = I915_READ_HEAD(ring);
 	ering->tail = I915_READ_TAIL(ring);
 	ering->ctl = I915_READ_CTL(ring);
 	if (I915_NEED_GFX_HWS(dev)) {
 		int mmio;
 		if (IS_GEN7(dev)) {
 			switch (ring->id) {
 			default:
 			case RCS:
 				mmio = RENDER_HWS_PGA_GEN7;
 				break;
 			case BCS:
 				mmio = BLT_HWS_PGA_GEN7;
 				break;
 			case VCS:
 				mmio = BSD_HWS_PGA_GEN7;
 				break;
 			case VECS:
 				mmio = VEBOX_HWS_PGA_GEN7;
 				break;
+			}
 		} else if (IS_GEN6(ring->dev)) {
 			mmio = RING_HWS_PGA_GEN6(ring->mmio_base);
 		} else {
 			/* XXX: gen8 returns to sanity */
 			mmio = RING_HWS_PGA(ring->mmio_base);
+		}
 		ering->hws = I915_READ(mmio);
+	}
 	ering->hangcheck_score = ring->hangcheck.score;
 	ering->hangcheck_action = ring->hangcheck.action;
 	if (USES_PPGTT(dev)) {
 		int i;
 		ering->vm_info.gfx_mode = I915_READ(RING_MODE_GEN7(ring));
 		if (IS_GEN6(dev))
 			ering->vm_info.pp_dir_base =
 				I915_READ(RING_PP_DIR_BASE_READ(ring));
 		else if (IS_GEN7(dev))
 			ering->vm_info.pp_dir_base =
 				I915_READ(RING_PP_DIR_BASE(ring));
 		else if (INTEL_INFO(dev)->gen >= 8)
 			for (i = 0; i < 4; i++) {
 				ering->vm_info.pdp[i] =
 					I915_READ(GEN8_RING_PDP_UDW(ring, i));
 				ering->vm_info.pdp[i] <<= 32;
 				ering->vm_info.pdp[i] |=
 					I915_READ(GEN8_RING_PDP_LDW(ring, i));
+			}
+	}
+}
 static void i915_gem_record_active_context(struct intel_engine_cs *ring,
 					   struct drm_i915_error_state *error,
 					   struct drm_i915_error_ring *ering)
+{
 	struct drm_i915_private *dev_priv = ring->dev->dev_private;
 	struct drm_i915_gem_object *obj;
 	/* Currently render ring is the only HW context user */
 	if (ring->id != RCS || !error->ccid)
 		return;
 	list_for_each_entry(obj, &dev_priv->mm.bound_list, global_list) {
 		if (!i915_gem_obj_ggtt_bound(obj))
 			continue;
 		if ((error->ccid & PAGE_MASK) == i915_gem_obj_ggtt_offset(obj)) {
 			ering->ctx = i915_error_ggtt_object_create(dev_priv, obj);
 			break;
+		}
+	}
+}
 static void i915_gem_record_rings(struct drm_device *dev,
 				  struct drm_i915_error_state *error)
+{
 	struct drm_i915_private *dev_priv = dev->dev_private;
 	struct drm_i915_gem_request *request;
 	int i, count;
 	for (i = 0; i < I915_NUM_RINGS; i++) {
 		struct intel_engine_cs *ring = &dev_priv->ring[i];
 		struct intel_ringbuffer *rbuf;
 		error->ring[i].pid = -1;
 		if (ring->dev == NULL)
 			continue;
 		error->ring[i].valid = true;
 		i915_record_ring_state(dev, error, ring, &error->ring[i]);
 		request = i915_gem_find_active_request(ring);
 		if (request) {
 			struct i915_address_space *vm;
 			vm = request->ctx && request->ctx->ppgtt ?
 				&request->ctx->ppgtt->base :
 				&dev_priv->gtt.base;
 			/* We need to copy these to an anonymous buffer
 			 * as the simplest method to avoid being overwritten
 			 * by userspace.
 			 */
 			error->ring[i].batchbuffer =
 				i915_error_object_create(dev_priv,
 							 request->batch_obj,
 							 vm);
 			if (HAS_BROKEN_CS_TLB(dev_priv->dev))
 				error->ring[i].wa_batchbuffer =
 					i915_error_ggtt_object_create(dev_priv,
 							     ring->scratch.obj);
 #ifndef __NetBSD__		/* XXX not a clue */
 			if (request->pid) {
 				struct task_struct *task;
 				rcu_read_lock();
 				task = pid_task(request->pid, PIDTYPE_PID);
 				if (task) {
 					strcpy(error->ring[i].comm, task->comm);
 					error->ring[i].pid = task->pid;
+				}
 				rcu_read_unlock();
+			}
 #endif
+		}
 		if (i915.enable_execlists) {
 			/* TODO: This is only a small fix to keep basic error
 			 * capture working, but we need to add more information
 			 * for it to be useful (e.g. dump the context being
 			 * executed).
 			 */
 			if (request)
 				rbuf = request->ctx->engine[ring->id].ringbuf;
 			else
 				rbuf = ring->default_context->engine[ring->id].ringbuf;
 		} else
 			rbuf = ring->buffer;
 		error->ring[i].cpu_ring_head = rbuf->head;
 		error->ring[i].cpu_ring_tail = rbuf->tail;
 		error->ring[i].ringbuffer =
 			i915_error_ggtt_object_create(dev_priv, rbuf->obj);
 		error->ring[i].hws_page =
 			i915_error_ggtt_object_create(dev_priv, ring->status_page.obj);
 		i915_gem_record_active_context(ring, error, &error->ring[i]);
 		count = 0;
 		list_for_each_entry(request, &ring->request_list, list)
 			count++;
 		error->ring[i].num_requests = count;
 		error->ring[i].requests =
 			kcalloc(count, sizeof(*error->ring[i].requests),
 				GFP_ATOMIC);
 		if (error->ring[i].requests == NULL) {
 			error->ring[i].num_requests = 0;
 			continue;
+		}
 		count = 0;
 		list_for_each_entry(request, &ring->request_list, list) {
 			struct drm_i915_error_request *erq;
 			erq = &error->ring[i].requests[count++];
 			erq->seqno = request->seqno;
 			erq->jiffies = request->emitted_jiffies;
 			erq->tail = request->postfix;
+		}
+	}
+}
 /* FIXME: Since pin count/bound list is global, we duplicate what we capture per
  * VM.
  */
 static void i915_gem_capture_vm(struct drm_i915_private *dev_priv,
 				struct drm_i915_error_state *error,
 				struct i915_address_space *vm,
 				const int ndx)
+{
 	struct drm_i915_error_buffer *active_bo = NULL, *pinned_bo = NULL;
 	struct drm_i915_gem_object *obj;
 	struct i915_vma *vma;
 	int i;
 	i = 0;
 	list_for_each_entry(vma, &vm->active_list, mm_list)
 		i++;
 	error->active_bo_count[ndx] = i;
 	list_for_each_entry(obj, &dev_priv->mm.bound_list, global_list) {
 		list_for_each_entry(vma, &obj->vma_list, vma_link)
 			if (vma->vm == vm && vma->pin_count > 0)
 				i++;
+	}
 	error->pinned_bo_count[ndx] = i - error->active_bo_count[ndx];
 	if (i) {
 		active_bo = kcalloc(i, sizeof(*active_bo), GFP_ATOMIC);
 		if (active_bo)
 			pinned_bo = active_bo + error->active_bo_count[ndx];
+	}
 	if (active_bo)
 		error->active_bo_count[ndx] =
 			capture_active_bo(active_bo,
 					  error->active_bo_count[ndx],
 					  &vm->active_list);
 	if (pinned_bo)
 		error->pinned_bo_count[ndx] =
 			capture_pinned_bo(pinned_bo,
 					  error->pinned_bo_count[ndx],
 					  &dev_priv->mm.bound_list, vm);
 	error->active_bo[ndx] = active_bo;
 	error->pinned_bo[ndx] = pinned_bo;
+}
 static void i915_gem_capture_buffers(struct drm_i915_private *dev_priv,
 				     struct drm_i915_error_state *error)
+{
 	struct i915_address_space *vm;
 	int cnt = 0, i = 0;
 	list_for_each_entry(vm, &dev_priv->vm_list, global_link)
 		cnt++;
 	error->active_bo = kcalloc(cnt, sizeof(*error->active_bo), GFP_ATOMIC);
 	error->pinned_bo = kcalloc(cnt, sizeof(*error->pinned_bo), GFP_ATOMIC);
 	error->active_bo_count = kcalloc(cnt, sizeof(*error->active_bo_count),
 					 GFP_ATOMIC);
 	error->pinned_bo_count = kcalloc(cnt, sizeof(*error->pinned_bo_count),
 					 GFP_ATOMIC);
 	if (error->active_bo == NULL ||
 	    error->pinned_bo == NULL ||
 	    error->active_bo_count == NULL ||
 	    error->pinned_bo_count == NULL) {
 		kfree(error->active_bo);
 		kfree(error->active_bo_count);
 		kfree(error->pinned_bo);
 		kfree(error->pinned_bo_count);
 		error->active_bo = NULL;
 		error->active_bo_count = NULL;
 		error->pinned_bo = NULL;
 		error->pinned_bo_count = NULL;
 	} else {
 		list_for_each_entry(vm, &dev_priv->vm_list, global_link)
 			i915_gem_capture_vm(dev_priv, error, vm, i++);
 		error->vm_count = cnt;
+	}
+}
 /* Capture all registers which don't fit into another category. */
 static void i915_capture_reg_state(struct drm_i915_private *dev_priv,
 				   struct drm_i915_error_state *error)
+{
 	struct drm_device *dev = dev_priv->dev;
 	int i;
 	/* General organization
 	 * 1. Registers specific to a single generation
 	 * 2. Registers which belong to multiple generations
 	 * 3. Feature specific registers.
 	 * 4. Everything else
 	 * Please try to follow the order.
 	 */
 	/* 1: Registers specific to a single generation */
 	if (IS_VALLEYVIEW(dev)) {
 		error->gtier[0] = I915_READ(GTIER);
 		error->ier = I915_READ(VLV_IER);
 		error->forcewake = I915_READ(FORCEWAKE_VLV);
+	}
 	if (IS_GEN7(dev))
 		error->err_int = I915_READ(GEN7_ERR_INT);
 	if (INTEL_INFO(dev)->gen >= 8) {
 		error->fault_data0 = I915_READ(GEN8_FAULT_TLB_DATA0);
 		error->fault_data1 = I915_READ(GEN8_FAULT_TLB_DATA1);
+	}
 	if (IS_GEN6(dev)) {
 		error->forcewake = I915_READ(FORCEWAKE);
 		error->gab_ctl = I915_READ(GAB_CTL);
 		error->gfx_mode = I915_READ(GFX_MODE);
+	}
 	/* 2: Registers which belong to multiple generations */
 	if (INTEL_INFO(dev)->gen >= 7)
 		error->forcewake = I915_READ(FORCEWAKE_MT);
 	if (INTEL_INFO(dev)->gen >= 6) {
 		error->derrmr = I915_READ(DERRMR);
 		error->error = I915_READ(ERROR_GEN6);
 		error->done_reg = I915_READ(DONE_REG);
+	}
 	/* 3: Feature specific registers */
 	if (IS_GEN6(dev) || IS_GEN7(dev)) {
 		error->gam_ecochk = I915_READ(GAM_ECOCHK);
 		error->gac_eco = I915_READ(GAC_ECO_BITS);
+	}
 	/* 4: Everything else */
 	if (HAS_HW_CONTEXTS(dev))
 		error->ccid = I915_READ(CCID);
 	if (INTEL_INFO(dev)->gen >= 8) {
 		error->ier = I915_READ(GEN8_DE_MISC_IER);
 		for (i = 0; i < 4; i++)
 			error->gtier[i] = I915_READ(GEN8_GT_IER(i));
 	} else if (HAS_PCH_SPLIT(dev)) {
 		error->ier = I915_READ(DEIER);
 		error->gtier[0] = I915_READ(GTIER);
 	} else if (IS_GEN2(dev)) {
 		error->ier = I915_READ16(IER);
 	} else if (!IS_VALLEYVIEW(dev)) {
 		error->ier = I915_READ(IER);
+	}
 	error->eir = I915_READ(EIR);
 	error->pgtbl_er = I915_READ(PGTBL_ER);
 	i915_get_extra_instdone(dev, error->extra_instdone);
+}
 static void i915_error_capture_msg(struct drm_device *dev,
 				   struct drm_i915_error_state *error,
 				   bool wedged,
 				   const char *error_msg)
+{
 	struct drm_i915_private *dev_priv = dev->dev_private;
 	u32 ecode;
 	int ring_id = -1, len;
 	ecode = i915_error_generate_code(dev_priv, error, &ring_id);
 	len = scnprintf(error->error_msg, sizeof(error->error_msg),
 			"GPU HANG: ecode %d:%d:0x%08x",
 			INTEL_INFO(dev)->gen, ring_id, ecode);
 	if (ring_id != -1 && error->ring[ring_id].pid != -1)
 		len += scnprintf(error->error_msg + len,
 				 sizeof(error->error_msg) - len,
 				 ", in %s [%d]",
 				 error->ring[ring_id].comm,
 				 error->ring[ring_id].pid);
 	scnprintf(error->error_msg + len, sizeof(error->error_msg) - len,
 		  ", reason: %s, action: %s",
 		  error_msg,
 		  wedged ? "reset" : "continue");
+}
 static void i915_capture_gen_state(struct drm_i915_private *dev_priv,
 				   struct drm_i915_error_state *error)
+{
 	error->iommu = -1;
 #ifdef CONFIG_INTEL_IOMMU
 	error->iommu = intel_iommu_gfx_mapped;
 #endif
 	error->reset_count = i915_reset_count(&dev_priv->gpu_error);
 	error->suspend_count = dev_priv->suspend_count;
+}
 /**
  * i915_capture_error_state - capture an error record for later analysis
  * @dev: drm device
+ *
  * Should be called when an error is detected (either a hang or an error
  * interrupt) to capture error state from the time of the error.  Fills
  * out a structure which becomes available in debugfs for user level tools
  * to pick up.
  */
 void i915_capture_error_state(struct drm_device *dev, bool wedged,
 			      const char *error_msg)
+{
 	static bool warned;
 	struct drm_i915_private *dev_priv = dev->dev_private;
 	struct drm_i915_error_state *error;
 	unsigned long flags;
 	/* Account for pipe specific data like PIPE*STAT */
 	error = kzalloc(sizeof(*error), GFP_ATOMIC);
 	if (!error) {
 		DRM_DEBUG_DRIVER("out of memory, not capturing error state\n");
 		return;
+	}
 	kref_init(&error->ref);
 	i915_capture_gen_state(dev_priv, error);
 	i915_capture_reg_state(dev_priv, error);
 	i915_gem_capture_buffers(dev_priv, error);
 	i915_gem_record_fences(dev, error);
 	i915_gem_record_rings(dev, error);
 	do_gettimeofday(&error->time);

 @@ -1,177 +1,181 @@
-/*	$NetBSD: kernel.h,v 1.11 2018/08/27 06:07:20 riastradh Exp $	*/
+/*	$NetBSD: kernel.h,v 1.12 2018/08/27 06:08:25 riastradh Exp $	*/
 /*-
  * Copyright (c) 2013 The NetBSD Foundation, Inc.
  * All rights reserved.
+ *
  * This code is derived from software contributed to The NetBSD Foundation
  * by Taylor R. Campbell.
+ *
  * Redistribution and use in source and binary forms, with or without
  * modification, are permitted provided that the following conditions
  * are met:
  * 1. Redistributions of source code must retain the above copyright
  *    notice, this list of conditions and the following disclaimer.
  * 2. Redistributions in binary form must reproduce the above copyright
  *    notice, this list of conditions and the following disclaimer in the
  *    documentation and/or other materials provided with the distribution.
+ *
  * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
  * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
  * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
  * PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
  * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
  * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
  * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
  * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
  * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
  * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
  * POSSIBILITY OF SUCH DAMAGE.
  */
 #ifndef _LINUX_KERNEL_H_
 #define _LINUX_KERNEL_H_
 #include <sys/cdefs.h>
 #include <sys/types.h>
 #include <sys/param.h>
 #include <sys/systm.h>
 #include <lib/libkern/libkern.h>
 #include <linux/printk.h>
 #define U16_MAX UINT16_MAX
 #define U32_MAX UINT32_MAX
 #define U64_MAX UINT64_MAX
 #define	oops_in_progress	(panicstr != NULL)
 #define	IS_ENABLED(option)	(option)
 #define	IS_BUILTIN(option)	(1) /* Probably... */
 #define	__printf	__printflike
 #define	__user
 #define	__must_check	/* __attribute__((warn_unused_result)), if GCC */
 #define	__always_unused	__unused
 #define	barrier()	__insn_barrier()
 #define	likely(X)	__predict_true(X)
 #define	unlikely(X)	__predict_false(X)
 /*
  * XXX Linux kludge to work around GCC uninitialized variable warning.
  * Linux does `x = x', which is bollocks.
  */
 #define	uninitialized_var(x)	x = 0
 /* XXX These will multiply evaluate their arguments.  */
 #define	min(X, Y)	MIN(X, Y)
 #define	max(X, Y)	MAX(X, Y)
 #define	max_t(T, X, Y)	MAX(X, Y)
 #define	min_t(T, X, Y)	MIN(X, Y)
 #define	clamp_t(T, X, MIN, MAX)	min_t(T, max_t(T, X, MIN), MAX)
 #define	clamp(X, MN, MX)	MIN(MAX(X, MN), MX)
 /*
  * Rounding to nearest.
  */
 #define	DIV_ROUND_CLOSEST(N, D)						\
 	((0 < (N)) ? (((N) + ((D) / 2)) / (D))				\
 	    : (((N) - ((D) / 2)) / (D)))
 /*
  * Rounding to what may or may not be powers of two.
  */
 #define	DIV_ROUND_UP(X, N)	(((X) + (N) - 1) / (N))
 #define	DIV_ROUND_UP_ULL(X, N)	DIV_ROUND_UP((unsigned long long)(X), (N))
 /*
  * Rounding to powers of two -- carefully avoiding multiple evaluation
  * of arguments and pitfalls with C integer arithmetic rules.
  */
 #define	round_up(X, N)		((((X) - 1) | ((N) - 1)) + 1)
 #define	round_down(X, N)	((X) & ~(uintmax_t)((N) - 1))
 #define	IS_ALIGNED(X, N)	(((X) & ((N) - 1)) == 0)
 /*
  * These select 32-bit halves of what may be 32- or 64-bit quantities,
  * for which straight 32-bit shifts may be undefined behaviour (and do
  * the wrong thing on most machines: return the input unshifted by
  * ignoring the upper bits of the shift count).
  */
 #define	upper_32_bits(X)	((uint32_t) (((X) >> 16) >> 16))
 #define	lower_32_bits(X)	((uint32_t) ((X) & 0xffffffffUL))
 #define	ARRAY_SIZE(ARRAY)	__arraycount(ARRAY)
 #define	swap(X, Y)	do						\
 {									\
 	/* XXX Kludge for type-safety.  */				\
 	if (&(X) != &(Y)) {						\
 		CTASSERT(sizeof(X) == sizeof(Y));			\
 		/* XXX Can't do this much better without typeof.  */	\
 		char __swap_tmp[sizeof(X)];				\
 		(void)memcpy(__swap_tmp, &(X), sizeof(X));		\
 		(void)memcpy(&(X), &(Y), sizeof(X));			\
 		(void)memcpy(&(Y), __swap_tmp, sizeof(X));		\
 	}								\
 } while (0)
 static inline int64_t
 abs64(int64_t x)
+{
 	return (x < 0? (-x) : x);
+}
 static inline uintmax_t
 mult_frac(uintmax_t x, uintmax_t multiplier, uintmax_t divisor)
+{
 	uintmax_t q = (x / divisor);
 	uintmax_t r = (x % divisor);
 	return ((q * multiplier) + ((r * multiplier) / divisor));
+}
 static int panic_timeout __unused = 0;
 static inline int
 vscnprintf(char *buf, size_t size, const char *fmt, va_list va)
+{
 	int ret;
 	ret = vsnprintf(buf, size, fmt, va);
 	if (__predict_false(ret < 0))
 		return ret;
 	if (__predict_false(size == 0))
 		return 0;
 	if (__predict_false(size <= ret))
 		return (size - 1);
 	return ret;
+}
 static inline int
 scnprintf(char *buf, size_t size, const char *fmt, ...)
+{
 	va_list va;
 	int ret;
 	va_start(va, fmt);
 	ret = vscnprintf(buf, size, fmt, va);
 	va_end(va);
 	return ret;
+}
 static inline int
 kstrtol(const char *s, unsigned base, long *vp)
+{
 	long long v;
 	v = strtoll(s, NULL, base);
 	if (v < LONG_MIN || LONG_MAX < v)
 		return -ERANGE;
 	*vp = v;
 	return 0;
+}
 #endif  /* _LINUX_KERNEL_H_ */

 @@ -1,65 +1,61 @@
-/*	$OpenBSD: drm_linux.h,v 1.89 2018/06/25 22:29:16 kettenis Exp $	*/
+/*	$OpenBSD$	*/
 /*
  * Copyright (c) 2013, 2014, 2015 Mark Kettenis
  * Copyright (c) 2017 Martin Pieuchot
+ *
  * Permission to use, copy, modify, and distribute this software for any
  * purpose with or without fee is hereby granted, provided that the above
  * copyright notice and this permission notice appear in all copies.
+ *
  * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
  * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
  * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
  * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
  * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
  * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
  * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
  */
 #ifndef _LINUX_HASHTABLE_H_
 #define _LINUX_HASHTABLE_H_
 #include <linux/list.h>
 #define DECLARE_HASHTABLE(name, bits) struct list_head name[1 << (bits)]
 static inline void
 __hash_init(struct list_head *table, u_int size)
+{
 	u_int i;
 	for (i = 0; i < size; i++)
 		INIT_LIST_HEAD(&table[i]);
+}
 static inline bool
 __hash_empty(struct list_head *table, u_int size)
+{
 	u_int i;
 	for (i = 0; i < size; i++) {
 		if (!list_empty(&table[i]))
 			return false;
+	}
 	return true;
+}
 #define __hash(table, key)	&table[key % (nitems(table) - 1)]
 #define hash_init(table)	__hash_init(table, nitems(table))
 #define hash_add(table, node, key) \
 	hlist_add_head(node, __hash(table, key))
 #define hash_del(node)		hlist_del_init(node)
 #define hash_empty(table)	__hash_empty(table, nitems(table))
 #define hash_for_each_possible(table, obj, member, key) \
 	hlist_for_each_entry(obj, __hash(table, key), member)
 #define hash_for_each_safe(table, i, tmp, obj, member) 	\
 	for (i = 0; i < nitems(table); i++)		\
 	       list_for_each_entry_safe(obj, tmp, &table[i], member)
 #define DECLARE_HASHTABLE(__a,__b) \
 	uint64_t __a /* XXX */
 #endif /*_LINUX_HASHTABLE_H_*/

 @@ -1,611 +1,653 @@
-/*	$NetBSD: i915_gem_gtt.h,v 1.3 2018/08/27 05:35:11 riastradh Exp $	*/
+/*	$NetBSD: i915_gem_gtt.h,v 1.4 2018/08/27 06:08:25 riastradh Exp $	*/
 /*
  * Copyright © 2014 Intel Corporation
+ *
  * Permission is hereby granted, free of charge, to any person obtaining a
  * copy of this software and associated documentation files (the "Software"),
  * to deal in the Software without restriction, including without limitation
  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
  * and/or sell copies of the Software, and to permit persons to whom the
  * Software is furnished to do so, subject to the following conditions:
+ *
  * The above copyright notice and this permission notice (including the next
  * paragraph) shall be included in all copies or substantial portions of the
  * Software.
+ *
  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
  * IN THE SOFTWARE.
+ *
  * Please try to maintain the following order within this file unless it makes
  * sense to do otherwise. From top to bottom:
  * 1. typedefs
  * 2. #defines, and macros
  * 3. structure definitions
  * 4. function prototypes
+ *
  * Within each section, please try to order by generation in ascending order,
  * from top to bottom (ie. gen6 on the top, gen8 on the bottom).
  */
 #ifndef __I915_GEM_GTT_H__
 #define __I915_GEM_GTT_H__
 struct drm_i915_file_private;
 typedef uint32_t gen6_pte_t;
 typedef uint64_t gen8_pte_t;
 typedef uint64_t gen8_pde_t;
 typedef uint64_t gen8_ppgtt_pdpe_t;
 typedef uint64_t gen8_ppgtt_pml4e_t;
 #define gtt_total_entries(gtt) ((gtt).base.total >> PAGE_SHIFT)
 /* gen6-hsw has bit 11-4 for physical addr bit 39-32 */
 #define GEN6_GTT_ADDR_ENCODE(addr)	((addr) | (((addr) >> 28) & 0xff0))
 #define GEN6_PTE_ADDR_ENCODE(addr)	GEN6_GTT_ADDR_ENCODE(addr)
 #define GEN6_PDE_ADDR_ENCODE(addr)	GEN6_GTT_ADDR_ENCODE(addr)
 #define GEN6_PTE_CACHE_LLC		(2 << 1)
 #define GEN6_PTE_UNCACHED		(1 << 1)
 #define GEN6_PTE_VALID			(1 << 0)
 #define I915_PTES(pte_len)		(PAGE_SIZE / (pte_len))
 #define I915_PTE_MASK(pte_len)		(I915_PTES(pte_len) - 1)
 #define I915_PDES			512
 #define I915_PDE_MASK			(I915_PDES - 1)
 #define NUM_PTE(pde_shift)     (1 << (pde_shift - PAGE_SHIFT))
 #define GEN6_PTES			I915_PTES(sizeof(gen6_pte_t))
 #define GEN6_PD_SIZE		        (I915_PDES * PAGE_SIZE)
 #define GEN6_PD_ALIGN			(PAGE_SIZE * 16)
 #define GEN6_PDE_SHIFT			22
 #define GEN6_PDE_VALID			(1 << 0)
 #define GEN7_PTE_CACHE_L3_LLC		(3 << 1)
 #define BYT_PTE_SNOOPED_BY_CPU_CACHES	(1 << 2)
 #define BYT_PTE_WRITEABLE		(1 << 1)
 /* Cacheability Control is a 4-bit value. The low three bits are stored in bits
  * 3:1 of the PTE, while the fourth bit is stored in bit 11 of the PTE.
  */
 #define HSW_CACHEABILITY_CONTROL(bits)	((((bits) & 0x7) << 1) | \
 					 (((bits) & 0x8) << (11 - 3)))
 #define HSW_WB_LLC_AGE3			HSW_CACHEABILITY_CONTROL(0x2)
 #define HSW_WB_LLC_AGE0			HSW_CACHEABILITY_CONTROL(0x3)
 #define HSW_WB_ELLC_LLC_AGE3		HSW_CACHEABILITY_CONTROL(0x8)
 #define HSW_WB_ELLC_LLC_AGE0		HSW_CACHEABILITY_CONTROL(0xb)
 #define HSW_WT_ELLC_LLC_AGE3		HSW_CACHEABILITY_CONTROL(0x7)
 #define HSW_WT_ELLC_LLC_AGE0		HSW_CACHEABILITY_CONTROL(0x6)
 #define HSW_PTE_UNCACHED		(0)
 #define HSW_GTT_ADDR_ENCODE(addr)	((addr) | (((addr) >> 28) & 0x7f0))
 #define HSW_PTE_ADDR_ENCODE(addr)	HSW_GTT_ADDR_ENCODE(addr)
 /* GEN8 legacy style address is defined as a 3 level page table:
  * 31:30 | 29:21 | 20:12 |  11:0
  * PDPE  |  PDE  |  PTE  | offset
  * The difference as compared to normal x86 3 level page table is the PDPEs are
  * programmed via register.
+ *
  * GEN8 48b legacy style address is defined as a 4 level page table:
  * 47:39 | 38:30 | 29:21 | 20:12 |  11:0
  * PML4E | PDPE  |  PDE  |  PTE  | offset
  */
 #define GEN8_PML4ES_PER_PML4		512
 #define GEN8_PML4E_SHIFT		39
 #define GEN8_PML4E_MASK			(GEN8_PML4ES_PER_PML4 - 1)
 #define GEN8_PDPE_SHIFT			30
 /* NB: GEN8_PDPE_MASK is untrue for 32b platforms, but it has no impact on 32b page
  * tables */
 #define GEN8_PDPE_MASK			0x1ff
 #define GEN8_PDE_SHIFT			21
 #define GEN8_PDE_MASK			0x1ff
 #define GEN8_PTE_SHIFT			12
 #define GEN8_PTE_MASK			0x1ff
 #define GEN8_LEGACY_PDPES		4
 #define GEN8_PTES			I915_PTES(sizeof(gen8_pte_t))
 #define I915_PDPES_PER_PDP(dev) (USES_FULL_48BIT_PPGTT(dev) ?\
 				 GEN8_PML4ES_PER_PML4 : GEN8_LEGACY_PDPES)
 #define PPAT_UNCACHED_INDEX		(_PAGE_PWT | _PAGE_PCD)
 #define PPAT_CACHED_PDE_INDEX		0 /* WB LLC */
 #define PPAT_CACHED_INDEX		_PAGE_PAT /* WB LLCeLLC */
 #define PPAT_DISPLAY_ELLC_INDEX		_PAGE_PCD /* WT eLLC */
 #define CHV_PPAT_SNOOP			(1<<6)
 #define GEN8_PPAT_AGE(x)		(x<<4)
 #define GEN8_PPAT_LLCeLLC		(3<<2)
 #define GEN8_PPAT_LLCELLC		(2<<2)
 #define GEN8_PPAT_LLC			(1<<2)
 #define GEN8_PPAT_WB			(3<<0)
 #define GEN8_PPAT_WT			(2<<0)
 #define GEN8_PPAT_WC			(1<<0)
 #define GEN8_PPAT_UC			(0<<0)
 #define GEN8_PPAT_ELLC_OVERRIDE		(0<<2)
 #define GEN8_PPAT(i, x)			((uint64_t) (x) << ((i) * 8))
 enum i915_ggtt_view_type {
 	I915_GGTT_VIEW_NORMAL = 0,
 	I915_GGTT_VIEW_ROTATED,
 	I915_GGTT_VIEW_PARTIAL,
 };
 struct intel_rotation_info {
 	unsigned int height;
 	unsigned int pitch;
 	unsigned int uv_offset;
 	uint32_t pixel_format;
 	uint64_t fb_modifier;
 	unsigned int width_pages, height_pages;
 	uint64_t size;
 	unsigned int width_pages_uv, height_pages_uv;
 	uint64_t size_uv;
 	unsigned int uv_start_page;
 };
 struct i915_ggtt_view {
 	enum i915_ggtt_view_type type;
 	union {
 		struct {
 			u64 offset;
 			unsigned int size;
 		} partial;
 	} params;
 #ifdef __NetBSD__
 	bus_dmamap_t pages;
 #else
 	struct sg_table *pages;
 #endif
 	union {
 		struct intel_rotation_info rotation_info;
 	};
 };
 extern const struct i915_ggtt_view i915_ggtt_view_normal;
 extern const struct i915_ggtt_view i915_ggtt_view_rotated;
 enum i915_cache_level;
 /**
  * A VMA represents a GEM BO that is bound into an address space. Therefore, a
  * VMA's presence cannot be guaranteed before binding, or after unbinding the
  * object into/from the address space.
+ *
  * To make things as simple as possible (ie. no refcounting), a VMA's lifetime
  * will always be <= an objects lifetime. So object refcounting should cover us.
  */
 struct i915_vma {
 	struct drm_mm_node node;
 	struct drm_i915_gem_object *obj;
 	struct i915_address_space *vm;
 	/** Flags and address space this VMA is bound to */
 #define GLOBAL_BIND	(1<<0)
 #define LOCAL_BIND	(1<<1)
 	unsigned int bound : 4;
 	/**
 	 * Support different GGTT views into the same object.
 	 * This means there can be multiple VMA mappings per object and per VM.
 	 * i915_ggtt_view_type is used to distinguish between those entries.
 	 * The default one of zero (I915_GGTT_VIEW_NORMAL) is default and also
 	 * assumed in GEM functions which take no ggtt view parameter.
 	 */
 	struct i915_ggtt_view ggtt_view;
 	/** This object's place on the active/inactive lists */
 	struct list_head mm_list;
 	struct list_head vma_link; /* Link in the object's VMA list */
 	/** This vma's place in the batchbuffer or on the eviction list */
 	struct list_head exec_list;
 	/**
 	 * Used for performing relocations during execbuffer insertion.
 	 */
 	struct hlist_node exec_node;
 	unsigned long exec_handle;
 	struct drm_i915_gem_exec_object2 *exec_entry;
 	/**
 	 * How many users have pinned this object in GTT space. The following
 	 * users can each hold at most one reference: pwrite/pread, execbuffer
 	 * (objects are not allowed multiple times for the same batchbuffer),
 	 * and the framebuffer code. When switching/pageflipping, the
 	 * framebuffer code has at most two buffers pinned per crtc.
+	 *
 	 * In the worst case this is 1 + 1 + 1 + 2*2 = 7. That would fit into 3
 	 * bits with absolutely no headroom. So use 4 bits. */
 	unsigned int pin_count:4;
 #define DRM_I915_GEM_OBJECT_MAX_PIN_COUNT 0xf
 };
 struct i915_page_dma {
 #ifdef __NetBSD__
 	union {
 		bus_dma_segment_t seg;
 		uint32_t ggtt_offset;
 	};
 	bus_dmamap_t map;
 #else
 	struct page *page;
 	union {
 		dma_addr_t daddr;
 		/* For gen6/gen7 only. This is the offset in the GGTT
 		 * where the page directory entries for PPGTT begin
 		 */
 		uint32_t ggtt_offset;
 	};
 #endif
 };
 #define px_base(px) (&(px)->base)
 #define px_page(px) (px_base(px)->page)
 #ifdef __NetBSD__
 #define px_dma(x) (px_base(px)->map->dm_seg[0].ds_addr)
 #else
 #define px_dma(px) (px_base(px)->daddr)
 #endif
 struct i915_page_scratch {
 	struct i915_page_dma base;
 };
 struct i915_page_table {
 	struct i915_page_dma base;
 	unsigned long *used_ptes;
 };
 struct i915_page_directory {
 	struct i915_page_dma base;
 	unsigned long *used_pdes;
 	struct i915_page_table *page_table[I915_PDES]; /* PDEs */
 };
 struct i915_page_directory_pointer {
 	struct i915_page_dma base;
 	unsigned long *used_pdpes;
 	struct i915_page_directory **page_directory;
 };
 struct i915_pml4 {
 	struct i915_page_dma base;
 	DECLARE_BITMAP(used_pml4es, GEN8_PML4ES_PER_PML4);
 	struct i915_page_directory_pointer *pdps[GEN8_PML4ES_PER_PML4];
 };
 struct i915_address_space {
 	struct drm_mm mm;
 	struct drm_device *dev;
 	struct list_head global_link;
 	u64 start;		/* Start offset always 0 for dri2 */
 	u64 total;		/* size addr space maps (ex. 2GB for ggtt) */
 	struct i915_page_scratch *scratch_page;
 	struct i915_page_table *scratch_pt;
 	struct i915_page_directory *scratch_pd;
 	struct i915_page_directory_pointer *scratch_pdp; /* GEN8+ & 48b PPGTT */
 	/**
 	 * List of objects currently involved in rendering.
+	 *
 	 * Includes buffers having the contents of their GPU caches
 	 * flushed, not necessarily primitives. last_read_req
 	 * represents when the rendering involved will be completed.
+	 *
 	 * A reference is held on the buffer while on this list.
 	 */
 	struct list_head active_list;
 	/**
 	 * LRU list of objects which are not in the ringbuffer and
 	 * are ready to unbind, but are still in the GTT.
+	 *
 	 * last_read_req is NULL while an object is in this list.
+	 *
 	 * A reference is not held on the buffer while on this list,
 	 * as merely being GTT-bound shouldn't prevent its being
 	 * freed, and we'll pull it off the list in the free path.
 	 */
 	struct list_head inactive_list;
 	/* FIXME: Need a more generic return type */
 	gen6_pte_t (*pte_encode)(dma_addr_t addr,
 				 enum i915_cache_level level,
 				 bool valid, u32 flags); /* Create a valid PTE */
 	/* flags for pte_encode */
 #define PTE_READ_ONLY	(1<<0)
 	int (*allocate_va_range)(struct i915_address_space *vm,
 				 uint64_t start,
 				 uint64_t length);
 	void (*clear_range)(struct i915_address_space *vm,
 			    uint64_t start,
 			    uint64_t length,
 			    bool use_scratch);
 	void (*insert_entries)(struct i915_address_space *vm,
 #ifdef __NetBSD__
 			       bus_dmamap_t dmamap,
 #else
 			       struct sg_table *st,
 #endif
 			       uint64_t start,
 			       enum i915_cache_level cache_level, u32 flags);
 	void (*cleanup)(struct i915_address_space *vm);
 	/** Unmap an object from an address space. This usually consists of
 	 * setting the valid PTE entries to a reserved scratch page. */
 	void (*unbind_vma)(struct i915_vma *vma);
 	/* Map an object into an address space with the given cache flags. */
 	int (*bind_vma)(struct i915_vma *vma,
 			enum i915_cache_level cache_level,
 			u32 flags);
 };
 /* The Graphics Translation Table is the way in which GEN hardware translates a
  * Graphics Virtual Address into a Physical Address. In addition to the normal
  * collateral associated with any va->pa translations GEN hardware also has a
  * portion of the GTT which can be mapped by the CPU and remain both coherent
  * and correct (in cases like swizzling). That region is referred to as GMADR in
  * the spec.
  */
 struct i915_gtt {
 	struct i915_address_space base;
 	size_t stolen_size;		/* Total size of stolen memory */
 	size_t stolen_usable_size;	/* Total size minus BIOS reserved */
 	u64 mappable_end;		/* End offset that we can CPU map */
 	struct io_mapping *mappable;	/* Mapping to our CPU mappable region */
 	phys_addr_t mappable_base;	/* PA of our GMADR */
 	/** "Graphics Stolen Memory" holds the global PTEs */
 #ifdef __NetBSD__
 	/*
 	 * This is not actually the `Graphics Stolen Memory'; it is the
 	 * graphics translation table, which we write to through the
 	 * GTTADR/GTTMMADR PCI BAR, and which is backed by `Graphics
 	 * GTT Stolen Memory'.  That isn't the `Graphics Stolen Memory'
 	 * either, although it is stolen from main memory.
 	 */
 	bus_space_tag_t		bst;
 	bus_space_handle_t	bsh;
 	bus_size_t		size;
 	/* Maximum physical address that can be wired into a GTT entry.  */
 	uint64_t		max_paddr;
 	/* Page freelist for pages limited to the above maximum address.  */
 	int			pgfl;
 #else
 	void __iomem *gsm;
 #endif
 	bool do_idle_maps;
 	int mtrr;
 	/* global gtt ops */
 	int (*gtt_probe)(struct drm_device *dev, u64 *gtt_total,
 			  size_t *stolen, phys_addr_t *mappable_base,
 			  u64 *mappable_end);
 };
 struct i915_hw_ppgtt {
 	struct i915_address_space base;
 	struct kref ref;
 	struct drm_mm_node node;
 	unsigned long pd_dirty_rings;
 	union {
 		struct i915_pml4 pml4;		/* GEN8+ & 48b PPGTT */
 		struct i915_page_directory_pointer pdp;	/* GEN8+ */
 		struct i915_page_directory pd;		/* GEN6-7 */
 	};
 	struct drm_i915_file_private *file_priv;
 #ifndef __NetBSD__
 	gen6_pte_t __iomem *pd_addr;
 #endif
 	int (*enable)(struct i915_hw_ppgtt *ppgtt);
 	int (*switch_mm)(struct i915_hw_ppgtt *ppgtt,
 			 struct drm_i915_gem_request *req);
 	void (*debug_dump)(struct i915_hw_ppgtt *ppgtt, struct seq_file *m);
 };
 /* For each pde iterates over every pde between from start until start + length.
  * If start, and start+length are not perfectly divisible, the macro will round
  * down, and up as needed. The macro modifies pde, start, and length. Dev is
  * only used to differentiate shift values. Temp is temp.  On gen6/7, start = 0,
  * and length = 2G effectively iterates over every PDE in the system.
+ *
  * XXX: temp is not actually needed, but it saves doing the ALIGN operation.
  */
 #ifdef __NetBSD__ /* ALIGN means something else */
 #define gen6_for_each_pde(pt, pd, start, length, temp, iter) \
 	for (iter = gen6_pde_index(start); \
 	     length > 0 && iter < I915_PDES ? \
 			(pt = (pd)->page_table[iter]), 1 : 0; \
 	     iter++, \
 	     temp = round_up(start+1, 1 << GEN6_PDE_SHIFT) - start, \
 	     temp = min_t(unsigned, temp, length), \
 	     start += temp, length -= temp)
 #else
 #define gen6_for_each_pde(pt, pd, start, length, temp, iter) \
 	for (iter = gen6_pde_index(start); \
 	     length > 0 && iter < I915_PDES ? \
 			(pt = (pd)->page_table[iter]), 1 : 0; \
 	     iter++, \
 	     temp = ALIGN(start+1, 1 << GEN6_PDE_SHIFT) - start, \
 	     temp = min_t(unsigned, temp, length), \
 	     start += temp, length -= temp)
 #endif
 #define gen6_for_all_pdes(pt, ppgtt, iter)  \
 	for (iter = 0;		\
 	     pt = ppgtt->pd.page_table[iter], iter < I915_PDES;	\
 	     iter++)
 static inline uint32_t i915_pte_index(uint64_t address, uint32_t pde_shift)
+{
 	const uint32_t mask = NUM_PTE(pde_shift) - 1;
 	return (address >> PAGE_SHIFT) & mask;
+}
 /* Helper to counts the number of PTEs within the given length. This count
  * does not cross a page table boundary, so the max value would be
  * GEN6_PTES for GEN6, and GEN8_PTES for GEN8.
 */
 static inline uint32_t i915_pte_count(uint64_t addr, size_t length,
 				      uint32_t pde_shift)
+{
 	const uint64_t mask = ~((1 << pde_shift) - 1);
 	uint64_t end;
 	WARN_ON(length == 0);
 	WARN_ON(offset_in_page(addr|length));
 	end = addr + length;
 	if ((addr & mask) != (end & mask))
 		return NUM_PTE(pde_shift) - i915_pte_index(addr, pde_shift);
 	return i915_pte_index(end, pde_shift) - i915_pte_index(addr, pde_shift);
+}
 static inline uint32_t i915_pde_index(uint64_t addr, uint32_t shift)
+{
 	return (addr >> shift) & I915_PDE_MASK;
+}
 static inline uint32_t gen6_pte_index(uint32_t addr)
+{
 	return i915_pte_index(addr, GEN6_PDE_SHIFT);
+}
 static inline size_t gen6_pte_count(uint32_t addr, uint32_t length)
+{
 	return i915_pte_count(addr, length, GEN6_PDE_SHIFT);
+}
 static inline uint32_t gen6_pde_index(uint32_t addr)
+{
 	return i915_pde_index(addr, GEN6_PDE_SHIFT);
+}
 /* Equivalent to the gen6 version, For each pde iterates over every pde
  * between from start until start + length. On gen8+ it simply iterates
  * over every page directory entry in a page directory.
  */
 #ifdef __NetBSD__ /* ALIGN means something else */
 #define gen8_for_each_pde(pt, pd, start, length, temp, iter)		\
 	for (iter = gen8_pde_index(start); \
 	     length > 0 && iter < I915_PDES ? \
 			(pt = (pd)->page_table[iter]), 1 : 0; \
 	     iter++,				\
 	     temp = round_up(start+1, 1 << GEN8_PDE_SHIFT) - start,	\
 	     temp = min(temp, length),					\
 	     start += temp, length -= temp)
 #define gen8_for_each_pdpe(pd, pdp, start, length, temp, iter)	\
 	for (iter = gen8_pdpe_index(start); \
 	     length > 0 && (iter < I915_PDPES_PER_PDP(dev)) ? \
 			(pd = (pdp)->page_directory[iter]), 1 : 0; \
 	     iter++,				\
 	     temp = round_up(start+1, 1 << GEN8_PDPE_SHIFT) - start,	\
 	     temp = min(temp, length),					\
 	     start += temp, length -= temp)
 #define gen8_for_each_pml4e(pdp, pml4, start, length, temp, iter)	\
 	for (iter = gen8_pml4e_index(start);	\
 	     length > 0 && iter < GEN8_PML4ES_PER_PML4 ? \
 			(pdp = (pml4)->pdps[iter]), 1 : 0; \
 	     iter++,				\
 	     temp = round_up(start+1, 1ULL << GEN8_PML4E_SHIFT) - start,	\
 	     temp = min(temp, length),					\
 	     start += temp, length -= temp)
 #else
 #define gen8_for_each_pde(pt, pd, start, length, temp, iter)		\
 	for (iter = gen8_pde_index(start); \
 	     length > 0 && iter < I915_PDES ? \
 			(pt = (pd)->page_table[iter]), 1 : 0; \
 	     iter++,				\
 	     temp = ALIGN(start+1, 1 << GEN8_PDE_SHIFT) - start,	\
 	     temp = min(temp, length),					\
 	     start += temp, length -= temp)
 #define gen8_for_each_pdpe(pd, pdp, start, length, temp, iter)	\
 	for (iter = gen8_pdpe_index(start); \
 	     length > 0 && (iter < I915_PDPES_PER_PDP(dev)) ? \
 			(pd = (pdp)->page_directory[iter]), 1 : 0; \
 	     iter++,				\
 	     temp = ALIGN(start+1, 1 << GEN8_PDPE_SHIFT) - start,	\
 	     temp = min(temp, length),					\
 	     start += temp, length -= temp)
 #define gen8_for_each_pml4e(pdp, pml4, start, length, temp, iter)	\
 	for (iter = gen8_pml4e_index(start);	\
 	     length > 0 && iter < GEN8_PML4ES_PER_PML4 ? \
 			(pdp = (pml4)->pdps[iter]), 1 : 0; \
 	     iter++,				\
 	     temp = ALIGN(start+1, 1ULL << GEN8_PML4E_SHIFT) - start,	\
 	     temp = min(temp, length),					\
 	     start += temp, length -= temp)
 #endif
 static inline uint32_t gen8_pte_index(uint64_t address)
+{
 	return i915_pte_index(address, GEN8_PDE_SHIFT);
+}
 static inline uint32_t gen8_pde_index(uint64_t address)
+{
 	return i915_pde_index(address, GEN8_PDE_SHIFT);
+}
 static inline uint32_t gen8_pdpe_index(uint64_t address)
+{
 	return (address >> GEN8_PDPE_SHIFT) & GEN8_PDPE_MASK;
+}
 static inline uint32_t gen8_pml4e_index(uint64_t address)
+{
 	return (address >> GEN8_PML4E_SHIFT) & GEN8_PML4E_MASK;
+}
 static inline size_t gen8_pte_count(uint64_t address, uint64_t length)
+{
 	return i915_pte_count(address, length, GEN8_PDE_SHIFT);
+}
 static inline dma_addr_t
 i915_page_dir_dma_addr(const struct i915_hw_ppgtt *ppgtt, const unsigned n)
+{
 	return test_bit(n, ppgtt->pdp.used_pdpes) ?
 		px_dma(ppgtt->pdp.page_directory[n]) :
 		px_dma(ppgtt->base.scratch_pd);
+}
 int i915_gem_gtt_init(struct drm_device *dev);
 void i915_gem_init_global_gtt(struct drm_device *dev);
 void i915_global_gtt_cleanup(struct drm_device *dev);
 int i915_ppgtt_init(struct drm_device *dev, struct i915_hw_ppgtt *ppgtt);
 int i915_ppgtt_init_hw(struct drm_device *dev);
 int i915_ppgtt_init_ring(struct drm_i915_gem_request *req);
 void i915_ppgtt_release(struct kref *kref);
 struct i915_hw_ppgtt *i915_ppgtt_create(struct drm_device *dev,
 					struct drm_i915_file_private *fpriv);
 static inline void i915_ppgtt_get(struct i915_hw_ppgtt *ppgtt)
+{
 	if (ppgtt)
 		kref_get(&ppgtt->ref);
+}
 static inline void i915_ppgtt_put(struct i915_hw_ppgtt *ppgtt)
+{
 	if (ppgtt)
 		kref_put(&ppgtt->ref, i915_ppgtt_release);
+}
 void i915_check_and_clear_faults(struct drm_device *dev);
 void i915_gem_suspend_gtt_mappings(struct drm_device *dev);
 void i915_gem_restore_gtt_mappings(struct drm_device *dev);
 int __must_check i915_gem_gtt_prepare_object(struct drm_i915_gem_object *obj);
 void i915_gem_gtt_finish_object(struct drm_i915_gem_object *obj);
 static inline bool
 i915_ggtt_view_equal(const struct i915_ggtt_view *a,
                      const struct i915_ggtt_view *b)
+{
 	if (WARN_ON(!a || !b))
 		return false;
 	if (a->type != b->type)
 		return false;
 	if (a->type == I915_GGTT_VIEW_PARTIAL)
 		return !memcmp(&a->params, &b->params, sizeof(a->params));
 	return true;
+}
 size_t
 i915_ggtt_view_size(struct drm_i915_gem_object *obj,
 		    const struct i915_ggtt_view *view);
 #endif