 @@ -1,1029 +1,1029 @@
-/*	$NetBSD: intel_display.c,v 1.16 2018/08/27 04:58:24 riastradh Exp $	*/
+/*	$NetBSD: intel_display.c,v 1.17 2018/08/27 06:16:01 riastradh Exp $	*/
 /*
  * Copyright © 2006-2007 Intel Corporation
+ *
  * Permission is hereby granted, free of charge, to any person obtaining a
  * copy of this software and associated documentation files (the "Software"),
  * to deal in the Software without restriction, including without limitation
  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
  * and/or sell copies of the Software, and to permit persons to whom the
  * Software is furnished to do so, subject to the following conditions:
+ *
  * The above copyright notice and this permission notice (including the next
  * paragraph) shall be included in all copies or substantial portions of the
  * Software.
+ *
  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
  * DEALINGS IN THE SOFTWARE.
+ *
  * Authors:
  *	Eric Anholt <eric@anholt.net>
  */
 #include <sys/cdefs.h>
-__KERNEL_RCSID(0, "$NetBSD: intel_display.c,v 1.16 2018/08/27 04:58:24 riastradh Exp $");
+__KERNEL_RCSID(0, "$NetBSD: intel_display.c,v 1.17 2018/08/27 06:16:01 riastradh Exp $");
 #include <linux/dmi.h>
 #include <linux/module.h>
 #include <linux/input.h>
 #include <linux/i2c.h>
 #include <linux/kernel.h>
 #include <linux/slab.h>
 #include <linux/vgaarb.h>
 #include <drm/drm_edid.h>
 #include <drm/drmP.h>
 #include "intel_drv.h"
 #include <drm/i915_drm.h>
 #include "i915_drv.h"
 #include "i915_trace.h"
 #include <drm/drm_atomic.h>
 #include <drm/drm_atomic_helper.h>
 #include <drm/drm_dp_helper.h>
 #include <drm/drm_crtc_helper.h>
 #include <drm/drm_plane_helper.h>
 #include <drm/drm_rect.h>
 #include <linux/dma_remapping.h>
 #include <linux/err.h>
 #include <asm/bug.h>
 #include <linux/math64.h>
 #include <linux/bitops.h>
 #include <linux/log2.h>
 /* Primary plane formats for gen <= 3 */
 static const uint32_t i8xx_primary_formats[] = {
 	DRM_FORMAT_C8,
 	DRM_FORMAT_RGB565,
 	DRM_FORMAT_XRGB1555,
 	DRM_FORMAT_XRGB8888,
 };
 /* Primary plane formats for gen >= 4 */
 static const uint32_t i965_primary_formats[] = {
 	DRM_FORMAT_C8,
 	DRM_FORMAT_RGB565,
 	DRM_FORMAT_XRGB8888,
 	DRM_FORMAT_XBGR8888,
 	DRM_FORMAT_XRGB2101010,
 	DRM_FORMAT_XBGR2101010,
 };
 static const uint32_t skl_primary_formats[] = {
 	DRM_FORMAT_C8,
 	DRM_FORMAT_RGB565,
 	DRM_FORMAT_XRGB8888,
 	DRM_FORMAT_XBGR8888,
 	DRM_FORMAT_ARGB8888,
 	DRM_FORMAT_ABGR8888,
 	DRM_FORMAT_XRGB2101010,
 	DRM_FORMAT_XBGR2101010,
 	DRM_FORMAT_YUYV,
 	DRM_FORMAT_YVYU,
 	DRM_FORMAT_UYVY,
 	DRM_FORMAT_VYUY,
 };
 /* Cursor formats */
 static const uint32_t intel_cursor_formats[] = {
 	DRM_FORMAT_ARGB8888,
 };
 static void intel_crtc_update_cursor(struct drm_crtc *crtc, bool on);
 static void i9xx_crtc_clock_get(struct intel_crtc *crtc,
 				struct intel_crtc_state *pipe_config);
 static void ironlake_pch_clock_get(struct intel_crtc *crtc,
 				   struct intel_crtc_state *pipe_config);
 static int intel_framebuffer_init(struct drm_device *dev,
 				  struct intel_framebuffer *ifb,
 				  struct drm_mode_fb_cmd2 *mode_cmd,
 				  struct drm_i915_gem_object *obj);
 static void i9xx_set_pipeconf(struct intel_crtc *intel_crtc);
 static void intel_set_pipe_timings(struct intel_crtc *intel_crtc);
 static void intel_cpu_transcoder_set_m_n(struct intel_crtc *crtc,
 					 struct intel_link_m_n *m_n,
 					 struct intel_link_m_n *m2_n2);
 static void ironlake_set_pipeconf(struct drm_crtc *crtc);
 static void haswell_set_pipeconf(struct drm_crtc *crtc);
 static void intel_set_pipe_csc(struct drm_crtc *crtc);
 static void vlv_prepare_pll(struct intel_crtc *crtc,
 			    const struct intel_crtc_state *pipe_config);
 static void chv_prepare_pll(struct intel_crtc *crtc,
 			    const struct intel_crtc_state *pipe_config);
 static void intel_begin_crtc_commit(struct drm_crtc *, struct drm_crtc_state *);
 static void intel_finish_crtc_commit(struct drm_crtc *, struct drm_crtc_state *);
 static void skl_init_scalers(struct drm_device *dev, struct intel_crtc *intel_crtc,
 	struct intel_crtc_state *crtc_state);
 static int i9xx_get_refclk(const struct intel_crtc_state *crtc_state,
 			   int num_connectors);
 static void skylake_pfit_enable(struct intel_crtc *crtc);
 static void ironlake_pfit_disable(struct intel_crtc *crtc, bool force);
 static void ironlake_pfit_enable(struct intel_crtc *crtc);
 static void intel_modeset_setup_hw_state(struct drm_device *dev);
 static void intel_pre_disable_primary(struct drm_crtc *crtc);
 typedef struct {
 	int	min, max;
 } intel_range_t;
 typedef struct {
 	int	dot_limit;
 	int	p2_slow, p2_fast;
 } intel_p2_t;
 typedef struct intel_limit intel_limit_t;
 struct intel_limit {
 	intel_range_t   dot, vco, n, m, m1, m2, p, p1;
 	intel_p2_t	    p2;
 };
 /* returns HPLL frequency in kHz */
 static int valleyview_get_vco(struct drm_i915_private *dev_priv)
+{
 	int hpll_freq, vco_freq[] = { 800, 1600, 2000, 2400 };
 	/* Obtain SKU information */
 	mutex_lock(&dev_priv->sb_lock);
 	hpll_freq = vlv_cck_read(dev_priv, CCK_FUSE_REG) &
 		CCK_FUSE_HPLL_FREQ_MASK;
 	mutex_unlock(&dev_priv->sb_lock);
 	return vco_freq[hpll_freq] * 1000;
+}
 static int vlv_get_cck_clock_hpll(struct drm_i915_private *dev_priv,
 				  const char *name, u32 reg)
+{
 	u32 val;
 	int divider;
 	if (dev_priv->hpll_freq == 0)
 		dev_priv->hpll_freq = valleyview_get_vco(dev_priv);
 	mutex_lock(&dev_priv->sb_lock);
 	val = vlv_cck_read(dev_priv, reg);
 	mutex_unlock(&dev_priv->sb_lock);
 	divider = val & CCK_FREQUENCY_VALUES;
 	WARN((val & CCK_FREQUENCY_STATUS) !=
 	     (divider << CCK_FREQUENCY_STATUS_SHIFT),
 	     "%s change in progress\n", name);
 	return DIV_ROUND_CLOSEST(dev_priv->hpll_freq << 1, divider + 1);
+}
 int
 intel_pch_rawclk(struct drm_device *dev)
+{
 	struct drm_i915_private *dev_priv = dev->dev_private;
 	WARN_ON(!HAS_PCH_SPLIT(dev));
 	return I915_READ(PCH_RAWCLK_FREQ) & RAWCLK_FREQ_MASK;
+}
 /* hrawclock is 1/4 the FSB frequency */
 int intel_hrawclk(struct drm_device *dev)
+{
 	struct drm_i915_private *dev_priv = dev->dev_private;
 	uint32_t clkcfg;
 	/* There is no CLKCFG reg in Valleyview. VLV hrawclk is 200 MHz */
 	if (IS_VALLEYVIEW(dev))
 		return 200;
 	clkcfg = I915_READ(CLKCFG);
 	switch (clkcfg & CLKCFG_FSB_MASK) {
 	case CLKCFG_FSB_400:
 		return 100;
 	case CLKCFG_FSB_533:
 		return 133;
 	case CLKCFG_FSB_667:
 		return 166;
 	case CLKCFG_FSB_800:
 		return 200;
 	case CLKCFG_FSB_1067:
 		return 266;
 	case CLKCFG_FSB_1333:
 		return 333;
 	/* these two are just a guess; one of them might be right */
 	case CLKCFG_FSB_1600:
 	case CLKCFG_FSB_1600_ALT:
 		return 400;
 	default:
 		return 133;
+	}
+}
 static void intel_update_czclk(struct drm_i915_private *dev_priv)
+{
 	if (!IS_VALLEYVIEW(dev_priv))
 		return;
 	dev_priv->czclk_freq = vlv_get_cck_clock_hpll(dev_priv, "czclk",
 						      CCK_CZ_CLOCK_CONTROL);
 	DRM_DEBUG_DRIVER("CZ clock rate: %d kHz\n", dev_priv->czclk_freq);
+}
 static inline u32 /* units of 100MHz */
 intel_fdi_link_freq(struct drm_device *dev)
+{
 	if (IS_GEN5(dev)) {
 		struct drm_i915_private *dev_priv = dev->dev_private;
 		return (I915_READ(FDI_PLL_BIOS_0) & FDI_PLL_FB_CLOCK_MASK) + 2;
 	} else
 		return 27;
+}
 static const intel_limit_t intel_limits_i8xx_dac = {
 	.dot = { .min = 25000, .max = 350000 },
 	.vco = { .min = 908000, .max = 1512000 },
 	.n = { .min = 2, .max = 16 },
 	.m = { .min = 96, .max = 140 },
 	.m1 = { .min = 18, .max = 26 },
 	.m2 = { .min = 6, .max = 16 },
 	.p = { .min = 4, .max = 128 },
 	.p1 = { .min = 2, .max = 33 },
 	.p2 = { .dot_limit = 165000,
 		.p2_slow = 4, .p2_fast = 2 },
 };
 static const intel_limit_t intel_limits_i8xx_dvo = {
 	.dot = { .min = 25000, .max = 350000 },
 	.vco = { .min = 908000, .max = 1512000 },
 	.n = { .min = 2, .max = 16 },
 	.m = { .min = 96, .max = 140 },
 	.m1 = { .min = 18, .max = 26 },
 	.m2 = { .min = 6, .max = 16 },
 	.p = { .min = 4, .max = 128 },
 	.p1 = { .min = 2, .max = 33 },
 	.p2 = { .dot_limit = 165000,
 		.p2_slow = 4, .p2_fast = 4 },
 };
 static const intel_limit_t intel_limits_i8xx_lvds = {
 	.dot = { .min = 25000, .max = 350000 },
 	.vco = { .min = 908000, .max = 1512000 },
 	.n = { .min = 2, .max = 16 },
 	.m = { .min = 96, .max = 140 },
 	.m1 = { .min = 18, .max = 26 },
 	.m2 = { .min = 6, .max = 16 },
 	.p = { .min = 4, .max = 128 },
 	.p1 = { .min = 1, .max = 6 },
 	.p2 = { .dot_limit = 165000,
 		.p2_slow = 14, .p2_fast = 7 },
 };
 static const intel_limit_t intel_limits_i9xx_sdvo = {
 	.dot = { .min = 20000, .max = 400000 },
 	.vco = { .min = 1400000, .max = 2800000 },
 	.n = { .min = 1, .max = 6 },
 	.m = { .min = 70, .max = 120 },
 	.m1 = { .min = 8, .max = 18 },
 	.m2 = { .min = 3, .max = 7 },
 	.p = { .min = 5, .max = 80 },
 	.p1 = { .min = 1, .max = 8 },
 	.p2 = { .dot_limit = 200000,
 		.p2_slow = 10, .p2_fast = 5 },
 };
 static const intel_limit_t intel_limits_i9xx_lvds = {
 	.dot = { .min = 20000, .max = 400000 },
 	.vco = { .min = 1400000, .max = 2800000 },
 	.n = { .min = 1, .max = 6 },
 	.m = { .min = 70, .max = 120 },
 	.m1 = { .min = 8, .max = 18 },
 	.m2 = { .min = 3, .max = 7 },
 	.p = { .min = 7, .max = 98 },
 	.p1 = { .min = 1, .max = 8 },
 	.p2 = { .dot_limit = 112000,
 		.p2_slow = 14, .p2_fast = 7 },
 };
 static const intel_limit_t intel_limits_g4x_sdvo = {
 	.dot = { .min = 25000, .max = 270000 },
 	.vco = { .min = 1750000, .max = 3500000},
 	.n = { .min = 1, .max = 4 },
 	.m = { .min = 104, .max = 138 },
 	.m1 = { .min = 17, .max = 23 },
 	.m2 = { .min = 5, .max = 11 },
 	.p = { .min = 10, .max = 30 },
 	.p1 = { .min = 1, .max = 3},
 	.p2 = { .dot_limit = 270000,
 		.p2_slow = 10,
 		.p2_fast = 10
 	},
 };
 static const intel_limit_t intel_limits_g4x_hdmi = {
 	.dot = { .min = 22000, .max = 400000 },
 	.vco = { .min = 1750000, .max = 3500000},
 	.n = { .min = 1, .max = 4 },
 	.m = { .min = 104, .max = 138 },
 	.m1 = { .min = 16, .max = 23 },
 	.m2 = { .min = 5, .max = 11 },
 	.p = { .min = 5, .max = 80 },
 	.p1 = { .min = 1, .max = 8},
 	.p2 = { .dot_limit = 165000,
 		.p2_slow = 10, .p2_fast = 5 },
 };
 static const intel_limit_t intel_limits_g4x_single_channel_lvds = {
 	.dot = { .min = 20000, .max = 115000 },
 	.vco = { .min = 1750000, .max = 3500000 },
 	.n = { .min = 1, .max = 3 },
 	.m = { .min = 104, .max = 138 },
 	.m1 = { .min = 17, .max = 23 },
 	.m2 = { .min = 5, .max = 11 },
 	.p = { .min = 28, .max = 112 },
 	.p1 = { .min = 2, .max = 8 },
 	.p2 = { .dot_limit = 0,
 		.p2_slow = 14, .p2_fast = 14
 	},
 };
 static const intel_limit_t intel_limits_g4x_dual_channel_lvds = {
 	.dot = { .min = 80000, .max = 224000 },
 	.vco = { .min = 1750000, .max = 3500000 },
 	.n = { .min = 1, .max = 3 },
 	.m = { .min = 104, .max = 138 },
 	.m1 = { .min = 17, .max = 23 },
 	.m2 = { .min = 5, .max = 11 },
 	.p = { .min = 14, .max = 42 },
 	.p1 = { .min = 2, .max = 6 },
 	.p2 = { .dot_limit = 0,
 		.p2_slow = 7, .p2_fast = 7
 	},
 };
 static const intel_limit_t intel_limits_pineview_sdvo = {
 	.dot = { .min = 20000, .max = 400000},
 	.vco = { .min = 1700000, .max = 3500000 },
 	/* Pineview's Ncounter is a ring counter */
 	.n = { .min = 3, .max = 6 },
 	.m = { .min = 2, .max = 256 },
 	/* Pineview only has one combined m divider, which we treat as m2. */
 	.m1 = { .min = 0, .max = 0 },
 	.m2 = { .min = 0, .max = 254 },
 	.p = { .min = 5, .max = 80 },
 	.p1 = { .min = 1, .max = 8 },
 	.p2 = { .dot_limit = 200000,
 		.p2_slow = 10, .p2_fast = 5 },
 };
 static const intel_limit_t intel_limits_pineview_lvds = {
 	.dot = { .min = 20000, .max = 400000 },
 	.vco = { .min = 1700000, .max = 3500000 },
 	.n = { .min = 3, .max = 6 },
 	.m = { .min = 2, .max = 256 },
 	.m1 = { .min = 0, .max = 0 },
 	.m2 = { .min = 0, .max = 254 },
 	.p = { .min = 7, .max = 112 },
 	.p1 = { .min = 1, .max = 8 },
 	.p2 = { .dot_limit = 112000,
 		.p2_slow = 14, .p2_fast = 14 },
 };
 /* Ironlake / Sandybridge
+ *
  * We calculate clock using (register_value + 2) for N/M1/M2, so here
  * the range value for them is (actual_value - 2).
  */
 static const intel_limit_t intel_limits_ironlake_dac = {
 	.dot = { .min = 25000, .max = 350000 },
 	.vco = { .min = 1760000, .max = 3510000 },
 	.n = { .min = 1, .max = 5 },
 	.m = { .min = 79, .max = 127 },
 	.m1 = { .min = 12, .max = 22 },
 	.m2 = { .min = 5, .max = 9 },
 	.p = { .min = 5, .max = 80 },
 	.p1 = { .min = 1, .max = 8 },
 	.p2 = { .dot_limit = 225000,
 		.p2_slow = 10, .p2_fast = 5 },
 };
 static const intel_limit_t intel_limits_ironlake_single_lvds = {
 	.dot = { .min = 25000, .max = 350000 },
 	.vco = { .min = 1760000, .max = 3510000 },
 	.n = { .min = 1, .max = 3 },
 	.m = { .min = 79, .max = 118 },
 	.m1 = { .min = 12, .max = 22 },
 	.m2 = { .min = 5, .max = 9 },
 	.p = { .min = 28, .max = 112 },
 	.p1 = { .min = 2, .max = 8 },
 	.p2 = { .dot_limit = 225000,
 		.p2_slow = 14, .p2_fast = 14 },
 };
 static const intel_limit_t intel_limits_ironlake_dual_lvds = {
 	.dot = { .min = 25000, .max = 350000 },
 	.vco = { .min = 1760000, .max = 3510000 },
 	.n = { .min = 1, .max = 3 },
 	.m = { .min = 79, .max = 127 },
 	.m1 = { .min = 12, .max = 22 },
 	.m2 = { .min = 5, .max = 9 },
 	.p = { .min = 14, .max = 56 },
 	.p1 = { .min = 2, .max = 8 },
 	.p2 = { .dot_limit = 225000,
 		.p2_slow = 7, .p2_fast = 7 },
 };
 /* LVDS 100mhz refclk limits. */
 static const intel_limit_t intel_limits_ironlake_single_lvds_100m = {
 	.dot = { .min = 25000, .max = 350000 },
 	.vco = { .min = 1760000, .max = 3510000 },
 	.n = { .min = 1, .max = 2 },
 	.m = { .min = 79, .max = 126 },
 	.m1 = { .min = 12, .max = 22 },
 	.m2 = { .min = 5, .max = 9 },
 	.p = { .min = 28, .max = 112 },
 	.p1 = { .min = 2, .max = 8 },
 	.p2 = { .dot_limit = 225000,
 		.p2_slow = 14, .p2_fast = 14 },
 };
 static const intel_limit_t intel_limits_ironlake_dual_lvds_100m = {
 	.dot = { .min = 25000, .max = 350000 },
 	.vco = { .min = 1760000, .max = 3510000 },
 	.n = { .min = 1, .max = 3 },
 	.m = { .min = 79, .max = 126 },
 	.m1 = { .min = 12, .max = 22 },
 	.m2 = { .min = 5, .max = 9 },
 	.p = { .min = 14, .max = 42 },
 	.p1 = { .min = 2, .max = 6 },
 	.p2 = { .dot_limit = 225000,
 		.p2_slow = 7, .p2_fast = 7 },
 };
 static const intel_limit_t intel_limits_vlv = {
 	 /*
 	  * These are the data rate limits (measured in fast clocks)
 	  * since those are the strictest limits we have. The fast
 	  * clock and actual rate limits are more relaxed, so checking
 	  * them would make no difference.
 	  */
 	.dot = { .min = 25000 * 5, .max = 270000 * 5 },
 	.vco = { .min = 4000000, .max = 6000000 },
 	.n = { .min = 1, .max = 7 },
 	.m1 = { .min = 2, .max = 3 },
 	.m2 = { .min = 11, .max = 156 },
 	.p1 = { .min = 2, .max = 3 },
 	.p2 = { .p2_slow = 2, .p2_fast = 20 }, /* slow=min, fast=max */
 };
 static const intel_limit_t intel_limits_chv = {
 	/*
 	 * These are the data rate limits (measured in fast clocks)
 	 * since those are the strictest limits we have.  The fast
 	 * clock and actual rate limits are more relaxed, so checking
 	 * them would make no difference.
 	 */
 	.dot = { .min = 25000 * 5, .max = 540000 * 5},
 	.vco = { .min = 4800000, .max = 6480000 },
 	.n = { .min = 1, .max = 1 },
 	.m1 = { .min = 2, .max = 2 },
 	.m2 = { .min = 24 << 22, .max = 175 << 22 },
 	.p1 = { .min = 2, .max = 4 },
 	.p2 = {	.p2_slow = 1, .p2_fast = 14 },
 };
 static const intel_limit_t intel_limits_bxt = {
 	/* FIXME: find real dot limits */
 	.dot = { .min = 0, .max = INT_MAX },
 	.vco = { .min = 4800000, .max = 6700000 },
 	.n = { .min = 1, .max = 1 },
 	.m1 = { .min = 2, .max = 2 },
 	/* FIXME: find real m2 limits */
 	.m2 = { .min = 2 << 22, .max = 255 << 22 },
 	.p1 = { .min = 2, .max = 4 },
 	.p2 = { .p2_slow = 1, .p2_fast = 20 },
 };
 static bool
 needs_modeset(struct drm_crtc_state *state)
+{
 	return drm_atomic_crtc_needs_modeset(state);
+}
 /**
  * Returns whether any output on the specified pipe is of the specified type
  */
 bool intel_pipe_has_type(struct intel_crtc *crtc, enum intel_output_type type)
+{
 	struct drm_device *dev = crtc->base.dev;
 	struct intel_encoder *encoder;
 	for_each_encoder_on_crtc(dev, &crtc->base, encoder)
 		if (encoder->type == type)
 			return true;
 	return false;
+}
 /**
  * Returns whether any output on the specified pipe will have the specified
  * type after a staged modeset is complete, i.e., the same as
  * intel_pipe_has_type() but looking at encoder->new_crtc instead of
  * encoder->crtc.
  */
 static bool intel_pipe_will_have_type(const struct intel_crtc_state *crtc_state,
 				      int type)
+{
 	struct drm_atomic_state *state = crtc_state->base.state;
 	struct drm_connector *connector;
 	struct drm_connector_state *connector_state;
 	struct intel_encoder *encoder;
 	int i, num_connectors = 0;
 	for_each_connector_in_state(state, connector, connector_state, i) {
 		if (connector_state->crtc != crtc_state->base.crtc)
 			continue;
 		num_connectors++;
 		encoder = to_intel_encoder(connector_state->best_encoder);
 		if (encoder->type == type)
 			return true;
+	}
 	WARN_ON(num_connectors == 0);
 	return false;
+}
 static const intel_limit_t *
 intel_ironlake_limit(struct intel_crtc_state *crtc_state, int refclk)
+{
 	struct drm_device *dev = crtc_state->base.crtc->dev;
 	const intel_limit_t *limit;
 	if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS)) {
 		if (intel_is_dual_link_lvds(dev)) {
 			if (refclk == 100000)
 				limit = &intel_limits_ironlake_dual_lvds_100m;
 			else
 				limit = &intel_limits_ironlake_dual_lvds;
 		} else {
 			if (refclk == 100000)
 				limit = &intel_limits_ironlake_single_lvds_100m;
 			else
 				limit = &intel_limits_ironlake_single_lvds;
+		}
 	} else
 		limit = &intel_limits_ironlake_dac;
 	return limit;
+}
 static const intel_limit_t *
 intel_g4x_limit(struct intel_crtc_state *crtc_state)
+{
 	struct drm_device *dev = crtc_state->base.crtc->dev;
 	const intel_limit_t *limit;
 	if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS)) {
 		if (intel_is_dual_link_lvds(dev))
 			limit = &intel_limits_g4x_dual_channel_lvds;
 		else
 			limit = &intel_limits_g4x_single_channel_lvds;
 	} else if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_HDMI) ||
 		   intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_ANALOG)) {
 		limit = &intel_limits_g4x_hdmi;
 	} else if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_SDVO)) {
 		limit = &intel_limits_g4x_sdvo;
 	} else /* The option is for other outputs */
 		limit = &intel_limits_i9xx_sdvo;
 	return limit;
+}
 static const intel_limit_t *
 intel_limit(struct intel_crtc_state *crtc_state, int refclk)
+{
 	struct drm_device *dev = crtc_state->base.crtc->dev;
 	const intel_limit_t *limit;
 	if (IS_BROXTON(dev))
 		limit = &intel_limits_bxt;
 	else if (HAS_PCH_SPLIT(dev))
 		limit = intel_ironlake_limit(crtc_state, refclk);
 	else if (IS_G4X(dev)) {
 		limit = intel_g4x_limit(crtc_state);
 	} else if (IS_PINEVIEW(dev)) {
 		if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS))
 			limit = &intel_limits_pineview_lvds;
 		else
 			limit = &intel_limits_pineview_sdvo;
 	} else if (IS_CHERRYVIEW(dev)) {
 		limit = &intel_limits_chv;
 	} else if (IS_VALLEYVIEW(dev)) {
 		limit = &intel_limits_vlv;
 	} else if (!IS_GEN2(dev)) {
 		if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS))
 			limit = &intel_limits_i9xx_lvds;
 		else
 			limit = &intel_limits_i9xx_sdvo;
 	} else {
 		if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS))
 			limit = &intel_limits_i8xx_lvds;
 		else if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_DVO))
 			limit = &intel_limits_i8xx_dvo;
 		else
 			limit = &intel_limits_i8xx_dac;
+	}
 	return limit;
+}
 /*
  * Platform specific helpers to calculate the port PLL loopback- (clock.m),
  * and post-divider (clock.p) values, pre- (clock.vco) and post-divided fast
  * (clock.dot) clock rates. This fast dot clock is fed to the port's IO logic.
  * The helpers' return value is the rate of the clock that is fed to the
  * display engine's pipe which can be the above fast dot clock rate or a
  * divided-down version of it.
  */
 /* m1 is reserved as 0 in Pineview, n is a ring counter */
 static int pnv_calc_dpll_params(int refclk, intel_clock_t *clock)
+{
 	clock->m = clock->m2 + 2;
 	clock->p = clock->p1 * clock->p2;
 	if (WARN_ON(clock->n == 0 || clock->p == 0))
 		return 0;
 	clock->vco = DIV_ROUND_CLOSEST(refclk * clock->m, clock->n);
 	clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
 	return clock->dot;
+}
 static uint32_t i9xx_dpll_compute_m(struct dpll *dpll)
+{
 	return 5 * (dpll->m1 + 2) + (dpll->m2 + 2);
+}
 static int i9xx_calc_dpll_params(int refclk, intel_clock_t *clock)
+{
 	clock->m = i9xx_dpll_compute_m(clock);
 	clock->p = clock->p1 * clock->p2;
 	if (WARN_ON(clock->n + 2 == 0 || clock->p == 0))
 		return 0;
 	clock->vco = DIV_ROUND_CLOSEST(refclk * clock->m, clock->n + 2);
 	clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
 	return clock->dot;
+}
 static int vlv_calc_dpll_params(int refclk, intel_clock_t *clock)
+{
 	clock->m = clock->m1 * clock->m2;
 	clock->p = clock->p1 * clock->p2;
 	if (WARN_ON(clock->n == 0 || clock->p == 0))
 		return 0;
 	clock->vco = DIV_ROUND_CLOSEST(refclk * clock->m, clock->n);
 	clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
 	return clock->dot / 5;
+}
 int chv_calc_dpll_params(int refclk, intel_clock_t *clock)
+{
 	clock->m = clock->m1 * clock->m2;
 	clock->p = clock->p1 * clock->p2;
 	if (WARN_ON(clock->n == 0 || clock->p == 0))
 		return 0;
 	clock->vco = DIV_ROUND_CLOSEST_ULL((uint64_t)refclk * clock->m,
 			clock->n << 22);
 	clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
 	return clock->dot / 5;
+}
 #define INTELPllInvalid(s)   do { /* DRM_DEBUG(s); */ return false; } while (0)
 /**
  * Returns whether the given set of divisors are valid for a given refclk with
  * the given connectors.
  */
 static bool intel_PLL_is_valid(struct drm_device *dev,
 			       const intel_limit_t *limit,
 			       const intel_clock_t *clock)
+{
 	if (clock->n   < limit->n.min   || limit->n.max   < clock->n)
 		INTELPllInvalid("n out of range\n");
 	if (clock->p1  < limit->p1.min  || limit->p1.max  < clock->p1)
 		INTELPllInvalid("p1 out of range\n");
 	if (clock->m2  < limit->m2.min  || limit->m2.max  < clock->m2)
 		INTELPllInvalid("m2 out of range\n");
 	if (clock->m1  < limit->m1.min  || limit->m1.max  < clock->m1)
 		INTELPllInvalid("m1 out of range\n");
 	if (!IS_PINEVIEW(dev) && !IS_VALLEYVIEW(dev) && !IS_BROXTON(dev))
 		if (clock->m1 <= clock->m2)
 			INTELPllInvalid("m1 <= m2\n");
 	if (!IS_VALLEYVIEW(dev) && !IS_BROXTON(dev)) {
 		if (clock->p < limit->p.min || limit->p.max < clock->p)
 			INTELPllInvalid("p out of range\n");
 		if (clock->m < limit->m.min || limit->m.max < clock->m)
 			INTELPllInvalid("m out of range\n");
+	}
 	if (clock->vco < limit->vco.min || limit->vco.max < clock->vco)
 		INTELPllInvalid("vco out of range\n");
 	/* XXX: We may need to be checking "Dot clock" depending on the multiplier,
 	 * connector, etc., rather than just a single range.
 	 */
 	if (clock->dot < limit->dot.min || limit->dot.max < clock->dot)
 		INTELPllInvalid("dot out of range\n");
 	return true;
+}
 static int
 i9xx_select_p2_div(const intel_limit_t *limit,
 		   const struct intel_crtc_state *crtc_state,
 		   int target)
+{
 	struct drm_device *dev = crtc_state->base.crtc->dev;
 	if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS)) {
 		/*
 		 * For LVDS just rely on its current settings for dual-channel.
 		 * We haven't figured out how to reliably set up different
 		 * single/dual channel state, if we even can.
 		 */
 		if (intel_is_dual_link_lvds(dev))
 			return limit->p2.p2_fast;
 		else
 			return limit->p2.p2_slow;
 	} else {
 		if (target < limit->p2.dot_limit)
 			return limit->p2.p2_slow;
 		else
 			return limit->p2.p2_fast;
+	}
+}
 static bool
 i9xx_find_best_dpll(const intel_limit_t *limit,
 		    struct intel_crtc_state *crtc_state,
 		    int target, int refclk, intel_clock_t *match_clock,
 		    intel_clock_t *best_clock)
+{
 	struct drm_device *dev = crtc_state->base.crtc->dev;
 	intel_clock_t clock;
 	int err = target;
 	memset(best_clock, 0, sizeof(*best_clock));
 	clock.p2 = i9xx_select_p2_div(limit, crtc_state, target);
 	for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max;
 	     clock.m1++) {
 		for (clock.m2 = limit->m2.min;
 		     clock.m2 <= limit->m2.max; clock.m2++) {
 			if (clock.m2 >= clock.m1)
 				break;
 			for (clock.n = limit->n.min;
 			     clock.n <= limit->n.max; clock.n++) {
 				for (clock.p1 = limit->p1.min;
 					clock.p1 <= limit->p1.max; clock.p1++) {
 					int this_err;
 					i9xx_calc_dpll_params(refclk, &clock);
 					if (!intel_PLL_is_valid(dev, limit,
 								&clock))
 						continue;
 					if (match_clock &&
 					    clock.p != match_clock->p)
 						continue;
 					this_err = abs(clock.dot - target);
 					if (this_err < err) {
 						*best_clock = clock;
 						err = this_err;
+					}
+				}
+			}
+		}
+	}
 	return (err != target);
+}
 static bool
 pnv_find_best_dpll(const intel_limit_t *limit,
 		   struct intel_crtc_state *crtc_state,
 		   int target, int refclk, intel_clock_t *match_clock,
 		   intel_clock_t *best_clock)
+{
 	struct drm_device *dev = crtc_state->base.crtc->dev;
 	intel_clock_t clock;
 	int err = target;
 	memset(best_clock, 0, sizeof(*best_clock));
 	clock.p2 = i9xx_select_p2_div(limit, crtc_state, target);
 	for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max;
 	     clock.m1++) {
 		for (clock.m2 = limit->m2.min;
 		     clock.m2 <= limit->m2.max; clock.m2++) {
 			for (clock.n = limit->n.min;
 			     clock.n <= limit->n.max; clock.n++) {
 				for (clock.p1 = limit->p1.min;
 					clock.p1 <= limit->p1.max; clock.p1++) {
 					int this_err;
 					pnv_calc_dpll_params(refclk, &clock);
 					if (!intel_PLL_is_valid(dev, limit,
 								&clock))
 						continue;
 					if (match_clock &&
 					    clock.p != match_clock->p)
 						continue;
 					this_err = abs(clock.dot - target);
 					if (this_err < err) {
 						*best_clock = clock;
 						err = this_err;
+					}
+				}
+			}
+		}
+	}
 	return (err != target);
+}
 static bool
 g4x_find_best_dpll(const intel_limit_t *limit,
 		   struct intel_crtc_state *crtc_state,
 		   int target, int refclk, intel_clock_t *match_clock,
 		   intel_clock_t *best_clock)
+{
 	struct drm_device *dev = crtc_state->base.crtc->dev;
 	intel_clock_t clock;
 	int max_n;
 	bool found = false;
 	/* approximately equals target * 0.00585 */
 	int err_most = (target >> 8) + (target >> 9);
 	memset(best_clock, 0, sizeof(*best_clock));
 	clock.p2 = i9xx_select_p2_div(limit, crtc_state, target);
 	max_n = limit->n.max;
 	/* based on hardware requirement, prefer smaller n to precision */
 	for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) {
 		/* based on hardware requirement, prefere larger m1,m2 */
 		for (clock.m1 = limit->m1.max;
 		     clock.m1 >= limit->m1.min; clock.m1--) {
 			for (clock.m2 = limit->m2.max;
 			     clock.m2 >= limit->m2.min; clock.m2--) {
 				for (clock.p1 = limit->p1.max;
 				     clock.p1 >= limit->p1.min; clock.p1--) {
 					int this_err;
 					i9xx_calc_dpll_params(refclk, &clock);
 					if (!intel_PLL_is_valid(dev, limit,
 								&clock))
 						continue;
 					this_err = abs(clock.dot - target);
 					if (this_err < err_most) {
 						*best_clock = clock;
 						err_most = this_err;
 						max_n = clock.n;
 						found = true;
+					}
+				}
+			}
+		}
+	}
 	return found;
+}
 /*
  * Check if the calculated PLL configuration is more optimal compared to the
  * best configuration and error found so far. Return the calculated error.
  */
 static bool vlv_PLL_is_optimal(struct drm_device *dev, int target_freq,
 			       const intel_clock_t *calculated_clock,
 			       const intel_clock_t *best_clock,
 			       unsigned int best_error_ppm,
 			       unsigned int *error_ppm)
+{
 	/*
 	 * For CHV ignore the error and consider only the P value.
 	 * Prefer a bigger P value based on HW requirements.
 	 */
 	if (IS_CHERRYVIEW(dev)) {
 		*error_ppm = 0;
 		return calculated_clock->p > best_clock->p;
+	}
 	if (WARN_ON_ONCE(!target_freq))
 		return false;
 	*error_ppm = div_u64(1000000ULL *
 				abs(target_freq - calculated_clock->dot),
 			     target_freq);
 	/*
 	 * Prefer a better P value over a better (smaller) error if the error
 	 * is small. Ensure this preference for future configurations too by
 	 * setting the error to 0.
 	 */
 	if (*error_ppm < 100 && calculated_clock->p > best_clock->p) {
 		*error_ppm = 0;
 		return true;
+	}
 	return *error_ppm + 10 < best_error_ppm;
+}
 static bool
 vlv_find_best_dpll(const intel_limit_t *limit,
 		   struct intel_crtc_state *crtc_state,
 		   int target, int refclk, intel_clock_t *match_clock,
 		   intel_clock_t *best_clock)
+{
 	struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
 	struct drm_device *dev = crtc->base.dev;
 	intel_clock_t clock;
 	unsigned int bestppm = 1000000;
 	/* min update 19.2 MHz */
 	int max_n = min(limit->n.max, refclk / 19200);
 	bool found = false;
 	target *= 5; /* fast clock */
 	memset(best_clock, 0, sizeof(*best_clock));
 	/* based on hardware requirement, prefer smaller n to precision */
 	for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) {
 		for (clock.p1 = limit->p1.max; clock.p1 >= limit->p1.min; clock.p1--) {
 			for (clock.p2 = limit->p2.p2_fast; clock.p2 >= limit->p2.p2_slow;
 			     clock.p2 -= clock.p2 > 10 ? 2 : 1) {
 				clock.p = clock.p1 * clock.p2;
 				/* based on hardware requirement, prefer bigger m1,m2 values */
 				for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max; clock.m1++) {
 					unsigned int ppm;
 					clock.m2 = DIV_ROUND_CLOSEST(target * clock.p * clock.n,
 								     refclk * clock.m1);
 					vlv_calc_dpll_params(refclk, &clock);
 					if (!intel_PLL_is_valid(dev, limit,
 								&clock))
 						continue;
 					if (!vlv_PLL_is_optimal(dev, target,
 								&clock,
 								best_clock,
 								bestppm, &ppm))
 						continue;
 					*best_clock = clock;
 					bestppm = ppm;
 					found = true;
+				}
+			}
+		}
+	}
 	return found;
+}
 static bool
 chv_find_best_dpll(const intel_limit_t *limit,
 		   struct intel_crtc_state *crtc_state,
 		   int target, int refclk, intel_clock_t *match_clock,
 		   intel_clock_t *best_clock)
+{
 	struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
 	struct drm_device *dev = crtc->base.dev;
 	unsigned int best_error_ppm;
 	intel_clock_t clock;
 	uint64_t m2;
 	int found = false;
 	memset(best_clock, 0, sizeof(*best_clock));
 	best_error_ppm = 1000000;
 	/*
 	 * Based on hardware doc, the n always set to 1, and m1 always
 	 * set to 2.  If requires to support 200Mhz refclk, we need to
 	 * revisit this because n may not 1 anymore.
 	 */
 @@ -13774,2180 +13774,2185 @@ static struct drm_plane *intel_primary_p
 	primary->check_plane = intel_check_primary_plane;
 	primary->commit_plane = intel_commit_primary_plane;
 	primary->disable_plane = intel_disable_primary_plane;
 	if (HAS_FBC(dev) && INTEL_INFO(dev)->gen < 4)
 		primary->plane = !pipe;
 	if (INTEL_INFO(dev)->gen >= 9) {
 		intel_primary_formats = skl_primary_formats;
 		num_formats = ARRAY_SIZE(skl_primary_formats);
 	} else if (INTEL_INFO(dev)->gen >= 4) {
 		intel_primary_formats = i965_primary_formats;
 		num_formats = ARRAY_SIZE(i965_primary_formats);
 	} else {
 		intel_primary_formats = i8xx_primary_formats;
 		num_formats = ARRAY_SIZE(i8xx_primary_formats);
+	}
 	drm_universal_plane_init(dev, &primary->base, 0,
 				 &intel_plane_funcs,
 				 intel_primary_formats, num_formats,
 				 DRM_PLANE_TYPE_PRIMARY);
 	if (INTEL_INFO(dev)->gen >= 4)
 		intel_create_rotation_property(dev, primary);
 	drm_plane_helper_add(&primary->base, &intel_plane_helper_funcs);
 	return &primary->base;
+}
 void intel_create_rotation_property(struct drm_device *dev, struct intel_plane *plane)
+{
 	if (!dev->mode_config.rotation_property) {
 		unsigned long flags = BIT(DRM_ROTATE_0) |
 			BIT(DRM_ROTATE_180);
 		if (INTEL_INFO(dev)->gen >= 9)
 			flags |= BIT(DRM_ROTATE_90) | BIT(DRM_ROTATE_270);
 		dev->mode_config.rotation_property =
 			drm_mode_create_rotation_property(dev, flags);
+	}
 	if (dev->mode_config.rotation_property)
 		drm_object_attach_property(&plane->base.base,
 				dev->mode_config.rotation_property,
 				plane->base.state->rotation);
+}
 static int
 intel_check_cursor_plane(struct drm_plane *plane,
 			 struct intel_crtc_state *crtc_state,
 			 struct intel_plane_state *state)
+{
 	struct drm_crtc *crtc = crtc_state->base.crtc;
 	struct drm_framebuffer *fb = state->base.fb;
 	struct drm_i915_gem_object *obj = intel_fb_obj(fb);
 	enum i915_pipe pipe = to_intel_plane(plane)->pipe;
 	unsigned stride;
 	int ret;
 	ret = drm_plane_helper_check_update(plane, crtc, fb, &state->src,
 					    &state->dst, &state->clip,
 					    DRM_PLANE_HELPER_NO_SCALING,
 					    DRM_PLANE_HELPER_NO_SCALING,
 					    true, true, &state->visible);
 	if (ret)
 		return ret;
 	/* if we want to turn off the cursor ignore width and height */
 	if (!obj)
 		return 0;
 	/* Check for which cursor types we support */
 	if (!cursor_size_ok(plane->dev, state->base.crtc_w, state->base.crtc_h)) {
 		DRM_DEBUG("Cursor dimension %dx%d not supported\n",
 			  state->base.crtc_w, state->base.crtc_h);
 		return -EINVAL;
+	}
 	stride = roundup_pow_of_two(state->base.crtc_w) * 4;
 	if (obj->base.size < stride * state->base.crtc_h) {
 		DRM_DEBUG_KMS("buffer is too small\n");
 		return -ENOMEM;
+	}
 	if (fb->modifier[0] != DRM_FORMAT_MOD_NONE) {
 		DRM_DEBUG_KMS("cursor cannot be tiled\n");
 		return -EINVAL;
+	}
 	/*
 	 * There's something wrong with the cursor on CHV pipe C.
 	 * If it straddles the left edge of the screen then
 	 * moving it away from the edge or disabling it often
 	 * results in a pipe underrun, and often that can lead to
 	 * dead pipe (constant underrun reported, and it scans
 	 * out just a solid color). To recover from that, the
 	 * display power well must be turned off and on again.
 	 * Refuse the put the cursor into that compromised position.
 	 */
 	if (IS_CHERRYVIEW(plane->dev) && pipe == PIPE_C &&
 	    state->visible && state->base.crtc_x < 0) {
 		DRM_DEBUG_KMS("CHV cursor C not allowed to straddle the left screen edge\n");
 		return -EINVAL;
+	}
 	return 0;
+}
 static void
 intel_disable_cursor_plane(struct drm_plane *plane,
 			   struct drm_crtc *crtc)
+{
 	intel_crtc_update_cursor(crtc, false);
+}
 static void
 intel_commit_cursor_plane(struct drm_plane *plane,
 			  struct intel_plane_state *state)
+{
 	struct drm_crtc *crtc = state->base.crtc;
 	struct drm_device *dev = plane->dev;
 	struct intel_crtc *intel_crtc;
 	struct drm_i915_gem_object *obj = intel_fb_obj(state->base.fb);
 	uint32_t addr;
 	crtc = crtc ? crtc : plane->crtc;
 	intel_crtc = to_intel_crtc(crtc);
 	if (!obj)
 		addr = 0;
 	else if (!INTEL_INFO(dev)->cursor_needs_physical)
 		addr = i915_gem_obj_ggtt_offset(obj);
 	else
 		addr = obj->phys_handle->busaddr;
 	intel_crtc->cursor_addr = addr;
 	if (crtc->state->active)
 		intel_crtc_update_cursor(crtc, state->visible);
+}
 static struct drm_plane *intel_cursor_plane_create(struct drm_device *dev,
 						   int pipe)
+{
 	struct intel_plane *cursor;
 	struct intel_plane_state *state;
 	cursor = kzalloc(sizeof(*cursor), GFP_KERNEL);
 	if (cursor == NULL)
 		return NULL;
 	state = intel_create_plane_state(&cursor->base);
 	if (!state) {
 		kfree(cursor);
 		return NULL;
+	}
 	cursor->base.state = &state->base;
 	cursor->can_scale = false;
 	cursor->max_downscale = 1;
 	cursor->pipe = pipe;
 	cursor->plane = pipe;
 	cursor->frontbuffer_bit = INTEL_FRONTBUFFER_CURSOR(pipe);
 	cursor->check_plane = intel_check_cursor_plane;
 	cursor->commit_plane = intel_commit_cursor_plane;
 	cursor->disable_plane = intel_disable_cursor_plane;
 	drm_universal_plane_init(dev, &cursor->base, 0,
 				 &intel_plane_funcs,
 				 intel_cursor_formats,
 				 ARRAY_SIZE(intel_cursor_formats),
 				 DRM_PLANE_TYPE_CURSOR);
 	if (INTEL_INFO(dev)->gen >= 4) {
 		if (!dev->mode_config.rotation_property)
 			dev->mode_config.rotation_property =
 				drm_mode_create_rotation_property(dev,
 							BIT(DRM_ROTATE_0) |
 							BIT(DRM_ROTATE_180));
 		if (dev->mode_config.rotation_property)
 			drm_object_attach_property(&cursor->base.base,
 				dev->mode_config.rotation_property,
 				state->base.rotation);
+	}
 	if (INTEL_INFO(dev)->gen >=9)
 		state->scaler_id = -1;
 	drm_plane_helper_add(&cursor->base, &intel_plane_helper_funcs);
 	return &cursor->base;
+}
 static void skl_init_scalers(struct drm_device *dev, struct intel_crtc *intel_crtc,
 	struct intel_crtc_state *crtc_state)
+{
 	int i;
 	struct intel_scaler *intel_scaler;
 	struct intel_crtc_scaler_state *scaler_state = &crtc_state->scaler_state;
 	for (i = 0; i < intel_crtc->num_scalers; i++) {
 		intel_scaler = &scaler_state->scalers[i];
 		intel_scaler->in_use = 0;
 		intel_scaler->mode = PS_SCALER_MODE_DYN;
+	}
 	scaler_state->scaler_id = -1;
+}
 static void intel_crtc_init(struct drm_device *dev, int pipe)
+{
 	struct drm_i915_private *dev_priv = dev->dev_private;
 	struct intel_crtc *intel_crtc;
 	struct intel_crtc_state *crtc_state = NULL;
 	struct drm_plane *primary = NULL;
 	struct drm_plane *cursor = NULL;
 	int i, ret;
 	intel_crtc = kzalloc(sizeof(*intel_crtc), GFP_KERNEL);
 	if (intel_crtc == NULL)
 		return;
 	crtc_state = kzalloc(sizeof(*crtc_state), GFP_KERNEL);
 	if (!crtc_state)
 		goto fail;
 	intel_crtc->config = crtc_state;
 	intel_crtc->base.state = &crtc_state->base;
 	crtc_state->base.crtc = &intel_crtc->base;
 	/* initialize shared scalers */
 	if (INTEL_INFO(dev)->gen >= 9) {
 		if (pipe == PIPE_C)
 			intel_crtc->num_scalers = 1;
 		else
 			intel_crtc->num_scalers = SKL_NUM_SCALERS;
 		skl_init_scalers(dev, intel_crtc, crtc_state);
+	}
 	primary = intel_primary_plane_create(dev, pipe);
 	if (!primary)
 		goto fail;
 	cursor = intel_cursor_plane_create(dev, pipe);
 	if (!cursor)
 		goto fail;
 	ret = drm_crtc_init_with_planes(dev, &intel_crtc->base, primary,
 					cursor, &intel_crtc_funcs);
 	if (ret)
 		goto fail;
 	drm_mode_crtc_set_gamma_size(&intel_crtc->base, 256);
 	for (i = 0; i < 256; i++) {
 		intel_crtc->lut_r[i] = i;
 		intel_crtc->lut_g[i] = i;
 		intel_crtc->lut_b[i] = i;
+	}
 	/*
 	 * On gen2/3 only plane A can do fbc, but the panel fitter and lvds port
 	 * is hooked to pipe B. Hence we want plane A feeding pipe B.
 	 */
 	intel_crtc->pipe = pipe;
 	intel_crtc->plane = pipe;
 	if (HAS_FBC(dev) && INTEL_INFO(dev)->gen < 4) {
 		DRM_DEBUG_KMS("swapping pipes & planes for FBC\n");
 		intel_crtc->plane = !pipe;
+	}
 	intel_crtc->cursor_base = ~0;
 	intel_crtc->cursor_cntl = ~0;
 	intel_crtc->cursor_size = ~0;
 	intel_crtc->wm.cxsr_allowed = true;
 	BUG_ON(pipe >= ARRAY_SIZE(dev_priv->plane_to_crtc_mapping) ||
 	       dev_priv->plane_to_crtc_mapping[intel_crtc->plane] != NULL);
 	dev_priv->plane_to_crtc_mapping[intel_crtc->plane] = &intel_crtc->base;
 	dev_priv->pipe_to_crtc_mapping[intel_crtc->pipe] = &intel_crtc->base;
 	drm_crtc_helper_add(&intel_crtc->base, &intel_helper_funcs);
 	WARN_ON(drm_crtc_index(&intel_crtc->base) != intel_crtc->pipe);
 	return;
 fail:
 	if (primary)
 		drm_plane_cleanup(primary);
 	if (cursor)
 		drm_plane_cleanup(cursor);
 	kfree(crtc_state);
 	kfree(intel_crtc);
+}
 enum i915_pipe intel_get_pipe_from_connector(struct intel_connector *connector)
+{
 	struct drm_encoder *encoder = connector->base.encoder;
 	struct drm_device *dev = connector->base.dev;
 	WARN_ON(!drm_modeset_is_locked(&dev->mode_config.connection_mutex));
 	if (!encoder || WARN_ON(!encoder->crtc))
 		return INVALID_PIPE;
 	return to_intel_crtc(encoder->crtc)->pipe;
+}
 int intel_get_pipe_from_crtc_id(struct drm_device *dev, void *data,
 				struct drm_file *file)
+{
 	struct drm_i915_get_pipe_from_crtc_id *pipe_from_crtc_id = data;
 	struct drm_crtc *drmmode_crtc;
 	struct intel_crtc *crtc;
 	drmmode_crtc = drm_crtc_find(dev, pipe_from_crtc_id->crtc_id);
 	if (!drmmode_crtc) {
 		DRM_ERROR("no such CRTC id\n");
 		return -ENOENT;
+	}
 	crtc = to_intel_crtc(drmmode_crtc);
 	pipe_from_crtc_id->pipe = crtc->pipe;
 	return 0;
+}
 static int intel_encoder_clones(struct intel_encoder *encoder)
+{
 	struct drm_device *dev = encoder->base.dev;
 	struct intel_encoder *source_encoder;
 	int index_mask = 0;
 	int entry = 0;
 	for_each_intel_encoder(dev, source_encoder) {
 		if (encoders_cloneable(encoder, source_encoder))
 			index_mask |= (1 << entry);
 		entry++;
+	}
 	return index_mask;
+}
 static bool has_edp_a(struct drm_device *dev)
+{
 	struct drm_i915_private *dev_priv = dev->dev_private;
 	if (!IS_MOBILE(dev))
 		return false;
 	if ((I915_READ(DP_A) & DP_DETECTED) == 0)
 		return false;
 	if (IS_GEN5(dev) && (I915_READ(FUSE_STRAP) & ILK_eDP_A_DISABLE))
 		return false;
 	return true;
+}
 static bool intel_crt_present(struct drm_device *dev)
+{
 	struct drm_i915_private *dev_priv = dev->dev_private;
 	if (INTEL_INFO(dev)->gen >= 9)
 		return false;
 	if (IS_HSW_ULT(dev) || IS_BDW_ULT(dev))
 		return false;
 	if (IS_CHERRYVIEW(dev))
 		return false;
 	if (IS_VALLEYVIEW(dev) && !dev_priv->vbt.int_crt_support)
 		return false;
 	return true;
+}
 static void intel_setup_outputs(struct drm_device *dev)
+{
 	struct drm_i915_private *dev_priv = dev->dev_private;
 	struct intel_encoder *encoder;
 	bool dpd_is_edp = false;
 	intel_lvds_init(dev);
 	if (intel_crt_present(dev))
 		intel_crt_init(dev);
 	if (IS_BROXTON(dev)) {
 		/*
 		 * FIXME: Broxton doesn't support port detection via the
 		 * DDI_BUF_CTL_A or SFUSE_STRAP registers, find another way to
 		 * detect the ports.
 		 */
 		intel_ddi_init(dev, PORT_A);
 		intel_ddi_init(dev, PORT_B);
 		intel_ddi_init(dev, PORT_C);
 	} else if (HAS_DDI(dev)) {
 		int found;
 		/*
 		 * Haswell uses DDI functions to detect digital outputs.
 		 * On SKL pre-D0 the strap isn't connected, so we assume
 		 * it's there.
 		 */
 		found = I915_READ(DDI_BUF_CTL(PORT_A)) & DDI_INIT_DISPLAY_DETECTED;
 		/* WaIgnoreDDIAStrap: skl */
 		if (found || IS_SKYLAKE(dev))
 			intel_ddi_init(dev, PORT_A);
 		/* DDI B, C and D detection is indicated by the SFUSE_STRAP
 		 * register */
 		found = I915_READ(SFUSE_STRAP);
 		if (found & SFUSE_STRAP_DDIB_DETECTED)
 			intel_ddi_init(dev, PORT_B);
 		if (found & SFUSE_STRAP_DDIC_DETECTED)
 			intel_ddi_init(dev, PORT_C);
 		if (found & SFUSE_STRAP_DDID_DETECTED)
 			intel_ddi_init(dev, PORT_D);
 		/*
 		 * On SKL we don't have a way to detect DDI-E so we rely on VBT.
 		 */
 		if (IS_SKYLAKE(dev) &&
 		    (dev_priv->vbt.ddi_port_info[PORT_E].supports_dp ||
 		     dev_priv->vbt.ddi_port_info[PORT_E].supports_dvi ||
 		     dev_priv->vbt.ddi_port_info[PORT_E].supports_hdmi))
 			intel_ddi_init(dev, PORT_E);
 	} else if (HAS_PCH_SPLIT(dev)) {
 		int found;
 		dpd_is_edp = intel_dp_is_edp(dev, PORT_D);
 		if (has_edp_a(dev))
 			intel_dp_init(dev, DP_A, PORT_A);
 		if (I915_READ(PCH_HDMIB) & SDVO_DETECTED) {
 			/* PCH SDVOB multiplex with HDMIB */
 			found = intel_sdvo_init(dev, PCH_SDVOB, true);
 			if (!found)
 				intel_hdmi_init(dev, PCH_HDMIB, PORT_B);
 			if (!found && (I915_READ(PCH_DP_B) & DP_DETECTED))
 				intel_dp_init(dev, PCH_DP_B, PORT_B);
+		}
 		if (I915_READ(PCH_HDMIC) & SDVO_DETECTED)
 			intel_hdmi_init(dev, PCH_HDMIC, PORT_C);
 		if (!dpd_is_edp && I915_READ(PCH_HDMID) & SDVO_DETECTED)
 			intel_hdmi_init(dev, PCH_HDMID, PORT_D);
 		if (I915_READ(PCH_DP_C) & DP_DETECTED)
 			intel_dp_init(dev, PCH_DP_C, PORT_C);
 		if (I915_READ(PCH_DP_D) & DP_DETECTED)
 			intel_dp_init(dev, PCH_DP_D, PORT_D);
 	} else if (IS_VALLEYVIEW(dev)) {
 		bool has_edp, has_port;
 		/*
 		 * The DP_DETECTED bit is the latched state of the DDC
 		 * SDA pin at boot. However since eDP doesn't require DDC
 		 * (no way to plug in a DP->HDMI dongle) the DDC pins for
 		 * eDP ports may have been muxed to an alternate function.
 		 * Thus we can't rely on the DP_DETECTED bit alone to detect
 		 * eDP ports. Consult the VBT as well as DP_DETECTED to
 		 * detect eDP ports.
+		 *
 		 * Sadly the straps seem to be missing sometimes even for HDMI
 		 * ports (eg. on Voyo V3 - CHT x7-Z8700), so check both strap
 		 * and VBT for the presence of the port. Additionally we can't
 		 * trust the port type the VBT declares as we've seen at least
 		 * HDMI ports that the VBT claim are DP or eDP.
 		 */
 		has_edp = intel_dp_is_edp(dev, PORT_B);
 		has_port = intel_bios_is_port_present(dev_priv, PORT_B);
 		if (I915_READ(VLV_DP_B) & DP_DETECTED || has_port)
 			has_edp &= intel_dp_init(dev, VLV_DP_B, PORT_B);
 		if ((I915_READ(VLV_HDMIB) & SDVO_DETECTED || has_port) && !has_edp)
 			intel_hdmi_init(dev, VLV_HDMIB, PORT_B);
 		has_edp = intel_dp_is_edp(dev, PORT_C);
 		has_port = intel_bios_is_port_present(dev_priv, PORT_C);
 		if (I915_READ(VLV_DP_C) & DP_DETECTED || has_port)
 			has_edp &= intel_dp_init(dev, VLV_DP_C, PORT_C);
 		if ((I915_READ(VLV_HDMIC) & SDVO_DETECTED || has_port) && !has_edp)
 			intel_hdmi_init(dev, VLV_HDMIC, PORT_C);
 		if (IS_CHERRYVIEW(dev)) {
 			/*
 			 * eDP not supported on port D,
 			 * so no need to worry about it
 			 */
 			has_port = intel_bios_is_port_present(dev_priv, PORT_D);
 			if (I915_READ(CHV_DP_D) & DP_DETECTED || has_port)
 				intel_dp_init(dev, CHV_DP_D, PORT_D);
 			if (I915_READ(CHV_HDMID) & SDVO_DETECTED || has_port)
 				intel_hdmi_init(dev, CHV_HDMID, PORT_D);
+		}
 		intel_dsi_init(dev);
 	} else if (!IS_GEN2(dev) && !IS_PINEVIEW(dev)) {
 		bool found = false;
 		if (I915_READ(GEN3_SDVOB) & SDVO_DETECTED) {
 			DRM_DEBUG_KMS("probing SDVOB\n");
 			found = intel_sdvo_init(dev, GEN3_SDVOB, true);
 			if (!found && IS_G4X(dev)) {
 				DRM_DEBUG_KMS("probing HDMI on SDVOB\n");
 				intel_hdmi_init(dev, GEN4_HDMIB, PORT_B);
+			}
 			if (!found && IS_G4X(dev))
 				intel_dp_init(dev, DP_B, PORT_B);
+		}
 		/* Before G4X SDVOC doesn't have its own detect register */
 		if (I915_READ(GEN3_SDVOB) & SDVO_DETECTED) {
 			DRM_DEBUG_KMS("probing SDVOC\n");
 			found = intel_sdvo_init(dev, GEN3_SDVOC, false);
+		}
 		if (!found && (I915_READ(GEN3_SDVOC) & SDVO_DETECTED)) {
 			if (IS_G4X(dev)) {
 				DRM_DEBUG_KMS("probing HDMI on SDVOC\n");
 				intel_hdmi_init(dev, GEN4_HDMIC, PORT_C);
+			}
 			if (IS_G4X(dev))
 				intel_dp_init(dev, DP_C, PORT_C);
+		}
 		if (IS_G4X(dev) &&
 		    (I915_READ(DP_D) & DP_DETECTED))
 			intel_dp_init(dev, DP_D, PORT_D);
 	} else if (IS_GEN2(dev))
 		intel_dvo_init(dev);
 	if (SUPPORTS_TV(dev))
 		intel_tv_init(dev);
 	intel_psr_init(dev);
 	for_each_intel_encoder(dev, encoder) {
 		encoder->base.possible_crtcs = encoder->crtc_mask;
 		encoder->base.possible_clones =
 			intel_encoder_clones(encoder);
+	}
 	intel_init_pch_refclk(dev);
 	drm_helper_move_panel_connectors_to_head(dev);
+}
 static void intel_user_framebuffer_destroy(struct drm_framebuffer *fb)
+{
 	struct drm_device *dev = fb->dev;
 	struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
 	drm_framebuffer_cleanup(fb);
 	mutex_lock(&dev->struct_mutex);
 	WARN_ON(!intel_fb->obj->framebuffer_references--);
 	drm_gem_object_unreference(&intel_fb->obj->base);
 	mutex_unlock(&dev->struct_mutex);
 	kfree(intel_fb);
+}
 static int intel_user_framebuffer_create_handle(struct drm_framebuffer *fb,
 						struct drm_file *file,
 						unsigned int *handle)
+{
 	struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
 	struct drm_i915_gem_object *obj = intel_fb->obj;
 	if (obj->userptr.mm) {
 		DRM_DEBUG("attempting to use a userptr for a framebuffer, denied\n");
 		return -EINVAL;
+	}
 	return drm_gem_handle_create(file, &obj->base, handle);
+}
 static int intel_user_framebuffer_dirty(struct drm_framebuffer *fb,
 					struct drm_file *file,
 					unsigned flags, unsigned color,
 					struct drm_clip_rect *clips,
 					unsigned num_clips)
+{
 	struct drm_device *dev = fb->dev;
 	struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
 	struct drm_i915_gem_object *obj = intel_fb->obj;
 	mutex_lock(&dev->struct_mutex);
 	intel_fb_obj_flush(obj, false, ORIGIN_DIRTYFB);
 	mutex_unlock(&dev->struct_mutex);
 	return 0;
+}
 static const struct drm_framebuffer_funcs intel_fb_funcs = {
 	.destroy = intel_user_framebuffer_destroy,
 	.create_handle = intel_user_framebuffer_create_handle,
 	.dirty = intel_user_framebuffer_dirty,
 };
 static
 u32 intel_fb_pitch_limit(struct drm_device *dev, uint64_t fb_modifier,
 			 uint32_t pixel_format)
+{
 	u32 gen = INTEL_INFO(dev)->gen;
 	if (gen >= 9) {
 		/* "The stride in bytes must not exceed the of the size of 8K
 		 *  pixels and 32K bytes."
 		 */
 		 return min(8192*drm_format_plane_cpp(pixel_format, 0), 32768);
 	} else if (gen >= 5 && !IS_VALLEYVIEW(dev)) {
 		return 32*1024;
 	} else if (gen >= 4) {
 		if (fb_modifier == I915_FORMAT_MOD_X_TILED)
 			return 16*1024;
 		else
 			return 32*1024;
 	} else if (gen >= 3) {
 		if (fb_modifier == I915_FORMAT_MOD_X_TILED)
 			return 8*1024;
 		else
 			return 16*1024;
 	} else {
 		/* XXX DSPC is limited to 4k tiled */
 		return 8*1024;
+	}
+}
 static int intel_framebuffer_init(struct drm_device *dev,
 				  struct intel_framebuffer *intel_fb,
 				  struct drm_mode_fb_cmd2 *mode_cmd,
 				  struct drm_i915_gem_object *obj)
+{
 	unsigned int aligned_height;
 	int ret;
 	u32 pitch_limit, stride_alignment;
 	WARN_ON(!mutex_is_locked(&dev->struct_mutex));
 	if (mode_cmd->flags & DRM_MODE_FB_MODIFIERS) {
 		/* Enforce that fb modifier and tiling mode match, but only for
 		 * X-tiled. This is needed for FBC. */
 		if (!!(obj->tiling_mode == I915_TILING_X) !=
 		    !!(mode_cmd->modifier[0] == I915_FORMAT_MOD_X_TILED)) {
 			DRM_DEBUG("tiling_mode doesn't match fb modifier\n");
 			return -EINVAL;
+		}
 	} else {
 		if (obj->tiling_mode == I915_TILING_X)
 			mode_cmd->modifier[0] = I915_FORMAT_MOD_X_TILED;
 		else if (obj->tiling_mode == I915_TILING_Y) {
 			DRM_DEBUG("No Y tiling for legacy addfb\n");
 			return -EINVAL;
+		}
+	}
 	/* Passed in modifier sanity checking. */
 	switch (mode_cmd->modifier[0]) {
 	case I915_FORMAT_MOD_Y_TILED:
 	case I915_FORMAT_MOD_Yf_TILED:
 		if (INTEL_INFO(dev)->gen < 9) {
 			DRM_DEBUG("Unsupported tiling 0x%llx!\n",
 				  mode_cmd->modifier[0]);
 			return -EINVAL;
+		}
 	case DRM_FORMAT_MOD_NONE:
 	case I915_FORMAT_MOD_X_TILED:
 		break;
 	default:
 		DRM_DEBUG("Unsupported fb modifier 0x%llx!\n",
 			  mode_cmd->modifier[0]);
 		return -EINVAL;
+	}
 	stride_alignment = intel_fb_stride_alignment(dev, mode_cmd->modifier[0],
 						     mode_cmd->pixel_format);
 	if (mode_cmd->pitches[0] & (stride_alignment - 1)) {
 		DRM_DEBUG("pitch (%d) must be at least %u byte aligned\n",
 			  mode_cmd->pitches[0], stride_alignment);
 		return -EINVAL;
+	}
 	pitch_limit = intel_fb_pitch_limit(dev, mode_cmd->modifier[0],
 					   mode_cmd->pixel_format);
 	if (mode_cmd->pitches[0] > pitch_limit) {
 		DRM_DEBUG("%s pitch (%u) must be at less than %d\n",
 			  mode_cmd->modifier[0] != DRM_FORMAT_MOD_NONE ?
 			  "tiled" : "linear",
 			  mode_cmd->pitches[0], pitch_limit);
 		return -EINVAL;
+	}
 	if (mode_cmd->modifier[0] == I915_FORMAT_MOD_X_TILED &&
 	    mode_cmd->pitches[0] != obj->stride) {
 		DRM_DEBUG("pitch (%d) must match tiling stride (%d)\n",
 			  mode_cmd->pitches[0], obj->stride);
 		return -EINVAL;
+	}
 	/* Reject formats not supported by any plane early. */
 	switch (mode_cmd->pixel_format) {
 	case DRM_FORMAT_C8:
 	case DRM_FORMAT_RGB565:
 	case DRM_FORMAT_XRGB8888:
 	case DRM_FORMAT_ARGB8888:
 		break;
 	case DRM_FORMAT_XRGB1555:
 		if (INTEL_INFO(dev)->gen > 3) {
 			DRM_DEBUG("unsupported pixel format: %s\n",
 				  drm_get_format_name(mode_cmd->pixel_format));
 			return -EINVAL;
+		}
 		break;
 	case DRM_FORMAT_ABGR8888:
 		if (!IS_VALLEYVIEW(dev) && INTEL_INFO(dev)->gen < 9) {
 			DRM_DEBUG("unsupported pixel format: %s\n",
 				  drm_get_format_name(mode_cmd->pixel_format));
 			return -EINVAL;
+		}
 		break;
 	case DRM_FORMAT_XBGR8888:
 	case DRM_FORMAT_XRGB2101010:
 	case DRM_FORMAT_XBGR2101010:
 		if (INTEL_INFO(dev)->gen < 4) {
 			DRM_DEBUG("unsupported pixel format: %s\n",
 				  drm_get_format_name(mode_cmd->pixel_format));
 			return -EINVAL;
+		}
 		break;
 	case DRM_FORMAT_ABGR2101010:
 		if (!IS_VALLEYVIEW(dev)) {
 			DRM_DEBUG("unsupported pixel format: %s\n",
 				  drm_get_format_name(mode_cmd->pixel_format));
 			return -EINVAL;
+		}
 		break;
 	case DRM_FORMAT_YUYV:
 	case DRM_FORMAT_UYVY:
 	case DRM_FORMAT_YVYU:
 	case DRM_FORMAT_VYUY:
 		if (INTEL_INFO(dev)->gen < 5) {
 			DRM_DEBUG("unsupported pixel format: %s\n",
 				  drm_get_format_name(mode_cmd->pixel_format));
 			return -EINVAL;
+		}
 		break;
 	default:
 		DRM_DEBUG("unsupported pixel format: %s\n",
 			  drm_get_format_name(mode_cmd->pixel_format));
 		return -EINVAL;
+	}
 	/* FIXME need to adjust LINOFF/TILEOFF accordingly. */
 	if (mode_cmd->offsets[0] != 0)
 		return -EINVAL;
 	aligned_height = intel_fb_align_height(dev, mode_cmd->height,
 					       mode_cmd->pixel_format,
 					       mode_cmd->modifier[0]);
 	/* FIXME drm helper for size checks (especially planar formats)? */
 	if (obj->base.size < aligned_height * mode_cmd->pitches[0])
 		return -EINVAL;
 	drm_helper_mode_fill_fb_struct(&intel_fb->base, mode_cmd);
 	intel_fb->obj = obj;
 	intel_fb->obj->framebuffer_references++;
 	ret = drm_framebuffer_init(dev, &intel_fb->base, &intel_fb_funcs);
 	if (ret) {
 		DRM_ERROR("framebuffer init failed %d\n", ret);
 		return ret;
+	}
 	return 0;
+}
 static struct drm_framebuffer *
 intel_user_framebuffer_create(struct drm_device *dev,
 			      struct drm_file *filp,
 			      struct drm_mode_fb_cmd2 *user_mode_cmd)
+{
 	struct drm_gem_object *gobj;
 	struct drm_i915_gem_object *obj;
 	struct drm_mode_fb_cmd2 mode_cmd = *user_mode_cmd;
 	gobj = drm_gem_object_lookup(dev, filp, mode_cmd.handles[0]);
 	if (gobj == NULL)
 		return ERR_PTR(-ENOENT);
 	obj = to_intel_bo(gobj);
 	return intel_framebuffer_create(dev, &mode_cmd, obj);
+}
 #ifndef CONFIG_DRM_FBDEV_EMULATION
 static inline void intel_fbdev_output_poll_changed(struct drm_device *dev)
+{
+}
 #endif
 static const struct drm_mode_config_funcs intel_mode_funcs = {
 	.fb_create = intel_user_framebuffer_create,
 	.output_poll_changed = intel_fbdev_output_poll_changed,
 	.atomic_check = intel_atomic_check,
 	.atomic_commit = intel_atomic_commit,
 	.atomic_state_alloc = intel_atomic_state_alloc,
 	.atomic_state_clear = intel_atomic_state_clear,
 };
 /* Set up chip specific display functions */
 static void intel_init_display(struct drm_device *dev)
+{
 	struct drm_i915_private *dev_priv = dev->dev_private;
 	if (HAS_PCH_SPLIT(dev) || IS_G4X(dev))
 		dev_priv->display.find_dpll = g4x_find_best_dpll;
 	else if (IS_CHERRYVIEW(dev))
 		dev_priv->display.find_dpll = chv_find_best_dpll;
 	else if (IS_VALLEYVIEW(dev))
 		dev_priv->display.find_dpll = vlv_find_best_dpll;
 	else if (IS_PINEVIEW(dev))
 		dev_priv->display.find_dpll = pnv_find_best_dpll;
 	else
 		dev_priv->display.find_dpll = i9xx_find_best_dpll;
 	if (INTEL_INFO(dev)->gen >= 9) {
 		dev_priv->display.get_pipe_config = haswell_get_pipe_config;
 		dev_priv->display.get_initial_plane_config =
 			skylake_get_initial_plane_config;
 		dev_priv->display.crtc_compute_clock =
 			haswell_crtc_compute_clock;
 		dev_priv->display.crtc_enable = haswell_crtc_enable;
 		dev_priv->display.crtc_disable = haswell_crtc_disable;
 		dev_priv->display.update_primary_plane =
 			skylake_update_primary_plane;
 	} else if (HAS_DDI(dev)) {
 		dev_priv->display.get_pipe_config = haswell_get_pipe_config;
 		dev_priv->display.get_initial_plane_config =
 			ironlake_get_initial_plane_config;
 		dev_priv->display.crtc_compute_clock =
 			haswell_crtc_compute_clock;
 		dev_priv->display.crtc_enable = haswell_crtc_enable;
 		dev_priv->display.crtc_disable = haswell_crtc_disable;
 		dev_priv->display.update_primary_plane =
 			ironlake_update_primary_plane;
 	} else if (HAS_PCH_SPLIT(dev)) {
 		dev_priv->display.get_pipe_config = ironlake_get_pipe_config;
 		dev_priv->display.get_initial_plane_config =
 			ironlake_get_initial_plane_config;
 		dev_priv->display.crtc_compute_clock =
 			ironlake_crtc_compute_clock;
 		dev_priv->display.crtc_enable = ironlake_crtc_enable;
 		dev_priv->display.crtc_disable = ironlake_crtc_disable;
 		dev_priv->display.update_primary_plane =
 			ironlake_update_primary_plane;
 	} else if (IS_VALLEYVIEW(dev)) {
 		dev_priv->display.get_pipe_config = i9xx_get_pipe_config;
 		dev_priv->display.get_initial_plane_config =
 			i9xx_get_initial_plane_config;
 		dev_priv->display.crtc_compute_clock = i9xx_crtc_compute_clock;
 		dev_priv->display.crtc_enable = valleyview_crtc_enable;
 		dev_priv->display.crtc_disable = i9xx_crtc_disable;
 		dev_priv->display.update_primary_plane =
 			i9xx_update_primary_plane;
 	} else {
 		dev_priv->display.get_pipe_config = i9xx_get_pipe_config;
 		dev_priv->display.get_initial_plane_config =
 			i9xx_get_initial_plane_config;
 		dev_priv->display.crtc_compute_clock = i9xx_crtc_compute_clock;
 		dev_priv->display.crtc_enable = i9xx_crtc_enable;
 		dev_priv->display.crtc_disable = i9xx_crtc_disable;
 		dev_priv->display.update_primary_plane =
 			i9xx_update_primary_plane;
+	}
 	/* Returns the core display clock speed */
 	if (IS_SKYLAKE(dev))
 		dev_priv->display.get_display_clock_speed =
 			skylake_get_display_clock_speed;
 	else if (IS_BROXTON(dev))
 		dev_priv->display.get_display_clock_speed =
 			broxton_get_display_clock_speed;
 	else if (IS_BROADWELL(dev))
 		dev_priv->display.get_display_clock_speed =
 			broadwell_get_display_clock_speed;
 	else if (IS_HASWELL(dev))
 		dev_priv->display.get_display_clock_speed =
 			haswell_get_display_clock_speed;
 	else if (IS_VALLEYVIEW(dev))
 		dev_priv->display.get_display_clock_speed =
 			valleyview_get_display_clock_speed;
 	else if (IS_GEN5(dev))
 		dev_priv->display.get_display_clock_speed =
 			ilk_get_display_clock_speed;
 	else if (IS_I945G(dev) || IS_BROADWATER(dev) ||
 		 IS_GEN6(dev) || IS_IVYBRIDGE(dev))
 		dev_priv->display.get_display_clock_speed =
 			i945_get_display_clock_speed;
 	else if (IS_GM45(dev))
 		dev_priv->display.get_display_clock_speed =
 			gm45_get_display_clock_speed;
 	else if (IS_CRESTLINE(dev))
 		dev_priv->display.get_display_clock_speed =
 			i965gm_get_display_clock_speed;
 	else if (IS_PINEVIEW(dev))
 		dev_priv->display.get_display_clock_speed =
 			pnv_get_display_clock_speed;
 	else if (IS_G33(dev) || IS_G4X(dev))
 		dev_priv->display.get_display_clock_speed =
 			g33_get_display_clock_speed;
 	else if (IS_I915G(dev))
 		dev_priv->display.get_display_clock_speed =
 			i915_get_display_clock_speed;
 	else if (IS_I945GM(dev) || IS_845G(dev))
 		dev_priv->display.get_display_clock_speed =
 			i9xx_misc_get_display_clock_speed;
 	else if (IS_PINEVIEW(dev))
 		dev_priv->display.get_display_clock_speed =
 			pnv_get_display_clock_speed;
 	else if (IS_I915GM(dev))
 		dev_priv->display.get_display_clock_speed =
 			i915gm_get_display_clock_speed;
 	else if (IS_I865G(dev))
 		dev_priv->display.get_display_clock_speed =
 			i865_get_display_clock_speed;
 	else if (IS_I85X(dev))
 		dev_priv->display.get_display_clock_speed =
 			i85x_get_display_clock_speed;
 	else { /* 830 */
 		WARN(!IS_I830(dev), "Unknown platform. Assuming 133 MHz CDCLK\n");
 		dev_priv->display.get_display_clock_speed =
 			i830_get_display_clock_speed;
+	}
 	if (IS_GEN5(dev)) {
 		dev_priv->display.fdi_link_train = ironlake_fdi_link_train;
 	} else if (IS_GEN6(dev)) {
 		dev_priv->display.fdi_link_train = gen6_fdi_link_train;
 	} else if (IS_IVYBRIDGE(dev)) {
 		/* FIXME: detect B0+ stepping and use auto training */
 		dev_priv->display.fdi_link_train = ivb_manual_fdi_link_train;
 	} else if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
 		dev_priv->display.fdi_link_train = hsw_fdi_link_train;
 		if (IS_BROADWELL(dev)) {
 			dev_priv->display.modeset_commit_cdclk =
 				broadwell_modeset_commit_cdclk;
 			dev_priv->display.modeset_calc_cdclk =
 				broadwell_modeset_calc_cdclk;
+		}
 	} else if (IS_VALLEYVIEW(dev)) {
 		dev_priv->display.modeset_commit_cdclk =
 			valleyview_modeset_commit_cdclk;
 		dev_priv->display.modeset_calc_cdclk =
 			valleyview_modeset_calc_cdclk;
 	} else if (IS_BROXTON(dev)) {
 		dev_priv->display.modeset_commit_cdclk =
 			broxton_modeset_commit_cdclk;
 		dev_priv->display.modeset_calc_cdclk =
 			broxton_modeset_calc_cdclk;
+	}
 	switch (INTEL_INFO(dev)->gen) {
 	case 2:
 		dev_priv->display.queue_flip = intel_gen2_queue_flip;
 		break;
 	case 3:
 		dev_priv->display.queue_flip = intel_gen3_queue_flip;
 		break;
 	case 4:
 	case 5:
 		dev_priv->display.queue_flip = intel_gen4_queue_flip;
 		break;
 	case 6:
 		dev_priv->display.queue_flip = intel_gen6_queue_flip;
 		break;
 	case 7:
 	case 8: /* FIXME(BDW): Check that the gen8 RCS flip works. */
 		dev_priv->display.queue_flip = intel_gen7_queue_flip;
 		break;
 	case 9:
 		/* Drop through - unsupported since execlist only. */
 	default:
 		/* Default just returns -ENODEV to indicate unsupported */
 		dev_priv->display.queue_flip = intel_default_queue_flip;
+	}
 #ifdef __NetBSD__
 	linux_mutex_init(&dev_priv->pps_mutex);
 #else
 	mutex_init(&dev_priv->pps_mutex);
 #endif
+}
 /*
  * Some BIOSes insist on assuming the GPU's pipe A is enabled at suspend,
  * resume, or other times.  This quirk makes sure that's the case for
  * affected systems.
  */
 static void quirk_pipea_force(struct drm_device *dev)
+{
 	struct drm_i915_private *dev_priv = dev->dev_private;
 	dev_priv->quirks |= QUIRK_PIPEA_FORCE;
 	DRM_INFO("applying pipe a force quirk\n");
+}
 static void quirk_pipeb_force(struct drm_device *dev)
+{
 	struct drm_i915_private *dev_priv = dev->dev_private;
 	dev_priv->quirks |= QUIRK_PIPEB_FORCE;
 	DRM_INFO("applying pipe b force quirk\n");
+}
 /*
  * Some machines (Lenovo U160) do not work with SSC on LVDS for some reason
  */
 static void quirk_ssc_force_disable(struct drm_device *dev)
+{
 	struct drm_i915_private *dev_priv = dev->dev_private;
 	dev_priv->quirks |= QUIRK_LVDS_SSC_DISABLE;
 	DRM_INFO("applying lvds SSC disable quirk\n");
+}
 /*
  * A machine (e.g. Acer Aspire 5734Z) may need to invert the panel backlight
  * brightness value
  */
 static void quirk_invert_brightness(struct drm_device *dev)
+{
 	struct drm_i915_private *dev_priv = dev->dev_private;
 	dev_priv->quirks |= QUIRK_INVERT_BRIGHTNESS;
 	DRM_INFO("applying inverted panel brightness quirk\n");
+}
 /* Some VBT's incorrectly indicate no backlight is present */
 static void quirk_backlight_present(struct drm_device *dev)
+{
 	struct drm_i915_private *dev_priv = dev->dev_private;
 	dev_priv->quirks |= QUIRK_BACKLIGHT_PRESENT;
 	DRM_INFO("applying backlight present quirk\n");
+}
 struct intel_quirk {
 	int device;
 	int subsystem_vendor;
 	int subsystem_device;
 	void (*hook)(struct drm_device *dev);
 };
 /* For systems that don't have a meaningful PCI subdevice/subvendor ID */
 struct intel_dmi_quirk {
 	void (*hook)(struct drm_device *dev);
 	const struct dmi_system_id (*dmi_id_list)[];
 };
 static int intel_dmi_reverse_brightness(const struct dmi_system_id *id)
+{
 	DRM_INFO("Backlight polarity reversed on %s\n", id->ident);
 	return 1;
+}
 static const struct intel_dmi_quirk intel_dmi_quirks[] = {
+	{
 		.dmi_id_list = &(const struct dmi_system_id[]) {
+			{
 				.callback = intel_dmi_reverse_brightness,
 				.ident = "NCR Corporation",
 				.matches = {DMI_MATCH(DMI_SYS_VENDOR, "NCR Corporation"),
 					    DMI_MATCH(DMI_PRODUCT_NAME, ""),
 				},
 			},
 			{ .callback = NULL }  /* terminating entry */
 		},
 		.hook = quirk_invert_brightness,
 	},
 };
 static struct intel_quirk intel_quirks[] = {
 	/* Toshiba Protege R-205, S-209 needs pipe A force quirk */
 	{ 0x2592, 0x1179, 0x0001, quirk_pipea_force },
 	/* ThinkPad T60 needs pipe A force quirk (bug #16494) */
 	{ 0x2782, 0x17aa, 0x201a, quirk_pipea_force },
 	/* 830 needs to leave pipe A & dpll A up */
 	{ 0x3577, PCI_ANY_ID, PCI_ANY_ID, quirk_pipea_force },
 	/* 830 needs to leave pipe B & dpll B up */
 	{ 0x3577, PCI_ANY_ID, PCI_ANY_ID, quirk_pipeb_force },
 	/* Lenovo U160 cannot use SSC on LVDS */
 	{ 0x0046, 0x17aa, 0x3920, quirk_ssc_force_disable },
 	/* Sony Vaio Y cannot use SSC on LVDS */
 	{ 0x0046, 0x104d, 0x9076, quirk_ssc_force_disable },
 	/* Acer Aspire 5734Z must invert backlight brightness */
 	{ 0x2a42, 0x1025, 0x0459, quirk_invert_brightness },
 	/* Acer/eMachines G725 */
 	{ 0x2a42, 0x1025, 0x0210, quirk_invert_brightness },
 	/* Acer/eMachines e725 */
 	{ 0x2a42, 0x1025, 0x0212, quirk_invert_brightness },
 	/* Acer/Packard Bell NCL20 */
 	{ 0x2a42, 0x1025, 0x034b, quirk_invert_brightness },
 	/* Acer Aspire 4736Z */
 	{ 0x2a42, 0x1025, 0x0260, quirk_invert_brightness },
 	/* Acer Aspire 5336 */
 	{ 0x2a42, 0x1025, 0x048a, quirk_invert_brightness },
 	/* Acer C720 and C720P Chromebooks (Celeron 2955U) have backlights */
 	{ 0x0a06, 0x1025, 0x0a11, quirk_backlight_present },
 	/* Acer C720 Chromebook (Core i3 4005U) */
 	{ 0x0a16, 0x1025, 0x0a11, quirk_backlight_present },
 	/* Apple Macbook 2,1 (Core 2 T7400) */
 	{ 0x27a2, 0x8086, 0x7270, quirk_backlight_present },
 	/* Apple Macbook 4,1 */
 	{ 0x2a02, 0x106b, 0x00a1, quirk_backlight_present },
 	/* Toshiba CB35 Chromebook (Celeron 2955U) */
 	{ 0x0a06, 0x1179, 0x0a88, quirk_backlight_present },
 	/* HP Chromebook 14 (Celeron 2955U) */
 	{ 0x0a06, 0x103c, 0x21ed, quirk_backlight_present },
 	/* Dell Chromebook 11 */
 	{ 0x0a06, 0x1028, 0x0a35, quirk_backlight_present },
 	/* Dell Chromebook 11 (2015 version) */
 	{ 0x0a16, 0x1028, 0x0a35, quirk_backlight_present },
 };
 static void intel_init_quirks(struct drm_device *dev)
+{
 	struct pci_dev *d = dev->pdev;
 	int i;
 	for (i = 0; i < ARRAY_SIZE(intel_quirks); i++) {
 		struct intel_quirk *q = &intel_quirks[i];
 		if (d->device == q->device &&
 		    (d->subsystem_vendor == q->subsystem_vendor ||
 		     q->subsystem_vendor == PCI_ANY_ID) &&
 		    (d->subsystem_device == q->subsystem_device ||
 		     q->subsystem_device == PCI_ANY_ID))
 			q->hook(dev);
+	}
 	for (i = 0; i < ARRAY_SIZE(intel_dmi_quirks); i++) {
 		if (dmi_check_system(*intel_dmi_quirks[i].dmi_id_list) != 0)
 			intel_dmi_quirks[i].hook(dev);
+	}
+}
 /* Disable the VGA plane that we never use */
 void i915_disable_vga(struct drm_device *dev)
+{
 	struct drm_i915_private *dev_priv = dev->dev_private;
 	u8 sr1;
 	u32 vga_reg = i915_vgacntrl_reg(dev);
 #ifdef __NetBSD__
+    {
 	const bus_addr_t vgabase = 0x3c0;
 	const bus_space_tag_t iot = dev->pdev->pd_pa.pa_iot;
 	bus_space_handle_t ioh;
 	int error;
 	error = bus_space_map(iot, vgabase, 0x10, 0, &ioh);
 	if (error) {
 		aprint_error_dev(dev->pdev->pd_dev,
 		    "unable to map VGA registers: %d\n", error);
 	} else {
 		CTASSERT(vgabase <= VGA_SR_INDEX);
 		CTASSERT(vgabase <= VGA_SR_DATA);
 		bus_space_write_1(iot, ioh, VGA_SR_INDEX - vgabase, SR01);
 		sr1 = bus_space_read_1(iot, ioh, VGA_SR_DATA - vgabase);
 		bus_space_write_1(iot, ioh, VGA_SR_DATA - vgabase,
 		    (sr1 | __BIT(5)));
 		bus_space_unmap(iot, ioh, 0x10);
+	}
+    }
 #else
 	/* WaEnableVGAAccessThroughIOPort:ctg,elk,ilk,snb,ivb,vlv,hsw */
 	vga_get_uninterruptible(dev->pdev, VGA_RSRC_LEGACY_IO);
 	outb(SR01, VGA_SR_INDEX);
 	sr1 = inb(VGA_SR_DATA);
 	outb(sr1 | 1<<5, VGA_SR_DATA);
 	vga_put(dev->pdev, VGA_RSRC_LEGACY_IO);
 #endif
 	udelay(300);
 #endif
 	I915_WRITE(vga_reg, VGA_DISP_DISABLE);
 	POSTING_READ(vga_reg);
+}
 void intel_modeset_init_hw(struct drm_device *dev)
+{
 	intel_update_cdclk(dev);
 	intel_prepare_ddi(dev);
 	intel_init_clock_gating(dev);
 	intel_enable_gt_powersave(dev);
+}
 void intel_modeset_init(struct drm_device *dev)
+{
 	struct drm_i915_private *dev_priv = dev->dev_private;
 	int sprite, ret;
 	enum i915_pipe pipe;
 	struct intel_crtc *crtc;
 	drm_mode_config_init(dev);
 	dev->mode_config.min_width = 0;
 	dev->mode_config.min_height = 0;
 	dev->mode_config.preferred_depth = 24;
 	dev->mode_config.prefer_shadow = 1;
 	dev->mode_config.allow_fb_modifiers = true;
 	dev->mode_config.funcs = &intel_mode_funcs;
 	intel_init_quirks(dev);
 	intel_init_pm(dev);
 	if (INTEL_INFO(dev)->num_pipes == 0)
 		return;
 	/*
 	 * There may be no VBT; and if the BIOS enabled SSC we can
 	 * just keep using it to avoid unnecessary flicker.  Whereas if the
 	 * BIOS isn't using it, don't assume it will work even if the VBT
 	 * indicates as much.
 	 */
 	if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev)) {
 		bool bios_lvds_use_ssc = !!(I915_READ(PCH_DREF_CONTROL) &
 					    DREF_SSC1_ENABLE);
 		if (dev_priv->vbt.lvds_use_ssc != bios_lvds_use_ssc) {
 			DRM_DEBUG_KMS("SSC %sabled by BIOS, overriding VBT which says %sabled\n",
 				     bios_lvds_use_ssc ? "en" : "dis",
 				     dev_priv->vbt.lvds_use_ssc ? "en" : "dis");
 			dev_priv->vbt.lvds_use_ssc = bios_lvds_use_ssc;
+		}
+	}
 	intel_init_display(dev);
 	intel_init_audio(dev);
 	if (IS_GEN2(dev)) {
 		dev->mode_config.max_width = 2048;
 		dev->mode_config.max_height = 2048;
 	} else if (IS_GEN3(dev)) {
 		dev->mode_config.max_width = 4096;
 		dev->mode_config.max_height = 4096;
 	} else {
 		dev->mode_config.max_width = 8192;
 		dev->mode_config.max_height = 8192;
+	}
 	if (IS_845G(dev) || IS_I865G(dev)) {
 		dev->mode_config.cursor_width = IS_845G(dev) ? 64 : 512;
 		dev->mode_config.cursor_height = 1023;
 	} else if (IS_GEN2(dev)) {
 		dev->mode_config.cursor_width = GEN2_CURSOR_WIDTH;
 		dev->mode_config.cursor_height = GEN2_CURSOR_HEIGHT;
 	} else {
 		dev->mode_config.cursor_width = MAX_CURSOR_WIDTH;
 		dev->mode_config.cursor_height = MAX_CURSOR_HEIGHT;
+	}
 	dev->mode_config.fb_base = dev_priv->gtt.mappable_base;
 	DRM_DEBUG_KMS("%d display pipe%s available.\n",
 		      INTEL_INFO(dev)->num_pipes,
 		      INTEL_INFO(dev)->num_pipes > 1 ? "s" : "");
 	for_each_pipe(dev_priv, pipe) {
 		intel_crtc_init(dev, pipe);
 		for_each_sprite(dev_priv, pipe, sprite) {
 			ret = intel_plane_init(dev, pipe, sprite);
 			if (ret)
 				DRM_DEBUG_KMS("pipe %c sprite %c init failed: %d\n",
 					      pipe_name(pipe), sprite_name(pipe, sprite), ret);
+		}
+	}
 	intel_update_czclk(dev_priv);
 	intel_update_cdclk(dev);
 	intel_shared_dpll_init(dev);
 #ifndef __NetBSD__		/* XXX We wait until intelfb is ready.  */
 	/* Just disable it once at startup */
 	i915_disable_vga(dev);
 #endif
 	intel_setup_outputs(dev);
 	/* Just in case the BIOS is doing something questionable. */
 	intel_fbc_disable(dev_priv);
 	drm_modeset_lock_all(dev);
 	intel_modeset_setup_hw_state(dev);
 	drm_modeset_unlock_all(dev);
 	for_each_intel_crtc(dev, crtc) {
 		struct intel_initial_plane_config plane_config = {};
 		if (!crtc->active)
 			continue;
 		/*
 		 * Note that reserving the BIOS fb up front prevents us
 		 * from stuffing other stolen allocations like the ring
 		 * on top.  This prevents some ugliness at boot time, and
 		 * can even allow for smooth boot transitions if the BIOS
 		 * fb is large enough for the active pipe configuration.
 		 */
 		dev_priv->display.get_initial_plane_config(crtc,
 							   &plane_config);
 		/*
 		 * If the fb is shared between multiple heads, we'll
 		 * just get the first one.
 		 */
 		intel_find_initial_plane_obj(crtc, &plane_config);
+	}
+}
 static void intel_enable_pipe_a(struct drm_device *dev)
+{
 	struct intel_connector *connector;
 	struct drm_connector *crt = NULL;
 	struct intel_load_detect_pipe load_detect_temp;
 	struct drm_modeset_acquire_ctx *ctx = dev->mode_config.acquire_ctx;
 	/* We can't just switch on the pipe A, we need to set things up with a
 	 * proper mode and output configuration. As a gross hack, enable pipe A
 	 * by enabling the load detect pipe once. */
 	for_each_intel_connector(dev, connector) {
 		if (connector->encoder->type == INTEL_OUTPUT_ANALOG) {
 			crt = &connector->base;
 			break;
+		}
+	}
 	if (!crt)
 		return;
 	if (intel_get_load_detect_pipe(crt, NULL, &load_detect_temp, ctx))
 		intel_release_load_detect_pipe(crt, &load_detect_temp, ctx);
+}
 static bool
 intel_check_plane_mapping(struct intel_crtc *crtc)
+{
 	struct drm_device *dev = crtc->base.dev;
 	struct drm_i915_private *dev_priv = dev->dev_private;
 	u32 val;
 	if (INTEL_INFO(dev)->num_pipes == 1)
 		return true;
 	val = I915_READ(DSPCNTR(!crtc->plane));
 	if ((val & DISPLAY_PLANE_ENABLE) &&
 	    (!!(val & DISPPLANE_SEL_PIPE_MASK) == crtc->pipe))
 		return false;
 	return true;
+}
 static bool intel_crtc_has_encoders(struct intel_crtc *crtc)
+{
 	struct drm_device *dev = crtc->base.dev;
 	struct intel_encoder *encoder;
 	for_each_encoder_on_crtc(dev, &crtc->base, encoder)
 		return true;
 	return false;
+}
 static void intel_sanitize_crtc(struct intel_crtc *crtc)
+{
 	struct drm_device *dev = crtc->base.dev;
 	struct drm_i915_private *dev_priv = dev->dev_private;
 	u32 reg;
 	/* Clear any frame start delays used for debugging left by the BIOS */
 	reg = PIPECONF(crtc->config->cpu_transcoder);
 	I915_WRITE(reg, I915_READ(reg) & ~PIPECONF_FRAME_START_DELAY_MASK);
 	/* restore vblank interrupts to correct state */
 	drm_crtc_vblank_reset(&crtc->base);
 	if (crtc->active) {
 		struct intel_plane *plane;
 		drm_crtc_vblank_on(&crtc->base);
 		/* Disable everything but the primary plane */
 		for_each_intel_plane_on_crtc(dev, crtc, plane) {
 			if (plane->base.type == DRM_PLANE_TYPE_PRIMARY)
 				continue;
 			plane->disable_plane(&plane->base, &crtc->base);
+		}
+	}
 	/* We need to sanitize the plane -> pipe mapping first because this will
 	 * disable the crtc (and hence change the state) if it is wrong. Note
 	 * that gen4+ has a fixed plane -> pipe mapping.  */
 	if (INTEL_INFO(dev)->gen < 4 && !intel_check_plane_mapping(crtc)) {
 		bool plane;
 		DRM_DEBUG_KMS("[CRTC:%d] wrong plane connection detected!\n",
 			      crtc->base.base.id);
 		/* Pipe has the wrong plane attached and the plane is active.
 		 * Temporarily change the plane mapping and disable everything
 		 * ...  */
 		plane = crtc->plane;
 		to_intel_plane_state(crtc->base.primary->state)->visible = true;
 		crtc->plane = !plane;
 		intel_crtc_disable_noatomic(&crtc->base);
 		crtc->plane = plane;
+	}
 	if (dev_priv->quirks & QUIRK_PIPEA_FORCE &&
 	    crtc->pipe == PIPE_A && !crtc->active) {
 		/* BIOS forgot to enable pipe A, this mostly happens after
 		 * resume. Force-enable the pipe to fix this, the update_dpms
 		 * call below we restore the pipe to the right state, but leave
 		 * the required bits on. */
 		intel_enable_pipe_a(dev);
+	}
 	/* Adjust the state of the output pipe according to whether we
 	 * have active connectors/encoders. */
 	if (!intel_crtc_has_encoders(crtc))
 		intel_crtc_disable_noatomic(&crtc->base);
 	if (crtc->active != crtc->base.state->active) {
 		struct intel_encoder *encoder;
 		/* This can happen either due to bugs in the get_hw_state
 		 * functions or because of calls to intel_crtc_disable_noatomic,
 		 * or because the pipe is force-enabled due to the
 		 * pipe A quirk. */
 		DRM_DEBUG_KMS("[CRTC:%d] hw state adjusted, was %s, now %s\n",
 			      crtc->base.base.id,
 			      crtc->base.state->enable ? "enabled" : "disabled",
 			      crtc->active ? "enabled" : "disabled");
 		WARN_ON(drm_atomic_set_mode_for_crtc(crtc->base.state, NULL) < 0);
 		crtc->base.state->active = crtc->active;
 		crtc->base.enabled = crtc->active;
 		/* Because we only establish the connector -> encoder ->
 		 * crtc links if something is active, this means the
 		 * crtc is now deactivated. Break the links. connector
 		 * -> encoder links are only establish when things are
 		 *  actually up, hence no need to break them. */
 		WARN_ON(crtc->active);
 		for_each_encoder_on_crtc(dev, &crtc->base, encoder)
 			encoder->base.crtc = NULL;
+	}
 	if (crtc->active || HAS_GMCH_DISPLAY(dev)) {
 		/*
 		 * We start out with underrun reporting disabled to avoid races.
 		 * For correct bookkeeping mark this on active crtcs.
+		 *
 		 * Also on gmch platforms we dont have any hardware bits to
 		 * disable the underrun reporting. Which means we need to start
 		 * out with underrun reporting disabled also on inactive pipes,
 		 * since otherwise we'll complain about the garbage we read when
 		 * e.g. coming up after runtime pm.
+		 *
 		 * No protection against concurrent access is required - at
 		 * worst a fifo underrun happens which also sets this to false.
 		 */
 		crtc->cpu_fifo_underrun_disabled = true;
 		crtc->pch_fifo_underrun_disabled = true;
+	}
+}
 static void intel_sanitize_encoder(struct intel_encoder *encoder)
+{
 	struct intel_connector *connector;
 	struct drm_device *dev = encoder->base.dev;
 	bool active = false;
 	/* We need to check both for a crtc link (meaning that the
 	 * encoder is active and trying to read from a pipe) and the
 	 * pipe itself being active. */
 	bool has_active_crtc = encoder->base.crtc &&
 		to_intel_crtc(encoder->base.crtc)->active;
 	for_each_intel_connector(dev, connector) {
 		if (connector->base.encoder != &encoder->base)
 			continue;
 		active = true;
 		break;
+	}
 	if (active && !has_active_crtc) {
 		DRM_DEBUG_KMS("[ENCODER:%d:%s] has active connectors but no active pipe!\n",
 			      encoder->base.base.id,
 			      encoder->base.name);
 		/* Connector is active, but has no active pipe. This is
 		 * fallout from our resume register restoring. Disable
 		 * the encoder manually again. */
 		if (encoder->base.crtc) {
 			DRM_DEBUG_KMS("[ENCODER:%d:%s] manually disabled\n",
 				      encoder->base.base.id,
 				      encoder->base.name);
 			encoder->disable(encoder);
 			if (encoder->post_disable)
 				encoder->post_disable(encoder);
+		}
 		encoder->base.crtc = NULL;
 		/* Inconsistent output/port/pipe state happens presumably due to
 		 * a bug in one of the get_hw_state functions. Or someplace else
 		 * in our code, like the register restore mess on resume. Clamp
 		 * things to off as a safer default. */
 		for_each_intel_connector(dev, connector) {
 			if (connector->encoder != encoder)
 				continue;
 			connector->base.dpms = DRM_MODE_DPMS_OFF;
 			connector->base.encoder = NULL;
+		}
+	}
 	/* Enabled encoders without active connectors will be fixed in
 	 * the crtc fixup. */
+}
 void i915_redisable_vga_power_on(struct drm_device *dev)
+{
 	struct drm_i915_private *dev_priv = dev->dev_private;
 	u32 vga_reg = i915_vgacntrl_reg(dev);
 	if (!(I915_READ(vga_reg) & VGA_DISP_DISABLE)) {
 		DRM_DEBUG_KMS("Something enabled VGA plane, disabling it\n");
 		i915_disable_vga(dev);
+	}
+}
 void i915_redisable_vga(struct drm_device *dev)
+{
 	struct drm_i915_private *dev_priv = dev->dev_private;
 	/* This function can be called both from intel_modeset_setup_hw_state or
 	 * at a very early point in our resume sequence, where the power well
 	 * structures are not yet restored. Since this function is at a very
 	 * paranoid "someone might have enabled VGA while we were not looking"
 	 * level, just check if the power well is enabled instead of trying to
 	 * follow the "don't touch the power well if we don't need it" policy
 	 * the rest of the driver uses. */
 	if (!intel_display_power_is_enabled(dev_priv, POWER_DOMAIN_VGA))
 		return;
 	i915_redisable_vga_power_on(dev);
+}
 static bool primary_get_hw_state(struct intel_plane *plane)
+{
 	struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
 	return I915_READ(DSPCNTR(plane->plane)) & DISPLAY_PLANE_ENABLE;
+}
 /* FIXME read out full plane state for all planes */
 static void readout_plane_state(struct intel_crtc *crtc)
+{
 	struct drm_plane *primary = crtc->base.primary;
 	struct intel_plane_state *plane_state =
 		to_intel_plane_state(primary->state);
 	plane_state->visible =
 		primary_get_hw_state(to_intel_plane(primary));
 	if (plane_state->visible)
 		crtc->base.state->plane_mask |= 1 << drm_plane_index(primary);
+}
 static void intel_modeset_readout_hw_state(struct drm_device *dev)
+{
 	struct drm_i915_private *dev_priv = dev->dev_private;
 	enum i915_pipe pipe;
 	struct intel_crtc *crtc;
 	struct intel_encoder *encoder;
 	struct intel_connector *connector;
 	int i;
 	for_each_intel_crtc(dev, crtc) {
 		__drm_atomic_helper_crtc_destroy_state(&crtc->base, crtc->base.state);
 		memset(crtc->config, 0, sizeof(*crtc->config));
 		crtc->config->base.crtc = &crtc->base;
 		crtc->active = dev_priv->display.get_pipe_config(crtc,
 								 crtc->config);
 		crtc->base.state->active = crtc->active;
 		crtc->base.enabled = crtc->active;
 		readout_plane_state(crtc);
 		DRM_DEBUG_KMS("[CRTC:%d] hw state readout: %s\n",
 			      crtc->base.base.id,
 			      crtc->active ? "enabled" : "disabled");
+	}
 	for (i = 0; i < dev_priv->num_shared_dpll; i++) {
 		struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i];
 		pll->on = pll->get_hw_state(dev_priv, pll,
 					    &pll->config.hw_state);
 		pll->active = 0;
 		pll->config.crtc_mask = 0;
 		for_each_intel_crtc(dev, crtc) {
 			if (crtc->active && intel_crtc_to_shared_dpll(crtc) == pll) {
 				pll->active++;
 				pll->config.crtc_mask |= 1 << crtc->pipe;
+			}
+		}
 		DRM_DEBUG_KMS("%s hw state readout: crtc_mask 0x%08x, on %i\n",
 			      pll->name, pll->config.crtc_mask, pll->on);
 		if (pll->config.crtc_mask)
 			intel_display_power_get(dev_priv, POWER_DOMAIN_PLLS);
+	}
 	for_each_intel_encoder(dev, encoder) {
 		pipe = 0;
 		if (encoder->get_hw_state(encoder, &pipe)) {
 			crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
 			encoder->base.crtc = &crtc->base;
 			encoder->get_config(encoder, crtc->config);
 		} else {
 			encoder->base.crtc = NULL;
+		}
 		DRM_DEBUG_KMS("[ENCODER:%d:%s] hw state readout: %s, pipe %c\n",
 			      encoder->base.base.id,
 			      encoder->base.name,
 			      encoder->base.crtc ? "enabled" : "disabled",
 			      pipe_name(pipe));
+	}
 	for_each_intel_connector(dev, connector) {
 		if (connector->get_hw_state(connector)) {
 			connector->base.dpms = DRM_MODE_DPMS_ON;
 			connector->base.encoder = &connector->encoder->base;
 		} else {
 			connector->base.dpms = DRM_MODE_DPMS_OFF;
 			connector->base.encoder = NULL;
+		}
 		DRM_DEBUG_KMS("[CONNECTOR:%d:%s] hw state readout: %s\n",
 			      connector->base.base.id,
 			      connector->base.name,
 			      connector->base.encoder ? "enabled" : "disabled");
+	}
 	for_each_intel_crtc(dev, crtc) {
 		crtc->base.hwmode = crtc->config->base.adjusted_mode;
 		memset(&crtc->base.mode, 0, sizeof(crtc->base.mode));
 		if (crtc->base.state->active) {
 			intel_mode_from_pipe_config(&crtc->base.mode, crtc->config);
 			intel_mode_from_pipe_config(&crtc->base.state->adjusted_mode, crtc->config);
 			WARN_ON(drm_atomic_set_mode_for_crtc(crtc->base.state, &crtc->base.mode));
 			/*
 			 * The initial mode needs to be set in order to keep
 			 * the atomic core happy. It wants a valid mode if the
 			 * crtc's enabled, so we do the above call.
+			 *
 			 * At this point some state updated by the connectors
 			 * in their ->detect() callback has not run yet, so
 			 * no recalculation can be done yet.
+			 *
 			 * Even if we could do a recalculation and modeset
 			 * right now it would cause a double modeset if
 			 * fbdev or userspace chooses a different initial mode.
+			 *
 			 * If that happens, someone indicated they wanted a
 			 * mode change, which means it's safe to do a full
 			 * recalculation.
 			 */
 			crtc->base.state->mode.private_flags = I915_MODE_FLAG_INHERITED;
 			drm_calc_timestamping_constants(&crtc->base, &crtc->base.hwmode);
 			update_scanline_offset(crtc);
+		}
+	}
+}
 /* Scan out the current hw modeset state,
  * and sanitizes it to the current state
  */
 static void
 intel_modeset_setup_hw_state(struct drm_device *dev)
+{
 	struct drm_i915_private *dev_priv = dev->dev_private;
 	enum i915_pipe pipe;
 	struct intel_crtc *crtc;
 	struct intel_encoder *encoder;
 	int i;
 	intel_modeset_readout_hw_state(dev);
 	/* HW state is read out, now we need to sanitize this mess. */
 	for_each_intel_encoder(dev, encoder) {
 		intel_sanitize_encoder(encoder);
+	}
 	for_each_pipe(dev_priv, pipe) {
 		crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
 		intel_sanitize_crtc(crtc);
 		intel_dump_pipe_config(crtc, crtc->config,
 				       "[setup_hw_state]");
+	}
 	intel_modeset_update_connector_atomic_state(dev);
 	for (i = 0; i < dev_priv->num_shared_dpll; i++) {
 		struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i];
 		if (!pll->on || pll->active)
 			continue;
 		DRM_DEBUG_KMS("%s enabled but not in use, disabling\n", pll->name);
 		pll->disable(dev_priv, pll);
 		pll->on = false;
+	}
 	if (IS_VALLEYVIEW(dev))
 		vlv_wm_get_hw_state(dev);
 	else if (IS_GEN9(dev))
 		skl_wm_get_hw_state(dev);
 	else if (HAS_PCH_SPLIT(dev))
 		ilk_wm_get_hw_state(dev);
 	for_each_intel_crtc(dev, crtc) {
 		unsigned long put_domains;
 		put_domains = modeset_get_crtc_power_domains(&crtc->base);
 		if (WARN_ON(put_domains))
 			modeset_put_power_domains(dev_priv, put_domains);
+	}
 	intel_display_set_init_power(dev_priv, false);
+}
 void intel_display_resume(struct drm_device *dev)
+{
 	struct drm_atomic_state *state = drm_atomic_state_alloc(dev);
 	struct intel_connector *conn;
 	struct intel_plane *plane;
 	struct drm_crtc *crtc;
 	int ret;
 	if (!state)
 		return;
 	state->acquire_ctx = dev->mode_config.acquire_ctx;
 	/* preserve complete old state, including dpll */
 	intel_atomic_get_shared_dpll_state(state);
 	for_each_crtc(dev, crtc) {
 		struct drm_crtc_state *crtc_state =
 			drm_atomic_get_crtc_state(state, crtc);
 		ret = PTR_ERR_OR_ZERO(crtc_state);
 		if (ret)
 			goto err;
 		/* force a restore */
 		crtc_state->mode_changed = true;
+	}
 	for_each_intel_plane(dev, plane) {
 		ret = PTR_ERR_OR_ZERO(drm_atomic_get_plane_state(state, &plane->base));
 		if (ret)
 			goto err;
+	}
 	for_each_intel_connector(dev, conn) {
 		ret = PTR_ERR_OR_ZERO(drm_atomic_get_connector_state(state, &conn->base));
 		if (ret)
 			goto err;
+	}
 	intel_modeset_setup_hw_state(dev);
 	i915_redisable_vga(dev);
 	ret = drm_atomic_commit(state);
 	if (!ret)
 		return;
 err:
 	DRM_ERROR("Restoring old state failed with %i\n", ret);
 	drm_atomic_state_free(state);
+}
 void intel_modeset_gem_init(struct drm_device *dev)
+{
 	struct drm_crtc *c;
 	struct drm_i915_gem_object *obj;
 	int ret;
 	mutex_lock(&dev->struct_mutex);
 	intel_init_gt_powersave(dev);
 	mutex_unlock(&dev->struct_mutex);
 	intel_modeset_init_hw(dev);
 	intel_setup_overlay(dev);
 	/*
 	 * Make sure any fbs we allocated at startup are properly
 	 * pinned & fenced.  When we do the allocation it's too early
 	 * for this.
 	 */
 	for_each_crtc(dev, c) {
 		obj = intel_fb_obj(c->primary->fb);
 		if (obj == NULL)
 			continue;
 		mutex_lock(&dev->struct_mutex);
 		ret = intel_pin_and_fence_fb_obj(c->primary,
 						 c->primary->fb,
 						 c->primary->state,
 						 NULL, NULL);
 		mutex_unlock(&dev->struct_mutex);
 		if (ret) {
 			DRM_ERROR("failed to pin boot fb on pipe %d\n",
 				  to_intel_crtc(c)->pipe);
 			drm_framebuffer_unreference(c->primary->fb);
 			c->primary->fb = NULL;
 			c->primary->crtc = c->primary->state->crtc = NULL;
 			update_state_fb(c->primary);
 			c->state->plane_mask &= ~(1 << drm_plane_index(c->primary));
+		}
+	}
 	intel_backlight_register(dev);
+}
 void intel_connector_unregister(struct intel_connector *intel_connector)
+{
 	struct drm_connector *connector = &intel_connector->base;
 	intel_panel_destroy_backlight(connector);
 	drm_connector_unregister(connector);
+}
 void intel_modeset_cleanup(struct drm_device *dev)
+{
 	struct drm_i915_private *dev_priv = dev->dev_private;
 	struct drm_connector *connector;
 	intel_disable_gt_powersave(dev);
 	intel_backlight_unregister(dev);
 	/*
 	 * Interrupts and polling as the first thing to avoid creating havoc.
 	 * Too much stuff here (turning of connectors, ...) would
 	 * experience fancy races otherwise.
 	 */
 	intel_irq_uninstall(dev_priv);
 	/*
 	 * Due to the hpd irq storm handling the hotplug work can re-arm the
 	 * poll handlers. Hence disable polling after hpd handling is shut down.
 	 */
 	drm_kms_helper_poll_fini(dev);
 	intel_unregister_dsm_handler();
 	intel_fbc_disable(dev_priv);
 	/* flush any delayed tasks or pending work */
 	flush_scheduled_work();
 	/* destroy the backlight and sysfs files before encoders/connectors */
 	list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
 		struct intel_connector *intel_connector;
 		intel_connector = to_intel_connector(connector);
 		intel_connector->unregister(intel_connector);
+	}
 	drm_mode_config_cleanup(dev);
 	intel_cleanup_overlay(dev);
 	mutex_lock(&dev->struct_mutex);
 	intel_cleanup_gt_powersave(dev);
 	mutex_unlock(&dev->struct_mutex);
 	intel_teardown_gmbus(dev);
+}
 /*
  * Return which encoder is currently attached for connector.
  */
 struct drm_encoder *intel_best_encoder(struct drm_connector *connector)
+{
 	return &intel_attached_encoder(connector)->base;
+}
 void intel_connector_attach_encoder(struct intel_connector *connector,
 				    struct intel_encoder *encoder)
+{
 	connector->encoder = encoder;
 	drm_mode_connector_attach_encoder(&connector->base,
 					  &encoder->base);
+}
 /*
  * set vga decode state - true == enable VGA decode
  */
 int intel_modeset_vga_set_state(struct drm_device *dev, bool state)
+{
 	struct drm_i915_private *dev_priv = dev->dev_private;
 	unsigned reg = INTEL_INFO(dev)->gen >= 6 ? SNB_GMCH_CTRL : INTEL_GMCH_CTRL;
 	u16 gmch_ctrl;
 	if (pci_read_config_word(dev_priv->bridge_dev, reg, &gmch_ctrl)) {
 		DRM_ERROR("failed to read control word\n");
 		return -EIO;
+	}
 	if (!!(gmch_ctrl & INTEL_GMCH_VGA_DISABLE) == !state)
 		return 0;
 	if (state)
 		gmch_ctrl &= ~INTEL_GMCH_VGA_DISABLE;
 	else
 		gmch_ctrl |= INTEL_GMCH_VGA_DISABLE;
 	if (pci_write_config_word(dev_priv->bridge_dev, reg, gmch_ctrl)) {
 		DRM_ERROR("failed to write control word\n");
 		return -EIO;
+	}
 	return 0;
+}
 struct intel_display_error_state {
 	u32 power_well_driver;
 	int num_transcoders;
 	struct intel_cursor_error_state {
 		u32 control;
 		u32 position;
 		u32 base;
 		u32 size;
 	} cursor[I915_MAX_PIPES];
 	struct intel_pipe_error_state {
 		bool power_domain_on;
 		u32 source;
 		u32 stat;
 	} pipe[I915_MAX_PIPES];
 	struct intel_plane_error_state {
 		u32 control;
 		u32 stride;
 		u32 size;
 		u32 pos;
 		u32 addr;
 		u32 surface;
 		u32 tile_offset;
 	} plane[I915_MAX_PIPES];
 	struct intel_transcoder_error_state {
 		bool power_domain_on;
 		enum transcoder cpu_transcoder;
 		u32 conf;
 		u32 htotal;
 		u32 hblank;
 		u32 hsync;
 		u32 vtotal;
 		u32 vblank;
 		u32 vsync;
 	} transcoder[4];
 };
 struct intel_display_error_state *
 intel_display_capture_error_state(struct drm_device *dev)
+{
 	struct drm_i915_private *dev_priv = dev->dev_private;
 	struct intel_display_error_state *error;
 	int transcoders[] = {
 		TRANSCODER_A,
 		TRANSCODER_B,
 		TRANSCODER_C,
 		TRANSCODER_EDP,
 	};
 	int i;
 	if (INTEL_INFO(dev)->num_pipes == 0)
 		return NULL;
 	error = kzalloc(sizeof(*error), GFP_ATOMIC);
 	if (error == NULL)
 		return NULL;
 	if (IS_HASWELL(dev) || IS_BROADWELL(dev))
 		error->power_well_driver = I915_READ(HSW_PWR_WELL_DRIVER);
 	for_each_pipe(dev_priv, i) {
 		error->pipe[i].power_domain_on =
 			__intel_display_power_is_enabled(dev_priv,
 							 POWER_DOMAIN_PIPE(i));
 		if (!error->pipe[i].power_domain_on)
 			continue;
 		error->cursor[i].control = I915_READ(CURCNTR(i));
 		error->cursor[i].position = I915_READ(CURPOS(i));
 		error->cursor[i].base = I915_READ(CURBASE(i));
 		error->plane[i].control = I915_READ(DSPCNTR(i));
 		error->plane[i].stride = I915_READ(DSPSTRIDE(i));
 		if (INTEL_INFO(dev)->gen <= 3) {
 			error->plane[i].size = I915_READ(DSPSIZE(i));
 			error->plane[i].pos = I915_READ(DSPPOS(i));
+		}
 		if (INTEL_INFO(dev)->gen <= 7 && !IS_HASWELL(dev))
 			error->plane[i].addr = I915_READ(DSPADDR(i));
 		if (INTEL_INFO(dev)->gen >= 4) {
 			error->plane[i].surface = I915_READ(DSPSURF(i));
 			error->plane[i].tile_offset = I915_READ(DSPTILEOFF(i));
+		}
 		error->pipe[i].source = I915_READ(PIPESRC(i));
 		if (HAS_GMCH_DISPLAY(dev))
 			error->pipe[i].stat = I915_READ(PIPESTAT(i));
+	}
 	error->num_transcoders = INTEL_INFO(dev)->num_pipes;
 	if (HAS_DDI(dev_priv->dev))
 		error->num_transcoders++; /* Account for eDP. */
 	for (i = 0; i < error->num_transcoders; i++) {
 		enum transcoder cpu_transcoder = transcoders[i];
 		error->transcoder[i].power_domain_on =
 			__intel_display_power_is_enabled(dev_priv,
 				POWER_DOMAIN_TRANSCODER(cpu_transcoder));
 		if (!error->transcoder[i].power_domain_on)
 			continue;
 		error->transcoder[i].cpu_transcoder = cpu_transcoder;
 		error->transcoder[i].conf = I915_READ(PIPECONF(cpu_transcoder));
 		error->transcoder[i].htotal = I915_READ(HTOTAL(cpu_transcoder));
 		error->transcoder[i].hblank = I915_READ(HBLANK(cpu_transcoder));
 		error->transcoder[i].hsync = I915_READ(HSYNC(cpu_transcoder));
 		error->transcoder[i].vtotal = I915_READ(VTOTAL(cpu_transcoder));
 		error->transcoder[i].vblank = I915_READ(VBLANK(cpu_transcoder));
 		error->transcoder[i].vsync = I915_READ(VSYNC(cpu_transcoder));
+	}
 	return error;
+}
 #define err_printf(e, ...) i915_error_printf(e, __VA_ARGS__)
 void
 intel_display_print_error_state(struct drm_i915_error_state_buf *m,
 				struct drm_device *dev,
 				struct intel_display_error_state *error)
+{
 	struct drm_i915_private *dev_priv = dev->dev_private;
 	int i;
 	if (!error)
 		return;
 	err_printf(m, "Num Pipes: %d\n", INTEL_INFO(dev)->num_pipes);
 	if (IS_HASWELL(dev) || IS_BROADWELL(dev))
 		err_printf(m, "PWR_WELL_CTL2: %08x\n",
 			   error->power_well_driver);
 	for_each_pipe(dev_priv, i) {
 		err_printf(m, "Pipe [%d]:\n", i);
 		err_printf(m, "  Power: %s\n",
 			   error->pipe[i].power_domain_on ? "on" : "off");
 		err_printf(m, "  SRC: %08x\n", error->pipe[i].source);
 		err_printf(m, "  STAT: %08x\n", error->pipe[i].stat);
 		err_printf(m, "Plane [%d]:\n", i);
 		err_printf(m, "  CNTR: %08x\n", error->plane[i].control);
 		err_printf(m, "  STRIDE: %08x\n", error->plane[i].stride);
 		if (INTEL_INFO(dev)->gen <= 3) {
 			err_printf(m, "  SIZE: %08x\n", error->plane[i].size);
 			err_printf(m, "  POS: %08x\n", error->plane[i].pos);
+		}
 		if (INTEL_INFO(dev)->gen <= 7 && !IS_HASWELL(dev))
 			err_printf(m, "  ADDR: %08x\n", error->plane[i].addr);
 		if (INTEL_INFO(dev)->gen >= 4) {
 			err_printf(m, "  SURF: %08x\n", error->plane[i].surface);
 			err_printf(m, "  TILEOFF: %08x\n", error->plane[i].tile_offset);
+		}
 		err_printf(m, "Cursor [%d]:\n", i);
 		err_printf(m, "  CNTR: %08x\n", error->cursor[i].control);
 		err_printf(m, "  POS: %08x\n", error->cursor[i].position);
 		err_printf(m, "  BASE: %08x\n", error->cursor[i].base);
+	}
 	for (i = 0; i < error->num_transcoders; i++) {
 		err_printf(m, "CPU transcoder: %c\n",
 			   transcoder_name(error->transcoder[i].cpu_transcoder));
 		err_printf(m, "  Power: %s\n",
 			   error->transcoder[i].power_domain_on ? "on" : "off");
 		err_printf(m, "  CONF: %08x\n", error->transcoder[i].conf);
 		err_printf(m, "  HTOTAL: %08x\n", error->transcoder[i].htotal);
 		err_printf(m, "  HBLANK: %08x\n", error->transcoder[i].hblank);
 		err_printf(m, "  HSYNC: %08x\n", error->transcoder[i].hsync);
 		err_printf(m, "  VTOTAL: %08x\n", error->transcoder[i].vtotal);
 		err_printf(m, "  VBLANK: %08x\n", error->transcoder[i].vblank);
 		err_printf(m, "  VSYNC: %08x\n", error->transcoder[i].vsync);
+	}
+}
 void intel_modeset_preclose(struct drm_device *dev, struct drm_file *file)
+{
 	struct intel_crtc *crtc;
 	for_each_intel_crtc(dev, crtc) {
 		struct intel_unpin_work *work;
 		spin_lock_irq(&dev->event_lock);
 		work = crtc->unpin_work;
 		if (work && work->event &&
 		    work->event->base.file_priv == file) {
 			kfree(work->event);
 			work->event = NULL;
+		}
 		spin_unlock_irq(&dev->event_lock);
+	}
+}

 @@ -1,1609 +1,1613 @@
-/*	$NetBSD: intel_dp.c,v 1.11 2018/08/27 04:58:24 riastradh Exp $	*/
+/*	$NetBSD: intel_dp.c,v 1.12 2018/08/27 06:16:01 riastradh Exp $	*/
 /*
  * Copyright © 2008 Intel Corporation
+ *
  * Permission is hereby granted, free of charge, to any person obtaining a
  * copy of this software and associated documentation files (the "Software"),
  * to deal in the Software without restriction, including without limitation
  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
  * and/or sell copies of the Software, and to permit persons to whom the
  * Software is furnished to do so, subject to the following conditions:
+ *
  * The above copyright notice and this permission notice (including the next
  * paragraph) shall be included in all copies or substantial portions of the
  * Software.
+ *
  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
  * IN THE SOFTWARE.
+ *
  * Authors:
  *    Keith Packard <keithp@keithp.com>
+ *
  */
 #include <sys/cdefs.h>
-__KERNEL_RCSID(0, "$NetBSD: intel_dp.c,v 1.11 2018/08/27 04:58:24 riastradh Exp $");
+__KERNEL_RCSID(0, "$NetBSD: intel_dp.c,v 1.12 2018/08/27 06:16:01 riastradh Exp $");
 #include <linux/i2c.h>
 #include <linux/slab.h>
 #include <linux/export.h>
 #include <linux/notifier.h>
 #include <linux/reboot.h>
 #include <linux/err.h>
 #include <linux/module.h>
 #include <linux/printk.h>
 #include <linux/pm_qos.h>
 #include <drm/drmP.h>
 #include <drm/drm_atomic_helper.h>
 #include <drm/drm_crtc.h>
 #include <drm/drm_crtc_helper.h>
 #include <drm/drm_edid.h>
 #include "intel_drv.h"
 #include <drm/i915_drm.h>
 #include "i915_drv.h"
 #define DP_LINK_CHECK_TIMEOUT	(10 * 1000)
 /* Compliance test status bits  */
 #define INTEL_DP_RESOLUTION_SHIFT_MASK	0
 #define INTEL_DP_RESOLUTION_PREFERRED	(1 << INTEL_DP_RESOLUTION_SHIFT_MASK)
 #define INTEL_DP_RESOLUTION_STANDARD	(2 << INTEL_DP_RESOLUTION_SHIFT_MASK)
 #define INTEL_DP_RESOLUTION_FAILSAFE	(3 << INTEL_DP_RESOLUTION_SHIFT_MASK)
 struct dp_link_dpll {
 	int clock;
 	struct dpll dpll;
 };
 static const struct dp_link_dpll gen4_dpll[] = {
 	{ 162000,
 		{ .p1 = 2, .p2 = 10, .n = 2, .m1 = 23, .m2 = 8 } },
 	{ 270000,
 		{ .p1 = 1, .p2 = 10, .n = 1, .m1 = 14, .m2 = 2 } }
 };
 static const struct dp_link_dpll pch_dpll[] = {
 	{ 162000,
 		{ .p1 = 2, .p2 = 10, .n = 1, .m1 = 12, .m2 = 9 } },
 	{ 270000,
 		{ .p1 = 1, .p2 = 10, .n = 2, .m1 = 14, .m2 = 8 } }
 };
 static const struct dp_link_dpll vlv_dpll[] = {
 	{ 162000,
 		{ .p1 = 3, .p2 = 2, .n = 5, .m1 = 3, .m2 = 81 } },
 	{ 270000,
 		{ .p1 = 2, .p2 = 2, .n = 1, .m1 = 2, .m2 = 27 } }
 };
 /*
  * CHV supports eDP 1.4 that have  more link rates.
  * Below only provides the fixed rate but exclude variable rate.
  */
 static const struct dp_link_dpll chv_dpll[] = {
 	/*
 	 * CHV requires to program fractional division for m2.
 	 * m2 is stored in fixed point format using formula below
 	 * (m2_int << 22) | m2_fraction
 	 */
 	{ 162000,	/* m2_int = 32, m2_fraction = 1677722 */
 		{ .p1 = 4, .p2 = 2, .n = 1, .m1 = 2, .m2 = 0x819999a } },
 	{ 270000,	/* m2_int = 27, m2_fraction = 0 */
 		{ .p1 = 4, .p2 = 1, .n = 1, .m1 = 2, .m2 = 0x6c00000 } },
 	{ 540000,	/* m2_int = 27, m2_fraction = 0 */
 		{ .p1 = 2, .p2 = 1, .n = 1, .m1 = 2, .m2 = 0x6c00000 } }
 };
 static const int bxt_rates[] = { 162000, 216000, 243000, 270000,
 , 432000, 540000 };
 static const int skl_rates[] = { 162000, 216000, 270000,
 , 432000, 540000 };
 static const int default_rates[] = { 162000, 270000, 540000 };
 /**
  * is_edp - is the given port attached to an eDP panel (either CPU or PCH)
  * @intel_dp: DP struct
+ *
  * If a CPU or PCH DP output is attached to an eDP panel, this function
  * will return true, and false otherwise.
  */
 static bool is_edp(struct intel_dp *intel_dp)
+{
 	struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
 	return intel_dig_port->base.type == INTEL_OUTPUT_EDP;
+}
 static struct drm_device *intel_dp_to_dev(struct intel_dp *intel_dp)
+{
 	struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
 	return intel_dig_port->base.base.dev;
+}
 static struct intel_dp *intel_attached_dp(struct drm_connector *connector)
+{
 	return enc_to_intel_dp(&intel_attached_encoder(connector)->base);
+}
 static void intel_dp_link_down(struct intel_dp *intel_dp);
 static bool edp_panel_vdd_on(struct intel_dp *intel_dp);
 static void edp_panel_vdd_off(struct intel_dp *intel_dp, bool sync);
 static void vlv_init_panel_power_sequencer(struct intel_dp *intel_dp);
 static void vlv_steal_power_sequencer(struct drm_device *dev,
 				      enum pipe pipe);
 static unsigned int intel_dp_unused_lane_mask(int lane_count)
+{
 	return ~((1 << lane_count) - 1) & 0xf;
+}
 static int
 intel_dp_max_link_bw(struct intel_dp  *intel_dp)
+{
 	int max_link_bw = intel_dp->dpcd[DP_MAX_LINK_RATE];
 	switch (max_link_bw) {
 	case DP_LINK_BW_1_62:
 	case DP_LINK_BW_2_7:
 	case DP_LINK_BW_5_4:
 		break;
 	default:
 		WARN(1, "invalid max DP link bw val %x, using 1.62Gbps\n",
 		     max_link_bw);
 		max_link_bw = DP_LINK_BW_1_62;
 		break;
+	}
 	return max_link_bw;
+}
 static u8 intel_dp_max_lane_count(struct intel_dp *intel_dp)
+{
 	struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
 	struct drm_device *dev = intel_dig_port->base.base.dev;
 	u8 source_max, sink_max;
 	source_max = 4;
 	if (HAS_DDI(dev) && intel_dig_port->port == PORT_A &&
 	    (intel_dig_port->saved_port_bits & DDI_A_4_LANES) == 0)
 		source_max = 2;
 	sink_max = drm_dp_max_lane_count(intel_dp->dpcd);
 	return min(source_max, sink_max);
+}
 /*
  * The units on the numbers in the next two are... bizarre.  Examples will
  * make it clearer; this one parallels an example in the eDP spec.
+ *
  * intel_dp_max_data_rate for one lane of 2.7GHz evaluates as:
+ *
  *     270000 * 1 * 8 / 10 == 216000
+ *
  * The actual data capacity of that configuration is 2.16Gbit/s, so the
  * units are decakilobits.  ->clock in a drm_display_mode is in kilohertz -
  * or equivalently, kilopixels per second - so for 1680x1050R it'd be
  * 119000.  At 18bpp that's 2142000 kilobits per second.
+ *
  * Thus the strange-looking division by 10 in intel_dp_link_required, to
  * get the result in decakilobits instead of kilobits.
  */
 static int
 intel_dp_link_required(int pixel_clock, int bpp)
+{
 	return (pixel_clock * bpp + 9) / 10;
+}
 static int
 intel_dp_max_data_rate(int max_link_clock, int max_lanes)
+{
 	return (max_link_clock * max_lanes * 8) / 10;
+}
 static enum drm_mode_status
 intel_dp_mode_valid(struct drm_connector *connector,
 		    struct drm_display_mode *mode)
+{
 	struct intel_dp *intel_dp = intel_attached_dp(connector);
 	struct intel_connector *intel_connector = to_intel_connector(connector);
 	struct drm_display_mode *fixed_mode = intel_connector->panel.fixed_mode;
 	int target_clock = mode->clock;
 	int max_rate, mode_rate, max_lanes, max_link_clock;
 	if (is_edp(intel_dp) && fixed_mode) {
 		if (mode->hdisplay > fixed_mode->hdisplay)
 			return MODE_PANEL;
 		if (mode->vdisplay > fixed_mode->vdisplay)
 			return MODE_PANEL;
 		target_clock = fixed_mode->clock;
+	}
 	max_link_clock = intel_dp_max_link_rate(intel_dp);
 	max_lanes = intel_dp_max_lane_count(intel_dp);
 	max_rate = intel_dp_max_data_rate(max_link_clock, max_lanes);
 	mode_rate = intel_dp_link_required(target_clock, 18);
 	if (mode_rate > max_rate)
 		return MODE_CLOCK_HIGH;
 	if (mode->clock < 10000)
 		return MODE_CLOCK_LOW;
 	if (mode->flags & DRM_MODE_FLAG_DBLCLK)
 		return MODE_H_ILLEGAL;
 	return MODE_OK;
+}
 uint32_t intel_dp_pack_aux(const uint8_t *src, int src_bytes)
+{
 	int	i;
 	uint32_t v = 0;
 	if (src_bytes > 4)
 		src_bytes = 4;
 	for (i = 0; i < src_bytes; i++)
 		v |= ((uint32_t) src[i]) << ((3-i) * 8);
 	return v;
+}
 static void intel_dp_unpack_aux(uint32_t src, uint8_t *dst, int dst_bytes)
+{
 	int i;
 	if (dst_bytes > 4)
 		dst_bytes = 4;
 	for (i = 0; i < dst_bytes; i++)
 		dst[i] = src >> ((3-i) * 8);
+}
 static void
 intel_dp_init_panel_power_sequencer(struct drm_device *dev,
 				    struct intel_dp *intel_dp);
 static void
 intel_dp_init_panel_power_sequencer_registers(struct drm_device *dev,
 					      struct intel_dp *intel_dp);
 static void pps_lock(struct intel_dp *intel_dp)
+{
 	struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
 	struct intel_encoder *encoder = &intel_dig_port->base;
 	struct drm_device *dev = encoder->base.dev;
 	struct drm_i915_private *dev_priv = dev->dev_private;
 	enum intel_display_power_domain power_domain;
 	/*
 	 * See vlv_power_sequencer_reset() why we need
 	 * a power domain reference here.
 	 */
 	power_domain = intel_display_port_aux_power_domain(encoder);
 	intel_display_power_get(dev_priv, power_domain);
 	mutex_lock(&dev_priv->pps_mutex);
+}
 static void pps_unlock(struct intel_dp *intel_dp)
+{
 	struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
 	struct intel_encoder *encoder = &intel_dig_port->base;
 	struct drm_device *dev = encoder->base.dev;
 	struct drm_i915_private *dev_priv = dev->dev_private;
 	enum intel_display_power_domain power_domain;
 	mutex_unlock(&dev_priv->pps_mutex);
 	power_domain = intel_display_port_aux_power_domain(encoder);
 	intel_display_power_put(dev_priv, power_domain);
+}
 static void
 vlv_power_sequencer_kick(struct intel_dp *intel_dp)
+{
 	struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
 	struct drm_device *dev = intel_dig_port->base.base.dev;
 	struct drm_i915_private *dev_priv = dev->dev_private;
 	enum pipe pipe = intel_dp->pps_pipe;
 	bool pll_enabled, release_cl_override = false;
 	enum dpio_phy phy = DPIO_PHY(pipe);
 	enum dpio_channel ch = vlv_pipe_to_channel(pipe);
 	uint32_t DP;
 	if (WARN(I915_READ(intel_dp->output_reg) & DP_PORT_EN,
 		 "skipping pipe %c power seqeuncer kick due to port %c being active\n",
 		 pipe_name(pipe), port_name(intel_dig_port->port)))
 		return;
 	DRM_DEBUG_KMS("kicking pipe %c power sequencer for port %c\n",
 		      pipe_name(pipe), port_name(intel_dig_port->port));
 	/* Preserve the BIOS-computed detected bit. This is
 	 * supposed to be read-only.
 	 */
 	DP = I915_READ(intel_dp->output_reg) & DP_DETECTED;
 	DP |= DP_VOLTAGE_0_4 | DP_PRE_EMPHASIS_0;
 	DP |= DP_PORT_WIDTH(1);
 	DP |= DP_LINK_TRAIN_PAT_1;
 	if (IS_CHERRYVIEW(dev))
 		DP |= DP_PIPE_SELECT_CHV(pipe);
 	else if (pipe == PIPE_B)
 		DP |= DP_PIPEB_SELECT;
 	pll_enabled = I915_READ(DPLL(pipe)) & DPLL_VCO_ENABLE;
 	/*
 	 * The DPLL for the pipe must be enabled for this to work.
 	 * So enable temporarily it if it's not already enabled.
 	 */
 	if (!pll_enabled) {
 		release_cl_override = IS_CHERRYVIEW(dev) &&
 			!chv_phy_powergate_ch(dev_priv, phy, ch, true);
 		vlv_force_pll_on(dev, pipe, IS_CHERRYVIEW(dev) ?
 				 &chv_dpll[0].dpll : &vlv_dpll[0].dpll);
+	}
 	/*
 	 * Similar magic as in intel_dp_enable_port().
 	 * We _must_ do this port enable + disable trick
 	 * to make this power seqeuencer lock onto the port.
 	 * Otherwise even VDD force bit won't work.
 	 */
 	I915_WRITE(intel_dp->output_reg, DP);
 	POSTING_READ(intel_dp->output_reg);
 	I915_WRITE(intel_dp->output_reg, DP | DP_PORT_EN);
 	POSTING_READ(intel_dp->output_reg);
 	I915_WRITE(intel_dp->output_reg, DP & ~DP_PORT_EN);
 	POSTING_READ(intel_dp->output_reg);
 	if (!pll_enabled) {
 		vlv_force_pll_off(dev, pipe);
 		if (release_cl_override)
 			chv_phy_powergate_ch(dev_priv, phy, ch, false);
+	}
+}
 static enum i915_pipe
 vlv_power_sequencer_pipe(struct intel_dp *intel_dp)
+{
 	struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
 	struct drm_device *dev = intel_dig_port->base.base.dev;
 	struct drm_i915_private *dev_priv = dev->dev_private;
 	struct intel_encoder *encoder;
 	unsigned int pipes = (1 << PIPE_A) | (1 << PIPE_B);
 	enum i915_pipe pipe;
 	lockdep_assert_held(&dev_priv->pps_mutex);
 	/* We should never land here with regular DP ports */
 	WARN_ON(!is_edp(intel_dp));
 	if (intel_dp->pps_pipe != INVALID_PIPE)
 		return intel_dp->pps_pipe;
 	/*
 	 * We don't have power sequencer currently.
 	 * Pick one that's not used by other ports.
 	 */
 	list_for_each_entry(encoder, &dev->mode_config.encoder_list,
 			    base.head) {
 		struct intel_dp *tmp;
 		if (encoder->type != INTEL_OUTPUT_EDP)
 			continue;
 		tmp = enc_to_intel_dp(&encoder->base);
 		if (tmp->pps_pipe != INVALID_PIPE)
 			pipes &= ~(1 << tmp->pps_pipe);
+	}
 	/*
 	 * Didn't find one. This should not happen since there
 	 * are two power sequencers and up to two eDP ports.
 	 */
 	if (WARN_ON(pipes == 0))
 		pipe = PIPE_A;
 	else
 		pipe = ffs(pipes) - 1;
 	vlv_steal_power_sequencer(dev, pipe);
 	intel_dp->pps_pipe = pipe;
 	DRM_DEBUG_KMS("picked pipe %c power sequencer for port %c\n",
 		      pipe_name(intel_dp->pps_pipe),
 		      port_name(intel_dig_port->port));
 	/* init power sequencer on this pipe and port */
 	intel_dp_init_panel_power_sequencer(dev, intel_dp);
 	intel_dp_init_panel_power_sequencer_registers(dev, intel_dp);
 	/*
 	 * Even vdd force doesn't work until we've made
 	 * the power sequencer lock in on the port.
 	 */
 	vlv_power_sequencer_kick(intel_dp);
 	return intel_dp->pps_pipe;
+}
 typedef bool (*vlv_pipe_check)(struct drm_i915_private *dev_priv,
 			       enum pipe pipe);
 static bool vlv_pipe_has_pp_on(struct drm_i915_private *dev_priv,
 			       enum pipe pipe)
+{
 	return I915_READ(VLV_PIPE_PP_STATUS(pipe)) & PP_ON;
+}
 static bool vlv_pipe_has_vdd_on(struct drm_i915_private *dev_priv,
 				enum pipe pipe)
+{
 	return I915_READ(VLV_PIPE_PP_CONTROL(pipe)) & EDP_FORCE_VDD;
+}
 static bool vlv_pipe_any(struct drm_i915_private *dev_priv,
 			 enum pipe pipe)
+{
 	return true;
+}
 static enum pipe
 vlv_initial_pps_pipe(struct drm_i915_private *dev_priv,
 		     enum port port,
 		     vlv_pipe_check pipe_check)
+{
 	enum pipe pipe;
 	for (pipe = PIPE_A; pipe <= PIPE_B; pipe++) {
 		u32 port_sel = I915_READ(VLV_PIPE_PP_ON_DELAYS(pipe)) &
 			PANEL_PORT_SELECT_MASK;
 		if (port_sel != PANEL_PORT_SELECT_VLV(port))
 			continue;
 		if (!pipe_check(dev_priv, pipe))
 			continue;
 		return pipe;
+	}
 	return INVALID_PIPE;
+}
 static void
 vlv_initial_power_sequencer_setup(struct intel_dp *intel_dp)
+{
 	struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
 	struct drm_device *dev = intel_dig_port->base.base.dev;
 	struct drm_i915_private *dev_priv = dev->dev_private;
 	enum port port = intel_dig_port->port;
 	lockdep_assert_held(&dev_priv->pps_mutex);
 	/* try to find a pipe with this port selected */
 	/* first pick one where the panel is on */
 	intel_dp->pps_pipe = vlv_initial_pps_pipe(dev_priv, port,
 						  vlv_pipe_has_pp_on);
 	/* didn't find one? pick one where vdd is on */
 	if (intel_dp->pps_pipe == INVALID_PIPE)
 		intel_dp->pps_pipe = vlv_initial_pps_pipe(dev_priv, port,
 							  vlv_pipe_has_vdd_on);
 	/* didn't find one? pick one with just the correct port */
 	if (intel_dp->pps_pipe == INVALID_PIPE)
 		intel_dp->pps_pipe = vlv_initial_pps_pipe(dev_priv, port,
 							  vlv_pipe_any);
 	/* didn't find one? just let vlv_power_sequencer_pipe() pick one when needed */
 	if (intel_dp->pps_pipe == INVALID_PIPE) {
 		DRM_DEBUG_KMS("no initial power sequencer for port %c\n",
 			      port_name(port));
 		return;
+	}
 	DRM_DEBUG_KMS("initial power sequencer for port %c: pipe %c\n",
 		      port_name(port), pipe_name(intel_dp->pps_pipe));
 	intel_dp_init_panel_power_sequencer(dev, intel_dp);
 	intel_dp_init_panel_power_sequencer_registers(dev, intel_dp);
+}
 void vlv_power_sequencer_reset(struct drm_i915_private *dev_priv)
+{
 	struct drm_device *dev = dev_priv->dev;
 	struct intel_encoder *encoder;
 	if (WARN_ON(!IS_VALLEYVIEW(dev)))
 		return;
 	/*
 	 * We can't grab pps_mutex here due to deadlock with power_domain
 	 * mutex when power_domain functions are called while holding pps_mutex.
 	 * That also means that in order to use pps_pipe the code needs to
 	 * hold both a power domain reference and pps_mutex, and the power domain
 	 * reference get/put must be done while _not_ holding pps_mutex.
 	 * pps_{lock,unlock}() do these steps in the correct order, so one
 	 * should use them always.
 	 */
 	list_for_each_entry(encoder, &dev->mode_config.encoder_list, base.head) {
 		struct intel_dp *intel_dp;
 		if (encoder->type != INTEL_OUTPUT_EDP)
 			continue;
 		intel_dp = enc_to_intel_dp(&encoder->base);
 		intel_dp->pps_pipe = INVALID_PIPE;
+	}
+}
 static u32 _pp_ctrl_reg(struct intel_dp *intel_dp)
+{
 	struct drm_device *dev = intel_dp_to_dev(intel_dp);
 	if (IS_BROXTON(dev))
 		return BXT_PP_CONTROL(0);
 	else if (HAS_PCH_SPLIT(dev))
 		return PCH_PP_CONTROL;
 	else
 		return VLV_PIPE_PP_CONTROL(vlv_power_sequencer_pipe(intel_dp));
+}
 static u32 _pp_stat_reg(struct intel_dp *intel_dp)
+{
 	struct drm_device *dev = intel_dp_to_dev(intel_dp);
 	if (IS_BROXTON(dev))
 		return BXT_PP_STATUS(0);
 	else if (HAS_PCH_SPLIT(dev))
 		return PCH_PP_STATUS;
 	else
 		return VLV_PIPE_PP_STATUS(vlv_power_sequencer_pipe(intel_dp));
+}
 /* Reboot notifier handler to shutdown panel power to guarantee T12 timing
    This function only applicable when panel PM state is not to be tracked */
 static int edp_notify_handler(struct notifier_block *this, unsigned long code,
 			      void *unused)
+{
 #ifdef __NetBSD__
 	panic("XXX");
 #else
 	struct intel_dp *intel_dp = container_of(this, typeof(* intel_dp),
 						 edp_notifier);
 	struct drm_device *dev = intel_dp_to_dev(intel_dp);
 	struct drm_i915_private *dev_priv = dev->dev_private;
 	if (!is_edp(intel_dp) || code != SYS_RESTART)
 		return 0;
 	pps_lock(intel_dp);
 	if (IS_VALLEYVIEW(dev)) {
 		enum pipe pipe = vlv_power_sequencer_pipe(intel_dp);
 		u32 pp_ctrl_reg, pp_div_reg;
 		u32 pp_div;
 		pp_ctrl_reg = VLV_PIPE_PP_CONTROL(pipe);
 		pp_div_reg  = VLV_PIPE_PP_DIVISOR(pipe);
 		pp_div = I915_READ(pp_div_reg);
 		pp_div &= PP_REFERENCE_DIVIDER_MASK;
 		/* 0x1F write to PP_DIV_REG sets max cycle delay */
 		I915_WRITE(pp_div_reg, pp_div | 0x1F);
 		I915_WRITE(pp_ctrl_reg, PANEL_UNLOCK_REGS | PANEL_POWER_OFF);
 		msleep(intel_dp->panel_power_cycle_delay);
+	}
 	pps_unlock(intel_dp);
 	return 0;
 #endif
+}
 static bool edp_have_panel_power(struct intel_dp *intel_dp)
+{
 	struct drm_device *dev = intel_dp_to_dev(intel_dp);
 	struct drm_i915_private *dev_priv = dev->dev_private;
 	lockdep_assert_held(&dev_priv->pps_mutex);
 	if (IS_VALLEYVIEW(dev) &&
 	    intel_dp->pps_pipe == INVALID_PIPE)
 		return false;
 	return (I915_READ(_pp_stat_reg(intel_dp)) & PP_ON) != 0;
+}
 static bool edp_have_panel_vdd(struct intel_dp *intel_dp)
+{
 	struct drm_device *dev = intel_dp_to_dev(intel_dp);
 	struct drm_i915_private *dev_priv = dev->dev_private;
 	lockdep_assert_held(&dev_priv->pps_mutex);
 	if (IS_VALLEYVIEW(dev) &&
 	    intel_dp->pps_pipe == INVALID_PIPE)
 		return false;
 	return I915_READ(_pp_ctrl_reg(intel_dp)) & EDP_FORCE_VDD;
+}
 static void
 intel_dp_check_edp(struct intel_dp *intel_dp)
+{
 	struct drm_device *dev = intel_dp_to_dev(intel_dp);
 	struct drm_i915_private *dev_priv = dev->dev_private;
 	if (!is_edp(intel_dp))
 		return;
 	if (!edp_have_panel_power(intel_dp) && !edp_have_panel_vdd(intel_dp)) {
 		WARN(1, "eDP powered off while attempting aux channel communication.\n");
 		DRM_DEBUG_KMS("Status 0x%08x Control 0x%08x\n",
 			      I915_READ(_pp_stat_reg(intel_dp)),
 			      I915_READ(_pp_ctrl_reg(intel_dp)));
+	}
+}
 static uint32_t
 intel_dp_aux_wait_done(struct intel_dp *intel_dp, bool has_aux_irq)
+{
 	struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
 	struct drm_device *dev = intel_dig_port->base.base.dev;
 	struct drm_i915_private *dev_priv = dev->dev_private;
 	uint32_t ch_ctl = intel_dp->aux_ch_ctl_reg;
 	uint32_t status;
 	bool done;
 #define C (((status = I915_READ_NOTRACE(ch_ctl)) & DP_AUX_CH_CTL_SEND_BUSY) == 0)
 #ifdef __NetBSD__
 	if (has_aux_irq && !cold) {
 		int ret;
 		spin_lock(&dev_priv->gmbus_wait_lock);
 		DRM_SPIN_TIMED_WAIT_NOINTR_UNTIL(ret,
 		    &dev_priv->gmbus_wait_queue, &dev_priv->gmbus_wait_lock,
 		    msecs_to_jiffies_timeout(10),
 		    C);
 		if (ret < 0)	/* Failure: pretend same as done.  */
 			done = true;
 		else if (ret == 0) /* Timed out: not done.  */
 			done = false;
 		else		/* Succeeded (ret > 0): done.  */
 			done = true;
 		spin_unlock(&dev_priv->gmbus_wait_lock);
 	} else {
 		done = wait_for_atomic(C, 10) == 0;
+	}
 #else
 	if (has_aux_irq)
 		done = wait_event_timeout(dev_priv->gmbus_wait_queue, C,
 					  msecs_to_jiffies_timeout(10));
 	else
 		done = wait_for_atomic(C, 10) == 0;
 #endif
 	if (!done)
 		DRM_ERROR("dp aux hw did not signal timeout (has irq: %i)!\n",
 			  has_aux_irq);
 #undef C
 	return status;
+}
 static uint32_t i9xx_get_aux_clock_divider(struct intel_dp *intel_dp, int index)
+{
 	struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
 	struct drm_device *dev = intel_dig_port->base.base.dev;
 	/*
 	 * The clock divider is based off the hrawclk, and would like to run at
 	 * 2MHz.  So, take the hrawclk value and divide by 2 and use that
 	 */
 	return index ? 0 : intel_hrawclk(dev) / 2;
+}
 static uint32_t ilk_get_aux_clock_divider(struct intel_dp *intel_dp, int index)
+{
 	struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
 	struct drm_device *dev = intel_dig_port->base.base.dev;
 	struct drm_i915_private *dev_priv = dev->dev_private;
 	if (index)
 		return 0;
 	if (intel_dig_port->port == PORT_A) {
 		return DIV_ROUND_UP(dev_priv->cdclk_freq, 2000);
 	} else {
 		return DIV_ROUND_UP(intel_pch_rawclk(dev), 2);
+	}
+}
 static uint32_t hsw_get_aux_clock_divider(struct intel_dp *intel_dp, int index)
+{
 	struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
 	struct drm_device *dev = intel_dig_port->base.base.dev;
 	struct drm_i915_private *dev_priv = dev->dev_private;
 	if (intel_dig_port->port == PORT_A) {
 		if (index)
 			return 0;
 		return DIV_ROUND_CLOSEST(dev_priv->cdclk_freq, 2000);
 	} else if (dev_priv->pch_id == INTEL_PCH_LPT_DEVICE_ID_TYPE) {
 		/* Workaround for non-ULT HSW */
 		switch (index) {
 		case 0: return 63;
 		case 1: return 72;
 		default: return 0;
+		}
 	} else  {
 		return index ? 0 : DIV_ROUND_UP(intel_pch_rawclk(dev), 2);
+	}
+}
 static uint32_t vlv_get_aux_clock_divider(struct intel_dp *intel_dp, int index)
+{
 	return index ? 0 : 100;
+}
 static uint32_t skl_get_aux_clock_divider(struct intel_dp *intel_dp, int index)
+{
 	/*
 	 * SKL doesn't need us to program the AUX clock divider (Hardware will
 	 * derive the clock from CDCLK automatically). We still implement the
 	 * get_aux_clock_divider vfunc to plug-in into the existing code.
 	 */
 	return index ? 0 : 1;
+}
 static uint32_t i9xx_get_aux_send_ctl(struct intel_dp *intel_dp,
 				      bool has_aux_irq,
 				      int send_bytes,
 				      uint32_t aux_clock_divider)
+{
 	struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
 	struct drm_device *dev = intel_dig_port->base.base.dev;
 	uint32_t precharge, timeout;
 	if (IS_GEN6(dev))
 		precharge = 3;
 	else
 		precharge = 5;
 	if (IS_BROADWELL(dev) && intel_dp->aux_ch_ctl_reg == DPA_AUX_CH_CTL)
 		timeout = DP_AUX_CH_CTL_TIME_OUT_600us;
 	else
 		timeout = DP_AUX_CH_CTL_TIME_OUT_400us;
 	return DP_AUX_CH_CTL_SEND_BUSY |
 	       DP_AUX_CH_CTL_DONE |
 	       (has_aux_irq ? DP_AUX_CH_CTL_INTERRUPT : 0) |
 	       DP_AUX_CH_CTL_TIME_OUT_ERROR |
 	       timeout |
 	       DP_AUX_CH_CTL_RECEIVE_ERROR |
 	       (send_bytes << DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT) |
 	       (precharge << DP_AUX_CH_CTL_PRECHARGE_2US_SHIFT) |
 	       (aux_clock_divider << DP_AUX_CH_CTL_BIT_CLOCK_2X_SHIFT);
+}
 static uint32_t skl_get_aux_send_ctl(struct intel_dp *intel_dp,
 				      bool has_aux_irq,
 				      int send_bytes,
 				      uint32_t unused)
+{
 	return DP_AUX_CH_CTL_SEND_BUSY |
 	       DP_AUX_CH_CTL_DONE |
 	       (has_aux_irq ? DP_AUX_CH_CTL_INTERRUPT : 0) |
 	       DP_AUX_CH_CTL_TIME_OUT_ERROR |
 	       DP_AUX_CH_CTL_TIME_OUT_1600us |
 	       DP_AUX_CH_CTL_RECEIVE_ERROR |
 	       (send_bytes << DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT) |
 	       DP_AUX_CH_CTL_SYNC_PULSE_SKL(32);
+}
 static int
 intel_dp_aux_ch(struct intel_dp *intel_dp,
 		const uint8_t *send, int send_bytes,
 		uint8_t *recv, int recv_size)
+{
 	struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
 	struct drm_device *dev = intel_dig_port->base.base.dev;
 	struct drm_i915_private *dev_priv = dev->dev_private;
 	uint32_t ch_ctl = intel_dp->aux_ch_ctl_reg;
 	uint32_t ch_data = ch_ctl + 4;
 	uint32_t aux_clock_divider;
 	int i, ret, recv_bytes;
 	uint32_t status;
 	int try, clock = 0;
 	bool has_aux_irq = HAS_AUX_IRQ(dev);
 	bool vdd;
 	pps_lock(intel_dp);
 	/*
 	 * We will be called with VDD already enabled for dpcd/edid/oui reads.
 	 * In such cases we want to leave VDD enabled and it's up to upper layers
 	 * to turn it off. But for eg. i2c-dev access we need to turn it on/off
 	 * ourselves.
 	 */
 	vdd = edp_panel_vdd_on(intel_dp);
 	/* dp aux is extremely sensitive to irq latency, hence request the
 	 * lowest possible wakeup latency and so prevent the cpu from going into
 	 * deep sleep states.
 	 */
 	pm_qos_update_request(&dev_priv->pm_qos, 0);
 	intel_dp_check_edp(intel_dp);
 	/* Try to wait for any previous AUX channel activity */
 	for (try = 0; try < 3; try++) {
 		status = I915_READ_NOTRACE(ch_ctl);
 		if ((status & DP_AUX_CH_CTL_SEND_BUSY) == 0)
 			break;
 		msleep(1);
+	}
 	if (try == 3) {
 		static u32 last_status = -1;
 		const u32 status = I915_READ(ch_ctl);
 		if (status != last_status) {
 			WARN(1, "dp_aux_ch not started status 0x%08x\n",
 			     status);
 			last_status = status;
+		}
 		ret = -EBUSY;
 		goto out;
+	}
 	/* Only 5 data registers! */
 	if (WARN_ON(send_bytes > 20 || recv_size > 20)) {
 		ret = -E2BIG;
 		goto out;
+	}
 	while ((aux_clock_divider = intel_dp->get_aux_clock_divider(intel_dp, clock++))) {
 		u32 send_ctl = intel_dp->get_aux_send_ctl(intel_dp,
 							  has_aux_irq,
 							  send_bytes,
 							  aux_clock_divider);
 		/* Must try at least 3 times according to DP spec */
 		for (try = 0; try < 5; try++) {
 			/* Load the send data into the aux channel data registers */
 			for (i = 0; i < send_bytes; i += 4)
 				I915_WRITE(ch_data + i,
 					   intel_dp_pack_aux(send + i,
 							     send_bytes - i));
 			/* Send the command and wait for it to complete */
 			I915_WRITE(ch_ctl, send_ctl);
 			status = intel_dp_aux_wait_done(intel_dp, has_aux_irq);
 			/* Clear done status and any errors */
 			I915_WRITE(ch_ctl,
 				   status |
 				   DP_AUX_CH_CTL_DONE |
 				   DP_AUX_CH_CTL_TIME_OUT_ERROR |
 				   DP_AUX_CH_CTL_RECEIVE_ERROR);
 			if (status & DP_AUX_CH_CTL_TIME_OUT_ERROR)
 				continue;
 			/* DP CTS 1.2 Core Rev 1.1, 4.2.1.1 & 4.2.1.2
 			 *   400us delay required for errors and timeouts
 			 *   Timeout errors from the HW already meet this
 			 *   requirement so skip to next iteration
 			 */
 			if (status & DP_AUX_CH_CTL_RECEIVE_ERROR) {
 				usleep_range(400, 500);
 				continue;
+			}
 			if (status & DP_AUX_CH_CTL_DONE)
 				goto done;
+		}
+	}
 	if ((status & DP_AUX_CH_CTL_DONE) == 0) {
 		DRM_ERROR("dp_aux_ch not done status 0x%08x\n", status);
 		ret = -EBUSY;
 		goto out;
+	}
 done:
 	/* Check for timeout or receive error.
 	 * Timeouts occur when the sink is not connected
 	 */
 	if (status & DP_AUX_CH_CTL_RECEIVE_ERROR) {
 		DRM_ERROR("dp_aux_ch receive error status 0x%08x\n", status);
 		ret = -EIO;
 		goto out;
+	}
 	/* Timeouts occur when the device isn't connected, so they're
 	 * "normal" -- don't fill the kernel log with these */
 	if (status & DP_AUX_CH_CTL_TIME_OUT_ERROR) {
 		DRM_DEBUG_KMS("dp_aux_ch timeout status 0x%08x\n", status);
 		ret = -ETIMEDOUT;
 		goto out;
+	}
 	/* Unload any bytes sent back from the other side */
 	recv_bytes = ((status & DP_AUX_CH_CTL_MESSAGE_SIZE_MASK) >>
 		      DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT);
 	if (recv_bytes > recv_size)
 		recv_bytes = recv_size;
 	for (i = 0; i < recv_bytes; i += 4)
 		intel_dp_unpack_aux(I915_READ(ch_data + i),
 				    recv + i, recv_bytes - i);
 	ret = recv_bytes;
 out:
 	pm_qos_update_request(&dev_priv->pm_qos, PM_QOS_DEFAULT_VALUE);
 	if (vdd)
 		edp_panel_vdd_off(intel_dp, false);
 	pps_unlock(intel_dp);
 	return ret;
+}
 #define BARE_ADDRESS_SIZE	3
 #define HEADER_SIZE		(BARE_ADDRESS_SIZE + 1)
 static ssize_t
 intel_dp_aux_transfer(struct drm_dp_aux *aux, struct drm_dp_aux_msg *msg)
+{
 	struct intel_dp *intel_dp = container_of(aux, struct intel_dp, aux);
 	uint8_t txbuf[20], rxbuf[20];
 	size_t txsize, rxsize;
 	int ret;
 	txbuf[0] = (msg->request << 4) |
 		((msg->address >> 16) & 0xf);
 	txbuf[1] = (msg->address >> 8) & 0xff;
 	txbuf[2] = msg->address & 0xff;
 	txbuf[3] = msg->size - 1;
 	switch (msg->request & ~DP_AUX_I2C_MOT) {
 	case DP_AUX_NATIVE_WRITE:
 	case DP_AUX_I2C_WRITE:
 	case DP_AUX_I2C_WRITE_STATUS_UPDATE:
 		txsize = msg->size ? HEADER_SIZE + msg->size : BARE_ADDRESS_SIZE;
 		rxsize = 2; /* 0 or 1 data bytes */
 		if (WARN_ON(txsize > 20))
 			return -E2BIG;
 		memcpy(txbuf + HEADER_SIZE, msg->buffer, msg->size);
 		ret = intel_dp_aux_ch(intel_dp, txbuf, txsize, rxbuf, rxsize);
 		if (ret > 0) {
 			msg->reply = rxbuf[0] >> 4;
 			if (ret > 1) {
 				/* Number of bytes written in a short write. */
 				ret = clamp_t(int, rxbuf[1], 0, msg->size);
 			} else {
 				/* Return payload size. */
 				ret = msg->size;
+			}
+		}
 		break;
 	case DP_AUX_NATIVE_READ:
 	case DP_AUX_I2C_READ:
 		txsize = msg->size ? HEADER_SIZE : BARE_ADDRESS_SIZE;
 		rxsize = msg->size + 1;
 		if (WARN_ON(rxsize > 20))
 			return -E2BIG;
 		ret = intel_dp_aux_ch(intel_dp, txbuf, txsize, rxbuf, rxsize);
 		if (ret > 0) {
 			msg->reply = rxbuf[0] >> 4;
 			/*
 			 * Assume happy day, and copy the data. The caller is
 			 * expected to check msg->reply before touching it.
+			 *
 			 * Return payload size.
 			 */
 			ret--;
 			memcpy(msg->buffer, rxbuf + 1, ret);
+		}
 		break;
 	default:
 		ret = -EINVAL;
 		break;
+	}
 	return ret;
+}
 static void
 intel_dp_aux_init(struct intel_dp *intel_dp, struct intel_connector *connector)
+{
 	struct drm_device *dev = intel_dp_to_dev(intel_dp);
 	struct drm_i915_private *dev_priv = dev->dev_private;
 	struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
 	enum port port = intel_dig_port->port;
 	struct ddi_vbt_port_info *info = &dev_priv->vbt.ddi_port_info[port];
 	const char *name = NULL;
 	uint32_t porte_aux_ctl_reg = DPA_AUX_CH_CTL;
 	int ret;
 	/* On SKL we don't have Aux for port E so we rely on VBT to set
 	 * a proper alternate aux channel.
 	 */
 	if (IS_SKYLAKE(dev) && port == PORT_E) {
 		switch (info->alternate_aux_channel) {
 		case DP_AUX_B:
 			porte_aux_ctl_reg = DPB_AUX_CH_CTL;
 			break;
 		case DP_AUX_C:
 			porte_aux_ctl_reg = DPC_AUX_CH_CTL;
 			break;
 		case DP_AUX_D:
 			porte_aux_ctl_reg = DPD_AUX_CH_CTL;
 			break;
 		case DP_AUX_A:
 		default:
 			porte_aux_ctl_reg = DPA_AUX_CH_CTL;
+		}
+	}
 	switch (port) {
 	case PORT_A:
 		intel_dp->aux_ch_ctl_reg = DPA_AUX_CH_CTL;
 		name = "DPDDC-A";
 		break;
 	case PORT_B:
 		intel_dp->aux_ch_ctl_reg = PCH_DPB_AUX_CH_CTL;
 		name = "DPDDC-B";
 		break;
 	case PORT_C:
 		intel_dp->aux_ch_ctl_reg = PCH_DPC_AUX_CH_CTL;
 		name = "DPDDC-C";
 		break;
 	case PORT_D:
 		intel_dp->aux_ch_ctl_reg = PCH_DPD_AUX_CH_CTL;
 		name = "DPDDC-D";
 		break;
 	case PORT_E:
 		intel_dp->aux_ch_ctl_reg = porte_aux_ctl_reg;
 		name = "DPDDC-E";
 		break;
 	default:
 		BUG();
+	}
 	/*
 	 * The AUX_CTL register is usually DP_CTL + 0x10.
+	 *
 	 * On Haswell and Broadwell though:
 	 *   - Both port A DDI_BUF_CTL and DDI_AUX_CTL are on the CPU
 	 *   - Port B/C/D AUX channels are on the PCH, DDI_BUF_CTL on the CPU
+	 *
 	 * Skylake moves AUX_CTL back next to DDI_BUF_CTL, on the CPU.
 	 */
 	if (!IS_HASWELL(dev) && !IS_BROADWELL(dev) && port != PORT_E)
 		intel_dp->aux_ch_ctl_reg = intel_dp->output_reg + 0x10;
 	intel_dp->aux.name = name;
 	intel_dp->aux.dev = dev->dev;
 	intel_dp->aux.transfer = intel_dp_aux_transfer;
 #ifdef __NetBSD__
 	DRM_DEBUG_KMS("registering %s bus for %s\n", name,
 		      device_xname(connector->base.dev->dev));
 #else
 	DRM_DEBUG_KMS("registering %s bus for %s\n", name,
 		      connector->base.kdev->kobj.name);
 #endif
 	ret = drm_dp_aux_register(&intel_dp->aux);
 	if (ret < 0) {
 		DRM_ERROR("drm_dp_aux_register() for %s failed (%d)\n",
 			  name, ret);
 		return;
+	}
 #ifndef __NetBSD__
 	ret = sysfs_create_link(&connector->base.kdev->kobj,
 				&intel_dp->aux.ddc.dev.kobj,
 				intel_dp->aux.ddc.dev.kobj.name);
 	if (ret < 0) {
 		DRM_ERROR("sysfs_create_link() for %s failed (%d)\n", name, ret);
 		drm_dp_aux_unregister(&intel_dp->aux);
+	}
 #endif
+}
 static void
 intel_dp_connector_unregister(struct intel_connector *intel_connector)
+{
 #ifndef __NetBSD__
 	struct intel_dp *intel_dp = intel_attached_dp(&intel_connector->base);
 #endif
 #ifndef __NetBSD__
 	if (!intel_connector->mst_port)
 		sysfs_remove_link(&intel_connector->base.kdev->kobj,
 				  intel_dp->aux.ddc.dev.kobj.name);
 #endif
 	intel_connector_unregister(intel_connector);
+}
 static void
 skl_edp_set_pll_config(struct intel_crtc_state *pipe_config)
+{
 	u32 ctrl1;
 	memset(&pipe_config->dpll_hw_state, 0,
 	       sizeof(pipe_config->dpll_hw_state));
 	pipe_config->ddi_pll_sel = SKL_DPLL0;
 	pipe_config->dpll_hw_state.cfgcr1 = 0;
 	pipe_config->dpll_hw_state.cfgcr2 = 0;
 	ctrl1 = DPLL_CTRL1_OVERRIDE(SKL_DPLL0);
 	switch (pipe_config->port_clock / 2) {
 	case 81000:
 		ctrl1 |= DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_810,
 					      SKL_DPLL0);
 		break;
 	case 135000:
 		ctrl1 |= DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_1350,
 					      SKL_DPLL0);
 		break;
 	case 270000:
 		ctrl1 |= DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_2700,
 					      SKL_DPLL0);
 		break;
 	case 162000:
 		ctrl1 |= DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_1620,
 					      SKL_DPLL0);
 		break;
 	/* TBD: For DP link rates 2.16 GHz and 4.32 GHz, VCO is 8640 which
 	results in CDCLK change. Need to handle the change of CDCLK by
 	disabling pipes and re-enabling them */
 	case 108000:
 		ctrl1 |= DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_1080,
 					      SKL_DPLL0);
 		break;
 	case 216000:
 		ctrl1 |= DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_2160,
 					      SKL_DPLL0);
 		break;
+	}
 	pipe_config->dpll_hw_state.ctrl1 = ctrl1;
+}
 void
 hsw_dp_set_ddi_pll_sel(struct intel_crtc_state *pipe_config)
+{
 	memset(&pipe_config->dpll_hw_state, 0,
 	       sizeof(pipe_config->dpll_hw_state));
 	switch (pipe_config->port_clock / 2) {
 	case 81000:
 		pipe_config->ddi_pll_sel = PORT_CLK_SEL_LCPLL_810;
 		break;
 	case 135000:
 		pipe_config->ddi_pll_sel = PORT_CLK_SEL_LCPLL_1350;
 		break;
 	case 270000:
 		pipe_config->ddi_pll_sel = PORT_CLK_SEL_LCPLL_2700;
 		break;
+	}
+}
 static int
 intel_dp_sink_rates(struct intel_dp *intel_dp, const int **sink_rates)
+{
 	if (intel_dp->num_sink_rates) {
 		*sink_rates = intel_dp->sink_rates;
 		return intel_dp->num_sink_rates;
+	}
 	*sink_rates = default_rates;
 	return (intel_dp_max_link_bw(intel_dp) >> 3) + 1;
+}
 static bool intel_dp_source_supports_hbr2(struct drm_device *dev)
+{
 	/* WaDisableHBR2:skl */
 	if (IS_SKYLAKE(dev) && INTEL_REVID(dev) <= SKL_REVID_B0)
 		return false;
 	if ((IS_HASWELL(dev) && !IS_HSW_ULX(dev)) || IS_BROADWELL(dev) ||
 	    (INTEL_INFO(dev)->gen >= 9))
 		return true;
 	else
 		return false;
+}
 static int
 intel_dp_source_rates(struct drm_device *dev, const int **source_rates)
+{
 	int size;
 	if (IS_BROXTON(dev)) {
 		*source_rates = bxt_rates;
 		size = ARRAY_SIZE(bxt_rates);
 	} else if (IS_SKYLAKE(dev)) {
 		*source_rates = skl_rates;
 		size = ARRAY_SIZE(skl_rates);
 	} else {
 		*source_rates = default_rates;
 		size = ARRAY_SIZE(default_rates);
+	}
 	/* This depends on the fact that 5.4 is last value in the array */
 	if (!intel_dp_source_supports_hbr2(dev))
 		size--;
 	return size;
+}
 static void
 intel_dp_set_clock(struct intel_encoder *encoder,
 		   struct intel_crtc_state *pipe_config)
+{
 	struct drm_device *dev = encoder->base.dev;
 	const struct dp_link_dpll *divisor = NULL;
 	int i, count = 0;
 	if (IS_G4X(dev)) {
 		divisor = gen4_dpll;
 		count = ARRAY_SIZE(gen4_dpll);
 	} else if (HAS_PCH_SPLIT(dev)) {
 		divisor = pch_dpll;
 		count = ARRAY_SIZE(pch_dpll);
 	} else if (IS_CHERRYVIEW(dev)) {
 		divisor = chv_dpll;
 		count = ARRAY_SIZE(chv_dpll);
 	} else if (IS_VALLEYVIEW(dev)) {
 		divisor = vlv_dpll;
 		count = ARRAY_SIZE(vlv_dpll);
+	}
 	if (divisor && count) {
 		for (i = 0; i < count; i++) {
 			if (pipe_config->port_clock == divisor[i].clock) {
 				pipe_config->dpll = divisor[i].dpll;
 				pipe_config->clock_set = true;
 				break;
+			}
+		}
+	}
+}
 static int intersect_rates(const int *source_rates, int source_len,
 			   const int *sink_rates, int sink_len,
 			   int *common_rates)
+{
 	int i = 0, j = 0, k = 0;
 	while (i < source_len && j < sink_len) {
 		if (source_rates[i] == sink_rates[j]) {
 			if (WARN_ON(k >= DP_MAX_SUPPORTED_RATES))
 				return k;
 			common_rates[k] = source_rates[i];
 			++k;
 			++i;
 			++j;
 		} else if (source_rates[i] < sink_rates[j]) {
 			++i;
 		} else {
 			++j;
+		}
+	}
 	return k;
+}
 static int intel_dp_common_rates(struct intel_dp *intel_dp,
 				 int *common_rates)
+{
 	struct drm_device *dev = intel_dp_to_dev(intel_dp);
 	const int *source_rates, *sink_rates;
 	int source_len, sink_len;
 	sink_len = intel_dp_sink_rates(intel_dp, &sink_rates);
 	source_len = intel_dp_source_rates(dev, &source_rates);
 	return intersect_rates(source_rates, source_len,
 			       sink_rates, sink_len,
 			       common_rates);
+}
 static void snprintf_int_array(char *str, size_t len,
 			       const int *array, int nelem)
+{
 	int i;
 	str[0] = '\0';
 	for (i = 0; i < nelem; i++) {
 		int r = snprintf(str, len, "%s%d", i ? ", " : "", array[i]);
 		if (r >= len)
 			return;
 		str += r;
 		len -= r;
+	}
+}
 static void intel_dp_print_rates(struct intel_dp *intel_dp)
+{
 	struct drm_device *dev = intel_dp_to_dev(intel_dp);
 	const int *source_rates, *sink_rates;
 	int source_len, sink_len, common_len;
 	int common_rates[DP_MAX_SUPPORTED_RATES];
 	char str[128]; /* FIXME: too big for stack? */
 	if ((drm_debug & DRM_UT_KMS) == 0)
 		return;
 	source_len = intel_dp_source_rates(dev, &source_rates);
 	snprintf_int_array(str, sizeof(str), source_rates, source_len);
 	DRM_DEBUG_KMS("source rates: %s\n", str);
 	sink_len = intel_dp_sink_rates(intel_dp, &sink_rates);
 	snprintf_int_array(str, sizeof(str), sink_rates, sink_len);
 	DRM_DEBUG_KMS("sink rates: %s\n", str);
 	common_len = intel_dp_common_rates(intel_dp, common_rates);
 	snprintf_int_array(str, sizeof(str), common_rates, common_len);
 	DRM_DEBUG_KMS("common rates: %s\n", str);
+}
 static int rate_to_index(int find, const int *rates)
+{
 	int i = 0;
 	for (i = 0; i < DP_MAX_SUPPORTED_RATES; ++i)
 		if (find == rates[i])
 			break;
 	return i;
+}
 int
 intel_dp_max_link_rate(struct intel_dp *intel_dp)
+{
 	int rates[DP_MAX_SUPPORTED_RATES] = {};
 	int len;
 	len = intel_dp_common_rates(intel_dp, rates);
 	if (WARN_ON(len <= 0))
 		return 162000;
 	return rates[rate_to_index(0, rates) - 1];
+}
 int intel_dp_rate_select(struct intel_dp *intel_dp, int rate)
+{
 	return rate_to_index(rate, intel_dp->sink_rates);
+}
 static void intel_dp_compute_rate(struct intel_dp *intel_dp, int port_clock,
 				  uint8_t *link_bw, uint8_t *rate_select)
+{
 	if (intel_dp->num_sink_rates) {
 		*link_bw = 0;
 		*rate_select =
 			intel_dp_rate_select(intel_dp, port_clock);
 	} else {
 		*link_bw = drm_dp_link_rate_to_bw_code(port_clock);
 		*rate_select = 0;
+	}
+}
 bool
 intel_dp_compute_config(struct intel_encoder *encoder,
 			struct intel_crtc_state *pipe_config)
+{
 	struct drm_device *dev = encoder->base.dev;
 	struct drm_i915_private *dev_priv = dev->dev_private;
 	struct drm_display_mode *adjusted_mode = &pipe_config->base.adjusted_mode;
 	struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
 	enum port port = dp_to_dig_port(intel_dp)->port;
 	struct intel_crtc *intel_crtc = to_intel_crtc(pipe_config->base.crtc);
 	struct intel_connector *intel_connector = intel_dp->attached_connector;
 	int lane_count, clock;
 	int min_lane_count = 1;
 	int max_lane_count = intel_dp_max_lane_count(intel_dp);
 	/* Conveniently, the link BW constants become indices with a shift...*/
 	int min_clock = 0;
 	int max_clock;
 	int bpp, mode_rate;
 	int link_avail, link_clock;
 	int common_rates[DP_MAX_SUPPORTED_RATES] = {};
 	int common_len;
 	uint8_t link_bw, rate_select;
 	common_len = intel_dp_common_rates(intel_dp, common_rates);
 	/* No common link rates between source and sink */
 	WARN_ON(common_len <= 0);
 	max_clock = common_len - 1;
 	if (HAS_PCH_SPLIT(dev) && !HAS_DDI(dev) && port != PORT_A)
 		pipe_config->has_pch_encoder = true;
 	pipe_config->has_dp_encoder = true;
 	pipe_config->has_drrs = false;
 	pipe_config->has_audio = intel_dp->has_audio && port != PORT_A;
 	if (is_edp(intel_dp) && intel_connector->panel.fixed_mode) {
 		intel_fixed_panel_mode(intel_connector->panel.fixed_mode,
 				       adjusted_mode);
 		if (INTEL_INFO(dev)->gen >= 9) {
 			int ret;
 			ret = skl_update_scaler_crtc(pipe_config);
 			if (ret)
 				return ret;
+		}
 		if (!HAS_PCH_SPLIT(dev))
 			intel_gmch_panel_fitting(intel_crtc, pipe_config,
 						 intel_connector->panel.fitting_mode);
 		else
 			intel_pch_panel_fitting(intel_crtc, pipe_config,
 						intel_connector->panel.fitting_mode);
+	}
 	if (adjusted_mode->flags & DRM_MODE_FLAG_DBLCLK)
 		return false;
 	DRM_DEBUG_KMS("DP link computation with max lane count %i "
 		      "max bw %d pixel clock %iKHz\n",
 		      max_lane_count, common_rates[max_clock],
 		      adjusted_mode->crtc_clock);
 	/* Walk through all bpp values. Luckily they're all nicely spaced with 2
 	 * bpc in between. */
 	bpp = pipe_config->pipe_bpp;
 	if (is_edp(intel_dp)) {
 		/* Get bpp from vbt only for panels that dont have bpp in edid */
 		if (intel_connector->base.display_info.bpc == 0 &&
 			(dev_priv->vbt.edp_bpp && dev_priv->vbt.edp_bpp < bpp)) {
 			DRM_DEBUG_KMS("clamping bpp for eDP panel to BIOS-provided %i\n",
 				      dev_priv->vbt.edp_bpp);
 			bpp = dev_priv->vbt.edp_bpp;
+		}
 		/*
 		 * Use the maximum clock and number of lanes the eDP panel
 		 * advertizes being capable of. The panels are generally
 		 * designed to support only a single clock and lane
 		 * configuration, and typically these values correspond to the
 		 * native resolution of the panel.
 		 */
 		min_lane_count = max_lane_count;
 		min_clock = max_clock;
+	}
 	for (; bpp >= 6*3; bpp -= 2*3) {
 		mode_rate = intel_dp_link_required(adjusted_mode->crtc_clock,
 						   bpp);
 		for (clock = min_clock; clock <= max_clock; clock++) {
 			for (lane_count = min_lane_count;
 				lane_count <= max_lane_count;
 				lane_count <<= 1) {
 				link_clock = common_rates[clock];
 				link_avail = intel_dp_max_data_rate(link_clock,
 								    lane_count);
 				if (mode_rate <= link_avail) {
 					goto found;
+				}
+			}
+		}
+	}
 	return false;
 found:
 	if (intel_dp->color_range_auto) {
 		/*
 		 * See:
 		 * CEA-861-E - 5.1 Default Encoding Parameters
 		 * VESA DisplayPort Ver.1.2a - 5.1.1.1 Video Colorimetry
 		 */
 		pipe_config->limited_color_range =
 			bpp != 18 && drm_match_cea_mode(adjusted_mode) > 1;
 	} else {
 		pipe_config->limited_color_range =
 			intel_dp->limited_color_range;
+	}
 	pipe_config->lane_count = lane_count;
 	pipe_config->pipe_bpp = bpp;
 	pipe_config->port_clock = common_rates[clock];
 	intel_dp_compute_rate(intel_dp, pipe_config->port_clock,
 			      &link_bw, &rate_select);
 	DRM_DEBUG_KMS("DP link bw %02x rate select %02x lane count %d clock %d bpp %d\n",
 		      link_bw, rate_select, pipe_config->lane_count,
 		      pipe_config->port_clock, bpp);
 	DRM_DEBUG_KMS("DP link bw required %i available %i\n",
 		      mode_rate, link_avail);
 	intel_link_compute_m_n(bpp, lane_count,
 			       adjusted_mode->crtc_clock,
 			       pipe_config->port_clock,
 			       &pipe_config->dp_m_n);
 	if (intel_connector->panel.downclock_mode != NULL &&
 		dev_priv->drrs.type == SEAMLESS_DRRS_SUPPORT) {
 			pipe_config->has_drrs = true;
 			intel_link_compute_m_n(bpp, lane_count,
 				intel_connector->panel.downclock_mode->clock,
 				pipe_config->port_clock,
 				&pipe_config->dp_m2_n2);
+	}
 	if (IS_SKYLAKE(dev) && is_edp(intel_dp))
 		skl_edp_set_pll_config(pipe_config);
 	else if (IS_BROXTON(dev))
 		/* handled in ddi */;
 	else if (IS_HASWELL(dev) || IS_BROADWELL(dev))
 		hsw_dp_set_ddi_pll_sel(pipe_config);
 	else
 		intel_dp_set_clock(encoder, pipe_config);
 	return true;
+}
 static void ironlake_set_pll_cpu_edp(struct intel_dp *intel_dp)
+{
 	struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
 	struct intel_crtc *crtc = to_intel_crtc(dig_port->base.base.crtc);
 	struct drm_device *dev = crtc->base.dev;
 	struct drm_i915_private *dev_priv = dev->dev_private;
 	u32 dpa_ctl;
 	DRM_DEBUG_KMS("eDP PLL enable for clock %d\n",
 		      crtc->config->port_clock);
 	dpa_ctl = I915_READ(DP_A);
 	dpa_ctl &= ~DP_PLL_FREQ_MASK;
 	if (crtc->config->port_clock == 162000) {
 		/* For a long time we've carried around a ILK-DevA w/a for the
 		 * 160MHz clock. If we're really unlucky, it's still required.
 		 */
 		DRM_DEBUG_KMS("160MHz cpu eDP clock, might need ilk devA w/a\n");
 		dpa_ctl |= DP_PLL_FREQ_160MHZ;
 		intel_dp->DP |= DP_PLL_FREQ_160MHZ;
 	} else {
 		dpa_ctl |= DP_PLL_FREQ_270MHZ;
 		intel_dp->DP |= DP_PLL_FREQ_270MHZ;
+	}
 	I915_WRITE(DP_A, dpa_ctl);
 	POSTING_READ(DP_A);

 @@ -1,46 +1,48 @@
-/*	$NetBSD: drm_irq_netbsd.h,v 1.4 2015/01/01 01:15:42 mrg Exp $	*/
+/*	$NetBSD: drm_irq_netbsd.h,v 1.5 2018/08/27 06:16:01 riastradh Exp $	*/
 /*-
  * Copyright (c) 2013 The NetBSD Foundation, Inc.
  * All rights reserved.
+ *
  * This code is derived from software contributed to The NetBSD Foundation
  * by Taylor R. Campbell.
+ *
  * Redistribution and use in source and binary forms, with or without
  * modification, are permitted provided that the following conditions
  * are met:
  * 1. Redistributions of source code must retain the above copyright
  *    notice, this list of conditions and the following disclaimer.
  * 2. Redistributions in binary form must reproduce the above copyright
  *    notice, this list of conditions and the following disclaimer in the
  *    documentation and/or other materials provided with the distribution.
+ *
  * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
  * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
  * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
  * PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
  * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
  * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
  * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
  * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
  * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
  * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
  * POSSIBILITY OF SUCH DAMAGE.
  */
 #ifndef _DRM_DRM_IRQ_NETBSD_H_
 #define _DRM_DRM_IRQ_NETBSD_H_
 typedef int irqreturn_t;
-#define	IRQ_NONE	0
+enum irqreturn {
-#define	IRQ_HANDLED	1
+	IRQ_NONE = 0x0,
 	IRQ_HANDLED = 0x1,
 };
 #define	DRM_IRQ_ARGS	void *arg
 #define	IRQF_SHARED	0	/* XXX */
 #define	IPL_DRM		IPL_TTY	/* XXX */
 #endif  /* _DRM_DRM_IRQ_NETBSD_H_ */