 @@ -1,40 +1,40 @@
-/*	$NetBSD: amdgpu_cik.c,v 1.1 2018/08/27 14:22:31 riastradh Exp $	*/
+/*	$NetBSD: amdgpu_cik.c,v 1.2 2018/08/27 14:23:31 riastradh Exp $	*/
 /*
  * Copyright 2012 Advanced Micro Devices, Inc.
+ *
  * Permission is hereby granted, free of charge, to any person obtaining a
  * copy of this software and associated documentation files (the "Software"),
  * to deal in the Software without restriction, including without limitation
  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
  * and/or sell copies of the Software, and to permit persons to whom the
  * Software is furnished to do so, subject to the following conditions:
+ *
  * The above copyright notice and this permission notice shall be included in
  * all copies or substantial portions of the Software.
+ *
  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  * OTHER DEALINGS IN THE SOFTWARE.
+ *
  * Authors: Alex Deucher
  */
 #include <sys/cdefs.h>
-__KERNEL_RCSID(0, "$NetBSD: amdgpu_cik.c,v 1.1 2018/08/27 14:22:31 riastradh Exp $");
+__KERNEL_RCSID(0, "$NetBSD: amdgpu_cik.c,v 1.2 2018/08/27 14:23:31 riastradh Exp $");
 #include <linux/firmware.h>
 #include <linux/slab.h>
 #include <linux/module.h>
 #include "drmP.h"
 #include "amdgpu.h"
 #include "amdgpu_atombios.h"
 #include "amdgpu_ih.h"
 #include "amdgpu_uvd.h"
 #include "amdgpu_vce.h"
 #include "cikd.h"
 #include "atom.h"
 @@ -1556,26 +1556,27 @@ static int cik_set_vce_clocks(struct amd
 	for (i = 0; i < 100; i++) {
 		if (RREG32_SMC(ixCG_ECLK_STATUS) & CG_ECLK_STATUS__ECLK_STATUS_MASK)
 			break;
 		mdelay(10);
+	}
 	if (i == 100)
 		return -ETIMEDOUT;
 	return 0;
+}
 static void cik_pcie_gen3_enable(struct amdgpu_device *adev)
+{
 #ifndef __NetBSD__		/* XXX amdgpu pcie */
 	struct pci_dev *root = adev->pdev->bus->self;
 	int bridge_pos, gpu_pos;
 	u32 speed_cntl, mask, current_data_rate;
 	int ret, i;
 	u16 tmp16;
 	if (pci_is_root_bus(adev->pdev->bus))
 		return;
 	if (amdgpu_pcie_gen2 == 0)
 		return;
 	if (adev->flags & AMD_IS_APU)
 @@ -1716,26 +1717,27 @@ static void cik_pcie_gen3_enable(struct
 		tmp16 |= 1; /* gen1 */
 	pci_write_config_word(adev->pdev, gpu_pos + PCI_EXP_LNKCTL2, tmp16);
 	speed_cntl = RREG32_PCIE(ixPCIE_LC_SPEED_CNTL);
 	speed_cntl |= PCIE_LC_SPEED_CNTL__LC_INITIATE_LINK_SPEED_CHANGE_MASK;
 	WREG32_PCIE(ixPCIE_LC_SPEED_CNTL, speed_cntl);
 	for (i = 0; i < adev->usec_timeout; i++) {
 		speed_cntl = RREG32_PCIE(ixPCIE_LC_SPEED_CNTL);
 		if ((speed_cntl & PCIE_LC_SPEED_CNTL__LC_INITIATE_LINK_SPEED_CHANGE_MASK) == 0)
 			break;
 		udelay(1);
+	}
 #endif
+}
 static void cik_program_aspm(struct amdgpu_device *adev)
+{
 	u32 data, orig;
 	bool disable_l0s = false, disable_l1 = false, disable_plloff_in_l1 = false;
 	bool disable_clkreq = false;
 	if (amdgpu_aspm == 0)
 		return;
 	/* XXX double check APUs */
 	if (adev->flags & AMD_IS_APU)
 @@ -1803,33 +1805,37 @@ static void cik_program_aspm(struct amdg
 				PB1_PIF_PWRDOWN_1__PLL_POWER_STATE_IN_TXS2_1_MASK);
 			data |= (7 << PB1_PIF_PWRDOWN_1__PLL_POWER_STATE_IN_OFF_1__SHIFT) |
 				(7 << PB1_PIF_PWRDOWN_1__PLL_POWER_STATE_IN_TXS2_1__SHIFT);
 			if (orig != data)
 				WREG32_PCIE(ixPB1_PIF_PWRDOWN_1, data);
 			orig = data = RREG32_PCIE(ixPCIE_LC_LINK_WIDTH_CNTL);
 			data &= ~PCIE_LC_LINK_WIDTH_CNTL__LC_DYN_LANES_PWR_STATE_MASK;
 			data |= ~(3 << PCIE_LC_LINK_WIDTH_CNTL__LC_DYN_LANES_PWR_STATE__SHIFT);
 			if (orig != data)
 				WREG32_PCIE(ixPCIE_LC_LINK_WIDTH_CNTL, data);
 			if (!disable_clkreq) {
 #ifdef __NetBSD__		/* XXX amdgpu pcie */
 				clk_req_support = false;
 #else
 				struct pci_dev *root = adev->pdev->bus->self;
 				u32 lnkcap;
 				clk_req_support = false;
 				pcie_capability_read_dword(root, PCI_EXP_LNKCAP, &lnkcap);
 				if (lnkcap & PCI_EXP_LNKCAP_CLKPM)
 					clk_req_support = true;
 #endif
 			} else {
 				clk_req_support = false;
+			}
 			if (clk_req_support) {
 				orig = data = RREG32_PCIE(ixPCIE_LC_CNTL2);
 				data |= PCIE_LC_CNTL2__LC_ALLOW_PDWN_IN_L1_MASK |
 					PCIE_LC_CNTL2__LC_ALLOW_PDWN_IN_L23_MASK;
 				if (orig != data)
 					WREG32_PCIE(ixPCIE_LC_CNTL2, data);
 				orig = data = RREG32_SMC(ixTHM_CLK_CNTL);
 				data &= ~(THM_CLK_CNTL__CMON_CLK_SEL_MASK |