| @@ -3,15 +3,18 @@ | | | @@ -3,15 +3,18 @@ |
| 3 | #include "../../../external/gpl2/dts/dist/arch/arm/boot/dts/socfpga_cyclone5_de0_sockit.dts" | | 3 | #include "../../../external/gpl2/dts/dist/arch/arm/boot/dts/socfpga_cyclone5_de0_sockit.dts" |
| 4 | | | 4 | |
| 5 | / { | | 5 | / { |
| 6 | soc { | | 6 | soc { |
| 7 | gtimer@fffec200 { | | 7 | gtimer@fffec200 { |
| 8 | compatible = "arm,cortex-a9-global-timer"; | | 8 | compatible = "arm,cortex-a9-global-timer"; |
| 9 | reg = <0xfffec200 0x20>; | | 9 | reg = <0xfffec200 0x20>; |
| 10 | clocks = <&mpu_periph_clk>; | | 10 | clocks = <&mpu_periph_clk>; |
| 11 | interrupts = <1 11 0x301>; | | 11 | interrupts = <1 11 0x301>; |
| 12 | }; | | 12 | }; |
| 13 | usb@ffb40000 { | | 13 | usb@ffb40000 { |
| 14 | dr_mode = "host"; | | 14 | dr_mode = "host"; |
| 15 | }; | | 15 | }; |
| | | 16 | watchdog@ffd02000 { |
| | | 17 | resets = <&rst L4WD0_RESET>; |
| | | 18 | }; |
| 16 | }; | | 19 | }; |
| 17 | }; | | 20 | }; |