 @@ -1,14 +1,14 @@
-/* $NetBSD: gicv3.c,v 1.6 2018/11/10 01:56:28 jmcneill Exp $ */
+/* $NetBSD: gicv3.c,v 1.7 2018/11/10 11:46:31 jmcneill Exp $ */
 /*-
  * Copyright (c) 2018 Jared McNeill <jmcneill@invisible.ca>
  * All rights reserved.
+ *
  * Redistribution and use in source and binary forms, with or without
  * modification, are permitted provided that the following conditions
  * are met:
  * 1. Redistributions of source code must retain the above copyright
  *    notice, this list of conditions and the following disclaimer.
  * 2. Redistributions in binary form must reproduce the above copyright
  *    notice, this list of conditions and the following disclaimer in the
  *    documentation and/or other materials provided with the distribution.
 @@ -21,27 +21,27 @@
  * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
  * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
  * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
  * SUCH DAMAGE.
  */
 #include "opt_multiprocessor.h"
 #define	_INTR_PRIVATE
 #include <sys/cdefs.h>
-__KERNEL_RCSID(0, "$NetBSD: gicv3.c,v 1.6 2018/11/10 01:56:28 jmcneill Exp $");
+__KERNEL_RCSID(0, "$NetBSD: gicv3.c,v 1.7 2018/11/10 11:46:31 jmcneill Exp $");
 #include <sys/param.h>
 #include <sys/kernel.h>
 #include <sys/bus.h>
 #include <sys/device.h>
 #include <sys/intr.h>
 #include <sys/systm.h>
 #include <sys/cpu.h>
 #include <arm/locore.h>
 #include <arm/armreg.h>
 #include <arm/cortex/gicv3.h>
 @@ -546,27 +546,27 @@ static void
 gicv3_lpi_establish_irq(struct pic_softc *pic, struct intrsource *is)
+{
 	struct gicv3_softc * const sc = LPITOSOFTC(pic);
 	sc->sc_lpiconf.base[is->is_irq] = IPL_TO_PRIORITY(is->is_ipl) | GIC_LPICONF_Res1;
 	bus_dmamap_sync(sc->sc_dmat, sc->sc_lpiconf.map, is->is_irq, 1, BUS_DMASYNC_PREWRITE);
+}
 static void
 gicv3_lpi_cpu_init(struct pic_softc *pic, struct cpu_info *ci)
+{
 	struct gicv3_softc * const sc = LPITOSOFTC(pic);
-	struct gicv3_cpu_init *cpu_init;
+	struct gicv3_lpi_callback *cb;
 	uint32_t ctlr;
 	/* If physical LPIs are not supported on this redistributor, just return. */
 	const uint64_t typer = gicr_read_8(sc, ci->ci_gic_redist, GICR_TYPER);
 	if ((typer & GICR_TYPER_PLPIS) == 0)
 		return;
 	/* Interrupt target address for this CPU, used by ITS when GITS_TYPER.PTA == 0 */
 	sc->sc_processor_id[cpu_index(ci)] = __SHIFTOUT(typer, GICR_TYPER_Processor_Number);
 	/* Disable LPIs before making changes */
 	ctlr = gicr_read_4(sc, ci->ci_gic_redist, GICR_CTLR);
 	ctlr &= ~GICR_CTLR_Enable_LPIs;
 @@ -584,36 +584,66 @@ gicv3_lpi_cpu_init(struct pic_softc *pic
 	const uint64_t pendbase = sc->sc_lpipend[cpu_index(ci)].segs[0].ds_addr |
 	    __SHIFTIN(GICR_Shareability_NS, GICR_PENDBASER_Shareability) |
 	    __SHIFTIN(GICR_Cache_NORMAL_NC, GICR_PENDBASER_InnerCache) |
 	    GICR_PENDBASER_PTZ;
 	gicr_write_8(sc, ci->ci_gic_redist, GICR_PENDBASER, pendbase);
 	/* Enable LPIs */
 	ctlr = gicr_read_4(sc, ci->ci_gic_redist, GICR_CTLR);
 	ctlr |= GICR_CTLR_Enable_LPIs;
 	gicr_write_4(sc, ci->ci_gic_redist, GICR_CTLR, ctlr);
 	arm_dsb();
 	/* Setup ITS if present */
-	LIST_FOREACH(cpu_init, &sc->sc_cpu_init, list)
+	LIST_FOREACH(cb, &sc->sc_lpi_callbacks, list)
-		cpu_init->func(cpu_init->arg, ci);
+		cb->cpu_init(cb->priv, ci);
+}
 #ifdef MULTIPROCESSOR
 static void
 gicv3_lpi_get_affinity(struct pic_softc *pic, size_t irq, kcpuset_t *affinity)
+{
 	struct gicv3_softc * const sc = LPITOSOFTC(pic);
 	struct gicv3_lpi_callback *cb;
 	LIST_FOREACH(cb, &sc->sc_lpi_callbacks, list)
 		cb->get_affinity(cb->priv, irq, affinity);
+}
 static int
 gicv3_lpi_set_affinity(struct pic_softc *pic, size_t irq, const kcpuset_t *affinity)
+{
 	struct gicv3_softc * const sc = LPITOSOFTC(pic);
 	struct gicv3_lpi_callback *cb;
 	int error = EINVAL;
 	LIST_FOREACH(cb, &sc->sc_lpi_callbacks, list) {
 		error = cb->set_affinity(cb->priv, irq, affinity);
 		if (error)
 			return error;
+	}
 	return error;
+}
 #endif
 static const struct pic_ops gicv3_lpiops = {
 	.pic_unblock_irqs = gicv3_lpi_unblock_irqs,
 	.pic_block_irqs = gicv3_lpi_block_irqs,
 	.pic_establish_irq = gicv3_lpi_establish_irq,
 #ifdef MULTIPROCESSOR
 	.pic_cpu_init = gicv3_lpi_cpu_init,
 	.pic_get_affinity = gicv3_lpi_get_affinity,
 	.pic_set_affinity = gicv3_lpi_set_affinity,
 #endif
 };
 void
 gicv3_dma_alloc(struct gicv3_softc *sc, struct gicv3_dma *dma, bus_size_t len, bus_size_t align)
+{
 	int nsegs, error;
 	dma->len = len;
 	error = bus_dmamem_alloc(sc->sc_dmat, dma->len, align, 0, dma->segs, 1, &nsegs, BUS_DMA_WAITOK);
 	if (error)
 		panic("bus_dmamem_alloc failed: %d", error);
 	error = bus_dmamem_map(sc->sc_dmat, dma->segs, nsegs, len, (void **)&dma->base, BUS_DMA_WAITOK);
 @@ -685,27 +715,27 @@ gicv3_irq_handler(void *frame)
 	if (ci->ci_cpl != oldipl)
 		pic_set_priority(ci, oldipl);
+}
 int
 gicv3_init(struct gicv3_softc *sc)
+{
 	const uint32_t gicd_typer = gicd_read_4(sc, GICD_TYPER);
 	int n;
 	KASSERT(CPU_IS_PRIMARY(curcpu()));
-	LIST_INIT(&sc->sc_cpu_init);
+	LIST_INIT(&sc->sc_lpi_callbacks);
 	for (n = 0; n < MAXCPUS; n++)
 		sc->sc_irouter[n] = UINT64_MAX;
 	sc->sc_pic.pic_ops = &gicv3_picops;
 	sc->sc_pic.pic_maxsources = GICD_TYPER_LINES(gicd_typer);
 	snprintf(sc->sc_pic.pic_name, sizeof(sc->sc_pic.pic_name), "gicv3");
 #ifdef MULTIPROCESSOR
 	sc->sc_pic.pic_cpus = kcpuset_running;
 #endif
 	pic_add(&sc->sc_pic, 0);
 	if ((gicd_typer & GICD_TYPER_LPIS) != 0) {

 @@ -1,14 +1,14 @@
-/* $NetBSD: gicv3.h,v 1.3 2018/11/10 01:56:28 jmcneill Exp $ */
+/* $NetBSD: gicv3.h,v 1.4 2018/11/10 11:46:31 jmcneill Exp $ */
 /*-
  * Copyright (c) 2018 Jared McNeill <jmcneill@invisible.ca>
  * All rights reserved.
+ *
  * Redistribution and use in source and binary forms, with or without
  * modification, are permitted provided that the following conditions
  * are met:
  * 1. Redistributions of source code must retain the above copyright
  *    notice, this list of conditions and the following disclaimer.
  * 2. Redistributions in binary form must reproduce the above copyright
  *    notice, this list of conditions and the following disclaimer in the
  *    documentation and/or other materials provided with the distribution.
 @@ -28,53 +28,56 @@
 #ifndef _ARM_CORTEX_GICV3_H
 #define _ARM_CORTEX_GICV3_H
 #include <sys/intr.h>
 struct gicv3_dma {
 	bus_dma_segment_t	segs[1];
 	bus_dmamap_t		map;
 	uint8_t			*base;
 	bus_size_t		len;
 };
-struct gicv3_cpu_init {
+struct gicv3_lpi_callback {
-	void			(*func)(void *, struct cpu_info *ci);
+	void			(*cpu_init)(void *, struct cpu_info *);
-	void			*arg;
+	void			(*get_affinity)(void *, size_t, kcpuset_t *);
 	int			(*set_affinity)(void *, size_t, const kcpuset_t *);
-	LIST_ENTRY(gicv3_cpu_init) list;
+	void			*priv;
 	LIST_ENTRY(gicv3_lpi_callback) list;
 };
 struct gicv3_softc {
 	struct pic_softc	sc_pic;		/* SGI/PPI/SGIs */
 	struct pic_softc	sc_lpi;		/* LPIs */
 	device_t		sc_dev;
 	bus_space_tag_t		sc_bst;
 	bus_dma_tag_t		sc_dmat;
 	bus_space_handle_t	sc_bsh_d;	/* GICD */
 	bus_space_handle_t	*sc_bsh_r;	/* GICR */
 	u_int			sc_bsh_r_count;
 	uint32_t		sc_enabled_sgippi;
 	uint64_t		sc_irouter[MAXCPUS];
 	/* LPI configuration table */
 	struct gicv3_dma	sc_lpiconf;
 	/* LPI pending tables */
 	struct gicv3_dma	sc_lpipend[MAXCPUS];
 	/* Unique identifier for PEs */
 	u_int			sc_processor_id[MAXCPUS];
-	/* CPU init callbacks */
+	/* Callbacks */
-	LIST_HEAD(, gicv3_cpu_init) sc_cpu_init;
+	LIST_HEAD(, gicv3_lpi_callback) sc_lpi_callbacks;
 };
 int	gicv3_init(struct gicv3_softc *);
 void	gicv3_dma_alloc(struct gicv3_softc *, struct gicv3_dma *, bus_size_t, bus_size_t);
 void	gicv3_irq_handler(void *);
 #endif /* _ARM_CORTEX_GICV3_H */

 @@ -1,14 +1,14 @@
-/* $NetBSD: gicv3_its.c,v 1.1 2018/11/09 23:36:24 jmcneill Exp $ */
+/* $NetBSD: gicv3_its.c,v 1.2 2018/11/10 11:46:31 jmcneill Exp $ */
 /*-
  * Copyright (c) 2018 The NetBSD Foundation, Inc.
  * All rights reserved.
+ *
  * This code is derived from software contributed to The NetBSD Foundation
  * by Jared McNeill <jmcneill@invisible.ca>.
+ *
  * Redistribution and use in source and binary forms, with or without
  * modification, are permitted provided that the following conditions
  * are met:
  * 1. Redistributions of source code must retain the above copyright
  *    notice, this list of conditions and the following disclaimer.
 @@ -22,27 +22,27 @@
  * PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
  * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
  * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
  * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
  * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
  * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
  * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
  * POSSIBILITY OF SUCH DAMAGE.
  */
 #define _INTR_PRIVATE
 #include <sys/cdefs.h>
-__KERNEL_RCSID(0, "$NetBSD: gicv3_its.c,v 1.1 2018/11/09 23:36:24 jmcneill Exp $");
+__KERNEL_RCSID(0, "$NetBSD: gicv3_its.c,v 1.2 2018/11/10 11:46:31 jmcneill Exp $");
 #include <sys/param.h>
 #include <sys/kmem.h>
 #include <sys/bus.h>
 #include <sys/cpu.h>
 #include <uvm/uvm.h>
 #include <dev/pci/pcireg.h>
 #include <dev/pci/pcivar.h>
 #include <arm/pic/picvar.h>
 #include <arm/cortex/gicv3_its.h>
 @@ -146,26 +146,43 @@ gits_command_mapi(struct gicv3_its *its,
 	/*
 	 * Map the event defined by EventID and DeviceID into an ITT entry with ICID and pINTID = EventID
 	 */
 	memset(&cmd, 0, sizeof(cmd));
 	cmd.dw[0] = GITS_CMD_MAPI | ((uint64_t)deviceid << 32);
 	cmd.dw[1] = eventid;
 	cmd.dw[2] = icid;
 	gits_command(its, &cmd);
+}
 static inline void
 gits_command_movi(struct gicv3_its *its, uint32_t deviceid, uint32_t eventid, uint16_t icid)
+{
 	struct gicv3_its_command cmd;
 	/*
 	 * Update the ICID field in the ITT entry for the event defined by DeviceID and
 	 * EventID.
 	 */
 	memset(&cmd, 0, sizeof(cmd));
 	cmd.dw[0] = GITS_CMD_MOVI | ((uint64_t)deviceid << 32);
 	cmd.dw[1] = eventid;
 	cmd.dw[2] = icid;
 	gits_command(its, &cmd);
+}
 static inline void
 gits_command_inv(struct gicv3_its *its, uint32_t deviceid, uint32_t eventid)
+{
 	struct gicv3_its_command cmd;
 	/*
 	 * Ensure any caching in the redistributors associated with the specified
 	 * EventID is consistent with the LPI configuration tables.
 	 */
 	memset(&cmd, 0, sizeof(cmd));
 	cmd.dw[0] = GITS_CMD_INV | ((uint64_t)deviceid << 32);
 	cmd.dw[1] = eventid;
 	gits_command(its, &cmd);
 @@ -369,28 +386,28 @@ gicv3_its_msix_disable(struct gicv3_its
 	if (!pci_get_capability(pc, tag, PCI_CAP_MSIX, &off, NULL))
 		panic("gicv3_its_msix_disable: device is not MSI-X-capable");
 	ctl = pci_conf_read(pc, tag, off + PCI_MSIX_CTL);
 	ctl &= ~PCI_MSIX_CTL_ENABLE;
 	pci_conf_write(pc, tag, off + PCI_MSIX_CTL, ctl);
+}
 static pci_intr_handle_t *
 gicv3_its_msi_alloc(struct arm_pci_msi *msi, int *count,
     const struct pci_attach_args *pa, bool exact)
+{
 	struct gicv3_its * const its = msi->msi_priv;
 	struct cpu_info * const ci = cpu_lookup(0);
 	struct gicv3_its_device *dev;
 	struct cpu_info *ci = curcpu();	/* XXX */
 	pci_intr_handle_t *vectors;
 	int n, off;
 	if (!pci_get_capability(pa->pa_pc, pa->pa_tag, PCI_CAP_MSI, &off, NULL))
 		return NULL;
 	const uint64_t typer = gits_read_8(its, GITS_TYPER);
 	const u_int id_bits = __SHIFTOUT(typer, GITS_TYPER_ID_bits) + 1;
 	if (*count == 0 || *count > (1 << id_bits))
 		return NULL;
 	const uint32_t devid = gicv3_its_devid(pa->pa_pc, pa->pa_tag);
 @@ -402,43 +419,48 @@ gicv3_its_msi_alloc(struct arm_pci_msi *
 	gits_wait(its);
 	vectors = kmem_alloc(sizeof(*vectors) * *count, KM_SLEEP);
 	for (n = 0; n < *count; n++) {
 		const int lpi = gicv3_its_msi_alloc_lpi(its, pa);
 		vectors[n] = ARM_PCI_INTR_MSI |
 		    __SHIFTIN(lpi, ARM_PCI_INTR_IRQ) |
 		    __SHIFTIN(n, ARM_PCI_INTR_MSI_VEC) |
 		    __SHIFTIN(msi->msi_id, ARM_PCI_INTR_FRAME);
 		gicv3_its_msi_enable(its, lpi);
 		/*
 		 * Record target PE
 		 */
 		its->its_targets[lpi - its->its_pic->pic_irqbase] = ci;
 		/*
 		 * Map event
 		 */
 		gits_command_mapi(its, devid, lpi, cpu_index(ci));
 		gits_command_sync(its, its->its_rdbase[cpu_index(ci)]);
+	}
 	gits_wait(its);
 	return vectors;
+}
 static pci_intr_handle_t *
 gicv3_its_msix_alloc(struct arm_pci_msi *msi, u_int *table_indexes, int *count,
     const struct pci_attach_args *pa, bool exact)
+{
 	struct gicv3_its * const its = msi->msi_priv;
 	struct cpu_info *ci = cpu_lookup(0);
 	struct gicv3_its_device *dev;
 	struct cpu_info *ci = curcpu();	/* XXX */
 	pci_intr_handle_t *vectors;
 	bus_space_tag_t bst;
 	bus_space_handle_t bsh;
 	bus_size_t bsz;
 	uint32_t table_offset, table_size;
 	int n, off, bar, error;
 	pcireg_t tbl;
 	if (!pci_get_capability(pa->pa_pc, pa->pa_tag, PCI_CAP_MSIX, &off, NULL))
 		return NULL;
 	const uint64_t typer = gits_read_8(its, GITS_TYPER);
 	const u_int id_bits = __SHIFTOUT(typer, GITS_TYPER_ID_bits) + 1;
 @@ -469,26 +491,31 @@ gicv3_its_msix_alloc(struct arm_pci_msi
 	vectors = kmem_alloc(sizeof(*vectors) * *count, KM_SLEEP);
 	for (n = 0; n < *count; n++) {
 		const int lpi = gicv3_its_msi_alloc_lpi(its, pa);
 		const int msix_vec = table_indexes ? table_indexes[n] : n;
 		vectors[msix_vec] = ARM_PCI_INTR_MSIX |
 		    __SHIFTIN(lpi, ARM_PCI_INTR_IRQ) |
 		    __SHIFTIN(msix_vec, ARM_PCI_INTR_MSI_VEC) |
 		    __SHIFTIN(msi->msi_id, ARM_PCI_INTR_FRAME);
 		gicv3_its_msix_enable(its, lpi, msix_vec, bst, bsh);
 		/*
 		 * Record target PE
 		 */
 		its->its_targets[lpi - its->its_pic->pic_irqbase] = ci;
 		/*
 		 * Map event
 		 */
 		gits_command_mapi(its, devid, lpi, cpu_index(ci));
 		gits_command_sync(its, its->its_rdbase[cpu_index(ci)]);
+	}
 	gits_wait(its);
 	bus_space_unmap(bst, bsh, bsz);
 	return vectors;
+}
 static void *
 @@ -521,26 +548,27 @@ gicv3_its_msi_intr_release(struct arm_pc
     int count)
+{
 	struct gicv3_its * const its = msi->msi_priv;
 	int n;
 	for (n = 0; n < count; n++) {
 		const int lpi = __SHIFTOUT(pih[n], ARM_PCI_INTR_IRQ);
 		KASSERT(lpi >= its->its_pic->pic_irqbase);
 		if (pih[n] & ARM_PCI_INTR_MSIX)
 			gicv3_its_msix_disable(its, lpi);
 		if (pih[n] & ARM_PCI_INTR_MSI)
 			gicv3_its_msi_disable(its, lpi);
 		gicv3_its_msi_free_lpi(its, lpi);
 		its->its_targets[lpi - its->its_pic->pic_irqbase] = NULL;
 		struct intrsource * const is =
 		    its->its_pic->pic_sources[lpi - its->its_pic->pic_irqbase];
 		if (is != NULL)
 			pic_disestablish_source(is);
+	}
+}
 static void
 gicv3_its_command_init(struct gicv3_softc *sc, struct gicv3_its *its)
+{
 	uint64_t cbaser;
 	gicv3_dma_alloc(sc, &its->its_cmd, GITS_COMMANDS_SIZE, GITS_COMMANDS_ALIGN);
 @@ -648,51 +676,92 @@ gicv3_its_cpu_init(void *priv, struct cp
 	} else {
 		rdbase = (uint64_t)sc->sc_processor_id[cpu_index(ci)] << 16;
+	}
 	its->its_rdbase[cpu_index(ci)] = rdbase;
 	/*
 	 * Map collection ID of this CPU's index to this CPU's redistributor.
 	 */
 	gits_command_mapc(its, cpu_index(ci), rdbase, true);
 	gits_command_invall(its, cpu_index(ci));
 	gits_wait(its);
+}
 static void
 gicv3_its_get_affinity(void *priv, size_t irq, kcpuset_t *affinity)
+{
 	struct gicv3_its * const its = priv;
 	struct cpu_info *ci;
 	kcpuset_zero(affinity);
 	ci = its->its_targets[irq - its->its_pic->pic_irqbase];
 	if (ci)
 		kcpuset_set(affinity, cpu_index(ci));
+}
 static int
 gicv3_its_set_affinity(void *priv, size_t irq, const kcpuset_t *affinity)
+{
 	struct gicv3_its * const its = priv;
 	const struct pci_attach_args *pa;
 	struct cpu_info *ci;
 	const int set = kcpuset_countset(affinity);
 	if (set != 1)
 		return EINVAL;
 	pa = its->its_pa[irq - its->its_pic->pic_irqbase];
 	if (pa == NULL)
 		return EINVAL;
 	ci = cpu_lookup(kcpuset_ffs(affinity));
 	const uint32_t devid = gicv3_its_devid(pa->pa_pc, pa->pa_tag);
 	gits_command_movi(its, devid, devid, cpu_index(ci));
 	gits_command_sync(its, its->its_rdbase[cpu_index(ci)]);
 	its->its_targets[irq - its->its_pic->pic_irqbase] = ci;
 	return 0;
+}
 int
 gicv3_its_init(struct gicv3_softc *sc, bus_space_handle_t bsh,
     uint64_t its_base, uint32_t its_id)
+{
 	struct gicv3_its *its;
 	struct arm_pci_msi *msi;
 	const uint64_t typer = bus_space_read_8(sc->sc_bst, bsh, GITS_TYPER);
 	if ((typer & GITS_TYPER_Physical) == 0)
 		return ENXIO;
 	its = kmem_alloc(sizeof(*its), KM_SLEEP);
 	its->its_id = its_id;
 	its->its_bst = sc->sc_bst;
 	its->its_bsh = bsh;
 	its->its_dmat = sc->sc_dmat;
 	its->its_base = its_base;
 	its->its_pic = &sc->sc_lpi;
 	KASSERT(its->its_pic->pic_maxsources > 0);
 	its->its_pa = kmem_zalloc(sizeof(struct pci_attach_args *) * its->its_pic->pic_maxsources, KM_SLEEP);
 	its->its_targets = kmem_zalloc(sizeof(struct cpu_info *) * its->its_pic->pic_maxsources, KM_SLEEP);
 	its->its_gic = sc;
-	its->its_init.func = gicv3_its_cpu_init;
+	its->its_cb.cpu_init = gicv3_its_cpu_init;
-	its->its_init.arg = its;
+	its->its_cb.get_affinity = gicv3_its_get_affinity;
 	its->its_cb.set_affinity = gicv3_its_set_affinity;
 	its->its_cb.priv = its;
 	LIST_INIT(&its->its_devices);
-	LIST_INSERT_HEAD(&sc->sc_cpu_init, &its->its_init, list);
+	LIST_INSERT_HEAD(&sc->sc_lpi_callbacks, &its->its_cb, list);
 	gicv3_its_command_init(sc, its);
 	gicv3_its_table_init(sc, its);
 	gicv3_its_enable(sc, its);
 	gicv3_its_cpu_init(its, curcpu());
 	msi = &its->its_msi;
 	msi->msi_dev = sc->sc_dev;
 	msi->msi_priv = its;
 	msi->msi_alloc = gicv3_its_msi_alloc;
 	msi->msix_alloc = gicv3_its_msix_alloc;

 @@ -1,14 +1,14 @@
-/* $NetBSD: gicv3_its.h,v 1.1 2018/11/09 23:36:24 jmcneill Exp $ */
+/* $NetBSD: gicv3_its.h,v 1.2 2018/11/10 11:46:31 jmcneill Exp $ */
 /*-
  * Copyright (c) 2018 The NetBSD Foundation, Inc.
  * All rights reserved.
+ *
  * This code is derived from software contributed to The NetBSD Foundation
  * by Jared McNeill <jmcneill@invisible.ca>.
+ *
  * Redistribution and use in source and binary forms, with or without
  * modification, are permitted provided that the following conditions
  * are met:
  * 1. Redistributions of source code must retain the above copyright
  *    notice, this list of conditions and the following disclaimer.
 @@ -42,29 +42,30 @@ struct gicv3_its_device {
 	LIST_ENTRY(gicv3_its_device) dev_list;
 };
 struct gicv3_its {
 	bus_space_tag_t		its_bst;
 	bus_space_handle_t	its_bsh;
 	bus_dma_tag_t		its_dmat;
 	uint32_t		its_id;
 	uint64_t		its_base;
 	uint64_t		its_rdbase[MAXCPUS];
 	struct gicv3_softc	*its_gic;
-	struct gicv3_cpu_init	its_init;
+	struct gicv3_lpi_callback its_cb;
 	struct pic_softc	*its_pic;
 	const struct pci_attach_args **its_pa;
 	struct cpu_info		**its_targets;
 	LIST_HEAD(, gicv3_its_device) its_devices;
 	struct gicv3_dma	its_cmd;		/* Command queue */
 	struct gicv3_dma	its_tab[8];		/* ITS tables */
 	struct arm_pci_msi	its_msi;
 };
 int	gicv3_its_init(struct gicv3_softc *, bus_space_handle_t, uint64_t, uint32_t);
 #endif /* !_ARM_CORTEX_GICV3_ITS_H */