 @@ -1,766 +1,801 @@
-/*	$NetBSD: cpufunc.S,v 1.33 2018/07/21 06:09:13 maxv Exp $	*/
+/*	$NetBSD: cpufunc.S,v 1.34 2018/12/22 21:27:22 cherry Exp $	*/
 /*
  * Copyright (c) 1998, 2007, 2008 The NetBSD Foundation, Inc.
  * All rights reserved.
+ *
  * This code is derived from software contributed to The NetBSD Foundation
  * by Charles M. Hannum, and by Andrew Doran.
+ *
  * Redistribution and use in source and binary forms, with or without
  * modification, are permitted provided that the following conditions
  * are met:
  * 1. Redistributions of source code must retain the above copyright
  *    notice, this list of conditions and the following disclaimer.
  * 2. Redistributions in binary form must reproduce the above copyright
  *    notice, this list of conditions and the following disclaimer in the
  *    documentation and/or other materials provided with the distribution.
+ *
  * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
  * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
  * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
  * PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
  * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
  * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
  * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
  * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
  * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
  * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
  * POSSIBILITY OF SUCH DAMAGE.
  */
 /*
  * Functions to provide access to i386-specific instructions.
  */
 #include <sys/errno.h>
 #include <machine/asm.h>
 #include <machine/frameasm.h>
 #include <machine/specialreg.h>
 #include <machine/segments.h>
 #include "opt_xen.h"
 #include "assym.h"
 /* Small and slow, so align less. */
 #undef _ALIGN_TEXT
 #define	_ALIGN_TEXT	.align 8
 ENTRY(x86_lfence)
 	lfence
 	ret
 END(x86_lfence)
 ENTRY(x86_sfence)
 	sfence
 	ret
 END(x86_sfence)
 ENTRY(x86_mfence)
 	mfence
 	ret
 END(x86_mfence)
 /*
  * These functions below should always be accessed via the corresponding wrapper
  * function names defined in x86/include/cpufunc.h and exported as WEAK_ALIAS()
+ *
  * We use this rather roundabout method so that a runtime wrapper function may
  * be made available for PVHVM, which could override both native and PV aliases
  * and decide which to invoke at run time.
  */
 WEAK_ALIAS(invlpg, amd64_invlpg)
 WEAK_ALIAS(lidt, amd64_lidt)
 WEAK_ALIAS(lldt, amd64_lldt)
 WEAK_ALIAS(ltr, amd64_ltr)
 WEAK_ALIAS(lcr0, amd64_lcr0)
 WEAK_ALIAS(rcr0, amd64_rcr0)
 WEAK_ALIAS(rcr2, amd64_rcr2)
 WEAK_ALIAS(lcr2, amd64_lcr2)
 WEAK_ALIAS(rcr3, amd64_rcr3)
 WEAK_ALIAS(lcr3, amd64_lcr3)
 WEAK_ALIAS(tlbflush, amd64_tlbflush)
 WEAK_ALIAS(tlbflushg, amd64_tlbflushg)
 WEAK_ALIAS(rdr0, amd64_rdr0)
 WEAK_ALIAS(ldr0, amd64_ldr0)
 WEAK_ALIAS(rdr1, amd64_rdr1)
 WEAK_ALIAS(ldr1, amd64_ldr1)
 WEAK_ALIAS(rdr2, amd64_rdr2)
 WEAK_ALIAS(ldr2, amd64_ldr2)
 WEAK_ALIAS(rdr3, amd64_rdr3)
 WEAK_ALIAS(ldr3, amd64_ldr3)
 WEAK_ALIAS(rdr6, amd64_rdr6)
 WEAK_ALIAS(ldr6, amd64_ldr6)
 WEAK_ALIAS(rdr7, amd64_rdr7)
 WEAK_ALIAS(ldr7, amd64_ldr7)
 WEAK_ALIAS(wbinvd, amd64_wbinvd)
 #ifndef XEN
-ENTRY(invlpg)
+ENTRY(amd64_invlpg)
 	invlpg	(%rdi)
 	ret
-END(invlpg)
+END(amd64_invlpg)
-ENTRY(lidt)
+ENTRY(amd64_lidt)
 	lidt	(%rdi)
 	ret
-END(lidt)
+END(amd64_lidt)
-ENTRY(lldt)
+ENTRY(amd64_lldt)
 	cmpl	%edi, CPUVAR(CURLDT)
 	jne	1f
 	ret
 :
 	movl	%edi, CPUVAR(CURLDT)
 	lldt	%di
 	ret
-END(lldt)
+END(amd64_lldt)
-ENTRY(ltr)
+ENTRY(amd64_ltr)
 	ltr	%di
 	ret
-END(ltr)
+END(amd64_ltr)
-ENTRY(lcr0)
+ENTRY(amd64_lcr0)
 	movq	%rdi, %cr0
 	ret
-END(lcr0)
+END(amd64_lcr0)
-ENTRY(rcr0)
+ENTRY(amd64_rcr0)
 	movq	%cr0, %rax
 	ret
-END(rcr0)
+END(amd64_rcr0)
-ENTRY(lcr2)
+ENTRY(amd64_lcr2)
 	movq	%rdi, %cr2
 	ret
-END(lcr2)
+END(amd64_lcr2)
-ENTRY(rcr2)
+ENTRY(amd64_rcr2)
 	movq	%cr2, %rax
 	ret
-END(rcr2)
+END(amd64_rcr2)
-ENTRY(lcr3)
+ENTRY(amd64_lcr3)
 	movq	%rdi, %cr3
 	ret
-END(lcr3)
+END(amd64_lcr3)
-ENTRY(rcr3)
+ENTRY(amd64_rcr3)
 	movq	%cr3, %rax
 	ret
-END(rcr3)
+END(amd64_rcr3)
 #endif
 ENTRY(lcr4)
 	movq	%rdi, %cr4
 	ret
 END(lcr4)
 ENTRY(rcr4)
 	movq	%cr4, %rax
 	ret
 END(rcr4)
 ENTRY(lcr8)
 	movq	%rdi, %cr8
 	ret
 END(lcr8)
 ENTRY(rcr8)
 	movq	%cr8, %rax
 	ret
 END(rcr8)
 /*
  * Big hammer: flush all TLB entries, including ones from PTE's
  * with the G bit set.  This should only be necessary if TLB
  * shootdown falls far behind.
+ *
  * Intel Architecture Software Developer's Manual, Volume 3,
  *	System Programming, section 9.10, "Invalidating the
  * Translation Lookaside Buffers (TLBS)":
  * "The following operations invalidate all TLB entries, irrespective
  * of the setting of the G flag:
  * ...
  * "(P6 family processors only): Writing to control register CR4 to
  * modify the PSE, PGE, or PAE flag."
+ *
  * (the alternatives not quoted above are not an option here.)
+ *
  * If PGE is not in use, we reload CR3.
  */
 #ifndef XEN
-ENTRY(tlbflushg)
+ENTRY(amd64_tlbflushg)
 	movq	%cr4, %rax
 	testq	$CR4_PGE, %rax
 	jz	1f
 	movq	%rax, %rdx
 	andq	$~CR4_PGE, %rdx
 	movq	%rdx, %cr4
 	movq	%rax, %cr4
 	ret
-END(tlbflushg)
+END(amd64_tlbflushg)
-ENTRY(tlbflush)
+ENTRY(amd64_tlbflush)
 :
 	movq	%cr3, %rax
 	movq	%rax, %cr3
 	ret
-END(tlbflush)
+END(amd64_tlbflush)
-ENTRY(ldr0)
+ENTRY(amd64_ldr0)
 	movq	%rdi, %dr0
 	ret
-END(ldr0)
+END(amd64_ldr0)
-ENTRY(rdr0)
+ENTRY(amd64_rdr0)
 	movq	%dr0, %rax
 	ret
-END(rdr0)
+END(amd64_rdr0)
-ENTRY(ldr1)
+ENTRY(amd64_ldr1)
 	movq	%rdi, %dr1
 	ret
-END(ldr1)
+END(amd64_ldr1)
-ENTRY(rdr1)
+ENTRY(amd64_rdr1)
 	movq	%dr1, %rax
 	ret
-END(rdr1)
+END(amd64_rdr1)
-ENTRY(ldr2)
+ENTRY(amd64_ldr2)
 	movq	%rdi, %dr2
 	ret
-END(ldr2)
+END(amd64_ldr2)
-ENTRY(rdr2)
+ENTRY(amd64_rdr2)
 	movq	%dr2, %rax
 	ret
-END(rdr2)
+END(amd64_rdr2)
-ENTRY(ldr3)
+ENTRY(amd64_ldr3)
 	movq	%rdi, %dr3
 	ret
-END(ldr3)
+END(amd64_ldr3)
-ENTRY(rdr3)
+ENTRY(amd64_rdr3)
 	movq	%dr3, %rax
 	ret
-END(rdr3)
+END(amd64_rdr3)
-ENTRY(ldr6)
+ENTRY(amd64_ldr6)
 	movq	%rdi, %dr6
 	ret
-END(ldr6)
+END(amd64_ldr6)
-ENTRY(rdr6)
+ENTRY(amd64_rdr6)
 	movq	%dr6, %rax
 	ret
-END(rdr6)
+END(amd64_rdr6)
-ENTRY(ldr7)
+ENTRY(amd64_ldr7)
 	movq	%rdi, %dr7
 	ret
-END(ldr7)
+END(amd64_ldr7)
-ENTRY(rdr7)
+ENTRY(amd64_rdr7)
 	movq	%dr7, %rax
 	ret
-END(rdr7)
+END(amd64_rdr7)
 ENTRY(x86_disable_intr)
 	cli
 	ret
 END(x86_disable_intr)
 ENTRY(x86_enable_intr)
 	sti
 	ret
 END(x86_enable_intr)
 ENTRY(x86_read_flags)
 	pushfq
 	popq	%rax
 	ret
 END(x86_read_flags)
 STRONG_ALIAS(x86_read_psl,x86_read_flags)
 ENTRY(x86_write_flags)
 	pushq	%rdi
 	popfq
 	ret
 END(x86_write_flags)
 STRONG_ALIAS(x86_write_psl,x86_write_flags)
 #endif /* XEN */
 ENTRY(rdmsr)
 	movq	%rdi, %rcx
 	xorq	%rax, %rax
 	rdmsr
 	shlq	$32, %rdx
 	orq	%rdx, %rax
 	ret
 END(rdmsr)
 ENTRY(wrmsr)
 	movq	%rdi, %rcx
 	movq	%rsi, %rax
 	movq	%rsi, %rdx
 	shrq	$32, %rdx
 	wrmsr
 	ret
 END(wrmsr)
 ENTRY(rdmsr_locked)
 	movq	%rdi, %rcx
 	xorq	%rax, %rax
 	movl	$OPTERON_MSR_PASSCODE, %edi
 	rdmsr
 	shlq	$32, %rdx
 	orq	%rdx, %rax
 	ret
 END(rdmsr_locked)
 ENTRY(wrmsr_locked)
 	movq	%rdi, %rcx
 	movq	%rsi, %rax
 	movq	%rsi, %rdx
 	shrq	$32, %rdx
 	movl	$OPTERON_MSR_PASSCODE, %edi
 	wrmsr
 	ret
 END(wrmsr_locked)
 /*
  * Support for reading MSRs in the safe manner (returns EFAULT on fault)
  */
 /* int rdmsr_safe(u_int msr, uint64_t *data) */
 ENTRY(rdmsr_safe)
 	movq	CPUVAR(CURLWP), %r8
 	movq	L_PCB(%r8), %r8
 	movq	$_C_LABEL(msr_onfault), PCB_ONFAULT(%r8)
 	movl	%edi, %ecx /* u_int msr */
 	rdmsr			/* Read MSR pointed by %ecx. Returns
 				   hi byte in edx, lo in %eax */
 	salq	$32, %rdx	/* sign-shift %rdx left */
 	movl	%eax, %eax	/* zero-extend %eax -> %rax */
 	orq	%rdx, %rax
 	movq	%rax, (%rsi)  /* *data */
 	xorq	%rax, %rax    /* "no error" */
 	movq	%rax, PCB_ONFAULT(%r8)
 	ret
 END(rdmsr_safe)
 ENTRY(rdxcr)
 	movq	%rdi, %rcx
 	xgetbv
 	shlq	$32, %rdx
 	orq	%rdx, %rax
 	ret
 END(rdxcr)
 ENTRY(wrxcr)
 	movq	%rdi, %rcx
 	movq	%rsi, %rax
 	movq	%rsi, %rdx
 	shrq	$32, %rdx
 	xsetbv
 	ret
 END(wrxcr)
 /*
  * MSR operations fault handler
  */
 ENTRY(msr_onfault)
 	movq	CPUVAR(CURLWP), %r8
 	movq	L_PCB(%r8), %r8
 	movq	$0, PCB_ONFAULT(%r8)
 	movl	$EFAULT, %eax
 	ret
 END(msr_onfault)
 #ifndef XEN
 ENTRY(wbinvd)
 	wbinvd
 	ret
 END(wbinvd)
 #endif
 ENTRY(cpu_counter)
 	xorq	%rax, %rax
 	rdtsc
 	shlq	$32, %rdx
 	orq	%rdx, %rax
 	addq	CPUVAR(CC_SKEW), %rax
 	ret
 END(cpu_counter)
 ENTRY(cpu_counter32)
 	rdtsc
 	addl	CPUVAR(CC_SKEW), %eax
 	ret
 END(cpu_counter32)
 ENTRY(rdpmc)
 	movq	%rdi, %rcx
 	xorq	%rax, %rax
 	rdpmc
 	shlq	$32, %rdx
 	orq	%rdx, %rax
 	ret
 END(rdpmc)
 ENTRY(rdtsc)
 	xorq	%rax,%rax
 	rdtsc
 	shlq	$32,%rdx
 	orq	%rdx,%rax
 	ret
 END(rdtsc)
 ENTRY(breakpoint)
 	pushq	%rbp
 	movq	%rsp, %rbp
 	int	$0x03		/* paranoid, not 'int3' */
 	leave
 	ret
 END(breakpoint)
 ENTRY(x86_curcpu)
 	movq	%gs:(CPU_INFO_SELF), %rax
 	ret
 END(x86_curcpu)
 ENTRY(x86_curlwp)
 	movq	%gs:(CPU_INFO_CURLWP), %rax
 	ret
 END(x86_curlwp)
 ENTRY(cpu_set_curpri)
 	movl	%edi, %gs:(CPU_INFO_CURPRIORITY)
 	ret
 END(cpu_set_curpri)
 ENTRY(__byte_swap_u32_variable)
 	movl	%edi, %eax
 	bswapl	%eax
 	ret
 END(__byte_swap_u32_variable)
 ENTRY(__byte_swap_u16_variable)
 	movl	%edi, %eax
 	xchgb	%al, %ah
 	ret
 END(__byte_swap_u16_variable)
 /*
  * void lgdt(struct region_descriptor *rdp);
+ *
  * Load a new GDT pointer (and do any necessary cleanup).
  * XXX It's somewhat questionable whether reloading all the segment registers
  * is necessary, since the actual descriptor data is not changed except by
  * process creation and exit, both of which clean up via task switches.
  */
 #ifndef XEN
 ENTRY(lgdt)
 	/* Reload the descriptor table. */
 	movq	%rdi,%rax
 	lgdt	(%rax)
 	/* Flush the prefetch q. */
 	jmp	1f
 	nop
 :	jmp	_C_LABEL(lgdt_finish)
 END(lgdt)
 #endif
 /*
  * void lgdt_finish(void);
  * Reload segments after a GDT change
  */
 ENTRY(lgdt_finish)
 	movl	$GSEL(GDATA_SEL, SEL_KPL),%eax
 	movl	%eax,%ds
 	movl	%eax,%es
 	movl	%eax,%ss
 	jmp	_C_LABEL(x86_flush)
 END(lgdt_finish)
 /*
  * void x86_flush()
+ *
  * Flush instruction pipelines by doing an intersegment (far) return.
  */
 ENTRY(x86_flush)
 	popq	%rax
 	pushq	$GSEL(GCODE_SEL, SEL_KPL)
 	pushq	%rax
 	lretq
 END(x86_flush)
 /* Waits - set up stack frame. */
 ENTRY(x86_hlt)
 	pushq	%rbp
 	movq	%rsp, %rbp
 	hlt
 	leave
 	ret
 END(x86_hlt)
 /* Waits - set up stack frame. */
 ENTRY(x86_stihlt)
 	pushq	%rbp
 	movq	%rsp, %rbp
 	sti
 	hlt
 	leave
 	ret
 END(x86_stihlt)
 ENTRY(x86_monitor)
 	movq	%rdi, %rax
 	movq	%rsi, %rcx
 	monitor	%rax, %rcx, %rdx
 	ret
 END(x86_monitor)
 /* Waits - set up stack frame. */
 ENTRY(x86_mwait)
 	pushq	%rbp
 	movq	%rsp, %rbp
 	movq	%rdi, %rax
 	movq	%rsi, %rcx
 	mwait	%rax, %rcx
 	leave
 	ret
 END(x86_mwait)
 ENTRY(x86_pause)
 	pause
 	ret
 END(x86_pause)
 ENTRY(x86_cpuid2)
 	movq	%rbx, %r8
 	movq	%rdi, %rax
 	movq	%rsi, %rcx
 	movq	%rdx, %rsi
 	cpuid
 	movl	%eax, 0(%rsi)
 	movl	%ebx, 4(%rsi)
 	movl	%ecx, 8(%rsi)
 	movl	%edx, 12(%rsi)
 	movq	%r8, %rbx
 	ret
 END(x86_cpuid2)
 ENTRY(x86_getss)
 	movl	%ss, %eax
 	ret
 END(x86_getss)
 ENTRY(fldcw)
 	fldcw	(%rdi)
 	ret
 END(fldcw)
 ENTRY(fnclex)
 	fnclex
 	ret
 END(fnclex)
 ENTRY(fninit)
 	fninit
 	ret
 END(fninit)
 ENTRY(fnsave)
 	fnsave	(%rdi)
 	ret
 END(fnsave)
 ENTRY(fnstcw)
 	fnstcw	(%rdi)
 	ret
 END(fnstcw)
 ENTRY(fngetsw)
 	fnstsw	%ax
 	ret
 END(fngetsw)
 ENTRY(fnstsw)
 	fnstsw	(%rdi)
 	ret
 END(fnstsw)
 ENTRY(fp_divide_by_0)
 	fldz
 	fld1
 	fdiv	%st, %st(1)
 	fwait
 	ret
 END(fp_divide_by_0)
 ENTRY(frstor)
 	frstor	(%rdi)
 	ret
 END(frstor)
 ENTRY(fwait)
 	fwait
 	ret
 END(fwait)
 ENTRY(clts)
 	clts
 	ret
 END(clts)
 ENTRY(stts)
 	movq	%cr0, %rax
 	orq	$CR0_TS, %rax
 	movq	%rax, %cr0
 	ret
 END(stts)
 ENTRY(fxsave)
 	fxsave	(%rdi)
 	ret
 END(fxsave)
 ENTRY(fxrstor)
 	fxrstor	(%rdi)
 	ret
 END(fxrstor)
 ENTRY(fldummy)
 	ffree	%st(7)
 	fldz
 	ret
 END(fldummy)
 ENTRY(xsave)
 	movq	%rsi, %rax
 	movq	%rsi, %rdx
 	shrq	$32, %rdx
 	xsave	(%rdi)
 	ret
 END(xsave)
 ENTRY(xsaveopt)
 	movq	%rsi, %rax
 	movq	%rsi, %rdx
 	shrq	$32, %rdx
 	xsaveopt	(%rdi)
 	ret
 END(xsaveopt)
 ENTRY(xrstor)
 	movq	%rsi, %rax
 	movq	%rsi, %rdx
 	shrq	$32, %rdx
 	xrstor	(%rdi)
 	ret
 END(xrstor)
 ENTRY(x86_stmxcsr)
 	stmxcsr	(%rdi)
 	ret
 END(x86_stmxcsr)
 ENTRY(x86_ldmxcsr)
 	ldmxcsr	(%rdi)
 	ret
 END(x86_ldmxcsr)
 ENTRY(inb)
 	movq	%rdi, %rdx
 	xorq	%rax, %rax
 	inb	%dx, %al
 	ret
 END(inb)
 ENTRY(insb)
 	movl	%edx, %ecx
 	movl	%edi, %edx
 	movq	%rsi, %rdi
 	rep
 	insb
 	ret
 END(insb)
 ENTRY(inw)
 	movq	%rdi, %rdx
 	xorq	%rax, %rax
 	inw	%dx, %ax
 	ret
 END(inw)
 ENTRY(insw)
 	movl	%edx, %ecx
 	movl	%edi, %edx
 	movq	%rsi, %rdi
 	rep
 	insw
 	ret
 END(insw)
 ENTRY(inl)
 	movq	%rdi, %rdx
 	xorq	%rax, %rax
 	inl	%dx, %eax
 	ret
 END(inl)
 ENTRY(insl)
 	movl	%edx, %ecx
 	movl	%edi, %edx
 	movq	%rsi, %rdi
 	rep
 	insl
 	ret
 END(insl)
 ENTRY(outb)
 	movq	%rdi, %rdx
 	movq	%rsi, %rax
 	outb	%al, %dx
 	ret
 END(outb)
 ENTRY(outsb)
 	movl	%edx, %ecx
 	movl	%edi, %edx
 	rep
 	outsb
 	ret
 END(outsb)
 ENTRY(outw)
 	movq	%rdi, %rdx
 	movq	%rsi, %rax
 	outw	%ax, %dx
 	ret
 END(outw)
 ENTRY(outsw)
 	movl	%edx, %ecx
 	movl	%edi, %edx
 	rep
 	outsw
 	ret
 END(outsw)
 ENTRY(outl)
 	movq	%rdi, %rdx
 	movq	%rsi, %rax
 	outl	%eax, %dx
 	ret
 END(outl)
 ENTRY(outsl)
 	movl	%edx, %ecx
 	movl	%edi, %edx
 	rep
 	outsl
 	ret
 END(outsl)
 ENTRY(setds)
 	movw	%di, %ds
 	ret
 END(setds)
 ENTRY(setes)
 	movw	%di, %es
 	ret
 END(setes)
 ENTRY(setfs)
 	movw	%di, %fs
 	ret
 END(setfs)
 #ifndef XEN
 ENTRY(setusergs)
 	CLI(ax)
 	swapgs
 	movw	%di, %gs
 	swapgs
 	STI(ax)
 	ret
 END(setusergs)
 #endif

 @@ -1,563 +1,575 @@
-/*	$NetBSD: cpufunc.S,v 1.25 2018/10/18 04:11:14 cherry Exp $	*/
+/*	$NetBSD: cpufunc.S,v 1.26 2018/12/22 21:27:22 cherry Exp $	*/
 /*-
  * Copyright (c) 1998, 2007 The NetBSD Foundation, Inc.
  * All rights reserved.
+ *
  * This code is derived from software contributed to The NetBSD Foundation
  * by Charles M. Hannum, and by Andrew Doran.
+ *
  * Redistribution and use in source and binary forms, with or without
  * modification, are permitted provided that the following conditions
  * are met:
  * 1. Redistributions of source code must retain the above copyright
  *    notice, this list of conditions and the following disclaimer.
  * 2. Redistributions in binary form must reproduce the above copyright
  *    notice, this list of conditions and the following disclaimer in the
  *    documentation and/or other materials provided with the distribution.
+ *
  * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
  * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
  * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
  * PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
  * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
  * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
  * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
  * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
  * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
  * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
  * POSSIBILITY OF SUCH DAMAGE.
  */
 /*
  * Functions to provide access to i386-specific instructions.
+ *
  * These are shared with NetBSD/xen.
  */
 #include <sys/errno.h>
 #include <machine/asm.h>
-__KERNEL_RCSID(0, "$NetBSD: cpufunc.S,v 1.25 2018/10/18 04:11:14 cherry Exp $");
+__KERNEL_RCSID(0, "$NetBSD: cpufunc.S,v 1.26 2018/12/22 21:27:22 cherry Exp $");
 #include "opt_xen.h"
 #include <machine/specialreg.h>
 #include <machine/segments.h>
 #include "assym.h"
 /*
  * These functions below should always be accessed via the corresponding wrapper
  * function names defined in x86/include/cpufunc.h and exported as WEAK_ALIAS()
+ *
  * We use this rather roundabout method so that a runtime wrapper function may
  * be made available for PVHVM, which could override both native and PV aliases
  * and decide which to invoke at run time.
  */
 WEAK_ALIAS(lidt, i386_lidt)
 WEAK_ALIAS(rcr3, i386_rcr3)
 ENTRY(x86_lfence)
 	lock
 	addl	$0, -4(%esp)
 	ret
 END(x86_lfence)
 ENTRY(x86_sfence)
 	lock
 	addl	$0, -4(%esp)
 	ret
 END(x86_sfence)
 ENTRY(x86_mfence)
 	lock
 	addl	$0, -4(%esp)
 	ret
 END(x86_mfence)
 #ifndef XEN
-ENTRY(lidt)
+ENTRY(i386_lidt)
 	movl	4(%esp), %eax
 	lidt	(%eax)
 	ret
-END(lidt)
+END(i386_lidt)
 #endif /* XEN */
-ENTRY(rcr3)
+ENTRY(i386_rcr3)
 	movl	%cr3, %eax
 	ret
-END(rcr3)
+END(i386_rcr3)
 ENTRY(lcr4)
 	movl	4(%esp), %eax
 	movl	%eax, %cr4
 	ret
 END(lcr4)
 ENTRY(rcr4)
 	movl	%cr4, %eax
 	ret
 END(rcr4)
 ENTRY(x86_read_flags)
 	pushfl
 	popl	%eax
 	ret
 END(x86_read_flags)
 ENTRY(x86_write_flags)
 	movl	4(%esp), %eax
 	pushl	%eax
 	popfl
 	ret
 END(x86_write_flags)
 #ifndef XEN
 STRONG_ALIAS(x86_write_psl,x86_write_flags)
 STRONG_ALIAS(x86_read_psl,x86_read_flags)
 #endif	/* XEN */
 ENTRY(rdmsr)
 	movl	4(%esp), %ecx
 	rdmsr
 	ret
 END(rdmsr)
 ENTRY(wrmsr)
 	movl	4(%esp), %ecx
 	movl	8(%esp), %eax
 	movl	12(%esp), %edx
 	wrmsr
 	ret
 END(wrmsr)
 ENTRY(rdmsr_locked)
 	movl	4(%esp), %ecx
 	pushl	%edi
 	movl	$OPTERON_MSR_PASSCODE, %edi
 	rdmsr
 	popl	%edi
 	ret
 END(rdmsr_locked)
 ENTRY(wrmsr_locked)
 	movl	4(%esp), %ecx
 	movl	8(%esp), %eax
 	movl	12(%esp), %edx
 	pushl	%edi
 	movl	$OPTERON_MSR_PASSCODE, %edi
 	wrmsr
 	popl	%edi
 	ret
 END(wrmsr_locked)
 /*
  * Support for reading MSRs in the safe manner (returns EFAULT on fault)
  */
 /* int rdmsr_safe(u_int msr, uint64_t *data) */
 ENTRY(rdmsr_safe)
 	movl	CPUVAR(CURLWP), %ecx
 	movl	L_PCB(%ecx), %ecx
 	movl	$_C_LABEL(msr_onfault), PCB_ONFAULT(%ecx)
 	movl	4(%esp), %ecx /* u_int msr */
 	rdmsr
 	movl	8(%esp), %ecx /* *data */
 	movl	%eax, (%ecx)  /* low-order bits */
 	movl	%edx, 4(%ecx) /* high-order bits */
 	xorl	%eax, %eax    /* "no error" */
 	movl	CPUVAR(CURLWP), %ecx
 	movl	L_PCB(%ecx), %ecx
 	movl	%eax, PCB_ONFAULT(%ecx)
 	ret
 END(rdmsr_safe)
 /* uint64_t rdxcr(uint32_t) */
 ENTRY(rdxcr)
 	movl	4(%esp), %ecx	/* extended control reg number */
 	xgetbv			/* Read to %edx:%eax */
 	ret
 END(rdxcr)
 /* void wrxcr(uint32_t, uint64_t) */
 ENTRY(wrxcr)
 	movl	4(%esp), %ecx	/* extended control reg number */
 	movl	8(%esp), %eax	/* feature mask bits */
 	movl	12(%esp), %edx
 	xsetbv
 	ret
 END(wrxcr)
 /*
  * MSR operations fault handler
  */
 ENTRY(msr_onfault)
 	movl	CPUVAR(CURLWP), %ecx
 	movl	L_PCB(%ecx), %ecx
 	movl	$0, PCB_ONFAULT(%ecx)
 	movl	$EFAULT, %eax
 	ret
 END(msr_onfault)
 ENTRY(cpu_counter)
 	rdtsc
 	addl	CPUVAR(CC_SKEW), %eax
 	adcl	CPUVAR(CC_SKEW+4), %edx
 	ret
 END(cpu_counter)
 ENTRY(cpu_counter32)
 	rdtsc
 	addl	CPUVAR(CC_SKEW), %eax
 	ret
 END(cpu_counter32)
 ENTRY(rdpmc)
 	movl	4(%esp), %ecx
 	rdpmc
 	ret
 END(rdpmc)
 ENTRY(rdtsc)
 	rdtsc
 	ret
 END(rdtsc)
 ENTRY(breakpoint)
 	pushl	%ebp
 	movl	%esp, %ebp
 	int	$0x03		/* paranoid, not 'int3' */
 	popl	%ebp
 	ret
 END(breakpoint)
 ENTRY(x86_curcpu)
 	movl	%fs:(CPU_INFO_SELF), %eax
 	ret
 END(x86_curcpu)
 ENTRY(x86_curlwp)
 	movl	%fs:(CPU_INFO_CURLWP), %eax
 	ret
 END(x86_curlwp)
 ENTRY(cpu_set_curpri)
 	movl	4(%esp), %eax
 	movl	%eax, %fs:(CPU_INFO_CURPRIORITY)
 	ret
 END(cpu_set_curpri)
 ENTRY(__byte_swap_u32_variable)
 	movl	4(%esp), %eax
 	bswapl	%eax
 	ret
 END(__byte_swap_u32_variable)
 ENTRY(__byte_swap_u16_variable)
 	movl	4(%esp), %eax
 	xchgb	%al, %ah
 	ret
 END(__byte_swap_u16_variable)
 /*
  * void x86_flush()
+ *
  * Flush instruction pipelines by doing an intersegment (far) return.
  */
 ENTRY(x86_flush)
 	popl	%eax
 	pushl	$GSEL(GCODE_SEL, SEL_KPL)
 	pushl	%eax
 	lret
 END(x86_flush)
 /* Waits - set up stack frame. */
 ENTRY(x86_hlt)
 	pushl	%ebp
 	movl	%esp, %ebp
 	hlt
 	leave
 	ret
 END(x86_hlt)
 /* Waits - set up stack frame. */
 ENTRY(x86_stihlt)
 	pushl	%ebp
 	movl	%esp, %ebp
 	sti
 	hlt
 	leave
 	ret
 END(x86_stihlt)
 ENTRY(x86_monitor)
 	movl	4(%esp), %eax
 	movl	8(%esp), %ecx
 	movl	12(%esp), %edx
 	monitor	%eax, %ecx, %edx
 	ret
 END(x86_monitor)
 /* Waits - set up stack frame. */
 ENTRY(x86_mwait)
 	pushl	%ebp
 	movl	%esp, %ebp
 	movl	8(%ebp), %eax
 	movl	12(%ebp), %ecx
 	mwait	%eax, %ecx
 	leave
 	ret
 END(x86_mwait)
 ENTRY(x86_pause)
 	pause
 	ret
 END(x86_pause)
 ENTRY(x86_cpuid2)
 	pushl	%ebx
 	pushl	%edi
 	movl	12(%esp), %eax
 	movl	16(%esp), %ecx
 	movl	20(%esp), %edi
 	cpuid
 	movl	%eax, 0(%edi)
 	movl	%ebx, 4(%edi)
 	movl	%ecx, 8(%edi)
 	movl	%edx, 12(%edi)
 	popl	%edi
 	popl	%ebx
 	ret
 END(x86_cpuid2)
 ENTRY(x86_getss)
 	movl	%ss, %eax
 	ret
 END(x86_getss)
 ENTRY(fldcw)
 	movl	4(%esp), %eax
 	fldcw	(%eax)
 	ret
 END(fldcw)
 ENTRY(fnclex)
 	fnclex
 	ret
 END(fnclex)
 ENTRY(fninit)
 	fninit
 	ret
 END(fninit)
 ENTRY(fnsave)
 	movl	4(%esp), %eax
 	fnsave	(%eax)
 	ret
 END(fnsave)
 ENTRY(fnstcw)
 	movl	4(%esp), %eax
 	fnstcw	(%eax)
 	ret
 END(fnstcw)
 ENTRY(fngetsw)
 	fnstsw	%ax
 	ret
 END(fngetsw)
 ENTRY(fnstsw)
 	movl	4(%esp), %eax
 	fnstsw	(%eax)
 	ret
 END(fnstsw)
 ENTRY(fp_divide_by_0)
 	fldz
 	fld1
 	fdiv	%st, %st(1)
 	fwait
 	ret
 END(fp_divide_by_0)
 ENTRY(frstor)
 	movl	4(%esp), %eax
 	frstor	(%eax)
 	ret
 END(frstor)
 ENTRY(fwait)
 	fwait
 	ret
 END(fwait)
 ENTRY(clts)
 	clts
 	ret
 END(clts)
 ENTRY(stts)
 	movl	%cr0, %eax
 	testl	$CR0_TS, %eax
 	jnz	1f
 	orl	$CR0_TS, %eax
 	movl	%eax, %cr0
 :
 	ret
 END(stts)
 ENTRY(fxsave)
 	movl	4(%esp), %eax
 	fxsave	(%eax)
 	ret
 END(fxsave)
 ENTRY(fxrstor)
 	movl	4(%esp), %eax
 	fxrstor	(%eax)
 	ret
 END(fxrstor)
 ENTRY(xsave)
 	movl	4(%esp), %ecx
 	movl	8(%esp), %eax	/* feature mask bits */
 	movl	12(%esp), %edx
 	xsave	(%ecx)
 	ret
 END(xsave)
 ENTRY(xsaveopt)
 	movl	4(%esp), %ecx
 	movl	8(%esp), %eax	/* feature mask bits */
 	movl	12(%esp), %edx
 	xsaveopt	(%ecx)
 	ret
 END(xsaveopt)
 ENTRY(xrstor)
 	movl	4(%esp), %ecx
 	movl	8(%esp), %eax	/* feature mask bits */
 	movl	12(%esp), %edx
 	xrstor	(%ecx)
 	ret
 END(xrstor)
 ENTRY(x86_stmxcsr)
 	movl	4(%esp), %eax
 	stmxcsr	(%eax)
 	ret
 END(x86_stmxcsr)
 ENTRY(x86_ldmxcsr)
 	movl	4(%esp), %eax
 	ldmxcsr	(%eax)
 	ret
 END(x86_ldmxcsr)
 ENTRY(fldummy)
 	ffree	%st(7)
 	fldz
 	ret
 END(fldummy)
 ENTRY(inb)
 	movl	4(%esp), %edx
 	xorl	%eax, %eax
 	inb	%dx, %al
 	ret
 END(inb)
 ENTRY(insb)
 	pushl	%edi
 	movl	8(%esp), %edx
 	movl	12(%esp), %edi
 	movl	16(%esp), %ecx
 	rep
 	insb
 	popl	%edi
 	ret
 END(insb)
 ENTRY(inw)
 	movl	4(%esp), %edx
 	xorl	%eax, %eax
 	inw	%dx, %ax
 	ret
 END(inw)
 ENTRY(insw)
 	pushl	%edi
 	movl	8(%esp), %edx
 	movl	12(%esp), %edi
 	movl	16(%esp), %ecx
 	rep
 	insw
 	popl	%edi
 	ret
 END(insw)
 ENTRY(inl)
 	movl	4(%esp), %edx
 	inl	%dx, %eax
 	ret
 END(inl)
 ENTRY(insl)
 	pushl	%edi
 	movl	8(%esp), %edx
 	movl	12(%esp), %edi
 	movl	16(%esp), %ecx
 	rep
 	insl
 	popl	%edi
 	ret
 END(insl)
 ENTRY(outb)
 	movl	4(%esp), %edx
 	movl	8(%esp), %eax
 	outb	%al, %dx
 	ret
 END(outb)
 ENTRY(outsb)
 	pushl	%esi
 	movl	8(%esp), %edx
 	movl	12(%esp), %esi
 	movl	16(%esp), %ecx
 	rep
 	outsb
 	popl	%esi
 	ret
 END(outsb)
 ENTRY(outw)
 	movl	4(%esp), %edx
 	movl	8(%esp), %eax
 	outw	%ax, %dx
 	ret
 END(outw)
 ENTRY(outsw)
 	pushl	%esi
 	movl	8(%esp), %edx
 	movl	12(%esp), %esi
 	movl	16(%esp), %ecx
 	rep
 	outsw
 	popl	%esi
 	ret
 END(outsw)
 ENTRY(outl)
 	movl	4(%esp), %edx
 	movl	8(%esp), %eax
 	outl	%eax, %dx
 	ret
 END(outl)
 ENTRY(outsl)
 	pushl	%esi
 	movl	8(%esp), %edx
 	movl	12(%esp), %esi
 	movl	16(%esp), %ecx
 	rep
 	outsl
 	popl	%esi
 	ret
 END(outsl)

 @@ -1,257 +1,290 @@
-/*	$NetBSD: i386func.S,v 1.18 2016/11/27 14:49:21 kamil Exp $	*/
+/*	$NetBSD: i386func.S,v 1.19 2018/12/22 21:27:22 cherry Exp $	*/
 /*-
  * Copyright (c) 1998, 2007, 2008 The NetBSD Foundation, Inc.
  * All rights reserved.
+ *
  * This code is derived from software contributed to The NetBSD Foundation
  * by Charles M. Hannum, and by Andrew Doran.
+ *
  * Redistribution and use in source and binary forms, with or without
  * modification, are permitted provided that the following conditions
  * are met:
  * 1. Redistributions of source code must retain the above copyright
  *    notice, this list of conditions and the following disclaimer.
  * 2. Redistributions in binary form must reproduce the above copyright
  *    notice, this list of conditions and the following disclaimer in the
  *    documentation and/or other materials provided with the distribution.
+ *
  * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
  * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
  * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
  * PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
  * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
  * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
  * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
  * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
  * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
  * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
  * POSSIBILITY OF SUCH DAMAGE.
  */
 /*
  * Functions to provide access to i386-specific instructions.
+ *
  * These are _not_ shared with NetBSD/xen.
  */
 #include <machine/asm.h>
-__KERNEL_RCSID(0, "$NetBSD: i386func.S,v 1.18 2016/11/27 14:49:21 kamil Exp $");
+__KERNEL_RCSID(0, "$NetBSD: i386func.S,v 1.19 2018/12/22 21:27:22 cherry Exp $");
 #include <machine/specialreg.h>
 #include <machine/segments.h>
 #include "assym.h"
-ENTRY(invlpg)
+/*
  * These functions below should always be accessed via the corresponding wrapper
  * function names defined in x86/include/cpufunc.h and exported as WEAK_ALIAS()
+ *
  * We use this rather roundabout method so that a runtime wrapper function may
  * be made available for PVHVM, which could override both native and PV aliases
  * and decide which to invoke at run time.
  */
 WEAK_ALIAS(invlpg, i386_invlpg)
 WEAK_ALIAS(lldt, i386_lldt)
 WEAK_ALIAS(ltr, i386_ltr)
 WEAK_ALIAS(lcr0, i386_lcr0)
 WEAK_ALIAS(rcr0, i386_rcr0)
 WEAK_ALIAS(lcr3, i386_lcr3)
 WEAK_ALIAS(tlbflush, i386_tlbflush)
 WEAK_ALIAS(tlbflushg, i386_tlbflushg)
 WEAK_ALIAS(rdr0, i386_rdr0)
 WEAK_ALIAS(ldr0, i386_ldr0)
 WEAK_ALIAS(rdr1, i386_rdr1)
 WEAK_ALIAS(ldr1, i386_ldr1)
 WEAK_ALIAS(rdr2, i386_rdr2)
 WEAK_ALIAS(ldr2, i386_ldr2)
 WEAK_ALIAS(rdr3, i386_rdr3)
 WEAK_ALIAS(ldr3, i386_ldr3)
 WEAK_ALIAS(rdr6, i386_rdr6)
 WEAK_ALIAS(ldr6, i386_ldr6)
 WEAK_ALIAS(rdr7, i386_rdr7)
 WEAK_ALIAS(ldr7, i386_ldr7)
 WEAK_ALIAS(rcr2, i386_rcr2)
 WEAK_ALIAS(lcr2, i386_lcr2)
 WEAK_ALIAS(wbinvd, i386_wbinvd)
 ENTRY(i386_invlpg)
 	movl	4(%esp), %eax
 	invlpg	(%eax)
 	ret
-END(invlpg)
+END(i386_invlpg)
-ENTRY(lldt)
+ENTRY(i386_lldt)
 	movl	4(%esp), %eax
 	cmpl	%eax, CPUVAR(CURLDT)
 	jne	1f
 	ret
 :
 	movl	%eax, CPUVAR(CURLDT)
 	lldt	%ax
 	ret
-END(lldt)
+END(i386_lldt)
-ENTRY(ltr)
+ENTRY(i386_ltr)
 	movl	4(%esp), %eax
 	ltr	%ax
 	ret
-END(ltr)
+END(i386_ltr)
-ENTRY(lcr0)
+ENTRY(i386_lcr0)
 	movl	4(%esp), %eax
 	movl	%eax, %cr0
 	ret
-END(lcr0)
+END(i386_lcr0)
-ENTRY(rcr0)
+ENTRY(i386_rcr0)
 	movl	%cr0, %eax
 	ret
-END(rcr0)
+END(i386_rcr0)
-ENTRY(lcr3)
+ENTRY(i386_lcr3)
 	movl	4(%esp), %eax
 	movl	%eax, %cr3
 	ret
-END(lcr3)
+END(i386_lcr3)
 /*
  * Big hammer: flush all TLB entries, including ones from PTE's
  * with the G bit set.  This should only be necessary if TLB
  * shootdown falls far behind.
+ *
  * Intel Architecture Software Developer's Manual, Volume 3,
  *	System Programming, section 9.10, "Invalidating the
  * Translation Lookaside Buffers (TLBS)":
  * "The following operations invalidate all TLB entries, irrespective
  * of the setting of the G flag:
  * ...
  * "(P6 family processors only): Writing to control register CR4 to
  * modify the PSE, PGE, or PAE flag."
+ *
  * (the alternatives not quoted above are not an option here.)
+ *
  * If PGE is not in use, we reload CR3.  Check for the PGE feature
  * first since i486 does not have CR4.  Note: the feature flag may
  * be present while the actual PGE functionality not yet enabled.
  */
-ENTRY(tlbflushg)
+ENTRY(i386_tlbflushg)
 	testl	$CPUID_PGE, _C_LABEL(cpu_feature)
 	jz	1f
 	movl	%cr4, %eax
 	testl	$CR4_PGE, %eax
 	jz	1f
 	movl	%eax, %edx
 	andl	$~CR4_PGE, %edx
 	movl	%edx, %cr4
 	movl	%eax, %cr4
 	ret
-END(tlbflushg)
+END(i386_tlbflushg)
-ENTRY(tlbflush)
+ENTRY(i386_tlbflush)
 :
 	movl	%cr3, %eax
 	movl	%eax, %cr3
 	ret
-END(tlbflush)
+END(i386_tlbflush)
-ENTRY(ldr0)
+ENTRY(i386_ldr0)
 	movl	4(%esp), %eax
 	movl	%eax, %dr0
 	ret
-END(ldr0)
+END(i386_ldr0)
-ENTRY(rdr0)
+ENTRY(i386_rdr0)
 	movl	%dr0, %eax
 	ret
-END(rdr0)
+END(i386_rdr0)
-ENTRY(ldr1)
+ENTRY(i386_ldr1)
 	movl	4(%esp), %eax
 	movl	%eax, %dr1
 	ret
-END(ldr1)
+END(i386_ldr1)
-ENTRY(rdr1)
+ENTRY(i386_rdr1)
 	movl	%dr1, %eax
 	ret
-END(rdr1)
+END(i386_rdr1)
-ENTRY(ldr2)
+ENTRY(i386_ldr2)
 	movl	4(%esp), %eax
 	movl	%eax, %dr2
 	ret
-END(ldr2)
+END(i386_ldr2)
-ENTRY(rdr2)
+ENTRY(i386_rdr2)
 	movl	%dr2, %eax
 	ret
-END(rdr2)
+END(i386_rdr2)
-ENTRY(ldr3)
+ENTRY(i386_ldr3)
 	movl	4(%esp), %eax
 	movl	%eax, %dr3
 	ret
-END(ldr3)
+END(i386_ldr3)
-ENTRY(rdr3)
+ENTRY(i386_rdr3)
 	movl	%dr3, %eax
 	ret
-END(rdr3)
+END(i386_rdr3)
-ENTRY(ldr6)
+ENTRY(i386_ldr6)
 	movl	4(%esp), %eax
 	movl	%eax, %dr6
 	ret
-END(ldr6)
+END(i386_ldr6)
-ENTRY(rdr6)
+ENTRY(i386_rdr6)
 	movl	%dr6, %eax
 	ret
-END(rdr6)
+END(i386_rdr6)
-ENTRY(ldr7)
+ENTRY(i386_ldr7)
 	movl	4(%esp), %eax
 	movl	%eax, %dr7
 	ret
-END(ldr7)
+END(i386_ldr7)
-ENTRY(rdr7)
+ENTRY(i386_rdr7)
 	movl	%dr7, %eax
 	ret
-END(rdr7)
+END(i386_rdr7)
-ENTRY(rcr2)
+ENTRY(i386_rcr2)
 	movl	%cr2, %eax
 	ret
-END(rcr2)
+END(i386_rcr2)
-ENTRY(lcr2)
+ENTRY(i386_lcr2)
 	movl	4(%esp), %eax
 	movl	%eax, %cr2
 	ret
-END(lcr2)
+END(i386_lcr2)
-ENTRY(wbinvd)
+ENTRY(i386_wbinvd)
 	wbinvd
 	ret
-END(wbinvd)
+END(i386_wbinvd)
 ENTRY(x86_disable_intr)
 	cli
 	ret
 END(x86_disable_intr)
 ENTRY(x86_enable_intr)
 	sti
 	ret
 END(x86_enable_intr)
 /*
  * void lgdt(struct region_descriptor *rdp);
+ *
  * Load a new GDT pointer (and do any necessary cleanup).
  * XXX It's somewhat questionable whether reloading all the segment registers
  * is necessary, since the actual descriptor data is not changed except by
  * process creation and exit, both of which clean up via task switches.  OTOH,
  * this only happens at run time when the GDT is resized.
  */
 ENTRY(lgdt)
 	/* Reload the descriptor table. */
 	movl	4(%esp), %eax
 	lgdt	(%eax)
 	/* Flush the prefetch queue. */
 	jmp	1f
 	nop
 :	/* Reload "stale" selectors. */
 	movl	$GSEL(GDATA_SEL, SEL_KPL), %eax
 	movl	%eax, %ds
 	movl	%eax, %es
 	movl	%eax, %gs
 	movl	%eax, %ss
 	movl	$GSEL(GCPU_SEL, SEL_KPL), %eax
 	movl	%eax, %fs
 	jmp	_C_LABEL(x86_flush)
 END(lgdt)
 ENTRY(tsc_get_timecount)
 	movl	CPUVAR(CURLWP), %ecx
 :
 	pushl	L_NCSW(%ecx)
 	rdtsc
 	addl	CPUVAR(CC_SKEW), %eax
 	popl	%edx
 	cmpl	%edx, L_NCSW(%ecx)
 	jne	2f
 	ret
 :
 	jmp	1b
 END(tsc_get_timecount)

 @@ -1,265 +1,331 @@
-/*	$NetBSD: xenfunc.c,v 1.22 2018/10/18 04:17:18 cherry Exp $	*/
+/*	$NetBSD: xenfunc.c,v 1.23 2018/12/22 21:27:22 cherry Exp $	*/
 /*
  * Copyright (c) 2004 Christian Limpach.
  * All rights reserved.
+ *
  * Redistribution and use in source and binary forms, with or without
  * modification, are permitted provided that the following conditions
  * are met:
  * 1. Redistributions of source code must retain the above copyright
  *    notice, this list of conditions and the following disclaimer.
  * 2. Redistributions in binary form must reproduce the above copyright
  *    notice, this list of conditions and the following disclaimer in the
  *    documentation and/or other materials provided with the distribution.
+ *
  * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
  * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
  * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
  * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
  * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
  * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
  * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  */
 #include <sys/cdefs.h>
-__KERNEL_RCSID(0, "$NetBSD: xenfunc.c,v 1.22 2018/10/18 04:17:18 cherry Exp $");
+__KERNEL_RCSID(0, "$NetBSD: xenfunc.c,v 1.23 2018/12/22 21:27:22 cherry Exp $");
 #include <sys/param.h>
 #include <uvm/uvm_extern.h>
 #include <machine/intr.h>
 #include <machine/vmparam.h>
 #include <machine/pmap.h>
 #include <xen/xen.h>
 #include <xen/hypervisor.h>
 //#include <xen/evtchn.h>
 #include <xen/xenpmap.h>
 #include <machine/pte.h>
 #define MAX_XEN_IDT 128
 void xen_set_ldt(vaddr_t, uint32_t);
 /*
  * We don't need to export these declarations, since they are used via
  * linker aliasing. They should always be accessed via the
  * corresponding wrapper function names defined in
  * x86/include/cpufunc.h and exported as __weak_alias()
+ *
  * We use this rather roundabout method so that a runtime wrapper
  * function may be made available for PVHVM, which could override both
  * native and PV aliases and decide which to invoke at run time.
  */
 void xen_invlpg(vaddr_t);
 void xen_lidt(struct region_descriptor *);
 void xen_lldt(u_short);
 void xen_ltr(u_short);
 void xen_lcr0(u_long);
 u_long xen_rcr0(void);
 void xen_tlbflush(void);
 void xen_tlbflushg(void);
 register_t xen_rdr0(void);
 void xen_ldr0(register_t);
 register_t xen_rdr1(void);
 void xen_ldr1(register_t);
 register_t xen_rdr2(void);
 void xen_ldr2(register_t);
 register_t xen_rdr3(void);
 void xen_ldr3(register_t);
 register_t xen_rdr6(void);
 void xen_ldr6(register_t);
 register_t xen_rdr7(void);
 void xen_ldr7(register_t);
 void xen_wbinvd(void);
 vaddr_t xen_rcr2(void);
 __weak_alias(invlpg, xen_invlpg);
 __weak_alias(lidt, xen_lidt);
 __weak_alias(lldt, xen_lldt);
 __weak_alias(ltr, xen_ltr);
 __weak_alias(lcr0, xen_lcr0);
 __weak_alias(rcr0, xen_rcr0);
 __weak_alias(tlbflush, xen_tlbflush);
 __weak_alias(tlbflushg, xen_tlbflushg);
 __weak_alias(rdr0, xen_rdr0);
 __weak_alias(ldr0, xen_ldr0);
 __weak_alias(rdr1, xen_rdr1);
 __weak_alias(ldr1, xen_ldr1);
 __weak_alias(rdr2, xen_rdr2);
 __weak_alias(ldr2, xen_ldr2);
 __weak_alias(rdr3, xen_rdr3);
 __weak_alias(ldr3, xen_ldr3);
 __weak_alias(rdr6, xen_rdr6);
 __weak_alias(ldr6, xen_ldr6);
 __weak_alias(rdr7, xen_rdr7);
 __weak_alias(ldr7, xen_ldr7);
 __weak_alias(wbinvd, xen_wbinvd);
 __weak_alias(rcr2, xen_rcr2);
 #ifdef __x86_64__
 void xen_setusergs(int);
 __weak_alias(setusergs, xen_setusergs);
 #else
 void xen_lcr3(vaddr_t);
 __weak_alias(lcr3, xen_lcr3);
 #endif
 void
-invlpg(vaddr_t addr)
+xen_invlpg(vaddr_t addr)
+{
 	int s = splvm(); /* XXXSMP */
 	xpq_queue_invlpg(addr);
 	splx(s);
+}
 void
-lidt(struct region_descriptor *rd)
+xen_lidt(struct region_descriptor *rd)
+{
 	/*
 	 * We need to do this because we can't assume kmem_alloc(9)
 	 * will be available at the boot stage when this is called.
 	 */
 	static char xen_idt_page[PAGE_SIZE] __attribute__((__aligned__ (PAGE_SIZE)));
 	memset(xen_idt_page, 0, PAGE_SIZE);
 	struct trap_info *xen_idt = (void * )xen_idt_page;
 	int xen_idt_idx = 0;
 	struct trap_info * idd = (void *) rd->rd_base;
 	const int nidt = rd->rd_limit / (sizeof *idd);
 	int i;
 	/*
 	 * Sweep in all initialised entries, consolidate them back to
 	 * back in the requestor array.
 	 */
 	for (i = 0; i < nidt; i++) {
 		if (idd[i].address == 0) /* Skip gap */
 			continue;
 		KASSERT(xen_idt_idx < MAX_XEN_IDT);
 		/* Copy over entry */
 		xen_idt[xen_idt_idx++] = idd[i];
+	}
 #if defined(__x86_64__)
 	/* page needs to be r/o */
 	pmap_changeprot_local((vaddr_t) xen_idt, VM_PROT_READ);
 #endif /* __x86_64 */
 	/* Hook it up in the hypervisor */
 	if (HYPERVISOR_set_trap_table(xen_idt))
 		panic("HYPERVISOR_set_trap_table() failed");
 #if defined(__x86_64__)
 	/* reset */
 	pmap_changeprot_local((vaddr_t) xen_idt, VM_PROT_READ|VM_PROT_WRITE);
 #endif /* __x86_64 */
+}
 void
-lldt(u_short sel)
+xen_lldt(u_short sel)
+{
 #ifndef __x86_64__
 	struct cpu_info *ci;
 	ci = curcpu();
 	if (ci->ci_curldt == sel)
 		return;
 	if (sel == GSEL(GLDT_SEL, SEL_KPL))
 		xen_set_ldt((vaddr_t)ldtstore, NLDT);
 	else
 		xen_set_ldt(ci->ci_gdt[IDXSELN(sel)].ld.ld_base,
 		    ci->ci_gdt[IDXSELN(sel)].ld.ld_entries);
 	ci->ci_curldt = sel;
 #endif
+}
 void
-ltr(u_short sel)
+xen_ltr(u_short sel)
+{
 	panic("XXX ltr not supported\n");
+}
 void
-lcr0(u_long val)
+xen_lcr0(u_long val)
+{
 	panic("XXX lcr0 not supported\n");
+}
 u_long
-rcr0(void)
+xen_rcr0(void)
+{
 	/* XXX: handle X86_CR0_TS ? */
 	return 0;
+}
 #ifndef __x86_64__
 void
-lcr3(vaddr_t val)
+xen_lcr3(vaddr_t val)
+{
 	int s = splvm(); /* XXXSMP */
 	xpq_queue_pt_switch(xpmap_ptom_masked(val));
 	splx(s);
+}
 #endif
 void
-tlbflush(void)
+xen_tlbflush(void)
+{
 	int s = splvm(); /* XXXSMP */
 	xpq_queue_tlb_flush();
 	splx(s);
+}
 void
-tlbflushg(void)
+xen_tlbflushg(void)
+{
 	tlbflush();
+}
 register_t
-rdr0(void)
+xen_rdr0(void)
+{
 	return HYPERVISOR_get_debugreg(0);
+}
 void
-ldr0(register_t val)
+xen_ldr0(register_t val)
+{
 	HYPERVISOR_set_debugreg(0, val);
+}
 register_t
-rdr1(void)
+xen_rdr1(void)
+{
 	return HYPERVISOR_get_debugreg(1);
+}
 void
-ldr1(register_t val)
+xen_ldr1(register_t val)
+{
 	HYPERVISOR_set_debugreg(1, val);
+}
 register_t
-rdr2(void)
+xen_rdr2(void)
+{
 	return HYPERVISOR_get_debugreg(2);
+}
 void
-ldr2(register_t val)
+xen_ldr2(register_t val)
+{
 	HYPERVISOR_set_debugreg(2, val);
+}
 register_t
-rdr3(void)
+xen_rdr3(void)
+{
 	return HYPERVISOR_get_debugreg(3);
+}
 void
-ldr3(register_t val)
+xen_ldr3(register_t val)
+{
 	HYPERVISOR_set_debugreg(3, val);
+}
 register_t
-rdr6(void)
+xen_rdr6(void)
+{
 	return HYPERVISOR_get_debugreg(6);
+}
 void
-ldr6(register_t val)
+xen_ldr6(register_t val)
+{
 	HYPERVISOR_set_debugreg(6, val);
+}
 register_t
-rdr7(void)
+xen_rdr7(void)
+{
 	return HYPERVISOR_get_debugreg(7);
+}
 void
-ldr7(register_t val)
+xen_ldr7(register_t val)
+{
 	HYPERVISOR_set_debugreg(7, val);
+}
 void
-wbinvd(void)
+xen_wbinvd(void)
+{
 	xpq_flush_cache();
+}
 vaddr_t
-rcr2(void)
+xen_rcr2(void)
+{
 	return curcpu()->ci_vcpu->arch.cr2;
+}
 #ifdef __x86_64__
 void
-setusergs(int gssel)
+xen_setusergs(int gssel)
+{
 	HYPERVISOR_set_segment_base(SEGBASE_GS_USER_SEL, gssel);
+}
 #endif