 @@ -1,319 +1,319 @@
-#	$NetBSD: files.sunxi,v 1.58 2019/01/03 11:01:59 jmcneill Exp $
+#	$NetBSD: files.sunxi,v 1.59 2019/01/03 14:44:21 jmcneill Exp $
+#
 # Configuration info for Allwinner sunxi family SoCs
+#
+#
 file	arch/arm/sunxi/sunxi_platform.c		soc_sunxi
 file	arch/arm/sunxi/sunxi_mc_smp.c		soc_sunxi_mc
 file	arch/arm/sunxi/sunxi_mc_mpstart.S	soc_sunxi_mc
 # CCU
 define	sunxi_ccu
 file	arch/arm/sunxi/sunxi_ccu.c		sunxi_ccu
 file	arch/arm/sunxi/sunxi_ccu_div.c		sunxi_ccu
 file	arch/arm/sunxi/sunxi_ccu_fixed_factor.c	sunxi_ccu
 file	arch/arm/sunxi/sunxi_ccu_fractional.c	sunxi_ccu
 file	arch/arm/sunxi/sunxi_ccu_gate.c		sunxi_ccu
 file	arch/arm/sunxi/sunxi_ccu_nm.c		sunxi_ccu
 file	arch/arm/sunxi/sunxi_ccu_nkmp.c		sunxi_ccu
 file	arch/arm/sunxi/sunxi_ccu_phase.c	sunxi_ccu
 file	arch/arm/sunxi/sunxi_ccu_prediv.c	sunxi_ccu
 file	arch/arm/sunxi/sunxi_ccu_display.c	sunxi_ccu
 # CCU (A10/A20)
 device	sun4ia10ccu: sunxi_ccu
 attach	sun4ia10ccu at fdt with sunxi_a10_ccu
 file	arch/arm/sunxi/sun4i_a10_ccu.c		sunxi_a10_ccu
 # CCU (A13)
 device	sun5ia13ccu: sunxi_ccu
 attach	sun5ia13ccu at fdt with sunxi_a13_ccu
 file	arch/arm/sunxi/sun5i_a13_ccu.c		sunxi_a13_ccu
 # CCU (A31)
 device	sun6ia31ccu: sunxi_ccu
 attach	sun6ia31ccu at fdt with sunxi_a31_ccu
 file	arch/arm/sunxi/sun6i_a31_ccu.c		sunxi_a31_ccu
 # CCU (A83T)
 device	sun8ia83tccu: sunxi_ccu
 attach	sun8ia83tccu at fdt with sunxi_a83t_ccu
 file	arch/arm/sunxi/sun8i_a83t_ccu.c		sunxi_a83t_ccu
 # CCU (H3)
 device	sun8ih3ccu: sunxi_ccu
 attach	sun8ih3ccu at fdt with sunxi_h3_ccu
 file	arch/arm/sunxi/sun8i_h3_ccu.c		sunxi_h3_ccu
 # CCU (H3 PRCM)
 device	sun8ih3rccu: sunxi_ccu
 attach	sun8ih3rccu at fdt with sunxi_h3_r_ccu
 file	arch/arm/sunxi/sun8i_h3_r_ccu.c		sunxi_h3_r_ccu
 # CCU (A80)
 device	sun9ia80ccu: sunxi_ccu
 attach	sun9ia80ccu at fdt with sunxi_a80_ccu
 file	arch/arm/sunxi/sun9i_a80_ccu.c		sunxi_a80_ccu
 # CCU (A64)
 device	sun50ia64ccu: sunxi_ccu
 attach	sun50ia64ccu at fdt with sunxi_a64_ccu
 file	arch/arm/sunxi/sun50i_a64_ccu.c		sunxi_a64_ccu
 # CCU (A64 PRCM)
 device	sun50ia64rccu: sunxi_ccu
 attach	sun50ia64rccu at fdt with sunxi_a64_r_ccu
 file	arch/arm/sunxi/sun50i_a64_r_ccu.c	sunxi_a64_r_ccu
 # CCU (H6)
 device	sun50ih6ccu: sunxi_ccu
 attach	sun50ih6ccu at fdt with sunxi_h6_ccu
 file	arch/arm/sunxi/sun50i_h6_ccu.c		sunxi_h6_ccu
 # CCU (H6 PRCM)
 device	sun50ih6rccu: sunxi_ccu
 attach	sun50ih6rccu at fdt with sunxi_h6_r_ccu
 file	arch/arm/sunxi/sun50i_h6_r_ccu.c	sunxi_h6_r_ccu
 # Misc. clock resets
 device	sunxiresets
 attach	sunxiresets at fdt with sunxi_resets
 file	arch/arm/sunxi/sunxi_resets.c		sunxi_resets
 # Misc. clock gates
 device	sunxigates
 attach	sunxigates at fdt with sunxi_gates
 file	arch/arm/sunxi/sunxi_gates.c		sunxi_gates
 # GMAC MII/RGMII clock mux
 device	sunxigmacclk
 attach	sunxigmacclk at fdt with sunxi_gmacclk
 file	arch/arm/sunxi/sunxi_gmacclk.c		sunxi_gmacclk
 # SD/MMC-COMM (A80)
 device	sun9immcclk
 attach	sun9immcclk at fdt with sunxi_a80_mmcclk
 file	arch/arm/sunxi/sun9i_a80_mmcclk.c	sunxi_a80_mmcclk
 # Interrupt controller
 device	sunxiintc: pic, pic_splfuncs
 attach	sunxiintc at fdt with sunxi_intc
 file	arch/arm/sunxi/sunxi_intc.c		sunxi_intc
 device	sunxinmi
 attach	sunxinmi at fdt with sunxi_nmi
 file	arch/arm/sunxi/sunxi_nmi.c		sunxi_nmi
 # GPIO
 device	sunxigpio: gpiobus
 attach	sunxigpio at fdt with sunxi_gpio
 file	arch/arm/sunxi/sunxi_gpio.c		sunxi_gpio
 file	arch/arm/sunxi/sun4i_a10_gpio.c		sunxi_gpio & soc_sun4i_a10
 file	arch/arm/sunxi/sun5i_a13_gpio.c		sunxi_gpio & soc_sun5i_a13
 file	arch/arm/sunxi/sun6i_a31_gpio.c		sunxi_gpio & soc_sun6i_a31
 file	arch/arm/sunxi/sun7i_a20_gpio.c		sunxi_gpio & soc_sun7i_a20
 file	arch/arm/sunxi/sun8i_a83t_gpio.c	sunxi_gpio & soc_sun8i_a83t
 file	arch/arm/sunxi/sun8i_h3_gpio.c		sunxi_gpio & soc_sun8i_h3
 file	arch/arm/sunxi/sun9i_a80_gpio.c		sunxi_gpio & soc_sun9i_a80
 file	arch/arm/sunxi/sun50i_a64_gpio.c	sunxi_gpio & soc_sun50i_a64
 file	arch/arm/sunxi/sun50i_h6_gpio.c		sunxi_gpio & soc_sun50i_h6
 # PWM
 device	sunxipwm: pwm
 attach	sunxipwm at fdt with sunxi_pwm
 file	arch/arm/sunxi/sunxi_pwm.c		sunxi_pwm
 # SD/MMC
 device	sunximmc: sdmmcbus
 attach	sunximmc at fdt with sunxi_mmc
 file	arch/arm/sunxi/sunxi_mmc.c		sunxi_mmc
 defparam opt_sunximmc.h				SUNXI_MMC_DEBUG
 # USB PHY
 device	sunxiusbphy
 attach	sunxiusbphy at fdt with sunxi_usbphy
 file	arch/arm/sunxi/sunxi_usbphy.c		sunxi_usbphy
 device	sunxiusb3phy
 attach	sunxiusb3phy at fdt with sunxi_usb3phy
 file	arch/arm/sunxi/sunxi_usb3phy.c		sunxi_usb3phy
 # EHCI
 attach	ehci at fdt with ehci_fdt
 file	dev/fdt/ehci_fdt.c			ehci_fdt
 # OHCI
 attach	ohci at fdt with ohci_fdt
 file	dev/fdt/ohci_fdt.c			ohci_fdt
 # TWI
 device	sunxitwi: i2cbus, i2cexec, mvi2c
 attach	sunxitwi at fdt with sunxi_twi
 file	arch/arm/sunxi/sunxi_twi.c		sunxi_twi
 # P2WI/RSB
 device	sunxirsb: i2cbus, i2cexec
 attach	sunxirsb at fdt with sunxi_rsb
 file	arch/arm/sunxi/sunxi_rsb.c		sunxi_rsb
 # RTC
 device	sunxirtc
 attach	sunxirtc at fdt with sunxi_rtc
 file	arch/arm/sunxi/sunxi_rtc.c		sunxi_rtc
 # EMAC (common)
 device	emac: arp, ether, ifnet, mii
 # EMAC (sun4i/sun5i/sun7i)
 ifdef arm
 attach	emac at fdt with sun4i_emac
 file	arch/arm/sunxi/sun4i_emac.c		sun4i_emac
 endif
 # EMAC (sun8i/sun50i)
 attach	emac at fdt with sunxi_emac
 file	arch/arm/sunxi/sunxi_emac.c		sunxi_emac
 # GMAC
 attach	awge at fdt with sunxi_gmac
 file	arch/arm/sunxi/sunxi_gmac.c		sunxi_gmac
 # Timer
 device	sunxitimer
 attach	sunxitimer at fdt with sunxi_timer
 file	arch/arm/sunxi/sunxi_timer.c		sunxi_timer
 # Watchdog
 device	sunxiwdt: sysmon_wdog
 attach	sunxiwdt at fdt with sunxi_wdt
 file	arch/arm/sunxi/sunxi_wdt.c		sunxi_wdt
 # DMA controller (sun4i)
 device	sun4idma
 attach	sun4idma at fdt with sun4i_dma
 file	arch/arm/sunxi/sun4i_dma.c		sun4i_dma
 # DMA controller (sun6i)
 device	sun6idma
 attach	sun6idma at fdt with sun6i_dma
 file	arch/arm/sunxi/sun6i_dma.c		sun6i_dma
 # Audio codec
 device	sunxicodec: audiobus, auconv, mulaw, aurateconv
 attach	sunxicodec at fdt with sunxi_codec
 file	arch/arm/sunxi/sunxi_codec.c		sunxi_codec
 file	arch/arm/sunxi/sun4i_a10_codec.c	sunxi_codec
 file	arch/arm/sunxi/sun6i_a31_codec.c	sunxi_codec
 # Audio codec (sun8i)
 device	sun8icodec
 attach	sun8icodec at fdt with sun8i_codec
 file	arch/arm/sunxi/sun8i_codec.c		sun8i_codec
 # H3 Audio codec (analog part)
 device	h3codec
 attach	h3codec at fdt with h3_codec
 file	arch/arm/sunxi/sun8i_h3_codec.c		h3_codec needs-flag
 # A64 Audio codec (analog part)
 device	a64acodec
 attach	a64acodec at fdt with a64_acodec
 file	arch/arm/sunxi/sun50i_a64_acodec.c	a64_acodec
 # I2S/PCM controller
 device	sunxii2s: auconv, mulaw, aurateconv
 attach	sunxii2s at fdt with sunxi_i2s
 file	arch/arm/sunxi/sunxi_i2s.c		sunxi_i2s
 # A10/A20 LCD/TV timing controller (TCON)
 device	sunxitcon
 attach	sunxitcon at fdt with sunxi_tcon
 file	arch/arm/sunxi/sunxi_tcon.c		sunxi_tcon needs-flag
 # A10/A20 Display engine backend (DE-BE)
 device	sunxidebe { }
 attach	sunxidebe at fdt with sunxi_debe
 file	arch/arm/sunxi/sunxi_debe.c		sunxi_debe needs-flag
 attach	genfb at sunxidebe with sunxi_befb
 # A10/A20 HDMI
 device	sunxihdmi: edid, videomode
 attach	sunxihdmi at fdt with sunxi_hdmi
 file	arch/arm/sunxi/sunxi_hdmi.c		sunxi_hdmi needs-flag
 # A10/A20 display engine pipeline
 device sunxidep
 attach	sunxidep at fdt with sunxi_dep
 file	arch/arm/sunxi/sunxi_dep.c		sunxi_dep
 # Touch Screen controller
 device	sunxits: wsmousedev, tpcalib, sysmon_envsys
 attach	sunxits at fdt with sunxi_ts
 file	arch/arm/sunxi/sunxi_ts.c		sunxi_ts
 # USB OTG
 attach	motg at fdt with sunxi_musb
 file	arch/arm/sunxi/sunxi_musb.c		sunxi_musb
 # Security ID EFUSE
 device	sunxisid
 attach	sunxisid at fdt with sunxi_sid
 file	arch/arm/sunxi/sunxi_sid.c		sunxi_sid
 # Thermal sensor controller
 device	sunxithermal: sysmon_envsys, sysmon_taskq
 attach	sunxithermal at fdt with sunxi_thermal
 file	arch/arm/sunxi/sunxi_thermal.c		sunxi_thermal
 # SATA
 attach	ahcisata at fdt with sunxi_sata
 file	arch/arm/sunxi/sunxi_sata.c		sunxi_sata
 # SRAM Controller
 device	sunxisramc
 attach	sunxisramc at fdt with sunxi_sramc
 file	arch/arm/sunxi/sunxi_sramc.c		sunxi_sramc
 # NAND Flash Controller
 device	sunxinand: nandbus
 attach	sunxinand at fdt with sunxi_nand
 file	arch/arm/sunxi/sunxi_nand.c		sunxi_nand
 # SPI Controller (sun6i-compatible)
 device	sun6ispi: spibus
 attach	sun6ispi at fdt with sun6i_spi
 file	arch/arm/sunxi/sun6i_spi.c		sun6i_spi
 # A10/A20 CAN
 device	sunxican { } : ifnet
 attach	sunxican at fdt with sunxi_can
 file	arch/arm/sunxi/sunxi_can.c		sunxi_can
 # LRADC
 device	sunxilradc
 attach	sunxilradc at fdt with sunxi_lradc
 file	arch/arm/sunxi/sunxi_lradc.c		sunxi_lradc
 # SOC parameters
 defflag	opt_soc.h			SOC_SUNXI
 defflag	opt_soc.h			SOC_SUNXI_MC
 defflag	opt_soc.h			SOC_SUN4I: SOC_SUNXI
 defflag	opt_soc.h			SOC_SUN4I_A10: SOC_SUN4I
 defflag	opt_soc.h			SOC_SUN5I: SOC_SUNXI
 defflag	opt_soc.h			SOC_SUN5I_A13: SOC_SUN5I
 defflag	opt_soc.h			SOC_SUN6I: SOC_SUNXI
 defflag	opt_soc.h			SOC_SUN6I_A31: SOC_SUN6I
 defflag	opt_soc.h			SOC_SUN7I: SOC_SUNXI
 defflag	opt_soc.h			SOC_SUN7I_A20: SOC_SUN7I
 defflag	opt_soc.h			SOC_SUN8I: SOC_SUNXI
 defflag	opt_soc.h			SOC_SUN8I_A83T: SOC_SUN8I, SOC_SUNXI_MC
 defflag	opt_soc.h			SOC_SUN8I_H3: SOC_SUN8I
 defflag	opt_soc.h			SOC_SUN9I: SOC_SUNXI
-defflag	opt_soc.h			SOC_SUN9I_A80: SOC_SUN9I
+defflag	opt_soc.h			SOC_SUN9I_A80: SOC_SUN9I, SOC_SUNXI_MC
 defflag	opt_soc.h			SOC_SUN50I: SOC_SUNXI
 defflag	opt_soc.h			SOC_SUN50I_A64: SOC_SUN50I
 defflag	opt_soc.h			SOC_SUN50I_H5: SOC_SUN50I, SOC_SUN8I_H3
 defflag	opt_soc.h			SOC_SUN50I_H6: SOC_SUN50I

 @@ -1,203 +1,263 @@
-/* $NetBSD: sunxi_mc_smp.c,v 1.2 2019/01/03 12:52:40 jmcneill Exp $ */
+/* $NetBSD: sunxi_mc_smp.c,v 1.3 2019/01/03 14:44:21 jmcneill Exp $ */
 /*-
  * Copyright (c) 2019 Jared McNeill <jmcneill@invisible.ca>
  * All rights reserved.
+ *
  * Redistribution and use in source and binary forms, with or without
  * modification, are permitted provided that the following conditions
  * are met:
  * 1. Redistributions of source code must retain the above copyright
  *    notice, this list of conditions and the following disclaimer.
  * 2. Redistributions in binary form must reproduce the above copyright
  *    notice, this list of conditions and the following disclaimer in the
  *    documentation and/or other materials provided with the distribution.
+ *
  * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
  * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
  * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
  * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
  * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
  * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
  * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
  * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
  * SUCH DAMAGE.
  */
 #include <sys/cdefs.h>
-__KERNEL_RCSID(0, "$NetBSD: sunxi_mc_smp.c,v 1.2 2019/01/03 12:52:40 jmcneill Exp $");
+__KERNEL_RCSID(0, "$NetBSD: sunxi_mc_smp.c,v 1.3 2019/01/03 14:44:21 jmcneill Exp $");
 #include <sys/param.h>
 #include <sys/bus.h>
 #include <sys/device.h>
 #include <sys/systm.h>
 #include <uvm/uvm_extern.h>
 #include <dev/fdt/fdtvar.h>
 #include <arm/armreg.h>
 #include <arm/cpu.h>
 #include <arm/cpufunc.h>
 #include <arm/locore.h>
 #include <arm/sunxi/sunxi_mc_smp.h>
-#define	A83T_SMP_ENABLE_METHOD	"allwinner,sun8i-a83t-smp"
+#define	A80_PRCM_BASE		0x08001400
 #define	A80_PRCM_SIZE		0x200
-#define	PRCM_BASE		0x01f01400
+#define	A83T_PRCM_BASE		0x01f01400
-#define	PRCM_SIZE		0x800
+#define	A83T_PRCM_SIZE		0x800
 #define	 PRCM_CL_RST_CTRL(cluster)	(0x4 + (cluster) * 0x4)
 #define	 PRCM_CL_PWROFF(cluster)	(0x100 + (cluster) * 0x4)
 #define	 PRCM_CL_PWR_CLAMP(cluster, cpu) (0x140 + (cluster) * 0x10 + (cpu) * 0x4)
 #define	 PRCM_CPU_SOFT_ENTRY		0x164
 #define	CPUCFG_BASE	0x01f01c00
 #define	CPUCFG_SIZE	0x400
 #define	 CPUCFG_CL_RST(cluster)		(0x30 + (cluster) * 0x4)
 #define	 CPUCFG_P_REG0			0x1a4
 #define	CPUXCFG_BASE	0x01700000
 #define	CPUXCFG_SIZE	0x400
 #define	 CPUXCFG_CL_RST(cluster)	(0x80 + (cluster) * 0x4)
 #define	  CPUXCFG_CL_RST_SOC_DBG_RST	__BIT(24)
 #define	  CPUXCFG_CL_RST_ETM_RST(cpu)	__BIT(20 + (cpu))
 #define	  CPUXCFG_CL_RST_DBG_RST(cpu)	__BIT(16 + (cpu))
 #define	  CPUXCFG_CL_RST_H_RST		__BIT(12)
 #define	  CPUXCFG_CL_RST_L2_RST		__BIT(8)
 #define	  CPUXCFG_CL_RST_CX_RST(cpu)	__BIT(4 + (cpu))
 #define	 CPUXCFG_CL_CTRL0(cluster)	(0x0 + (cluster) * 0x10)
 #define	 CPUXCFG_CL_CTRL1(cluster)	(0x4 + (cluster) * 0x10)
 #define	  CPUXCFG_CL_CTRL1_ACINACTM	__BIT(0)
-#define	CCI_BASE		0x01790000
+#define	A80_CCI_BASE		0x01c90000
-#define	CCI_SLAVEIF3_BASE	(CCI_BASE + 0x4000)
+#define	A83T_CCI_BASE		0x01790000
 #define	CCI_SLAVEIF4_BASE	(CCI_BASE + 0x5000)
 #define	CCI_SLAVEIF3_OFFSET	0x4000
 #define	CCI_SLAVEIF4_OFFSET	0x5000
 extern struct bus_space arm_generic_bs_tag;
-uint32_t sunxi_mc_cci_port[MAXCPUS] = {
+enum sunxi_mc_soc {
-	CCI_SLAVEIF3_BASE,
+	MC_SOC_A80,
-	CCI_SLAVEIF3_BASE,
+	MC_SOC_A83T
-	CCI_SLAVEIF3_BASE,
+};
 	CCI_SLAVEIF3_BASE,
-	CCI_SLAVEIF4_BASE,
+enum sunxi_mc_cpu {
-	CCI_SLAVEIF4_BASE,
+	MC_CORE_CA7,
-	CCI_SLAVEIF4_BASE,
+	MC_CORE_CA15
 	CCI_SLAVEIF4_BASE,
 };
 uint32_t sunxi_mc_cci_port[MAXCPUS];
 static uint32_t
 sunxi_mc_smp_pa(void)
+{
 	extern void sunxi_mc_mpstart(void);
 	bool ok __diagused;
 	paddr_t pa;
 	ok = pmap_extract(pmap_kernel(), (vaddr_t)sunxi_mc_mpstart, &pa);
 	KASSERT(ok);
 	return pa;
+}
 static int
 sunxi_mc_smp_start(bus_space_tag_t bst, bus_space_handle_t prcm, bus_space_handle_t cpucfg,
-    bus_space_handle_t cpuxcfg, u_int cluster, u_int cpu)
+    bus_space_handle_t cpuxcfg, u_int cluster, u_int cpu, enum sunxi_mc_soc soc,
     enum sunxi_mc_cpu core)
+{
 	uint32_t val;
 	int i;
 	/* Set start vector */
 	bus_space_write_4(bst, cpucfg, CPUCFG_P_REG0, sunxi_mc_smp_pa());
 	/* Assert core reset */
 	val = bus_space_read_4(bst, cpuxcfg, CPUXCFG_CL_RST(cluster));
 	val &= ~__BIT(cpu);
 	bus_space_write_4(bst, cpuxcfg, CPUXCFG_CL_RST(cluster), val);
-	/* Assert power-on reset */
+	if (soc == MC_SOC_A83T) {
-	val = bus_space_read_4(bst, cpucfg, CPUCFG_CL_RST(cluster));
+		/* Assert power-on reset */
-	val &= ~__BIT(cpu);
+		val = bus_space_read_4(bst, cpucfg, CPUCFG_CL_RST(cluster));
-	bus_space_write_4(bst, cpucfg, CPUCFG_CL_RST(cluster), val);
+		val &= ~__BIT(cpu);
 		bus_space_write_4(bst, cpucfg, CPUCFG_CL_RST(cluster), val);
+	}
-	/* Disable automatic L1 cache invalidate at reset */
+	if (core == MC_CORE_CA7) {
-	val = bus_space_read_4(bst, cpuxcfg, CPUXCFG_CL_CTRL0(cluster));
+		/* Disable automatic L1 cache invalidate at reset */
-	val &= ~__BIT(cpu);
+		val = bus_space_read_4(bst, cpuxcfg, CPUXCFG_CL_CTRL0(cluster));
-	bus_space_write_4(bst, cpuxcfg, CPUXCFG_CL_CTRL0(cluster), val);
+		val &= ~__BIT(cpu);
 		bus_space_write_4(bst, cpuxcfg, CPUXCFG_CL_CTRL0(cluster), val);
+	}
 	/* Release power clamp */
 	for (i = 0; i <= 8; i++) {
 		bus_space_write_4(bst, prcm, PRCM_CL_PWR_CLAMP(cluster, cpu), 0xff >> i);
 		delay(10);
+	}
 	for (i = 100000; i > 0; i--) {
 		if (bus_space_read_4(bst, prcm, PRCM_CL_PWR_CLAMP(cluster, cpu)) == 0)
 			break;
+	}
 	if (i == 0) {
 		printf("CPU %#llx failed to start\n", __SHIFTIN(cluster, MPIDR_AFF1) | __SHIFTIN(cpu, MPIDR_AFF0));
 		return ETIMEDOUT;
+	}
 	/* Clear power-off gating */
 	val = bus_space_read_4(bst, prcm, PRCM_CL_PWROFF(cluster));
-	if (cpu == 0)
+	if (soc == MC_SOC_A83T) {
-		val &= ~__BIT(4);
+		if (cpu == 0)
-	val &= ~__BIT(cpu);
+			val &= ~__BIT(4);
 		val &= ~__BIT(0);	/* cluster power gate */
 	} else {
 		val &= ~__BIT(cpu);
 		val &= ~__BIT(4);	/* cluster power gate */
+	}
 	bus_space_write_4(bst, prcm, PRCM_CL_PWROFF(cluster), val);
 	/* De-assert power-on reset */
 	val = bus_space_read_4(bst, prcm, PRCM_CL_RST_CTRL(cluster));
 	val |= __BIT(cpu);
 	bus_space_write_4(bst, prcm, PRCM_CL_RST_CTRL(cluster), val);
-	val = bus_space_read_4(bst, cpucfg, CPUCFG_CL_RST(cluster));
+	if (soc == MC_SOC_A83T) {
-	val |= __BIT(cpu);
+		val = bus_space_read_4(bst, cpucfg, CPUCFG_CL_RST(cluster));
-	bus_space_write_4(bst, cpucfg, CPUCFG_CL_RST(cluster), val);
+		val |= __BIT(cpu);
-	delay(10);
+		bus_space_write_4(bst, cpucfg, CPUCFG_CL_RST(cluster), val);
 		delay(10);
+	}
 	/* De-assert core reset */
 	val = bus_space_read_4(bst, cpuxcfg, CPUXCFG_CL_RST(cluster));
 	val |= __BIT(cpu);
 	val |= CPUXCFG_CL_RST_SOC_DBG_RST;
-	val |= CPUXCFG_CL_RST_ETM_RST(cpu);
+	if (core == MC_CORE_CA7)
 		val |= CPUXCFG_CL_RST_ETM_RST(cpu);
 	else
 		val |= CPUXCFG_CL_RST_CX_RST(cpu);
 	val |= CPUXCFG_CL_RST_DBG_RST(cpu);
 	val |= CPUXCFG_CL_RST_L2_RST;
 	val |= CPUXCFG_CL_RST_H_RST;
 	bus_space_write_4(bst, cpuxcfg, CPUXCFG_CL_RST(cluster), val);
 	/* De-assert ACINACTM */
 	val = bus_space_read_4(bst, cpuxcfg, CPUXCFG_CL_CTRL1(cluster));
 	val &= ~CPUXCFG_CL_CTRL1_ACINACTM;
 	bus_space_write_4(bst, cpuxcfg, CPUXCFG_CL_CTRL1(cluster), val);
 	return 0;
+}
 int
-sunxi_mc_smp_enable(u_int mpidr)
+sun8i_a83t_smp_enable(u_int mpidr)
+{
 	bus_space_tag_t bst = &arm_generic_bs_tag;
 	bus_space_handle_t prcm, cpucfg, cpuxcfg;
 	int error;
 	const u_int cluster = __SHIFTOUT(mpidr, MPIDR_AFF1);
 	const u_int cpu = __SHIFTOUT(mpidr, MPIDR_AFF0);
-	if (bus_space_map(bst, PRCM_BASE, PRCM_SIZE, 0, &prcm) != 0 ||
+	if (bus_space_map(bst, A83T_PRCM_BASE, A83T_PRCM_SIZE, 0, &prcm) != 0 ||
 	    bus_space_map(bst, CPUCFG_BASE, CPUCFG_SIZE, 0, &cpucfg) != 0 ||
 	    bus_space_map(bst, CPUXCFG_BASE, CPUXCFG_SIZE, 0, &cpuxcfg) != 0)
 		return ENOMEM;
-	error = sunxi_mc_smp_start(bst, prcm, cpucfg, cpuxcfg, cluster, cpu);
+	for (int i = 0; i < 4; i++)
 		sunxi_mc_cci_port[i] = A83T_CCI_BASE + CCI_SLAVEIF3_OFFSET;
 	for (int i = 4; i < 8; i++)
 		sunxi_mc_cci_port[i] = A83T_CCI_BASE + CCI_SLAVEIF4_OFFSET;
 	/* Set start vector */
 	bus_space_write_4(bst, cpucfg, CPUCFG_P_REG0, sunxi_mc_smp_pa());
 	cpu_idcache_wbinv_all();
 	error = sunxi_mc_smp_start(bst, prcm, cpucfg, cpuxcfg, cluster, cpu,
 	    MC_SOC_A83T, MC_CORE_CA7);
 	bus_space_unmap(bst, cpuxcfg, CPUXCFG_SIZE);
 	bus_space_unmap(bst, cpucfg, CPUCFG_SIZE);
-	bus_space_unmap(bst, prcm, PRCM_SIZE);
+	bus_space_unmap(bst, prcm, A83T_PRCM_SIZE);
 	return error;
+}
 int
 sun9i_a80_smp_enable(u_int mpidr)
+{
 	bus_space_tag_t bst = &arm_generic_bs_tag;
 	bus_space_handle_t prcm, cpuxcfg;
 	int error;
 	const u_int cluster = __SHIFTOUT(mpidr, MPIDR_AFF1);
 	const u_int cpu = __SHIFTOUT(mpidr, MPIDR_AFF0);
 	if (bus_space_map(bst, A80_PRCM_BASE, A80_PRCM_SIZE, 0, &prcm) != 0 ||
 	    bus_space_map(bst, CPUXCFG_BASE, CPUXCFG_SIZE, 0, &cpuxcfg) != 0)
 		return ENOMEM;
 	for (int i = 0; i < 4; i++)
 		sunxi_mc_cci_port[i] = A80_CCI_BASE + CCI_SLAVEIF3_OFFSET;
 	for (int i = 4; i < 8; i++)
 		sunxi_mc_cci_port[i] = A80_CCI_BASE + CCI_SLAVEIF4_OFFSET;
 	/* Set start vector */
 	bus_space_write_4(bst, prcm, PRCM_CPU_SOFT_ENTRY, sunxi_mc_smp_pa());
 	cpu_idcache_wbinv_all();
 	error = sunxi_mc_smp_start(bst, prcm, 0, cpuxcfg, cluster, cpu,
 	    MC_SOC_A80, cluster == 0 ? MC_CORE_CA7 : MC_CORE_CA15);
 	bus_space_unmap(bst, cpuxcfg, CPUXCFG_SIZE);
 	bus_space_unmap(bst, prcm, A80_PRCM_SIZE);
 	return error;
+}

 @@ -1,451 +1,486 @@
-/* $NetBSD: sunxi_platform.c,v 1.33 2019/01/03 12:52:40 jmcneill Exp $ */
+/* $NetBSD: sunxi_platform.c,v 1.34 2019/01/03 14:44:21 jmcneill Exp $ */
 /*-
  * Copyright (c) 2017 Jared McNeill <jmcneill@invisible.ca>
  * All rights reserved.
+ *
  * Redistribution and use in source and binary forms, with or without
  * modification, are permitted provided that the following conditions
  * are met:
  * 1. Redistributions of source code must retain the above copyright
  *    notice, this list of conditions and the following disclaimer.
  * 2. Redistributions in binary form must reproduce the above copyright
  *    notice, this list of conditions and the following disclaimer in the
  *    documentation and/or other materials provided with the distribution.
+ *
  * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
  * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
  * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
  * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
  * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
  * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
  * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
  * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
  * SUCH DAMAGE.
  */
 #include "opt_soc.h"
 #include "opt_multiprocessor.h"
 #include "opt_console.h"
 #include <sys/cdefs.h>
-__KERNEL_RCSID(0, "$NetBSD: sunxi_platform.c,v 1.33 2019/01/03 12:52:40 jmcneill Exp $");
+__KERNEL_RCSID(0, "$NetBSD: sunxi_platform.c,v 1.34 2019/01/03 14:44:21 jmcneill Exp $");
 #include <sys/param.h>
 #include <sys/bus.h>
 #include <sys/cpu.h>
 #include <sys/device.h>
 #include <sys/termios.h>
 #include <dev/fdt/fdtvar.h>
 #include <arm/fdt/arm_fdtvar.h>
 #include <uvm/uvm_extern.h>
 #include <machine/bootconfig.h>
 #include <arm/cpufunc.h>
 #include <arm/cortex/gtmr_var.h>
 #include <arm/cortex/gic_reg.h>
 #include <dev/ic/ns16550reg.h>
 #include <dev/ic/comreg.h>
 #include <arm/arm/psci.h>
 #include <arm/fdt/psci_fdtvar.h>
 #include <arm/sunxi/sunxi_platform.h>
 #if defined(SOC_SUNXI_MC)
 #include <arm/sunxi/sunxi_mc_smp.h>
 #endif
 #include <libfdt.h>
 #define	SUNXI_REF_FREQ	24000000
 #define	SUN4I_TIMER_BASE	0x01c20c00
 #define	SUN4I_TIMER_SIZE	0x90
 #define	SUN4I_TIMER_1_CTRL	0x20
 #define	 SUN4I_TIMER_1_CTRL_CLK_SRC	__BITS(3,2)
 #define	 SUN4I_TIMER_1_CTRL_CLK_SRC_OSC24M	1
 #define	 SUN4I_TIMER_1_CTRL_RELOAD	__BIT(1)
 #define	 SUN4I_TIMER_1_CTRL_EN		__BIT(0)
 #define	SUN4I_TIMER_1_INTV_VALUE 0x24
 #define	SUN4I_TIMER_1_VAL	0x28
 #define	SUN4I_WDT_BASE		0x01c20c90
 #define	SUN4I_WDT_SIZE		0x10
 #define	SUN4I_WDT_CTRL		0x00
 #define	 SUN4I_WDT_CTRL_KEY	(0x333 << 1)
 #define	 SUN4I_WDT_CTRL_RESTART	__BIT(0)
 #define	SUN4I_WDT_MODE		0x04
 #define	 SUN4I_WDT_MODE_RST_EN	__BIT(1)
 #define	 SUN4I_WDT_MODE_EN	__BIT(0)
 #define	SUN6I_WDT_BASE		0x01c20ca0
 #define	SUN6I_WDT_SIZE		0x20
 #define	SUN6I_WDT_CFG		0x14
 #define	 SUN6I_WDT_CFG_SYS	__BIT(0)
 #define	SUN6I_WDT_MODE		0x18
 #define	 SUN6I_WDT_MODE_EN	__BIT(0)
 #define	SUN9I_WDT_BASE		0x06000ca0
 #define	SUN9I_WDT_SIZE		0x20
 #define	SUN9I_WDT_CFG		0x14
 #define	 SUN9I_WDT_CFG_SYS	__BIT(0)
 #define	SUN9I_WDT_MODE		0x18
 #define	 SUN9I_WDT_MODE_EN	__BIT(0)
 #define	SUN50I_H6_WDT_BASE	0x01c20ca0
 #define	SUN50I_H6_WDT_SIZE	0x20
 #define	SUN50I_H6_WDT_CFG	0x14
 #define	 SUN50I_H6_WDT_CFG_SYS	__BIT(0)
 #define	SUN50I_H6_WDT_MODE	0x18
 #define	 SUN50I_H6_WDT_MODE_EN	__BIT(0)
 extern struct arm32_bus_dma_tag arm_generic_dma_tag;
 extern struct bus_space arm_generic_bs_tag;
 extern struct bus_space arm_generic_a4x_bs_tag;
 #define	sunxi_dma_tag		arm_generic_dma_tag
 #define	sunxi_bs_tag		arm_generic_bs_tag
 #define	sunxi_a4x_bs_tag	arm_generic_a4x_bs_tag
 static const struct pmap_devmap *
 sunxi_platform_devmap(void)
+{
 	static const struct pmap_devmap devmap[] = {
 		DEVMAP_ENTRY(SUNXI_CORE_VBASE,
 			     SUNXI_CORE_PBASE,
 			     SUNXI_CORE_SIZE),
 		DEVMAP_ENTRY_END
 	};
 	return devmap;
+}
-#define	SUN8I_A83T_CPU_VBASE	(SUNXI_CORE_VBASE + SUNXI_CORE_SIZE)
+#define	SUNXI_MC_CPU_VBASE	(SUNXI_CORE_VBASE + SUNXI_CORE_SIZE)
-#define	SUN8I_A83T_CPU_PBASE	0x01700000
+#define	SUNXI_MC_CPU_PBASE	0x01700000
-#define	SUN8I_A83T_CPU_SIZE	0x00100000
+#define	SUNXI_MC_CPU_SIZE	0x00100000
 static const struct pmap_devmap *
 sun8i_a83t_platform_devmap(void)
+{
 	static const struct pmap_devmap devmap[] = {
 		DEVMAP_ENTRY(SUNXI_CORE_VBASE,
 			     SUNXI_CORE_PBASE,
 			     SUNXI_CORE_SIZE),
-		DEVMAP_ENTRY(SUN8I_A83T_CPU_VBASE,
+		DEVMAP_ENTRY(SUNXI_MC_CPU_VBASE,
-			     SUN8I_A83T_CPU_PBASE,
+			     SUNXI_MC_CPU_PBASE,
-			     SUN8I_A83T_CPU_SIZE),
+			     SUNXI_MC_CPU_SIZE),
 		DEVMAP_ENTRY_END
 	};
 	return devmap;
+}
 #define	SUN9I_A80_PRCM_VBASE	(SUNXI_MC_CPU_VBASE + SUNXI_MC_CPU_PBASE)
 #define	SUN9I_A80_PRCM_PBASE	0x08000000
 #define	SUN9I_A80_PRCM_SIZE	0x00100000
 static const struct pmap_devmap *
 sun9i_a80_platform_devmap(void)
+{
 	static const struct pmap_devmap devmap[] = {
 		DEVMAP_ENTRY(SUNXI_CORE_VBASE,
 			     SUNXI_CORE_PBASE,
 			     SUNXI_CORE_SIZE),
 		DEVMAP_ENTRY(SUNXI_MC_CPU_VBASE,
 			     SUNXI_MC_CPU_PBASE,
 			     SUNXI_MC_CPU_SIZE),
 		DEVMAP_ENTRY(SUN9I_A80_PRCM_VBASE,
 			     SUN9I_A80_PRCM_PBASE,
 			     SUN9I_A80_PRCM_SIZE),
 		DEVMAP_ENTRY_END
 	};
 	return devmap;
+}
 static void
 sunxi_platform_init_attach_args(struct fdt_attach_args *faa)
+{
 	faa->faa_bst = &sunxi_bs_tag;
 	faa->faa_a4x_bst = &sunxi_a4x_bs_tag;
 	faa->faa_dmat = &sunxi_dma_tag;
+}
 void sunxi_platform_early_putchar(char);
 void
 sunxi_platform_early_putchar(char c)
+{
 #ifdef CONSADDR
 #define CONSADDR_VA	((CONSADDR - SUNXI_CORE_PBASE) + SUNXI_CORE_VBASE)
 	volatile uint32_t *uartaddr = cpu_earlydevice_va_p() ?
 	    (volatile uint32_t *)CONSADDR_VA :
 	    (volatile uint32_t *)CONSADDR;
 	while ((le32toh(uartaddr[com_lsr]) & LSR_TXRDY) == 0)
+		;
 	uartaddr[com_data] = htole32(c);
 #endif
+}
 static void
 sunxi_platform_device_register(device_t self, void *aux)
+{
 	prop_dictionary_t prop = device_properties(self);
 	if (device_is_a(self, "rgephy")) {
 		/* Pine64+ and NanoPi NEO Plus2 gigabit ethernet workaround */
 		const char * compat[] = {
 			"pine64,pine64-plus",
 			"friendlyarm,nanopi-neo-plus2",
 			NULL
 		};
 		if (of_match_compatible(OF_finddevice("/"), compat)) {
 			prop_dictionary_set_bool(prop, "no-rx-delay", true);
+		}
+	}
 	if (device_is_a(self, "armgtmr")) {
 		/* Allwinner A64 has an unstable architectural timer */
 		const char * compat[] = {
 			"allwinner,sun50i-a64",
 			NULL
 		};
 		if (of_match_compatible(OF_finddevice("/"), compat)) {
 			prop_dictionary_set_bool(prop, "sun50i-a64-unstable-timer", true);
+		}
+	}
+}
 static u_int
 sunxi_platform_uart_freq(void)
+{
 	return SUNXI_REF_FREQ;
+}
 static void
 sunxi_platform_bootstrap(void)
+{
 	arm_fdt_cpu_bootstrap();
 	void *fdt_data = __UNCONST(fdtbus_get_data());
 	const int chosen_off = fdt_path_offset(fdt_data, "/chosen");
 	if (chosen_off < 0)
 		return;
 	if (match_bootconf_option(boot_args, "console", "fb")) {
 		const int framebuffer_off =
 		    fdt_path_offset(fdt_data, "/chosen/framebuffer");
 		if (framebuffer_off >= 0) {
 			const char *status = fdt_getprop(fdt_data,
 			    framebuffer_off, "status", NULL);
 			if (status == NULL || strncmp(status, "ok", 2) == 0) {
 				fdt_setprop_string(fdt_data, chosen_off,
 				    "stdout-path", "/chosen/framebuffer");
+			}
+		}
 	} else if (match_bootconf_option(boot_args, "console", "serial")) {
 		fdt_setprop_string(fdt_data, chosen_off,
 		    "stdout-path", "serial0:115200n8");
+	}
+}
 #if defined(SOC_SUNXI_MC)
 static int
-cpu_enable_sunxi_mc(int phandle)
+cpu_enable_sun8i_a83t(int phandle)
+{
 	uint64_t mpidr;
 	fdtbus_get_reg64(phandle, 0, &mpidr, NULL);
-	return sunxi_mc_smp_enable(mpidr);
+	return sun8i_a83t_smp_enable(mpidr);
+}
-ARM_CPU_METHOD(sun8i_a83t, "allwinner,sun8i-a83t-smp", cpu_enable_sunxi_mc);
+ARM_CPU_METHOD(sun8i_a83t, "allwinner,sun8i-a83t-smp", cpu_enable_sun8i_a83t);
 static int
 cpu_enable_sun9i_a80(int phandle)
+{
 	uint64_t mpidr;
 	fdtbus_get_reg64(phandle, 0, &mpidr, NULL);
 	return sun9i_a80_smp_enable(mpidr);
+}
 ARM_CPU_METHOD(sun9i_a80, "allwinner,sun9i-a80-smp", cpu_enable_sun9i_a80);
 #endif
 static void
 sun4i_platform_reset(void)
+{
 	bus_space_tag_t bst = &sunxi_bs_tag;
 	bus_space_handle_t bsh;
 	bus_space_map(bst, SUN4I_WDT_BASE, SUN4I_WDT_SIZE, 0, &bsh);
 	bus_space_write_4(bst, bsh, SUN4I_WDT_CTRL,
 	    SUN4I_WDT_CTRL_KEY | SUN4I_WDT_CTRL_RESTART);
 	for (;;) {
 		bus_space_write_4(bst, bsh, SUN4I_WDT_MODE,
 		    SUN4I_WDT_MODE_EN | SUN4I_WDT_MODE_RST_EN);
+	}
+}
 static void
 sun4i_platform_delay(u_int n)
+{
 	static bus_space_tag_t bst = &sunxi_bs_tag;
 	static bus_space_handle_t bsh = 0;
 	const long incs_per_us = SUNXI_REF_FREQ / 1000000;
 	long ticks = n * incs_per_us;
 	uint32_t cur, prev;
 	if (bsh == 0) {
 		bus_space_map(bst, SUN4I_TIMER_BASE, SUN4I_TIMER_SIZE, 0, &bsh);
 		/* Enable Timer 1 */
 		bus_space_write_4(bst, bsh, SUN4I_TIMER_1_INTV_VALUE, ~0U);
 		bus_space_write_4(bst, bsh, SUN4I_TIMER_1_CTRL,
 		    SUN4I_TIMER_1_CTRL_EN |
 		    SUN4I_TIMER_1_CTRL_RELOAD |
 		    __SHIFTIN(SUN4I_TIMER_1_CTRL_CLK_SRC_OSC24M,
 			      SUN4I_TIMER_1_CTRL_CLK_SRC));
+	}
 	prev = ~bus_space_read_4(bst, bsh, SUN4I_TIMER_1_VAL);
 	while (ticks > 0) {
 		cur = ~bus_space_read_4(bst, bsh, SUN4I_TIMER_1_VAL);
 		if (cur > prev)
 			ticks -= (cur - prev);
 		else
 			ticks -= (~0U - cur + prev);
 		prev = cur;
+	}
+}
 static void
 sun6i_platform_reset(void)
+{
 	bus_space_tag_t bst = &sunxi_bs_tag;
 	bus_space_handle_t bsh;
 	bus_space_map(bst, SUN6I_WDT_BASE, SUN6I_WDT_SIZE, 0, &bsh);
 	bus_space_write_4(bst, bsh, SUN6I_WDT_CFG, SUN6I_WDT_CFG_SYS);
 	bus_space_write_4(bst, bsh, SUN6I_WDT_MODE, SUN6I_WDT_MODE_EN);
+}
 static void
 sun9i_platform_reset(void)
+{
 	bus_space_tag_t bst = &sunxi_bs_tag;
 	bus_space_handle_t bsh;
 	bus_space_map(bst, SUN9I_WDT_BASE, SUN9I_WDT_SIZE, 0, &bsh);
 	bus_space_write_4(bst, bsh, SUN9I_WDT_CFG, SUN9I_WDT_CFG_SYS);
 	bus_space_write_4(bst, bsh, SUN9I_WDT_MODE, SUN9I_WDT_MODE_EN);
+}
 static void
 sun50i_h6_platform_reset(void)
+{
 	bus_space_tag_t bst = &sunxi_bs_tag;
 	bus_space_handle_t bsh;
 	bus_space_map(bst, SUN50I_H6_WDT_BASE, SUN50I_H6_WDT_SIZE, 0, &bsh);
 	bus_space_write_4(bst, bsh, SUN50I_H6_WDT_CFG, SUN50I_H6_WDT_CFG_SYS);
 	bus_space_write_4(bst, bsh, SUN50I_H6_WDT_MODE, SUN50I_H6_WDT_MODE_EN);
+}
 static const struct arm_platform sun4i_platform = {
 	.ap_devmap = sunxi_platform_devmap,
 	.ap_bootstrap = sunxi_platform_bootstrap,
 	.ap_init_attach_args = sunxi_platform_init_attach_args,
 	.ap_device_register = sunxi_platform_device_register,
 	.ap_reset = sun4i_platform_reset,
 	.ap_delay = sun4i_platform_delay,
 	.ap_uart_freq = sunxi_platform_uart_freq,
 };
 ARM_PLATFORM(sun4i_a10, "allwinner,sun4i-a10", &sun4i_platform);
 static const struct arm_platform sun5i_platform = {
 	.ap_devmap = sunxi_platform_devmap,
 	.ap_bootstrap = sunxi_platform_bootstrap,
 	.ap_init_attach_args = sunxi_platform_init_attach_args,
 	.ap_device_register = sunxi_platform_device_register,
 	.ap_reset = sun4i_platform_reset,
 	.ap_delay = sun4i_platform_delay,
 	.ap_uart_freq = sunxi_platform_uart_freq,
 };
 ARM_PLATFORM(sun5i_a13, "allwinner,sun5i-a13", &sun5i_platform);
 ARM_PLATFORM(sun5i_gr8, "nextthing,gr8", &sun5i_platform);
 static const struct arm_platform sun6i_platform = {
 	.ap_devmap = sunxi_platform_devmap,
 	.ap_bootstrap = sunxi_platform_bootstrap,
 	.ap_init_attach_args = sunxi_platform_init_attach_args,
 	.ap_device_register = sunxi_platform_device_register,
 	.ap_reset = sun6i_platform_reset,
 	.ap_delay = gtmr_delay,
 	.ap_uart_freq = sunxi_platform_uart_freq,
 	.ap_mpstart = arm_fdt_cpu_mpstart,
 };
 ARM_PLATFORM(sun6i_a31, "allwinner,sun6i-a31", &sun6i_platform);
 static const struct arm_platform sun7i_platform = {
 	.ap_devmap = sunxi_platform_devmap,
 	.ap_bootstrap = sunxi_platform_bootstrap,
 	.ap_init_attach_args = sunxi_platform_init_attach_args,
 	.ap_device_register = sunxi_platform_device_register,
 	.ap_reset = sun4i_platform_reset,
 	.ap_delay = sun4i_platform_delay,
 	.ap_uart_freq = sunxi_platform_uart_freq,
 	.ap_mpstart = arm_fdt_cpu_mpstart,
 };
 ARM_PLATFORM(sun7i_a20, "allwinner,sun7i-a20", &sun7i_platform);
 static const struct arm_platform sun8i_platform = {
 	.ap_devmap = sunxi_platform_devmap,
 	.ap_bootstrap = sunxi_platform_bootstrap,
 	.ap_init_attach_args = sunxi_platform_init_attach_args,
 	.ap_device_register = sunxi_platform_device_register,
 	.ap_reset = sun6i_platform_reset,
 	.ap_delay = gtmr_delay,
 	.ap_uart_freq = sunxi_platform_uart_freq,
 	.ap_mpstart = arm_fdt_cpu_mpstart,
 };
 ARM_PLATFORM(sun8i_h2plus, "allwinner,sun8i-h2-plus", &sun8i_platform);
 ARM_PLATFORM(sun8i_h3, "allwinner,sun8i-h3", &sun8i_platform);
 static const struct arm_platform sun8i_a83t_platform = {
 	.ap_devmap = sun8i_a83t_platform_devmap,
 	.ap_bootstrap = sunxi_platform_bootstrap,
 	.ap_init_attach_args = sunxi_platform_init_attach_args,
 	.ap_device_register = sunxi_platform_device_register,
 	.ap_reset = sun6i_platform_reset,
 	.ap_delay = gtmr_delay,
 	.ap_uart_freq = sunxi_platform_uart_freq,
 	.ap_mpstart = arm_fdt_cpu_mpstart,
 };
 ARM_PLATFORM(sun8i_a83t, "allwinner,sun8i-a83t", &sun8i_a83t_platform);
 static const struct arm_platform sun9i_platform = {
-	.ap_devmap = sunxi_platform_devmap,
+	.ap_devmap = sun9i_a80_platform_devmap,
 	.ap_bootstrap = sunxi_platform_bootstrap,
 	.ap_init_attach_args = sunxi_platform_init_attach_args,
 	.ap_device_register = sunxi_platform_device_register,
 	.ap_reset = sun9i_platform_reset,
 	.ap_delay = gtmr_delay,
 	.ap_uart_freq = sunxi_platform_uart_freq,
 	.ap_mpstart = arm_fdt_cpu_mpstart,
 };
 ARM_PLATFORM(sun9i_a80, "allwinner,sun9i-a80", &sun9i_platform);
 static const struct arm_platform sun50i_platform = {
 	.ap_devmap = sunxi_platform_devmap,
 	.ap_bootstrap = sunxi_platform_bootstrap,
 	.ap_init_attach_args = sunxi_platform_init_attach_args,
 	.ap_device_register = sunxi_platform_device_register,
 	.ap_reset = sun6i_platform_reset,
 	.ap_delay = gtmr_delay,
 	.ap_uart_freq = sunxi_platform_uart_freq,
 	.ap_mpstart = arm_fdt_cpu_mpstart,
 };
 ARM_PLATFORM(sun50i_a64, "allwinner,sun50i-a64", &sun50i_platform);
 ARM_PLATFORM(sun50i_h5, "allwinner,sun50i-h5", &sun50i_platform);
 static const struct arm_platform sun50i_h6_platform = {
 	.ap_devmap = sunxi_platform_devmap,
 	.ap_bootstrap = sunxi_platform_bootstrap,
 	.ap_init_attach_args = sunxi_platform_init_attach_args,
 	.ap_device_register = sunxi_platform_device_register,
 	.ap_reset = sun50i_h6_platform_reset,
 	.ap_delay = gtmr_delay,
 	.ap_uart_freq = sunxi_platform_uart_freq,
 	.ap_mpstart = arm_fdt_cpu_mpstart,
 };
 ARM_PLATFORM(sun50i_h6, "allwinner,sun50i-h6", &sun50i_h6_platform);