Thu Jan 3 15:10:37 2019 UTC ()
Add CPU_ID_CORTEXA15R4


(jmcneill)
diff -r1.4 -r1.5 src/sys/arch/arm/include/cputypes.h
cvs diff -r1.4 -r1.5 src/sys/arch/arm/include/cputypes.h (expand / switch to unified diff)

--- src/sys/arch/arm/include/cputypes.h 2018/11/24 15:44:13 1.4
+++ src/sys/arch/arm/include/cputypes.h 2019/01/03 15:10:37 1.5
@@ -1,14 +1,14 @@ @@ -1,14 +1,14 @@
1/* $NetBSD: cputypes.h,v 1.4 2018/11/24 15:44:13 skrll Exp $ */ 1/* $NetBSD: cputypes.h,v 1.5 2019/01/03 15:10:37 jmcneill Exp $ */
2 2
3/* 3/*
4 * Copyright (c) 1998, 2001 Ben Harris 4 * Copyright (c) 1998, 2001 Ben Harris
5 * Copyright (c) 1994-1996 Mark Brinicombe. 5 * Copyright (c) 1994-1996 Mark Brinicombe.
6 * Copyright (c) 1994 Brini. 6 * Copyright (c) 1994 Brini.
7 * All rights reserved. 7 * All rights reserved.
8 * 8 *
9 * This code is derived from software written for Brini by Mark Brinicombe 9 * This code is derived from software written for Brini by Mark Brinicombe
10 * 10 *
11 * Redistribution and use in source and binary forms, with or without 11 * Redistribution and use in source and binary forms, with or without
12 * modification, are permitted provided that the following conditions 12 * modification, are permitted provided that the following conditions
13 * are met: 13 * are met:
14 * 1. Redistributions of source code must retain the above copyright 14 * 1. Redistributions of source code must retain the above copyright
@@ -143,26 +143,27 @@ @@ -143,26 +143,27 @@
143#define CPU_ID_ARM1176JZS 0x410fb760 143#define CPU_ID_ARM1176JZS 0x410fb760
144#define CPU_ID_ARM11_P(n) ((n & 0xff07f000) == 0x4107b000) 144#define CPU_ID_ARM11_P(n) ((n & 0xff07f000) == 0x4107b000)
145#define CPU_ID_CORTEXA5R0 0x410fc050 145#define CPU_ID_CORTEXA5R0 0x410fc050
146#define CPU_ID_CORTEXA7R0 0x410fc070 146#define CPU_ID_CORTEXA7R0 0x410fc070
147#define CPU_ID_CORTEXA8R1 0x411fc080 147#define CPU_ID_CORTEXA8R1 0x411fc080
148#define CPU_ID_CORTEXA8R2 0x412fc080 148#define CPU_ID_CORTEXA8R2 0x412fc080
149#define CPU_ID_CORTEXA8R3 0x413fc080 149#define CPU_ID_CORTEXA8R3 0x413fc080
150#define CPU_ID_CORTEXA9R1 0x411fc090 150#define CPU_ID_CORTEXA9R1 0x411fc090
151#define CPU_ID_CORTEXA9R2 0x412fc090 151#define CPU_ID_CORTEXA9R2 0x412fc090
152#define CPU_ID_CORTEXA9R3 0x413fc090 152#define CPU_ID_CORTEXA9R3 0x413fc090
153#define CPU_ID_CORTEXA9R4 0x414fc090 153#define CPU_ID_CORTEXA9R4 0x414fc090
154#define CPU_ID_CORTEXA15R2 0x412fc0f0 154#define CPU_ID_CORTEXA15R2 0x412fc0f0
155#define CPU_ID_CORTEXA15R3 0x413fc0f0 155#define CPU_ID_CORTEXA15R3 0x413fc0f0
 156#define CPU_ID_CORTEXA15R4 0x414fc0f0
156#define CPU_ID_CORTEXA17R1 0x411fc0e0 157#define CPU_ID_CORTEXA17R1 0x411fc0e0
157#define CPU_ID_CORTEXA35R0 0x410fd040 158#define CPU_ID_CORTEXA35R0 0x410fd040
158#define CPU_ID_CORTEXA53R0 0x410fd030 159#define CPU_ID_CORTEXA53R0 0x410fd030
159#define CPU_ID_CORTEXA55R1 0x411fd050 160#define CPU_ID_CORTEXA55R1 0x411fd050
160#define CPU_ID_CORTEXA57R0 0x410fd070 161#define CPU_ID_CORTEXA57R0 0x410fd070
161#define CPU_ID_CORTEXA57R1 0x411fd070 162#define CPU_ID_CORTEXA57R1 0x411fd070
162#define CPU_ID_CORTEXA72R0 0x410fd080 163#define CPU_ID_CORTEXA72R0 0x410fd080
163#define CPU_ID_CORTEXA73R0 0x410fd090 164#define CPU_ID_CORTEXA73R0 0x410fd090
164#define CPU_ID_CORTEXA75R2 0x412fd0a0 165#define CPU_ID_CORTEXA75R2 0x412fd0a0
165 166
166#define CPU_ID_CORTEX_P(n) ((n & 0xff0fe000) == 0x410fc000) 167#define CPU_ID_CORTEX_P(n) ((n & 0xff0fe000) == 0x410fc000)
167#define CPU_ID_CORTEX_A5_P(n) ((n & 0xff0ff0f0) == 0x410fc050) 168#define CPU_ID_CORTEX_A5_P(n) ((n & 0xff0ff0f0) == 0x410fc050)
168#define CPU_ID_CORTEX_A7_P(n) ((n & 0xff0ff0f0) == 0x410fc070) 169#define CPU_ID_CORTEX_A7_P(n) ((n & 0xff0ff0f0) == 0x410fc070)