Wed Feb 6 13:15:59 2019 UTC ()
Trailing whitespace


(skrll)
diff -r1.1 -r1.2 src/sys/arch/arm/sunxi/sunxi_mc_mpstart.S
cvs diff -r1.1 -r1.2 src/sys/arch/arm/sunxi/sunxi_mc_mpstart.S (expand / switch to unified diff)

--- src/sys/arch/arm/sunxi/sunxi_mc_mpstart.S 2019/01/03 11:01:59 1.1
+++ src/sys/arch/arm/sunxi/sunxi_mc_mpstart.S 2019/02/06 13:15:59 1.2
@@ -1,14 +1,14 @@ @@ -1,14 +1,14 @@
1/* $NetBSD: sunxi_mc_mpstart.S,v 1.1 2019/01/03 11:01:59 jmcneill Exp $ */ 1/* $NetBSD: sunxi_mc_mpstart.S,v 1.2 2019/02/06 13:15:59 skrll Exp $ */
2 2
3/*- 3/*-
4 * Copyright (c) 2018 Jared McNeill <jmcneill@invisible.ca> 4 * Copyright (c) 2018 Jared McNeill <jmcneill@invisible.ca>
5 * All rights reserved. 5 * All rights reserved.
6 * 6 *
7 * Redistribution and use in source and binary forms, with or without 7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions 8 * modification, are permitted provided that the following conditions
9 * are met: 9 * are met:
10 * 1. Redistributions of source code must retain the above copyright 10 * 1. Redistributions of source code must retain the above copyright
11 * notice, this list of conditions and the following disclaimer. 11 * notice, this list of conditions and the following disclaimer.
12 * 2. Redistributions in binary form must reproduce the above copyright 12 * 2. Redistributions in binary form must reproduce the above copyright
13 * notice, this list of conditions and the following disclaimer in the 13 * notice, this list of conditions and the following disclaimer in the
14 * documentation and/or other materials provided with the distribution. 14 * documentation and/or other materials provided with the distribution.
@@ -32,27 +32,27 @@ @@ -32,27 +32,27 @@
32#include <arm/armreg.h> 32#include <arm/armreg.h>
33#include "assym.h" 33#include "assym.h"
34 34
35#define CCI_SNOOP_CTRL 0x000 35#define CCI_SNOOP_CTRL 0x000
36#define CCI_SNOOP_CTRL_DVM __BIT(1) 36#define CCI_SNOOP_CTRL_DVM __BIT(1)
37#define CCI_SNOOP_CTRL_SNOOP __BIT(0) 37#define CCI_SNOOP_CTRL_SNOOP __BIT(0)
38 38
39 R_TMP1 .req r8 39 R_TMP1 .req r8
40 R_VTOPDIFF .req r10 40 R_VTOPDIFF .req r10
41 41
42 .global _C_LABEL(sunxi_mc_mpstart) 42 .global _C_LABEL(sunxi_mc_mpstart)
43_C_LABEL(sunxi_mc_mpstart): 43_C_LABEL(sunxi_mc_mpstart):
44 44
45 adr R_TMP1, sunxi_mc_mpstart  45 adr R_TMP1, sunxi_mc_mpstart
46 ldr R_VTOPDIFF, =sunxi_mc_mpstart 46 ldr R_VTOPDIFF, =sunxi_mc_mpstart
47 sub R_VTOPDIFF, R_VTOPDIFF, R_TMP1 47 sub R_VTOPDIFF, R_VTOPDIFF, R_TMP1
48 48
49 mrc p15, 0, r4, c0, c0, 5 // MPIDR get 49 mrc p15, 0, r4, c0, c0, 5 // MPIDR get
50 and r4, #(MPIDR_AFF2|MPIDR_AFF1|MPIDR_AFF0) 50 and r4, #(MPIDR_AFF2|MPIDR_AFF1|MPIDR_AFF0)
51 51
52 mov r0, #0 52 mov r0, #0
53 ldr r1, =cpu_mpidr 53 ldr r1, =cpu_mpidr
54 sub r1, R_VTOPDIFF 54 sub r1, R_VTOPDIFF
551: 551:
56 56
57 ldr r2, [r1, r0, lsl #2] // r2 = cpu_mpidr[r0] 57 ldr r2, [r1, r0, lsl #2] // r2 = cpu_mpidr[r0]
58 cmp r2, r4 58 cmp r2, r4