Wed Feb 13 10:55:13 2019 UTC ()
Drop support for software interrupts. I had initially added that to cover
the three event types available on AMD, but Intel has seven of them, all
with weird and twisted meanings, and they require extra parameters.

Software interrupts should not be used anyway.


(maxv)
diff -r1.21 -r1.22 src/sys/dev/nvmm/x86/nvmm_x86_svm.c
cvs diff -r1.21 -r1.22 src/sys/dev/nvmm/x86/nvmm_x86_svm.c (expand / switch to unified diff)

--- src/sys/dev/nvmm/x86/nvmm_x86_svm.c 2019/02/13 07:04:12 1.21
+++ src/sys/dev/nvmm/x86/nvmm_x86_svm.c 2019/02/13 10:55:13 1.22
@@ -1,14 +1,14 @@ @@ -1,14 +1,14 @@
1/* $NetBSD: nvmm_x86_svm.c,v 1.21 2019/02/13 07:04:12 maxv Exp $ */ 1/* $NetBSD: nvmm_x86_svm.c,v 1.22 2019/02/13 10:55:13 maxv Exp $ */
2 2
3/* 3/*
4 * Copyright (c) 2018 The NetBSD Foundation, Inc. 4 * Copyright (c) 2018 The NetBSD Foundation, Inc.
5 * All rights reserved. 5 * All rights reserved.
6 * 6 *
7 * This code is derived from software contributed to The NetBSD Foundation 7 * This code is derived from software contributed to The NetBSD Foundation
8 * by Maxime Villard. 8 * by Maxime Villard.
9 * 9 *
10 * Redistribution and use in source and binary forms, with or without 10 * Redistribution and use in source and binary forms, with or without
11 * modification, are permitted provided that the following conditions 11 * modification, are permitted provided that the following conditions
12 * are met: 12 * are met:
13 * 1. Redistributions of source code must retain the above copyright 13 * 1. Redistributions of source code must retain the above copyright
14 * notice, this list of conditions and the following disclaimer. 14 * notice, this list of conditions and the following disclaimer.
@@ -20,27 +20,27 @@ @@ -20,27 +20,27 @@
20 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 20 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
21 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 21 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
22 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 22 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
23 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 23 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
24 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 24 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
25 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 25 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
26 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 26 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
27 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 27 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
28 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 28 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
29 * POSSIBILITY OF SUCH DAMAGE. 29 * POSSIBILITY OF SUCH DAMAGE.
30 */ 30 */
31 31
32#include <sys/cdefs.h> 32#include <sys/cdefs.h>
33__KERNEL_RCSID(0, "$NetBSD: nvmm_x86_svm.c,v 1.21 2019/02/13 07:04:12 maxv Exp $"); 33__KERNEL_RCSID(0, "$NetBSD: nvmm_x86_svm.c,v 1.22 2019/02/13 10:55:13 maxv Exp $");
34 34
35#include <sys/param.h> 35#include <sys/param.h>
36#include <sys/systm.h> 36#include <sys/systm.h>
37#include <sys/kernel.h> 37#include <sys/kernel.h>
38#include <sys/kmem.h> 38#include <sys/kmem.h>
39#include <sys/cpu.h> 39#include <sys/cpu.h>
40#include <sys/xcall.h> 40#include <sys/xcall.h>
41 41
42#include <uvm/uvm.h> 42#include <uvm/uvm.h>
43#include <uvm/uvm_page.h> 43#include <uvm/uvm_page.h>
44 44
45#include <x86/cputypes.h> 45#include <x86/cputypes.h>
46#include <x86/specialreg.h> 46#include <x86/specialreg.h>
@@ -678,33 +678,33 @@ svm_vcpu_inject(struct nvmm_machine *mac @@ -678,33 +678,33 @@ svm_vcpu_inject(struct nvmm_machine *mac
678 return EAGAIN; 678 return EAGAIN;
679 } 679 }
680 svm_event_waitexit_enable(vcpu, true); 680 svm_event_waitexit_enable(vcpu, true);
681 } else { 681 } else {
682 if (((vmcb->state.rflags & PSL_I) == 0) || 682 if (((vmcb->state.rflags & PSL_I) == 0) ||
683 ((vmcb->ctrl.intr & VMCB_CTRL_INTR_SHADOW) != 0)) { 683 ((vmcb->ctrl.intr & VMCB_CTRL_INTR_SHADOW) != 0)) {
684 svm_event_waitexit_enable(vcpu, false); 684 svm_event_waitexit_enable(vcpu, false);
685 return EAGAIN; 685 return EAGAIN;
686 } 686 }
687 } 687 }
688 err = 0; 688 err = 0;
689 break; 689 break;
690 case NVMM_EVENT_INTERRUPT_SW: 690 case NVMM_EVENT_INTERRUPT_SW:
691 type = SVM_EVENT_TYPE_SW_INT; 691 return EINVAL;
692 err = 0; 
693 break; 
694 case NVMM_EVENT_EXCEPTION: 692 case NVMM_EVENT_EXCEPTION:
695 type = SVM_EVENT_TYPE_EXC; 693 type = SVM_EVENT_TYPE_EXC;
696 if (event->vector == 2 || event->vector >= 32) 694 if (event->vector == 2 || event->vector >= 32)
697 return EINVAL; 695 return EINVAL;
 696 if (event->vector == 3 || event->vector == 0)
 697 return EINVAL;
698 err = svm_event_has_error(event->vector); 698 err = svm_event_has_error(event->vector);
699 break; 699 break;
700 default: 700 default:
701 return EINVAL; 701 return EINVAL;
702 } 702 }
703 703
704 vmcb->ctrl.eventinj = 704 vmcb->ctrl.eventinj =
705 __SHIFTIN(event->vector, VMCB_CTRL_EVENTINJ_VECTOR) | 705 __SHIFTIN(event->vector, VMCB_CTRL_EVENTINJ_VECTOR) |
706 __SHIFTIN(type, VMCB_CTRL_EVENTINJ_TYPE) | 706 __SHIFTIN(type, VMCB_CTRL_EVENTINJ_TYPE) |
707 __SHIFTIN(err, VMCB_CTRL_EVENTINJ_EV) | 707 __SHIFTIN(err, VMCB_CTRL_EVENTINJ_EV) |
708 __SHIFTIN(1, VMCB_CTRL_EVENTINJ_V) | 708 __SHIFTIN(1, VMCB_CTRL_EVENTINJ_V) |
709 __SHIFTIN(event->u.error, VMCB_CTRL_EVENTINJ_ERRORCODE); 709 __SHIFTIN(event->u.error, VMCB_CTRL_EVENTINJ_ERRORCODE);
710 710