 @@ -1,14 +1,14 @@
-/* $NetBSD: sun50i_a64_ccu.c,v 1.11 2019/01/30 01:24:00 jmcneill Exp $ */
+/* $NetBSD: sun50i_a64_ccu.c,v 1.12 2019/06/27 14:51:33 jmcneill Exp $ */
 /*-
  * Copyright (c) 2017 Jared McNeill <jmcneill@invisible.ca>
  * All rights reserved.
+ *
  * Redistribution and use in source and binary forms, with or without
  * modification, are permitted provided that the following conditions
  * are met:
  * 1. Redistributions of source code must retain the above copyright
  *    notice, this list of conditions and the following disclaimer.
  * 2. Redistributions in binary form must reproduce the above copyright
  *    notice, this list of conditions and the following disclaimer in the
  *    documentation and/or other materials provided with the distribution.
 @@ -18,65 +18,67 @@
  * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
  * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
  * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
  * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
  * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
  * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
  * SUCH DAMAGE.
  */
 #include <sys/cdefs.h>
-__KERNEL_RCSID(1, "$NetBSD: sun50i_a64_ccu.c,v 1.11 2019/01/30 01:24:00 jmcneill Exp $");
+__KERNEL_RCSID(1, "$NetBSD: sun50i_a64_ccu.c,v 1.12 2019/06/27 14:51:33 jmcneill Exp $");
 #include <sys/param.h>
 #include <sys/bus.h>
 #include <sys/device.h>
 #include <sys/systm.h>
 #include <dev/fdt/fdtvar.h>
 #include <arm/sunxi/sunxi_ccu.h>
 #include <arm/sunxi/sun50i_a64_ccu.h>
 #define	PLL_CPUX_CTRL_REG	0x000
 #define	PLL_AUDIO_CTRL_REG	0x008
 #define	PLL_VIDEO0_CTRL_REG	0x010
 #define	PLL_PERIPH0_CTRL_REG	0x028
 #define	PLL_PERIPH1_CTRL_REG	0x02c
 #define	PLL_VIDEO1_CTRL_REG	0x030
 #define	PLL_GPU_CTRL_REG	0x038
 #define	PLL_DE_CTRL_REG		0x048
 #define	AHB1_APB1_CFG_REG	0x054
 #define	APB2_CFG_REG		0x058
 #define	AHB2_CFG_REG		0x05c
 #define	BUS_CLK_GATING_REG0	0x060
 #define	BUS_CLK_GATING_REG1	0x064
 #define	BUS_CLK_GATING_REG2	0x068
 #define	BUS_CLK_GATING_REG3	0x06c
 #define	BUS_CLK_GATING_REG4	0x070
 #define	THS_CLK_REG		0x074
 #define	SDMMC0_CLK_REG		0x088
 #define	SDMMC1_CLK_REG		0x08c
 #define	SDMMC2_CLK_REG		0x090
 #define	USBPHY_CFG_REG		0x0cc
 #define	DRAM_CFG_REG		0x0f4
 #define	MBUS_RST_REG		0x0fc
 #define	DE_CLK_REG		0x104
 #define	TCON1_CLK_REG		0x11c
 #define	AC_DIG_CLK_REG		0x140
 #define	HDMI_CLK_REG		0x150
 #define	HDMI_SLOW_CLK_REG	0x154
 #define	GPU_CLK_REG		0x1a0
 #define	BUS_SOFT_RST_REG0	0x2c0
 #define	BUS_SOFT_RST_REG1	0x2c4
 #define	BUS_SOFT_RST_REG2	0x2c8
 #define	BUS_SOFT_RST_REG3	0x2d0
 #define	BUS_SOFT_RST_REG4	0x2d8
 static int sun50i_a64_ccu_match(device_t, cfdata_t, void *);
 static void sun50i_a64_ccu_attach(device_t, device_t, void *);
 static const char * const compatible[] = {
 	"allwinner,sun50i-a64-ccu",
 	NULL
 };
 @@ -143,26 +145,27 @@ static struct sunxi_ccu_reset sun50i_a64
 	SUNXI_CCU_RESET(A64_RST_BUS_UART2, BUS_SOFT_RST_REG4, 18),
 	SUNXI_CCU_RESET(A64_RST_BUS_UART3, BUS_SOFT_RST_REG4, 19),
 };
 static const char *ahb1_parents[] = { "losc", "hosc", "axi", "pll_periph0" };
 static const char *ahb2_parents[] = { "ahb1", "pll_periph0" };
 static const char *apb1_parents[] = { "ahb1" };
 static const char *apb2_parents[] = { "losc", "hosc", "pll_periph0" };
 static const char *mmc_parents[] = { "hosc", "pll_periph0_2x", "pll_periph1_2x" };
 static const char *ths_parents[] = { "hosc", NULL, NULL, NULL };
 static const char *de_parents[] = { "pll_periph0_2x", "pll_de" };
 static const char *hdmi_parents[] = { "pll_video0", "pll_video1" };
 static const char *tcon1_parents[] = { "pll_video0", NULL, "pll_video1", NULL };
 static const char *gpu_parents[] = { "gpu" };
 static const struct sunxi_ccu_nkmp_tbl sun50i_a64_cpux_table[] = {
 	{ 60000000, 9, 0, 0, 2 },
 	{ 66000000, 10, 0, 0, 2 },
 	{ 72000000, 11, 0, 0, 2 },
 	{ 78000000, 12, 0, 0, 2 },
 	{ 84000000, 13, 0, 0, 2 },
 	{ 90000000, 14, 0, 0, 2 },
 	{ 96000000, 15, 0, 0, 2 },
 	{ 102000000, 16, 0, 0, 2 },
 	{ 108000000, 17, 0, 0, 2 },
 	{ 114000000, 18, 0, 0, 2 },
 	{ 120000000, 9, 0, 0, 1 },
 @@ -300,26 +303,39 @@ static struct sunxi_ccu_clk sun50i_a64_c
 	SUNXI_CCU_FRACTIONAL(A64_CLK_PLL_DE, "pll_de", "hosc",
 	    PLL_DE_CTRL_REG,		/* reg */
 	    __BITS(14,8),		/* m */
 ,				/* m_min */
 ,				/* m_max */
 	    __BIT(24),			/* div_en */
 	    __BIT(25),			/* frac_sel */
 	    270000000, 297000000,	/* frac values */
 	    __BITS(3,0),		/* prediv */
 ,				/* prediv_val */
 	    __BIT(31),			/* enable */
 	    SUNXI_CCU_FRACTIONAL_PLUSONE | SUNXI_CCU_FRACTIONAL_SET_ENABLE),
 	SUNXI_CCU_FRACTIONAL(A64_CLK_PLL_GPU, "pll_gpu", "hosc",
 	    PLL_GPU_CTRL_REG,		/* reg */
 	    __BITS(14,8),		/* m */
 ,				/* m_min */
 ,			/* m_max */
 	    __BIT(24),			/* div_en */
 	    __BIT(25),			/* frac_sel */
 	    270000000, 297000000,	/* frac values */
 	    __BITS(3,0),		/* prediv */
 ,				/* prediv_val */
 	    __BIT(31),			/* enable */
 	    SUNXI_CCU_FRACTIONAL_PLUSONE | SUNXI_CCU_FRACTIONAL_SET_ENABLE),
 	SUNXI_CCU_PREDIV(A64_CLK_AHB1, "ahb1", ahb1_parents,
 	    AHB1_APB1_CFG_REG,	/* reg */
 	    __BITS(7,6),	/* prediv */
 	    __BIT(3),		/* prediv_sel */
 	    __BITS(5,4),	/* div */
 	    __BITS(13,12),	/* sel */
 	    SUNXI_CCU_PREDIV_POWER_OF_TWO),
 	SUNXI_CCU_PREDIV(A64_CLK_AHB2, "ahb2", ahb2_parents,
 	    AHB2_CFG_REG,	/* reg */
 ,			/* prediv */
 	    __BIT(1),		/* prediv_sel */
 ,			/* div */
 @@ -388,26 +404,33 @@ static struct sunxi_ccu_clk sun50i_a64_c
 	    __BIT(31),		/* enable */
 ),
 	SUNXI_CCU_GATE(A64_CLK_HDMI_DDC, "hdmi-ddc", "hosc",
 	    HDMI_SLOW_CLK_REG, 31),
 	SUNXI_CCU_DIV_GATE(A64_CLK_TCON1, "tcon1", tcon1_parents,
 	    TCON1_CLK_REG,	/* reg */
 	    __BITS(3,0),	/* div */
 	    __BITS(25,24),	/* sel */
 	    __BIT(31),		/* enable */
 ),
 	SUNXI_CCU_DIV_GATE(A64_CLK_GPU, "gpu", gpu_parents,
 	    GPU_CLK_REG,	/* reg */
 	    __BITS(2,0),	/* div */
 ,			/* sel */
 	    __BIT(31),		/* enable */
 ),
 	SUNXI_CCU_GATE(A64_CLK_BUS_MIPI_DSI, "bus-mipi-dsi", "ahb1",
 	    BUS_CLK_GATING_REG0, 1),
 	SUNXI_CCU_GATE(A64_CLK_BUS_CE, "bus-ce", "ahb1",
 	    BUS_CLK_GATING_REG0, 5),
 	SUNXI_CCU_GATE(A64_CLK_BUS_DMA, "bus-dma", "ahb1",
 	    BUS_CLK_GATING_REG0, 6),
 	SUNXI_CCU_GATE(A64_CLK_BUS_MMC0, "bus-mmc0", "ahb1",
 	    BUS_CLK_GATING_REG0, 8),
 	SUNXI_CCU_GATE(A64_CLK_BUS_MMC1, "bus-mmc1", "ahb1",
 	    BUS_CLK_GATING_REG0, 9),
 	SUNXI_CCU_GATE(A64_CLK_BUS_MMC2, "bus-mmc2", "ahb1",
 	    BUS_CLK_GATING_REG0, 10),
 	SUNXI_CCU_GATE(A64_CLK_BUS_NAND, "bus-nand", "ahb1",