Fri Aug 30 13:11:28 2019 UTC ()
 Add definitions of AMD's CPUID Fn8000_0008 %ebx.


(msaitoh)
diff -r1.150 -r1.151 src/sys/arch/x86/include/specialreg.h
cvs diff -r1.150 -r1.151 src/sys/arch/x86/include/specialreg.h (expand / switch to unified diff)

--- src/sys/arch/x86/include/specialreg.h 2019/07/26 10:03:40 1.150
+++ src/sys/arch/x86/include/specialreg.h 2019/08/30 13:11:28 1.151
@@ -1,14 +1,14 @@ @@ -1,14 +1,14 @@
1/* $NetBSD: specialreg.h,v 1.150 2019/07/26 10:03:40 msaitoh Exp $ */ 1/* $NetBSD: specialreg.h,v 1.151 2019/08/30 13:11:28 msaitoh Exp $ */
2 2
3/* 3/*
4 * Copyright (c) 2014-2019 The NetBSD Foundation, Inc. 4 * Copyright (c) 2014-2019 The NetBSD Foundation, Inc.
5 * All rights reserved. 5 * All rights reserved.
6 * 6 *
7 * Redistribution and use in source and binary forms, with or without 7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions 8 * modification, are permitted provided that the following conditions
9 * are met: 9 * are met:
10 * 1. Redistributions of source code must retain the above copyright 10 * 1. Redistributions of source code must retain the above copyright
11 * notice, this list of conditions and the following disclaimer. 11 * notice, this list of conditions and the following disclaimer.
12 * 2. Redistributions in binary form must reproduce the above copyright 12 * 2. Redistributions in binary form must reproduce the above copyright
13 * notice, this list of conditions and the following disclaimer in the 13 * notice, this list of conditions and the following disclaimer in the
14 * documentation and/or other materials provided with the distribution. 14 * documentation and/or other materials provided with the distribution.
@@ -702,26 +702,58 @@ @@ -702,26 +702,58 @@
702#define CPUID_APM_CPB 0x00000200 /* Core performance boost */ 702#define CPUID_APM_CPB 0x00000200 /* Core performance boost */
703#define CPUID_APM_EFF 0x00000400 /* Effective Frequency (read-only) */ 703#define CPUID_APM_EFF 0x00000400 /* Effective Frequency (read-only) */
704#define CPUID_APM_PROCFI 0x00000800 /* Proc Feedback Interface */ 704#define CPUID_APM_PROCFI 0x00000800 /* Proc Feedback Interface */
705#define CPUID_APM_PROCPR 0x00001000 /* Proc Power Reporting */ 705#define CPUID_APM_PROCPR 0x00001000 /* Proc Power Reporting */
706#define CPUID_APM_CONNSTBY 0x00002000 /* Connected Standby */ 706#define CPUID_APM_CONNSTBY 0x00002000 /* Connected Standby */
707#define CPUID_APM_RAPL 0x00004000 /* Running Average Power Limit */ 707#define CPUID_APM_RAPL 0x00004000 /* Running Average Power Limit */
708 708
709#define CPUID_APM_FLAGS "\20" \ 709#define CPUID_APM_FLAGS "\20" \
710 "\1" "TS" "\2" "FID" "\3" "VID" "\4" "TTP" \ 710 "\1" "TS" "\2" "FID" "\3" "VID" "\4" "TTP" \
711 "\5" "HTC" "\6" "STC" "\7" "100" "\10" "HWP" \ 711 "\5" "HTC" "\6" "STC" "\7" "100" "\10" "HWP" \
712 "\11" "TSC" "\12" "CPB" "\13" "EffFreq" "\14" "PROCFI" \ 712 "\11" "TSC" "\12" "CPB" "\13" "EffFreq" "\14" "PROCFI" \
713 "\15" "PROCPR" "\16" "CONNSTBY" "\17" "RAPL" 713 "\15" "PROCPR" "\16" "CONNSTBY" "\17" "RAPL"
714 714
 715/*
 716 * AMD Processor Capacity Parameters and Extended Features
 717 * CPUID Fn8000_0008
 718 * %eax: Long Mode Size Identifiers
 719 * %ebx: Extended Feature Identifiers
 720 * %ecx: Size Identifiers
 721 */
 722
 723/* %ebx */
 724#define CPUID_CAPEX_CLZERO __BIT(0) /* CLZERO instruction */
 725#define CPUID_CAPEX_IRPERF __BIT(1) /* InstRetCntMsr */
 726#define CPUID_CAPEX_XSAVEERPTR __BIT(2) /* RstrFpErrPtrs by XRSTOR */
 727#define CPUID_CAPEX_RDPRU __BIT(4) /* RDPRU instruction */
 728#define CPUID_CAPEX_WBNOINVD __BIT(9) /* WBNOINVD instruction */
 729#define CPUID_CAPEX_IBPB __BIT(12) /* Speculation Control IBPB */
 730#define CPUID_CAPEX_IBRS __BIT(14) /* Speculation Control IBRS */
 731#define CPUID_CAPEX_STIBP __BIT(15) /* Speculation Control STIBP */
 732#define CPUID_CAPEX_IBRS_ALWAYSON __BIT(16) /* IBRS always on mode */
 733#define CPUID_CAPEX_STIBP_ALWAYSON __BIT(17) /* STIBP always on mode */
 734#define CPUID_CAPEX_PREFER_IBRS __BIT(18) /* IBRS preferred */
 735#define CPUID_CAPEX_SSBD __BIT(24) /* Speculation Control SSBD */
 736#define CPUID_CAPEX_VIRT_SSBD __BIT(25) /* Virt Spec Control SSBD */
 737#define CPUID_CAPEX_SSB_NO __BIT(26) /* SSBD not required */
 738
 739#define CPUID_CAPEX_FLAGS "\20" \
 740 "\1CLZERO" "\2IRPERF" "\3XSAVEERPTR" \
 741 "\5RDPRU" "\7B6" \
 742 "\11B8" "\12WBNOINVD" "\12B10" \
 743 "\15IBPB" "\16B13" "\17IBRS" "\20STIBP" \
 744 "\21IBRS_ALWAYSON" "\22STIBP_ALWAYSON" "\23PREFER_IBRS" "\24B19" \
 745 "\31SSBD" "\32VIRT_SSBD" "\33SSB_NO"
 746
715/* AMD Fn8000000a %edx features (SVM features) */ 747/* AMD Fn8000000a %edx features (SVM features) */
716#define CPUID_AMD_SVM_NP 0x00000001 748#define CPUID_AMD_SVM_NP 0x00000001
717#define CPUID_AMD_SVM_LbrVirt 0x00000002 749#define CPUID_AMD_SVM_LbrVirt 0x00000002
718#define CPUID_AMD_SVM_SVML 0x00000004 750#define CPUID_AMD_SVM_SVML 0x00000004
719#define CPUID_AMD_SVM_NRIPS 0x00000008 751#define CPUID_AMD_SVM_NRIPS 0x00000008
720#define CPUID_AMD_SVM_TSCRateCtrl 0x00000010 752#define CPUID_AMD_SVM_TSCRateCtrl 0x00000010
721#define CPUID_AMD_SVM_VMCBCleanBits 0x00000020 753#define CPUID_AMD_SVM_VMCBCleanBits 0x00000020
722#define CPUID_AMD_SVM_FlushByASID 0x00000040 754#define CPUID_AMD_SVM_FlushByASID 0x00000040
723#define CPUID_AMD_SVM_DecodeAssist 0x00000080 755#define CPUID_AMD_SVM_DecodeAssist 0x00000080
724#define CPUID_AMD_SVM_PauseFilter 0x00000400 756#define CPUID_AMD_SVM_PauseFilter 0x00000400
725#define CPUID_AMD_SVM_PFThreshold 0x0x001000 /* PAUSE filter threshold */ 757#define CPUID_AMD_SVM_PFThreshold 0x0x001000 /* PAUSE filter threshold */
726#define CPUID_AMD_SVM_AVIC 0x00002000 /* AMD Virtual intr. ctrl */ 758#define CPUID_AMD_SVM_AVIC 0x00002000 /* AMD Virtual intr. ctrl */
727#define CPUID_AMD_SVM_V_VMSAVE_VMLOAD 0x00008000 /* Virtual VM{SAVE/LOAD} */ 759#define CPUID_AMD_SVM_V_VMSAVE_VMLOAD 0x00008000 /* Virtual VM{SAVE/LOAD} */