 @@ -1,14 +1,14 @@
-/* $NetBSD: ciphy.c,v 1.26.10.1 2019/05/13 12:40:13 martin Exp $ */
+/* $NetBSD: ciphy.c,v 1.26.10.2 2019/09/01 10:19:04 martin Exp $ */
 /*-
  * Copyright (c) 2004
  *	Bill Paul <wpaul@windriver.com>.  All rights reserved.
+ *
  * Redistribution and use in source and binary forms, with or without
  * modification, are permitted provided that the following conditions
  * are met:
  * 1. Redistributions of source code must retain the above copyright
  *    notice, this list of conditions and the following disclaimer.
  * 2. Redistributions in binary form must reproduce the above copyright
  *    notice, this list of conditions and the following disclaimer in the
  *    documentation and/or other materials provided with the distribution.
 @@ -25,27 +25,27 @@
  * ARE DISCLAIMED.  IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD
  * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
  * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
  * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
  * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
  * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
  * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
  * THE POSSIBILITY OF SUCH DAMAGE.
+ *
  * FreeBSD: src/sys/dev/mii/ciphy.c,v 1.2 2005/01/06 01:42:55 imp Exp
  */
 #include <sys/cdefs.h>
-__KERNEL_RCSID(0, "$NetBSD: ciphy.c,v 1.26.10.1 2019/05/13 12:40:13 martin Exp $");
+__KERNEL_RCSID(0, "$NetBSD: ciphy.c,v 1.26.10.2 2019/09/01 10:19:04 martin Exp $");
 /*
  * Driver for the Cicada CS8201 10/100/1000 copper PHY.
  */
 #include <sys/param.h>
 #include <sys/systm.h>
 #include <sys/device.h>
 #include <sys/kernel.h>
 #include <sys/socket.h>
 #include <sys/bus.h>
 #include <net/if.h>
 @@ -73,49 +73,61 @@ static const struct mii_phy_funcs ciphy_
 	ciphy_service, ciphy_status, mii_phy_reset,
 };
 static const struct mii_phydesc ciphys[] = {
 	{ MII_OUI_CICADA,		MII_MODEL_CICADA_CS8201,
 	  MII_STR_CICADA_CS8201 },
 	{ MII_OUI_CICADA,		MII_MODEL_CICADA_CS8201A,
 	  MII_STR_CICADA_CS8201A },
 	{ MII_OUI_CICADA,		MII_MODEL_CICADA_CS8201B,
 	  MII_STR_CICADA_CS8201B },
 	{ MII_OUI_CICADA,		MII_MODEL_CICADA_CS8204,
 	  MII_STR_CICADA_CS8204 },
 	{ MII_OUI_CICADA,		MII_MODEL_CICADA_VSC8211,
 	  MII_STR_CICADA_VSC8211 },
 	{ MII_OUI_CICADA,		MII_MODEL_CICADA_CS8244,
 	  MII_STR_CICADA_CS8244 },
 	{ MII_OUI_xxCICADA,		MII_MODEL_CICADA_CS8201,
 	  MII_STR_CICADA_CS8201 },
 	{ MII_OUI_xxCICADA,		MII_MODEL_CICADA_CS8201A,
 	  MII_STR_CICADA_CS8201A },
 	{ MII_OUI_xxCICADA,		MII_MODEL_xxCICADA_CS8201B,
 	  MII_STR_xxCICADA_CS8201B },
 	{ MII_OUI_VITESSE,		MII_MODEL_VITESSE_VSC8601,
 	  MII_STR_VITESSE_VSC8601 },
 	{ 0,				0,
 	  NULL },
 };
 static int
 ciphymatch(device_t parent, cfdata_t match,
     void *aux)
+{
 	struct mii_attach_args *ma = aux;
 	if (mii_phy_match(ma, ciphys) != NULL)
-		return (10);
+		return 10;
-	return (0);
+	return 0;
+}
 static void
 ciphyattach(device_t parent, device_t self, void *aux)
+{
 	struct mii_softc *sc = device_private(self);
 	struct mii_attach_args *ma = aux;
 	struct mii_data *mii = ma->mii_data;
 	const struct mii_phydesc *mpd;
 	mpd = mii_phy_match(ma, ciphys);
 	aprint_naive(": Media interface\n");
 	aprint_normal(": %s, rev. %d\n", mpd->mpd_name, MII_REV(ma->mii_id2));
 @@ -141,131 +153,117 @@ ciphyattach(device_t parent, device_t se
 	else
 		mii_phy_add_media(sc);
 	aprint_normal("\n");
+}
 static int
 ciphy_service(struct mii_softc *sc, struct mii_data *mii, int cmd)
+{
 	struct ifmedia_entry *ife = mii->mii_media.ifm_cur;
 	int reg, speed, gig;
 	switch (cmd) {
 	case MII_POLLSTAT:
-		/*
+		/* If we're not polling our PHY instance, just return. */
 		 * If we're not polling our PHY instance, just return.
 		 */
 		if (IFM_INST(ife->ifm_media) != sc->mii_inst)
-			return (0);
+			return 0;
 		break;
 	case MII_MEDIACHG:
 		/*
 		 * If the media indicates a different PHY instance,
 		 * isolate ourselves.
 		 */
 		if (IFM_INST(ife->ifm_media) != sc->mii_inst) {
 			reg = PHY_READ(sc, MII_BMCR);
 			PHY_WRITE(sc, MII_BMCR, reg | BMCR_ISO);
-			return (0);
+			return 0;
+		}
-		/*
+		/* If the interface is not up, don't do anything. */
 		 * If the interface is not up, don't do anything.
 		 */
 		if ((mii->mii_ifp->if_flags & IFF_UP) == 0)
 			break;
 		ciphy_fixup(sc);	/* XXX hardware bug work-around */
 		switch (IFM_SUBTYPE(ife->ifm_media)) {
 		case IFM_AUTO:
 #ifdef foo
-			/*
+			/* If we're already in auto mode, just return. */
-			 * If we're already in auto mode, just return.
+			if (PHY_READ(sc, MII_BMCR) & BMCR_AUTOEN)
-			 */
+				return 0;
 			if (PHY_READ(sc, CIPHY_MII_BMCR) & CIPHY_BMCR_AUTOEN)
 				return (0);
 #endif
 			(void) mii_phy_auto(sc, 0);
 			break;
 		case IFM_1000_T:
-			speed = CIPHY_S1000;
+			speed = BMCR_S1000;
 			goto setit;
 		case IFM_100_TX:
-			speed = CIPHY_S100;
+			speed = BMCR_S100;
 			goto setit;
 		case IFM_10_T:
-			speed = CIPHY_S10;
+			speed = BMCR_S10;
 setit:
 			if ((ife->ifm_media & IFM_FDX) != 0) {
-				speed |= CIPHY_BMCR_FDX;
+				speed |= BMCR_FDX;
-				gig = CIPHY_1000CTL_AFD;
+				gig = GTCR_ADV_1000TFDX;
-			} else {
+			} else
-				gig = CIPHY_1000CTL_AHD;
+				gig = GTCR_ADV_1000THDX;
 			PHY_WRITE(sc, MII_100T2CR, 0);
-			PHY_WRITE(sc, CIPHY_MII_1000CTL, 0);
+			PHY_WRITE(sc, MII_BMCR, speed);
-			PHY_WRITE(sc, CIPHY_MII_BMCR, speed);
+			PHY_WRITE(sc, MII_ANAR, ANAR_CSMA);
 			PHY_WRITE(sc, CIPHY_MII_ANAR, CIPHY_SEL_TYPE);
 			if (IFM_SUBTYPE(ife->ifm_media) != IFM_1000_T)
 				break;
-			PHY_WRITE(sc, CIPHY_MII_1000CTL, gig);
+			PHY_WRITE(sc, MII_100T2CR, gig);
-			PHY_WRITE(sc, CIPHY_MII_BMCR,
+			PHY_WRITE(sc, MII_BMCR,
-			    speed|CIPHY_BMCR_AUTOEN|CIPHY_BMCR_STARTNEG);
+			    speed | BMCR_AUTOEN | BMCR_STARTNEG);
 			/*
 			 * When setting the link manually, one side must
 			 * be the master and the other the slave. However
 			 * ifmedia doesn't give us a good way to specify
 			 * this, so we fake it by using one of the LINK
 			 * flags. If LINK0 is set, we program the PHY to
 			 * be a master, otherwise it's a slave.
 			 */
 			if ((mii->mii_ifp->if_flags & IFF_LINK0)) {
-				PHY_WRITE(sc, CIPHY_MII_1000CTL,
+				PHY_WRITE(sc, MII_100T2CR,
-				    gig|CIPHY_1000CTL_MSE|CIPHY_1000CTL_MSC);
+				    gig | GTCR_MAN_MS | GTCR_ADV_MS);
 			} else {
-				PHY_WRITE(sc, CIPHY_MII_1000CTL,
+				PHY_WRITE(sc, MII_100T2CR, gig | GTCR_MAN_MS);
 				    gig|CIPHY_1000CTL_MSE);
+			}
 			break;
 		case IFM_NONE:
-			PHY_WRITE(sc, MII_BMCR, BMCR_ISO|BMCR_PDOWN);
+			PHY_WRITE(sc, MII_BMCR, BMCR_ISO | BMCR_PDOWN);
 			break;
 		case IFM_100_T4:
 		default:
-			return (EINVAL);
+			return EINVAL;
+		}
 		break;
 	case MII_TICK:
-		/*
+		/* If we're not currently selected, just return. */
 		 * If we're not currently selected, just return.
 		 */
 		if (IFM_INST(ife->ifm_media) != sc->mii_inst)
-			return (0);
+			return 0;
-		/*
+		/* Is the interface even up? */
 		 * Is the interface even up?
 		 */
 		if ((mii->mii_ifp->if_flags & IFF_UP) == 0)
-			return (0);
+			return 0;
-		/*
+		/* Only used for autonegotiation. */
 		 * Only used for autonegotiation.
 		 */
 		if ((IFM_SUBTYPE(ife->ifm_media) != IFM_AUTO) &&
 		    (IFM_SUBTYPE(ife->ifm_media) != IFM_1000_T)) {
 			/*
 			 * Reset autonegotiation timer to 0 just to make sure
 			 * the future autonegotiation start with 0.
 			 */
 			sc->mii_ticks = 0;
 			break;
+		}
 		/*
 		 * Check to see if we have link.  If we do, we don't
 		 * need to restart the autonegotiation process.  Read
 @@ -280,73 +278,71 @@ setit:
 			sc->mii_ticks = 0;
 			/* See above. */
 			break;
+		}
 		/*
 		 * mii_ticks == 0 means it's the first tick after changing the
 		 * media or the link became down since the last tick
 		 * (see above), so return with 0 to update the status.
 		 */
 		if (sc->mii_ticks++ == 0)
 			break;
-		/*
+		/* Only retry autonegotiation every N seconds. */
 		 * Only retry autonegotiation every N seconds.
 		 */
 		if (sc->mii_ticks <= MII_ANEGTICKS_GIGE)
 			break;
 		mii_phy_auto(sc, 0);
-		return (0);
+		return 0;
+	}
 	/* Update the media status. */
 	ciphy_status(sc);
 	/*
 	 * Callback if something changed. Note that we need to poke
 	 * apply fixups for certain PHY revs.
 	 */
 	if (sc->mii_media_active != mii->mii_media_active ||
 	    sc->mii_media_status != mii->mii_media_status ||
 	    cmd == MII_MEDIACHG) {
 		ciphy_fixup(sc);
+	}
 	mii_phy_update(sc, cmd);
-	return (0);
+	return 0;
+}
 static void
 ciphy_status(struct mii_softc *sc)
+{
 	struct mii_data *mii = sc->mii_pdata;
 	int bmsr, bmcr;
 	mii->mii_media_status = IFM_AVALID;
 	mii->mii_media_active = IFM_ETHER;
 	bmsr = PHY_READ(sc, MII_BMSR) | PHY_READ(sc, MII_BMSR);
 	if (bmsr & BMSR_LINK)
 		mii->mii_media_status |= IFM_ACTIVE;
-	bmcr = PHY_READ(sc, CIPHY_MII_BMCR);
+	bmcr = PHY_READ(sc, MII_BMCR);
-	if (bmcr & CIPHY_BMCR_LOOP)
+	if (bmcr & BMCR_LOOP)
 		mii->mii_media_active |= IFM_LOOP;
-	if (bmcr & CIPHY_BMCR_AUTOEN) {
+	if (bmcr & BMCR_AUTOEN) {
-		if ((bmsr & CIPHY_BMSR_ACOMP) == 0) {
+		if ((bmsr & BMSR_ACOMP) == 0) {
 			/* Erg, still trying, I guess... */
 			mii->mii_media_active |= IFM_NONE;
 			return;
+		}
+	}
 	bmsr = PHY_READ(sc, CIPHY_MII_AUXCSR);
 	switch (bmsr & CIPHY_AUXCSR_SPEED) {
 	case CIPHY_SPEED10:
 		mii->mii_media_active |= IFM_10_T;
 		break;
 	case CIPHY_SPEED100:
 		mii->mii_media_active |= IFM_100_TX;
 @@ -378,38 +374,39 @@ ciphy_reset(struct mii_softc *sc)
+}
 #define PHY_SETBIT(x, y, z) \
 	PHY_WRITE(x, y, (PHY_READ(x, y) | (z)))
 #define PHY_CLRBIT(x, y, z) \
 	PHY_WRITE(x, y, (PHY_READ(x, y) & ~(z)))
 static void
 ciphy_fixup(struct mii_softc *sc)
+{
 	uint16_t		model;
 	uint16_t		status, speed;
-	model = MII_MODEL(PHY_READ(sc, CIPHY_MII_PHYIDR2));
+	model = MII_MODEL(PHY_READ(sc, MII_PHYIDR2));
 	status = PHY_READ(sc, CIPHY_MII_AUXCSR);
 	speed = status & CIPHY_AUXCSR_SPEED;
 	if (device_is_a(device_parent(sc->mii_dev), "nfe")) {
-		/* need to set for 2.5V RGMII for NVIDIA adapters */
+		/* Need to set for 2.5V RGMII for NVIDIA adapters */
 		PHY_SETBIT(sc, CIPHY_MII_ECTL1, CIPHY_INTSEL_RGMII);
 		PHY_SETBIT(sc, CIPHY_MII_ECTL1, CIPHY_IOVOL_2500MV);
+	}
 	switch (model) {
 	case MII_MODEL_CICADA_CS8201:
 	case MII_MODEL_CICADA_CS8204:
 		/* Turn off "aux mode" (whatever that means) */
 		PHY_SETBIT(sc, CIPHY_MII_AUXCSR, CIPHY_AUXCSR_MDPPS);
 		/*
 		 * Work around speed polling bug in VT3119/VT3216
 		 * when using MII in full duplex mode.
 		 */
 		if ((speed == CIPHY_SPEED10 || speed == CIPHY_SPEED100) &&
 		    (status & CIPHY_AUXCSR_FDX)) {
 			PHY_SETBIT(sc, CIPHY_MII_10BTCSR, CIPHY_10BTCSR_ECHO);
 		} else {
 			PHY_CLRBIT(sc, CIPHY_MII_10BTCSR, CIPHY_10BTCSR_ECHO);
 @@ -420,26 +417,29 @@ ciphy_fixup(struct mii_softc *sc)
 		break;
 	case MII_MODEL_CICADA_CS8201A:
 	case MII_MODEL_CICADA_CS8201B:
 		/*
 		 * Work around speed polling bug in VT3119/VT3216
 		 * when using MII in full duplex mode.
 		 */
 		if ((speed == CIPHY_SPEED10 || speed == CIPHY_SPEED100) &&
 		    (status & CIPHY_AUXCSR_FDX)) {
 			PHY_SETBIT(sc, CIPHY_MII_10BTCSR, CIPHY_10BTCSR_ECHO);
-		} else {
+		} else
 			PHY_CLRBIT(sc, CIPHY_MII_10BTCSR, CIPHY_10BTCSR_ECHO);
 		break;
 	case MII_MODEL_CICADA_VSC8211:
 	case MII_MODEL_CICADA_CS8244:
 	case MII_MODEL_VITESSE_VSC8601:
 		break;
 	default:
 		aprint_error_dev(sc->mii_dev, "unknown CICADA PHY model %x\n",
 		    model);
 		break;
+	}
 	return;
+}

 @@ -1,14 +1,14 @@
-/* $NetBSD: ciphyreg.h,v 1.5 2014/06/16 14:43:22 msaitoh Exp $ */
+/* $NetBSD: ciphyreg.h,v 1.5.20.1 2019/09/01 10:19:04 martin Exp $ */
 /*-
  * Copyright (c) 2004
  *	Bill Paul <wpaul@windriver.com>.  All rights reserved.
+ *
  * Redistribution and use in source and binary forms, with or without
  * modification, are permitted provided that the following conditions
  * are met:
  * 1. Redistributions of source code must retain the above copyright
  *    notice, this list of conditions and the following disclaimer.
  * 2. Redistributions in binary form must reproduce the above copyright
  *    notice, this list of conditions and the following disclaimer in the
  *    documentation and/or other materials provided with the distribution.
 @@ -32,154 +32,26 @@
  * THE POSSIBILITY OF SUCH DAMAGE.
+ *
  * FreeBSD: src/sys/dev/mii/ciphyreg.h,v 1.2 2005/01/06 01:42:55 imp Exp
  */
 #ifndef _DEV_MII_CIPHYREG_H_
 #define	_DEV_MII_CIPHYREG_H_
 /*
  * Register definitions for the Cicada CS8201 10/100/1000 gigE copper
  * PHY, embedded within the VIA Networks VT6122 controller.
  */
 /* Command register */
 #define CIPHY_MII_BMCR		0x00
 #define CIPHY_BMCR_RESET	0x8000
 #define CIPHY_BMCR_LOOP		0x4000
 #define CIPHY_BMCR_SPD0		0x2000	/* speed select, lower bit */
 #define CIPHY_BMCR_AUTOEN	0x1000	/* Autoneg enabled */
 #define CIPHY_BMCR_PDOWN	0x0800	/* Power down */
 #define CIPHY_BMCR_STARTNEG	0x0200	/* Restart autoneg */
 #define CIPHY_BMCR_FDX		0x0100	/* Duplex mode */
 #define CIPHY_BMCR_CTEST	0x0080	/* Collision test enable */
 #define CIPHY_BMCR_SPD1		0x0040	/* Speed select, upper bit */
 #define CIPHY_S1000		CIPHY_BMCR_SPD1	/* 1000mbps */
 #define CIPHY_S100		CIPHY_BMCR_SPD0	/* 100mpbs */
 #define CIPHY_S10		0		/* 10mbps */
 /* Status register */
 #define CIPHY_MII_BMSR		0x01
 #define CIPHY_BMSR_100T4	0x8000	/* 100 base T4 capable */
 #define CIPHY_BMSR_100TXFDX	0x4000	/* 100 base Tx full duplex capable */
 #define CIPHY_BMSR_100TXHDX	0x2000	/* 100 base Tx half duplex capable */
 #define CIPHY_BMSR_10TFDX	0x1000	/* 10 base T full duplex capable */
 #define CIPHY_BMSR_10THDX	0x0800	/* 10 base T half duplex capable */
 #define CIPHY_BMSR_100T2FDX	0x0400	/* 100 base T2 full duplex capable */
 #define CIPHY_BMSR_100T2HDX	0x0200	/* 100 base T2 half duplex capable */
 #define CIPHY_BMSR_EXTSTS	0x0100	/* Extended status present */
 #define CIPHY_BMSR_PRESUB	0x0040	/* Preamble surpression */
 #define CIPHY_BMSR_ACOMP	0x0020	/* Autoneg complete */
 #define CIPHY_BMSR_RFAULT	0x0010	/* Remote fault condition occured */
 #define CIPHY_BMSR_ANEG		0x0008	/* Autoneg capable */
 #define CIPHY_BMSR_LINK		0x0004	/* Link status */
 #define CIPHY_BMSR_JABBER	0x0002	/* Jabber detected */
 #define CIPHY_BMSR_EXT		0x0001	/* Extended capability */
 /* PHY ID registers */
 #define CIPHY_MII_PHYIDR1	0x02
 #define CIPHY_MII_PHYIDR2	0x03
 /* Autoneg advertisement */
 #define CIPHY_MII_ANAR		0x04
 #define CIPHY_ANAR_NP		0x8000	/* Next page */
 #define CIPHY_ANAR_RF		0x2000	/* Remote fault */
 #define CIPHY_ANAR_ASP		0x0800	/* Asymmetric Pause */
 #define CIPHY_ANAR_PC		0x0400	/* Pause capable */
 #define CIPHY_ANAR_T4		0x0200	/* local device supports 100bT4 */
 #define CIPHY_ANAR_TX_FD	0x0100	/* local device supports 100bTx FD */
 #define CIPHY_ANAR_TX		0x0080	/* local device supports 100bTx */
 #define CIPHY_ANAR_10_FD	0x0040	/* local device supports 10bT FD */
 #define CIPHY_ANAR_10		0x0020	/* local device supports 10bT */
 #define CIPHY_ANAR_SEL		0x001F	/* selector field, 00001=Ethernet */
 /* Autoneg link partner ability */
 #define CIPHY_MII_ANLPAR	0x05
 #define CIPHY_ANLPAR_NP		0x8000	/* Next page */
 #define CIPHY_ANLPAR_ACK	0x4000	/* link partner acknowledge */
 #define CIPHY_ANLPAR_RF		0x2000	/* Remote fault */
 #define CIPHY_ANLPAR_ASP	0x0800	/* Asymmetric Pause */
 #define CIPHY_ANLPAR_PC		0x0400	/* Pause capable */
 #define CIPHY_ANLPAR_T4		0x0200	/* link partner supports 100bT4 */
 #define CIPHY_ANLPAR_TX_FD	0x0100	/* link partner supports 100bTx FD */
 #define CIPHY_ANLPAR_TX		0x0080	/* link partner supports 100bTx */
 #define CIPHY_ANLPAR_10_FD	0x0040	/* link partner supports 10bT FD */
 #define CIPHY_ANLPAR_10		0x0020	/* link partner supports 10bT */
 #define CIPHY_ANLPAR_SEL	0x001F	/* selector field, 00001=Ethernet */
 #define CIPHY_SEL_TYPE		0x0001	/* ethernet */
 /* Antoneg expansion register */
 #define CIPHY_MII_ANER		0x06
 #define CIPHY_ANER_PDF		0x0010	/* Parallel detection fault */
 #define CIPHY_ANER_LPNP		0x0008	/* Link partner can next page */
 #define CIPHY_ANER_NP		0x0004	/* Local PHY can next page */
 #define CIPHY_ANER_RX		0x0002	/* Next page received */
 #define CIPHY_ANER_LPAN		0x0001 	/* Link partner autoneg capable */
 /* Autoneg next page transmit regisyer */
 #define CIPHY_MII_NEXTP		0x07
 #define CIPHY_NEXTP_MOREP	0x8000	/* More pages to follow */
 #define CIPHY_NEXTP_MESS	0x2000	/* 1 = message page, 0 = unformatted */
 #define CIPHY_NEXTP_ACK2	0x1000	/* MAC acknowledge */
 #define CIPHY_NEXTP_TOGGLE	0x0800	/* Toggle */
 #define CIPHY_NEXTP_CODE	0x07FF	/* Code bits */
 /* Autoneg link partner next page receive register */
 #define CIPHY_MII_NEXTP_LP	0x08
 #define CIPHY_NEXTPLP_MOREP	0x8000	/* More pages to follow */
 #define CIPHY_NEXTPLP_MESS	0x2000	/* 1 = message page, 0 = unformatted */
 #define CIPHY_NEXTPLP_ACK2	0x1000	/* MAC acknowledge */
 #define CIPHY_NEXTPLP_TOGGLE	0x0800	/* Toggle */
 #define CIPHY_NEXTPLP_CODE	0x07FF	/* Code bits */
 /* 1000BT control register */
 #define CIPHY_MII_1000CTL	0x09
 #define CIPHY_1000CTL_TST	0xE000	/* test modes */
 #define CIPHY_1000CTL_MSE	0x1000	/* Master/Slave manual enable */
 #define CIPHY_1000CTL_MSC	0x0800	/* Master/Slave select */
 #define CIPHY_1000CTL_RD	0x0400	/* Repeater/DTE */
 #define CIPHY_1000CTL_AFD	0x0200	/* Advertise full duplex */
 #define CIPHY_1000CTL_AHD	0x0100	/* Advertise half duplex */
 #define CIPHY_TEST_TX_JITTER			0x2000
 #define CIPHY_TEST_TX_JITTER_MASTER_MODE	0x4000
 #define CIPHY_TEST_TX_JITTER_SLAVE_MODE		0x6000
 #define CIPHY_TEST_TX_DISTORTION		0x8000
 /* 1000BT status register */
 #define CIPHY_MII_1000STS	0x0A
 #define CIPHY_1000STS_MSF	0x8000	/* Master/slave fault */
 #define CIPHY_1000STS_MSR	0x4000	/* Master/slave result */
 #define CIPHY_1000STS_LRS	0x2000	/* Local receiver status */
 #define CIPHY_1000STS_RRS	0x1000	/* Remote receiver status */
 #define CIPHY_1000STS_LPFD	0x0800	/* Link partner can FD */
 #define CIPHY_1000STS_LPHD	0x0400	/* Link partner can HD */
 #define CIPHY_1000STS_IEC	0x00FF	/* Idle error count */
 #define CIPHY_MII_EXTSTS	0x0F	/* Extended status */
 #define CIPHY_EXTSTS_X_FD_CAP	0x8000	/* 1000base-X FD capable */
 #define CIPHY_EXTSTS_X_HD_CAP	0x4000	/* 1000base-X HD capable */
 #define CIPHY_EXTSTS_T_FD_CAP	0x2000	/* 1000base-T FD capable */
 #define CIPHY_EXTSTS_T_HD_CAP	0x1000	/* 1000base-T HD capable */
 /* 1000BT status extension register #1 */
 #define CIPHY_MII_1000STS1	0x0F
 #define CIPHY_1000STS1_1000XFDX	0x8000	/* 1000baseX FDX capable */
 #define CIPHY_1000STS1_1000XHDX	0x4000	/* 1000baseX HDX capable */
 #define CIPHY_1000STS1_1000TFDX	0x2000	/* 1000baseT FDX capable */
 #define CIPHY_1000STS1_1000THDX	0x1000	/* 1000baseT HDX capable */
 /* Vendor-specific PHY registers */
 /* 100baseTX status extension register */
 #define CIPHY_MII_100STS	0x10
 #define CIPHY_100STS_DESLCK	0x8000	/* descrambler locked */
 #define CIPHY_100STS_LKCERR	0x4000	/* lock error detected/lock lost */
 #define CIPHY_100STS_DISC	0x2000	/* disconnect state */
 #define CIPHY_100STS_LINK	0x1000	/* current link state */
 #define CIPHY_100STS_RXERR	0x0800	/* receive error detected */
 #define CIPHY_100STS_TXERR	0x0400	/* transmit error detected */
 #define CIPHY_100STS_SSDERR	0x0200	/* false carrier error detected */
 #define CIPHY_100STS_ESDERR	0x0100	/* premature end of stream error */