 @@ -1,14 +1,14 @@
-/* $NetBSD: if_vge.c,v 1.74 2019/09/13 07:55:07 msaitoh Exp $ */
+/* $NetBSD: if_vge.c,v 1.75 2019/10/08 14:26:27 msaitoh Exp $ */
 /*-
  * Copyright (c) 2004
  *	Bill Paul <wpaul@windriver.com>.  All rights reserved.
+ *
  * Redistribution and use in source and binary forms, with or without
  * modification, are permitted provided that the following conditions
  * are met:
  * 1. Redistributions of source code must retain the above copyright
  *    notice, this list of conditions and the following disclaimer.
  * 2. Redistributions in binary form must reproduce the above copyright
  *    notice, this list of conditions and the following disclaimer in the
  *    documentation and/or other materials provided with the distribution.
 @@ -25,27 +25,27 @@
  * ARE DISCLAIMED.  IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD
  * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
  * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
  * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
  * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
  * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
  * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
  * THE POSSIBILITY OF SUCH DAMAGE.
+ *
  * FreeBSD: src/sys/dev/vge/if_vge.c,v 1.5 2005/02/07 19:39:29 glebius Exp
  */
 #include <sys/cdefs.h>
-__KERNEL_RCSID(0, "$NetBSD: if_vge.c,v 1.74 2019/09/13 07:55:07 msaitoh Exp $");
+__KERNEL_RCSID(0, "$NetBSD: if_vge.c,v 1.75 2019/10/08 14:26:27 msaitoh Exp $");
 /*
  * VIA Networking Technologies VT612x PCI gigabit ethernet NIC driver.
+ *
  * Written by Bill Paul <wpaul@windriver.com>
  * Senior Networking Software Engineer
  * Wind River Systems
  */
 /*
  * The VIA Networking VT6122 is a 32bit, 33/66 MHz PCI device that
  * combines a tri-speed ethernet MAC and PHY, with the following
  * features:
 @@ -318,26 +318,27 @@ static int vge_resume(device_t);
 #endif
 static bool vge_shutdown(device_t, int);
 static uint16_t vge_read_eeprom(struct vge_softc *, int);
 static void vge_miipoll_start(struct vge_softc *);
 static void vge_miipoll_stop(struct vge_softc *);
 static int vge_miibus_readreg(device_t, int, int, uint16_t *);
 static int vge_miibus_writereg(device_t, int, int, uint16_t);
 static void vge_miibus_statchg(struct ifnet *);
 static void vge_cam_clear(struct vge_softc *);
 static int vge_cam_set(struct vge_softc *, uint8_t *);
 static void	vge_clrwol(struct vge_softc *);
 static void vge_setmulti(struct vge_softc *);
 static void vge_reset(struct vge_softc *);
 CFATTACH_DECL_NEW(vge, sizeof(struct vge_softc),
     vge_match, vge_attach, NULL, NULL);
 static inline void
 vge_set_txaddr(struct vge_txfrag *f, bus_addr_t daddr)
+{
 	f->tf_addrlo = htole32((uint32_t)daddr);
 	if (sizeof(bus_addr_t) == sizeof(uint64_t))
 		f->tf_addrhi = htole16(((uint64_t)daddr >> 32) & 0xFFFF);
 @@ -943,26 +944,29 @@ vge_attach(device_t parent, device_t sel
 	val = vge_read_eeprom(sc, VGE_EE_EADDR + 0);
 	eaddr[0] = val & 0xff;
 	eaddr[1] = val >> 8;
 	val = vge_read_eeprom(sc, VGE_EE_EADDR + 1);
 	eaddr[2] = val & 0xff;
 	eaddr[3] = val >> 8;
 	val = vge_read_eeprom(sc, VGE_EE_EADDR + 2);
 	eaddr[4] = val & 0xff;
 	eaddr[5] = val >> 8;
 	aprint_normal_dev(self, "Ethernet address %s\n",
 	    ether_sprintf(eaddr));
 	/* Clear WOL and take hardware from powerdown. */
 	vge_clrwol(sc);
 	/*
 	 * Use the 32bit tag. Hardware supports 48bit physical addresses,
 	 * but we don't use that for now.
 	 */
 	sc->sc_dmat = pa->pa_dmat;
 	if (vge_allocmem(sc) != 0)
 		return;
 	ifp = &sc->sc_ethercom.ec_if;
 	ifp->if_softc = sc;
 	strlcpy(ifp->if_xname, device_xname(self), IFNAMSIZ);
 	ifp->if_mtu = ETHERMTU;
 @@ -2146,13 +2150,40 @@ vge_resume(device_t dev)
  * Stop all chip I/O so that the kernel's probe routines don't
  * get confused by errant DMAs when rebooting.
  */
 static bool
 vge_shutdown(device_t self, int howto)
+{
 	struct vge_softc *sc;
 	sc = device_private(self);
 	vge_stop(&sc->sc_ethercom.ec_if, 1);
 	return true;
+}
 static void
 vge_clrwol(struct vge_softc *sc)
+{
 	uint8_t val;
 	val = CSR_READ_1(sc, VGE_PWRSTAT);
 	val &= ~VGE_STICKHW_SWPTAG;
 	CSR_WRITE_1(sc, VGE_PWRSTAT, val);
 	/* Disable WOL and clear power state indicator. */
 	val = CSR_READ_1(sc, VGE_PWRSTAT);
 	val &= ~(VGE_STICKHW_DS0 | VGE_STICKHW_DS1);
 	CSR_WRITE_1(sc, VGE_PWRSTAT, val);
 	CSR_CLRBIT_1(sc, VGE_DIAGCTL, VGE_DIAGCTL_GMII);
 	CSR_CLRBIT_1(sc, VGE_DIAGCTL, VGE_DIAGCTL_MACFORCE);
 	/* Clear WOL on pattern match. */
 	CSR_WRITE_1(sc, VGE_WOLCR0C, VGE_WOLCR0_PATTERN_ALL);
 	/* Disable WOL on magic/unicast packet. */
 	CSR_WRITE_1(sc, VGE_WOLCR1C, 0x0F);
 	CSR_WRITE_1(sc, VGE_WOLCFGC, VGE_WOLCFG_SAB | VGE_WOLCFG_SAM |
 	    VGE_WOLCFG_PMEOVR);
 	/* Clear WOL status on pattern match. */
 	CSR_WRITE_1(sc, VGE_WOLSR0C, 0xFF);
 	CSR_WRITE_1(sc, VGE_WOLSR1C, 0xFF);
+}

 @@ -530,26 +530,51 @@
 #define VGE_TXCFG_SNAPOPT	0x01	/* 1 == insert VLAN tag at
 th byte
 == insert VLANM tag after
 					   SNAP header (21st byte) */
 #define VGE_TXCFG_NONBLK	0x02	/* priority TX/non-blocking mode */
 #define VGE_TXCFG_NONBLK_THR	0x0C	/* non-blocking threshold */
 #define VGE_TXCFG_ARB_PRIO	0x80	/* arbitration priority */
 #define VGE_TXBLOCK_64PKTS	0x00
 #define VGE_TXBLOCK_32PKTS	0x04
 #define VGE_TXBLOCK_128PKTS	0x08
 #define VGE_TXBLOCK_8PKTS	0x0C
 /* Sticky bit shadow register */
 #define	VGE_STICKHW_DS0		0x01
 #define	VGE_STICKHW_DS1		0x02
 #define	VGE_STICKHW_WOL_ENB	0x04
 #define	VGE_STICKHW_WOL_STS	0x08
 #define	VGE_STICKHW_SWPTAG	0x10
 /* WOL pattern control */
 #define	VGE_WOLCR0_PATTERN0	0x01
 #define	VGE_WOLCR0_PATTERN1	0x02
 #define	VGE_WOLCR0_PATTERN2	0x04
 #define	VGE_WOLCR0_PATTERN3	0x08
 #define	VGE_WOLCR0_PATTERN4	0x10
 #define	VGE_WOLCR0_PATTERN5	0x20
 #define	VGE_WOLCR0_PATTERN6	0x40
 #define	VGE_WOLCR0_PATTERN7	0x80
 #define	VGE_WOLCR0_PATTERN_ALL	0xFF
 /* WOL config register */
 #define	VGE_WOLCFG_PHYINT_ENB	0x01
 #define	VGE_WOLCFG_SAB		0x10
 #define	VGE_WOLCFG_SAM		0x20
 #define	VGE_WOLCFG_PMEOVR	0x80
 /* EEPROM control/status register */
 #define VGE_EECSR_EDO		0x01	/* data out pin */
 #define VGE_EECSR_EDI		0x02	/* data in pin */
 #define VGE_EECSR_ECK		0x04	/* clock pin */
 #define VGE_EECSR_ECS		0x08	/* chip select pin */
 #define VGE_EECSR_DPM		0x10	/* direct program mode enable */
 #define VGE_EECSR_RELOAD	0x20	/* trigger reload from EEPROM */
 #define VGE_EECSR_EMBP		0x40	/* embedded program mode enable */
 /* EEPROM embedded command register */
 #define VGE_EECMD_ERD		0x01	/* EEPROM read command */