Sun Nov 10 10:36:01 2019 UTC ()

Select the correct MPLL and PHY settings for the requested pixel clock


(jmcneill)

diff -r1.1 -r1.2 src/sys/dev/ic/dw_hdmi_phy.c

--- src/sys/dev/ic/dw_hdmi_phy.c 2019/11/09 23:27:50	1.1
+++ src/sys/dev/ic/dw_hdmi_phy.c 2019/11/10 10:36:01	1.2

 @@ -1,14 +1,14 @@
-/* $NetBSD: dw_hdmi_phy.c,v 1.1 2019/11/09 23:27:50 jmcneill Exp $ */
+/* $NetBSD: dw_hdmi_phy.c,v 1.2 2019/11/10 10:36:01 jmcneill Exp $ */
 /*-
  * Copyright (c) 2015 Oleksandr Tymoshenko <gonzo@freebsd.org>
  * All rights reserved.
+ *
  * Redistribution and use in source and binary forms, with or without
  * modification, are permitted provided that the following conditions
  * are met:
  * 1. Redistributions of source code must retain the above copyright
  *    notice, this list of conditions and the following disclaimer.
  * 2. Redistributions in binary form must reproduce the above copyright
  *    notice, this list of conditions and the following disclaimer in the
  *    documentation and/or other materials provided with the distribution.
 @@ -17,27 +17,27 @@
  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
  * ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
  * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
  * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
  * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
  * SUCH DAMAGE.
  */
 #include <sys/cdefs.h>
-__KERNEL_RCSID(0, "$NetBSD: dw_hdmi_phy.c,v 1.1 2019/11/09 23:27:50 jmcneill Exp $");
+__KERNEL_RCSID(0, "$NetBSD: dw_hdmi_phy.c,v 1.2 2019/11/10 10:36:01 jmcneill Exp $");
 #include <sys/param.h>
 #include <drm/drmP.h>
 #include <dev/ic/dw_hdmi.h>
 #define	HDMI_IH_PHY_STAT0                       0x0104
 #define	  HDMI_IH_PHY_STAT0_HPD (1 << 0)
 #define	HDMI_IH_I2CMPHY_STAT0                   0x0108
 #define	  HDMI_IH_I2CMPHY_STAT0_DONE            (1 << 1)
 #define	  HDMI_IH_I2CMPHY_STAT0_ERROR           (1 << 0)
 @@ -290,35 +290,35 @@ dwhdmi_phy_configure(struct dwhdmi_softc
 	dwhdmi_phy_test_clear(sc, 1);
 	dwhdmi_write(sc, HDMI_PHY_I2CM_SLAVE_ADDR, HDMI_PHY_I2CM_SLAVE_ADDR_PHY_GEN2);
 	dwhdmi_phy_test_clear(sc, 0);
 	/*
 	 * Following initialization are for 8bit per color case
 	 */
 	/*
 	 * PLL/MPLL config
 	 */
 	for (mpll_conf = &sc->sc_mpll_config[0]; mpll_conf->pixel_clock != 0; mpll_conf++)
-		if (mpll_conf->pixel_clock <= mode->clock)
+		if (mode->clock <= mpll_conf->pixel_clock)
 			break;
 	dwhdmi_phy_i2c_write(sc, mpll_conf->cpce, HDMI_PHY_I2C_CPCE_CTRL);
 	dwhdmi_phy_i2c_write(sc, mpll_conf->gmp, HDMI_PHY_I2C_GMPCTRL);
 	dwhdmi_phy_i2c_write(sc, mpll_conf->curr, HDMI_PHY_I2C_CURRCTRL);
 	for (phy_conf = &sc->sc_phy_config[0]; phy_conf->pixel_clock != 0; phy_conf++)
-		if (phy_conf->pixel_clock <= mode->clock)
+		if (mode->clock <= phy_conf->pixel_clock)
 			break;
 	dwhdmi_phy_i2c_write(sc, 0x0000, HDMI_PHY_I2C_PLLPHBYCTRL);
 	dwhdmi_phy_i2c_write(sc, MSM_CTRL_FB_CLK, HDMI_PHY_I2C_MSM_CTRL);
 	dwhdmi_phy_i2c_write(sc, phy_conf->term, HDMI_PHY_I2C_TXTERM);
 	dwhdmi_phy_i2c_write(sc, phy_conf->sym, HDMI_PHY_I2C_CKSYMTXCTRL);
 	dwhdmi_phy_i2c_write(sc, phy_conf->vlev, HDMI_PHY_I2C_VLEVCTRL);
 	/* REMOVE CLK TERM */
 	dwhdmi_phy_i2c_write(sc, CKCALCTRL_OVERRIDE, HDMI_PHY_I2C_CKCALCTRL);
 	dwhdmi_phy_enable_power(sc, 1);