 @@ -1,14 +1,14 @@
-/* $NetBSD: rk3399_cru.c,v 1.12 2019/11/10 11:43:04 jmcneill Exp $ */
+/* $NetBSD: rk3399_cru.c,v 1.13 2019/11/16 13:23:13 jmcneill Exp $ */
 /*-
  * Copyright (c) 2018 Jared McNeill <jmcneill@invisible.ca>
  * All rights reserved.
+ *
  * Redistribution and use in source and binary forms, with or without
  * modification, are permitted provided that the following conditions
  * are met:
  * 1. Redistributions of source code must retain the above copyright
  *    notice, this list of conditions and the following disclaimer.
  * 2. Redistributions in binary form must reproduce the above copyright
  *    notice, this list of conditions and the following disclaimer in the
  *    documentation and/or other materials provided with the distribution.
 @@ -18,27 +18,27 @@
  * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
  * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
  * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
  * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
  * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
  * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
  * SUCH DAMAGE.
  */
 #include <sys/cdefs.h>
-__KERNEL_RCSID(1, "$NetBSD: rk3399_cru.c,v 1.12 2019/11/10 11:43:04 jmcneill Exp $");
+__KERNEL_RCSID(1, "$NetBSD: rk3399_cru.c,v 1.13 2019/11/16 13:23:13 jmcneill Exp $");
 #include <sys/param.h>
 #include <sys/bus.h>
 #include <sys/device.h>
 #include <sys/systm.h>
 #include <dev/fdt/fdtvar.h>
 #include <arm/rockchip/rk_cru.h>
 #include <arm/rockchip/rk3399_cru.h>
 #define	PLL_CON(n)	(0x0000 + (n) * 4)
 #define	CLKSEL_CON(n)	(0x0100 + (n) * 4)
 @@ -351,26 +351,31 @@ static const char * mux_pll_src_cpll_gpl
 static const char * mux_pll_src_cpll_gpll_npll_parents[] = { "cpll", "gpll", "npll" };
 static const char * mux_pll_src_cpll_gpll_ppll_parents[] = { "cpll", "gpll", "npll" };
 static const char * mux_pll_src_cpll_gpll_upll_parents[] = { "cpll", "gpll", "upll" };
 static const char * mux_pll_src_cpll_gpll_npll_24m_parents[] = { "cpll", "gpll", "npll", "xin24m" };
 static const char * mux_pll_src_cpll_gpll_npll_ppll_upll_24m_parents[] = { "cpll", "gpll", "npll", "ppll", "upll", "xin24m" };
 static const char * mux_pll_src_vpll_cpll_gpll_parents[] = { "vpll", "cpll", "gpll" };
 static const char * mux_pll_src_vpll_cpll_gpll_npll_parents[] = { "vpll", "cpll", "gpll", "npll" };
 static const char * mux_aclk_perilp0_parents[] = { "cpll_aclk_perilp0_src", "gpll_aclk_perilp0_src" };
 static const char * mux_hclk_perilp1_parents[] = { "cpll_hclk_perilp1_src", "gpll_hclk_perilp1_src" };
 static const char * mux_aclk_perihp_parents[] = { "cpll_aclk_perihp_src", "gpll_aclk_perihp_src" };
 static const char * mux_aclk_cci_parents[] = { "cpll_aclk_cci_src", "gpll_aclk_cci_src", "npll_aclk_cci_src", "vpll_aclk_cci_src" };
 static const char * mux_dclk_vop0_parents[] = { "dclk_vop0_div", "dclk_vop0_frac" };
 static const char * mux_dclk_vop1_parents[] = { "dclk_vop1_div", "dclk_vop1_frac" };
 static const char * mux_i2s0_parents[] = { "clk_i2s0_div", "clk_i2s0_frac", "clkin_i2s", "xin12m" };
 static const char * mux_i2s1_parents[] = { "clk_i2s1_div", "clk_i2s1_frac", "clkin_i2s", "xin12m" };
 static const char * mux_i2s2_parents[] = { "clk_i2s2_div", "clk_i2s2_frac", "clkin_i2s", "xin12m" };
 static const char * mux_i2sch_parents[] = { "clk_i2s0", "clk_i2s1", "clk_i2s2" };
 static const char * mux_i2sout_parents[] = { "clk_i2sout_src", "xin12m" };
 static const char * mux_uart0_parents[] = { "clk_uart0_div", "clk_uart0_frac", "xin24m" };
 static const char * mux_uart1_parents[] = { "clk_uart1_div", "clk_uart1_frac", "xin24m" };
 static const char * mux_uart2_parents[] = { "clk_uart2_div", "clk_uart2_frac", "xin24m" };
 static const char * mux_uart3_parents[] = { "clk_uart3_div", "clk_uart3_frac", "xin24m" };
 static const char * mux_rmii_parents[] = { "clk_gmac", "clkin_gmac" };
 static const char * mux_aclk_gmac_parents[] = { "cpll_aclk_gmac_src", "gpll_aclk_gmac_src" };
 static const char * mux_aclk_emmc_parents[] = { "cpll_aclk_emmc_src", "gpll_aclk_emmc_src" };
 static const char * mux_pll_src_24m_pciephy_parents[] = { "xin24m", "clk_pciephy_ref100m" };
 static const char * mux_pciecore_cru_phy_parents[] = { "clk_pcie_core_cru", "clk_pcie_core_phy" };
 static struct rk_cru_clk rk3399_cru_clks[] = {
 	RK3399_PLL(RK3399_PLL_APLLL, "lpll", pll_parents,
 		   PLL_CON(0),		/* con_base */
 @@ -929,47 +934,126 @@ static struct rk_cru_clk rk3399_cru_clks
 			   __BITS(14,10),	/* div_mask */
 			   CLKGATE_CON(11),	/* gate_reg */
 			   __BIT(10),		/* gate_mask */
 ),
 	RK_COMPOSITE(RK3399_SCLK_HDMI_CEC, "clk_hdmi_cec", pll_parents,
 		     CLKSEL_CON(45),	/* muxdiv_reg */
 		     __BIT(15),		/* mux_mask */
 		     __BITS(9,0),	/* div_mask */
 		     CLKGATE_CON(11),	/* gate_reg */
 		     __BIT(7),		/* gate_mask */
 ),
 	RK_GATE(RK3399_PCLK_HDMI_CTRL, "pclk_hdmi_ctrl", "pclk_hdcp", CLKGATE_CON(29), 6),
 	RK_GATE(RK3399_SCLK_HDMI_SFR, "clk_hdmi_sfr", "xin24m", CLKGATE_CON(11), 6),
 	/* I2S2 */
 	RK_COMPOSITE(0, "clk_i2s0_div", mux_pll_src_cpll_gpll_parents,
 		     CLKSEL_CON(28),	/* muxdiv_reg */
 		     __BIT(7),		/* mux_mask */
 		     __BITS(6,0),	/* div_mask */
 		     CLKGATE_CON(8),	/* gate_reg */
 		     __BIT(3),		/* gate_mask */
 ),
 	RK_COMPOSITE(0, "clk_i2s1_div", mux_pll_src_cpll_gpll_parents,
 		     CLKSEL_CON(29),	/* muxdiv_reg */
 		     __BIT(7),		/* mux_mask */
 		     __BITS(6,0),	/* div_mask */
 		     CLKGATE_CON(8),	/* gate_reg */
 		     __BIT(6),		/* gate_mask */
 ),
 	RK_COMPOSITE(0, "clk_i2s2_div", mux_pll_src_cpll_gpll_parents,
 		     CLKSEL_CON(30),	/* muxdiv_reg */
 		     __BIT(7),		/* mux_mask */
 		     __BITS(6,0),	/* div_mask */
 		     CLKGATE_CON(8),	/* gate_reg */
 		     __BIT(9),		/* gate_mask */
 ),
 	RK_COMPOSITE_FRAC(0, "clk_i2s0_frac", "clk_i2s0_div",
 			  CLKSEL_CON(96),	/* frac_reg */
 ),
 	RK_COMPOSITE_FRAC(0, "clk_i2s1_frac", "clk_i2s1_div",
 			  CLKSEL_CON(97),	/* frac_reg */
 ),
 	RK_COMPOSITE_FRAC(0, "clk_i2s2_frac", "clk_i2s2_div",
 			  CLKSEL_CON(98),	/* frac_reg */
 ),
 	RK_MUX(0, "clk_i2s0_mux", mux_i2s0_parents, CLKSEL_CON(28), __BITS(9,8)),
 	RK_MUX(0, "clk_i2s1_mux", mux_i2s1_parents, CLKSEL_CON(29), __BITS(9,8)),
 	RK_MUX(0, "clk_i2s2_mux", mux_i2s2_parents, CLKSEL_CON(30), __BITS(9,8)),
 	RK_GATE(RK3399_SCLK_I2S0_8CH, "clk_i2s0", "clk_i2s0_mux", CLKGATE_CON(8), 5),
 	RK_GATE(RK3399_SCLK_I2S1_8CH, "clk_i2s1", "clk_i2s1_mux", CLKGATE_CON(8), 8),
 	RK_GATE(RK3399_SCLK_I2S2_8CH, "clk_i2s2", "clk_i2s2_mux", CLKGATE_CON(8), 11),
 	RK_GATE(RK3399_HCLK_I2S0_8CH, "hclk_i2s0", "hclk_perilp1", CLKGATE_CON(34), 0),
 	RK_GATE(RK3399_HCLK_I2S1_8CH, "hclk_i2s1", "hclk_perilp1", CLKGATE_CON(34), 1),
 	RK_GATE(RK3399_HCLK_I2S2_8CH, "hclk_i2s2", "hclk_perilp1", CLKGATE_CON(34), 2),
 	RK_MUX(0, "clk_i2sout_src", mux_i2sch_parents, CLKSEL_CON(31), __BITS(1,0)),
 	RK_COMPOSITE(RK3399_SCLK_I2S_8CH_OUT, "clk_i2sout", mux_i2sout_parents,
 		     CLKSEL_CON(31),	/* muxdiv_reg */
 		     __BIT(2),		/* mux_mask */
 ,			/* div_mask */
 		     CLKGATE_CON(8),	/* gate_reg */
 		     __BIT(12),		/* gate_mask */
 		     RK_COMPOSITE_SET_RATE_PARENT),
 };
 static const struct rk3399_init_param {
 	const char *clk;
 	const char *parent;
 } rk3399_init_params[] = {
 	{ .clk = "clk_i2s0_mux",	.parent = "clk_i2s0_frac" },
 	{ .clk = "clk_i2s1_mux",	.parent = "clk_i2s1_frac" },
 	{ .clk = "clk_i2s2_mux",	.parent = "clk_i2s2_frac" },
 };
 static void
 rk3399_cru_init(struct rk_cru_softc *sc)
+{
-	struct rk_cru_clk *clk;
+	struct rk_cru_clk *clk, *pclk;
 	uint32_t write_mask, write_val;
 	int error;
 	u_int n;
 	/*
 	 * Force an update of BPLL to bring it out of slow mode.
 	 */
 	clk = rk_cru_clock_find(sc, "armclkb");
 	clk_set_rate(&clk->base, clk_get_rate(&clk->base));
 	/*
 	 * Set DCLK_VOP0 and DCLK_VOP1 dividers to 1.
 	 */
 	write_mask = __BITS(7,0) << 16;
 	write_val = 0;
 	CRU_WRITE(sc, CLKSEL_CON(49), write_mask | write_val);
 	CRU_WRITE(sc, CLKSEL_CON(50), write_mask | write_val);
 	/*
 	 * Set defaults
 	 */
 	for (n = 0; n < __arraycount(rk3399_init_params); n++) {
 		const struct rk3399_init_param *param = &rk3399_init_params[n];
 		clk = rk_cru_clock_find(sc, param->clk);
 		KASSERTMSG(clk != NULL, "couldn't find clock %s", param->clk);
 		if (param->parent != NULL) {
 			pclk = rk_cru_clock_find(sc, param->parent);
 			KASSERTMSG(pclk != NULL, "couldn't find clock %s", param->parent);
 			error = clk_set_parent(&clk->base, &pclk->base);
 			if (error != 0) {
 				aprint_error_dev(sc->sc_dev, "couldn't set %s parent to %s: %d\n",
 				    param->clk, param->parent, error);
 				continue;
+			}
+		}
+	}
+}
 static int
 rk3399_cru_match(device_t parent, cfdata_t cf, void *aux)
+{
 	struct fdt_attach_args * const faa = aux;
 	return of_match_compatible(faa->faa_phandle, compatible);
+}
 static void
 rk3399_cru_attach(device_t parent, device_t self, void *aux)
+{

 @@ -1,14 +1,14 @@
-/* $NetBSD: rk_cru.h,v 1.6 2019/11/10 11:43:04 jmcneill Exp $ */
+/* $NetBSD: rk_cru.h,v 1.7 2019/11/16 13:23:13 jmcneill Exp $ */
 /*-
  * Copyright (c) 2018 Jared McNeill <jmcneill@invisible.ca>
  * All rights reserved.
+ *
  * Redistribution and use in source and binary forms, with or without
  * modification, are permitted provided that the following conditions
  * are met:
  * 1. Redistributions of source code must retain the above copyright
  *    notice, this list of conditions and the following disclaimer.
  * 2. Redistributions in binary form must reproduce the above copyright
  *    notice, this list of conditions and the following disclaimer in the
  *    documentation and/or other materials provided with the distribution.
 @@ -190,68 +190,77 @@ int	rk_cru_arm_set_parent(struct rk_cru_
 		.set_rate = rk_cru_arm_set_rate,		\
 		.get_parent = rk_cru_arm_get_parent,		\
 		.set_parent = rk_cru_arm_set_parent,		\
+	}
 /* Composite clocks */
 struct rk_cru_composite {
 	bus_size_t	muxdiv_reg;
 	uint32_t	mux_mask;
 	uint32_t	div_mask;
 	bus_size_t	gate_reg;
 	uint32_t	gate_mask;
 	bus_size_t	frac_reg;
 	const char	**parents;
 	u_int		nparents;
 	u_int		flags;
 #define	RK_COMPOSITE_ROUND_DOWN		0x01
 #define	RK_COMPOSITE_SET_RATE_PARENT	0x02
 #define	RK_COMPOSITE_FRACDIV		0x04
 };
 int	rk_cru_composite_enable(struct rk_cru_softc *, struct rk_cru_clk *, int);
 u_int	rk_cru_composite_get_rate(struct rk_cru_softc *, struct rk_cru_clk *);
 int	rk_cru_composite_set_rate(struct rk_cru_softc *, struct rk_cru_clk *, u_int);
 const char *rk_cru_composite_get_parent(struct rk_cru_softc *, struct rk_cru_clk *);
 int	rk_cru_composite_set_parent(struct rk_cru_softc *, struct rk_cru_clk *, const char *);
-#define	RK_COMPOSITE(_id, _name, _parents, _muxdiv_reg, _mux_mask, _div_mask, _gate_reg, _gate_mask, _flags) \
+#define	_RK_COMPOSITE_INIT(_id, _name, _parents, _muxdiv_reg, _mux_mask, _div_mask, _gate_reg, _gate_mask, _frac_reg, _flags) \
 	{							\
 		.id = (_id),					\
 		.type = RK_CRU_COMPOSITE,			\
 		.base.name = (_name),				\
 		.base.flags = 0,				\
 		.u.composite.parents = (_parents),		\
 		.u.composite.nparents = __arraycount(_parents),	\
 		.u.composite.muxdiv_reg = (_muxdiv_reg),	\
 		.u.composite.mux_mask = (_mux_mask),		\
 		.u.composite.div_mask = (_div_mask),		\
 		.u.composite.gate_reg = (_gate_reg),		\
 		.u.composite.gate_mask = (_gate_mask),		\
 		.u.composite.frac_reg = (_frac_reg),		\
 		.u.composite.flags = (_flags),			\
 		.enable = rk_cru_composite_enable,		\
 		.get_rate = rk_cru_composite_get_rate,		\
 		.set_rate = rk_cru_composite_set_rate,		\
 		.get_parent = rk_cru_composite_get_parent,	\
 		.set_parent = rk_cru_composite_set_parent,	\
+	}
 #define	RK_COMPOSITE(_id, _name, _parents, _muxdiv_reg, _mux_mask, _div_mask, _gate_reg, _gate_mask, _flags) \
 	_RK_COMPOSITE_INIT(_id, _name, _parents, _muxdiv_reg, _mux_mask, _div_mask, _gate_reg, _gate_mask, 0, _flags)
 #define	RK_COMPOSITE_NOMUX(_id, _name, _parent, _div_reg, _div_mask, _gate_reg, _gate_mask, _flags) \
-	RK_COMPOSITE(_id, _name, (const char *[]){ _parent }, _div_reg, 0, _div_mask, _gate_reg, _gate_mask, _flags)
+	_RK_COMPOSITE_INIT(_id, _name, (const char *[]){ _parent }, _div_reg, 0, _div_mask, _gate_reg, _gate_mask, 0, _flags)
 #define	RK_COMPOSITE_NOGATE(_id, _name, _parents, _muxdiv_reg, _mux_mask, _div_mask, _flags) \
-	RK_COMPOSITE(_id, _name, _parents, _muxdiv_reg, _mux_mask, _div_mask, 0, 0, _flags)
+	_RK_COMPOSITE_INIT(_id, _name, _parents, _muxdiv_reg, _mux_mask, _div_mask, 0, 0, 0, _flags)
 #define	RK_COMPOSITE_FRAC(_id, _name, _parent, _frac_reg, _flags) \
 	_RK_COMPOSITE_INIT(_id, _name, (const char *[]){ _parent }, 0, 0, 0, 0, 0, _frac_reg, (_flags) | RK_COMPOSITE_FRACDIV)
 #define	RK_DIV(_id, _name, _parent, _div_reg, _div_mask, _flags) \
-	RK_COMPOSITE(_id, _name, (const char *[]){ _parent }, _div_reg, 0, _div_mask, 0, 0, _flags)
+	_RK_COMPOSITE_INIT(_id, _name, (const char *[]){ _parent }, _div_reg, 0, _div_mask, 0, 0, 0, _flags)
 /* Gate clocks */
 struct rk_cru_gate {
 	bus_size_t	reg;
 	uint32_t	mask;
 	const char	*parent;
 };
 int	rk_cru_gate_enable(struct rk_cru_softc *,
 			   struct rk_cru_clk *, int);
 const char *rk_cru_gate_get_parent(struct rk_cru_softc *,
 				   struct rk_cru_clk *);

 @@ -1,14 +1,14 @@
-/* $NetBSD: rk_cru_composite.c,v 1.4 2019/11/10 11:43:04 jmcneill Exp $ */
+/* $NetBSD: rk_cru_composite.c,v 1.5 2019/11/16 13:23:13 jmcneill Exp $ */
 /*-
  * Copyright (c) 2018 Jared McNeill <jmcneill@invisible.ca>
  * All rights reserved.
+ *
  * Redistribution and use in source and binary forms, with or without
  * modification, are permitted provided that the following conditions
  * are met:
  * 1. Redistributions of source code must retain the above copyright
  *    notice, this list of conditions and the following disclaimer.
  * 2. Redistributions in binary form must reproduce the above copyright
  *    notice, this list of conditions and the following disclaimer in the
  *    documentation and/or other materials provided with the distribution.
 @@ -17,27 +17,27 @@
  * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
  * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
  * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
  * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
  * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
  * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
  * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
  * SUCH DAMAGE.
  */
 #include <sys/cdefs.h>
-__KERNEL_RCSID(0, "$NetBSD: rk_cru_composite.c,v 1.4 2019/11/10 11:43:04 jmcneill Exp $");
+__KERNEL_RCSID(0, "$NetBSD: rk_cru_composite.c,v 1.5 2019/11/16 13:23:13 jmcneill Exp $");
 #include <sys/param.h>
 #include <sys/bus.h>
 #include <dev/clk/clk_backend.h>
 #include <arm/rockchip/rk_cru.h>
 #include <dev/fdt/fdtvar.h>
 int
 rk_cru_composite_enable(struct rk_cru_softc *sc, struct rk_cru_clk *clk,
     int enable)
 @@ -65,50 +65,99 @@ rk_cru_composite_get_rate(struct rk_cru_
 	struct clk *clkp, *clkp_parent;
 	KASSERT(clk->type == RK_CRU_COMPOSITE);
 	clkp = &clk->base;
 	clkp_parent = clk_get_parent(clkp);
 	if (clkp_parent == NULL)
 		return 0;
 	const u_int prate = clk_get_rate(clkp_parent);
 	if (prate == 0)
 		return 0;
-	const uint32_t val = CRU_READ(sc, composite->muxdiv_reg);
+	if (composite->flags & RK_COMPOSITE_FRACDIV) {
-	const u_int div = __SHIFTOUT(val, composite->div_mask) + 1;
+		const uint32_t val = CRU_READ(sc, composite->frac_reg);
 		const u_int num = (val >> 16) & 0xffff;
 		const u_int den = val & 0xffff;
-	return prate / div;
+		return (u_int)((uint64_t)prate * num / den);
 	} else {
 		const uint32_t val = CRU_READ(sc, composite->muxdiv_reg);
 		const u_int div = __SHIFTOUT(val, composite->div_mask) + 1;
 		return prate / div;
+	}
+}
 static u_int
 rk_cru_composite_get_frac_div(u_int n, u_int d)
+{
 	u_int tmp;
 	while (d > 0) {
 		tmp = d;
 		d = n % d;
 		n = tmp;
+	}
 	return n;
+}
 static int
 rk_cru_composite_set_rate_frac(struct rk_cru_softc *sc,
     struct rk_cru_clk *clk, u_int rate)
+{
 	struct rk_cru_composite *composite = &clk->u.composite;
 	struct clk *clk_parent;
 	clk_parent = clk_get_parent(&clk->base);
 	if (clk_parent == NULL)
 		return ENXIO;
 	const u_int prate = clk_get_rate(clk_parent);
 	const u_int v = rk_cru_composite_get_frac_div(prate, rate);
 	const u_int num = (prate / v) & 0xffff;
 	const u_int den = (rate / v) & 0xffff;
 	if (prate / num * den != rate)
 		return EINVAL;
 	CRU_WRITE(sc, composite->frac_reg, (den << 16) | num);
 	return 0;
+}
 int
 rk_cru_composite_set_rate(struct rk_cru_softc *sc,
     struct rk_cru_clk *clk, u_int rate)
+{
 	struct rk_cru_composite *composite = &clk->u.composite;
 	u_int best_div, best_mux, best_diff;
 	struct rk_cru_clk *rclk_parent;
 	struct clk *clk_parent;
 	KASSERT(clk->type == RK_CRU_COMPOSITE);
 	if (composite->flags & RK_COMPOSITE_SET_RATE_PARENT) {
 		clk_parent = clk_get_parent(&clk->base);
 		if (clk_parent == NULL)
 			return ENXIO;
 		return clk_set_rate(clk_parent, rate);
+	}
 	if (composite->flags & RK_COMPOSITE_FRACDIV) {
 		return rk_cru_composite_set_rate_frac(sc, clk, rate);
+	}
 	best_div = 0;
 	best_mux = 0;
 	best_diff = INT_MAX;
 	for (u_int mux = 0; mux < composite->nparents; mux++) {
 		rclk_parent = rk_cru_clock_find(sc, composite->parents[mux]);
 		if (rclk_parent != NULL)
 			clk_parent = &rclk_parent->base;
 		else
 			clk_parent = fdtbus_clock_byname(composite->parents[mux]);
 		if (clk_parent == NULL)
 			continue;
 		const u_int prate = clk_get_rate(clk_parent);