 @@ -1,14 +1,14 @@
-/*	$NetBSD: bus_space.c,v 1.41 2019/02/11 14:59:33 cherry Exp $	*/
+/*	$NetBSD: bus_space.c,v 1.42 2019/12/02 08:33:52 riastradh Exp $	*/
 /*-
  * Copyright (c) 1996, 1997, 1998 The NetBSD Foundation, Inc.
  * All rights reserved.
+ *
  * This code is derived from software contributed to The NetBSD Foundation
  * by Charles M. Hannum and by Jason R. Thorpe of the Numerical Aerospace
  * Simulation Facility, NASA Ames Research Center.
+ *
  * Redistribution and use in source and binary forms, with or without
  * modification, are permitted provided that the following conditions
  * are met:
  * 1. Redistributions of source code must retain the above copyright
 @@ -21,27 +21,27 @@
  * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
  * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
  * PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
  * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
  * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
  * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
  * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
  * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
  * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
  * POSSIBILITY OF SUCH DAMAGE.
  */
 #include <sys/cdefs.h>
-__KERNEL_RCSID(0, "$NetBSD: bus_space.c,v 1.41 2019/02/11 14:59:33 cherry Exp $");
+__KERNEL_RCSID(0, "$NetBSD: bus_space.c,v 1.42 2019/12/02 08:33:52 riastradh Exp $");
 #include <sys/param.h>
 #include <sys/systm.h>
 #include <sys/malloc.h>
 #include <sys/extent.h>
 #include <sys/kmem.h>
 #include <uvm/uvm_extern.h>
 #include <dev/isa/isareg.h>
 #include <sys/bus.h>
 #include <machine/pio.h>
 @@ -868,27 +868,59 @@ bus_space_copy_region_4(bus_space_tag_t
 			for (addr1 += 4 * (c - 1), addr2 += 4 * (c - 1);
 			    c != 0; c--, addr1 -= 4, addr2 -= 4)
 				*(volatile uint32_t *)(addr2) =
 				    *(volatile uint32_t *)(addr1);
+		}
+	}
+}
 void
 bus_space_barrier(bus_space_tag_t tag, bus_space_handle_t bsh,
 		  bus_size_t offset, bus_size_t len, int flags)
+{
-	/* Function call is enough to prevent reordering of loads. */
+	/*
 	 * For default mappings, which are mapped with UC-type memory
 	 * regions, all loads and stores are issued in program order.
+	 *
 	 * For BUS_SPACE_MAP_PREFETCHABLE mappings, which are mapped
 	 * with WC-type memory regions, loads and stores may be issued
 	 * out of order, potentially requiring any of the three x86
 	 * fences -- LFENCE, SFENCE, MFENCE.
+	 *
 	 * For BUS_SPACE_MAP_CACHEABLE mappings, which are mapped with
 	 * WB-type memory regions (like normal memory), store/load may
 	 * be reordered to load/store, potentially requiring MFENCE.
+	 *
 	 * We can't easily tell here how the region was mapped (without
 	 * consulting the page tables), so just issue the fence
 	 * unconditionally.  Chances are either it's necessary or the
 	 * cost is small in comparison to device register I/O.
 	 */
 	switch (flags) {
 	case 0:
 		break;
 	case BUS_SPACE_BARRIER_READ:
 		x86_lfence();
 		break;
 	case BUS_SPACE_BARRIER_WRITE:
 		x86_sfence();
 		break;
 	case BUS_SPACE_BARRIER_READ|BUS_SPACE_BARRIER_WRITE:
 		x86_mfence();
 		break;
 	default:
 		panic("unknown bus space barrier: 0x%x", (unsigned)flags);
+	}
+}
 void *
 bus_space_vaddr(bus_space_tag_t tag, bus_space_handle_t bsh)
+{
 	return x86_bus_space_is_mem(tag) ? (void *)bsh : NULL;
+}
 static const void *
 bit_to_function_pointer(const struct bus_space_overrides *ov, uint64_t bit)
+{
 	switch (bit) {