Thu Dec 5 05:17:55 2019 UTC ()
MAX_CACHE_LEVEL * struct aarch64_cache_info are required to statically allocate for cpu0.

avoid "cpu0: L2 512KB/64B 16-way write-back read-allocate write-allocate PIPT *UNK* cache" by r1.8


(ryo)
diff -r1.9 -r1.10 src/sys/arch/aarch64/aarch64/cpufunc.c
cvs diff -r1.9 -r1.10 src/sys/arch/aarch64/aarch64/cpufunc.c (expand / switch to unified diff)

--- src/sys/arch/aarch64/aarch64/cpufunc.c 2019/12/02 23:22:43 1.9
+++ src/sys/arch/aarch64/aarch64/cpufunc.c 2019/12/05 05:17:55 1.10
@@ -1,14 +1,14 @@ @@ -1,14 +1,14 @@
1/* $NetBSD: cpufunc.c,v 1.9 2019/12/02 23:22:43 ad Exp $ */ 1/* $NetBSD: cpufunc.c,v 1.10 2019/12/05 05:17:55 ryo Exp $ */
2 2
3/* 3/*
4 * Copyright (c) 2017 Ryo Shimizu <ryo@nerv.org> 4 * Copyright (c) 2017 Ryo Shimizu <ryo@nerv.org>
5 * All rights reserved. 5 * All rights reserved.
6 * 6 *
7 * Redistribution and use in source and binary forms, with or without 7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions 8 * modification, are permitted provided that the following conditions
9 * are met: 9 * are met:
10 * 1. Redistributions of source code must retain the above copyright 10 * 1. Redistributions of source code must retain the above copyright
11 * notice, this list of conditions and the following disclaimer. 11 * notice, this list of conditions and the following disclaimer.
12 * 2. Redistributions in binary form must reproduce the above copyright 12 * 2. Redistributions in binary form must reproduce the above copyright
13 * notice, this list of conditions and the following disclaimer in the 13 * notice, this list of conditions and the following disclaimer in the
14 * documentation and/or other materials provided with the distribution. 14 * documentation and/or other materials provided with the distribution.
@@ -19,47 +19,47 @@ @@ -19,47 +19,47 @@
19 * DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, 19 * DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT,
20 * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES 20 * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
21 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR 21 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
22 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 22 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
23 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, 23 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
24 * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING 24 * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
25 * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 25 * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
26 * POSSIBILITY OF SUCH DAMAGE. 26 * POSSIBILITY OF SUCH DAMAGE.
27 */ 27 */
28 28
29#include "opt_multiprocessor.h" 29#include "opt_multiprocessor.h"
30 30
31#include <sys/cdefs.h> 31#include <sys/cdefs.h>
32__KERNEL_RCSID(0, "$NetBSD: cpufunc.c,v 1.9 2019/12/02 23:22:43 ad Exp $"); 32__KERNEL_RCSID(0, "$NetBSD: cpufunc.c,v 1.10 2019/12/05 05:17:55 ryo Exp $");
33 33
34#include <sys/param.h> 34#include <sys/param.h>
35#include <sys/types.h> 35#include <sys/types.h>
36#include <sys/kmem.h> 36#include <sys/kmem.h>
37#include <sys/cpu.h> 37#include <sys/cpu.h>
38 38
39#include <aarch64/cpufunc.h> 39#include <aarch64/cpufunc.h>
40 40
41u_int cputype; /* compat arm */ 41u_int cputype; /* compat arm */
42u_int arm_dcache_align; /* compat arm */ 42u_int arm_dcache_align; /* compat arm */
43u_int arm_dcache_align_mask; /* compat arm */ 43u_int arm_dcache_align_mask; /* compat arm */
44u_int arm_dcache_maxline; 44u_int arm_dcache_maxline;
45 45
46u_int aarch64_cache_vindexsize; 46u_int aarch64_cache_vindexsize;
47u_int aarch64_cache_prefer_mask; 47u_int aarch64_cache_prefer_mask;
48 48
49/* cache info per cluster. the same cluster has the same cache configuration? */ 49/* cache info per cluster. the same cluster has the same cache configuration? */
50#define MAXCPUPACKAGES MAXCPUS /* maximum of ci->ci_package_id */ 50#define MAXCPUPACKAGES MAXCPUS /* maximum of ci->ci_package_id */
51static struct aarch64_cache_info *aarch64_cacheinfo[MAXCPUPACKAGES]; 51static struct aarch64_cache_info *aarch64_cacheinfo[MAXCPUPACKAGES];
52static struct aarch64_cache_info aarch64_cacheinfo0; 52static struct aarch64_cache_info aarch64_cacheinfo0[MAX_CACHE_LEVEL];
53 53
54 54
55static void 55static void
56extract_cacheunit(int level, bool insn, int cachetype, 56extract_cacheunit(int level, bool insn, int cachetype,
57 struct aarch64_cache_info *cacheinfo) 57 struct aarch64_cache_info *cacheinfo)
58{ 58{
59 struct aarch64_cache_unit *cunit; 59 struct aarch64_cache_unit *cunit;
60 uint32_t ccsidr; 60 uint32_t ccsidr;
61 61
62 /* select and extract level N data cache */ 62 /* select and extract level N data cache */
63 reg_csselr_el1_write(__SHIFTIN(level, CSSELR_LEVEL) | 63 reg_csselr_el1_write(__SHIFTIN(level, CSSELR_LEVEL) |
64 __SHIFTIN(insn ? 1 : 0, CSSELR_IND)); 64 __SHIFTIN(insn ? 1 : 0, CSSELR_IND));
65 __asm __volatile ("isb"); 65 __asm __volatile ("isb");