 @@ -1,14 +1,14 @@
-/*	$NetBSD: if_alc.c,v 1.24.8.4 2019/11/06 10:04:47 martin Exp $	*/
+/*	$NetBSD: if_alc.c,v 1.24.8.5 2019/12/05 16:50:54 bouyer Exp $	*/
 /*	$OpenBSD: if_alc.c,v 1.1 2009/08/08 09:31:13 kevlo Exp $	*/
 /*-
  * Copyright (c) 2009, Pyun YongHyeon <yongari@FreeBSD.org>
  * All rights reserved.
+ *
  * Redistribution and use in source and binary forms, with or without
  * modification, are permitted provided that the following conditions
  * are met:
  * 1. Redistributions of source code must retain the above copyright
  *    notice unmodified, this list of conditions, and the following
  *    disclaimer.
  * 2. Redistributions in binary form must reproduce the above copyright
  *    notice, this list of conditions and the following disclaimer in the
 @@ -735,27 +735,26 @@ alc_get_macaddr_816x(struct alc_softc *s
 					reg = CSR_READ_4(sc, ALC_EEPROM_LD);
 					if ((reg & EEPROM_LD_START) == 0)
 						break;
+				}
 			} else if (alcdebug)
 				printf("%s: reloading EEPROM/FLASH timed out!\n",
 			  	  device_xname(sc->sc_dev));
+		}
+	}
 	alc_get_macaddr_par(sc);
+}
 static void
 alc_get_macaddr_par(struct alc_softc *sc)
+{
 	uint32_t ea[2];
 	ea[0] = CSR_READ_4(sc, ALC_PAR0);
 	ea[1] = CSR_READ_4(sc, ALC_PAR1);
 	sc->alc_eaddr[0] = (ea[1] >> 8) & 0xFF;
 	sc->alc_eaddr[1] = (ea[1] >> 0) & 0xFF;
 	sc->alc_eaddr[2] = (ea[0] >> 24) & 0xFF;
 	sc->alc_eaddr[3] = (ea[0] >> 16) & 0xFF;
 	sc->alc_eaddr[4] = (ea[0] >> 8) & 0xFF;
 	sc->alc_eaddr[5] = (ea[0] >> 0) & 0xFF;
 @@ -2766,27 +2765,26 @@ alc_init_backend(struct ifnet *ifp, bool
 	/* Enable all clocks. */
 	if ((sc->alc_flags & ALC_FLAG_AR816X_FAMILY) != 0) {
 		CSR_WRITE_4(sc, ALC_CLK_GATING_CFG, CLK_GATING_DMAW_ENB |
 		    CLK_GATING_DMAR_ENB | CLK_GATING_TXQ_ENB |
 		    CLK_GATING_RXQ_ENB | CLK_GATING_TXMAC_ENB |
 		    CLK_GATING_RXMAC_ENB);
 		if (AR816X_REV(sc->alc_rev) >= AR816X_REV_B0)
 			CSR_WRITE_4(sc, ALC_IDLE_DECISN_TIMER,
 			    IDLE_DECISN_TIMER_DEFAULT_1MS);
 	} else
 		CSR_WRITE_4(sc, ALC_CLK_GATING_CFG, 0);
 	/* Reprogram the station address. */
 	memcpy(eaddr, CLLADDR(ifp->if_sadl), sizeof(eaddr));
 	CSR_WRITE_4(sc, ALC_PAR0,
 	    eaddr[2] << 24 | eaddr[3] << 16 | eaddr[4] << 8 | eaddr[5]);
 	CSR_WRITE_4(sc, ALC_PAR1, eaddr[0] << 8 | eaddr[1]);
 	/*
 	 * Clear WOL status and disable all WOL feature as WOL
 	 * would interfere Rx operation under normal environments.
 	 */
 	CSR_READ_4(sc, ALC_WOL_CFG);
 	CSR_WRITE_4(sc, ALC_WOL_CFG, 0);
 	/* Set Tx descriptor base addresses. */
 	paddr = sc->alc_rdata.alc_tx_ring_paddr;
 @@ -2822,27 +2820,27 @@ alc_init_backend(struct ifnet *ifp, bool
 	 * size by 8 bytes to make room for alignment fixup.
 	 */
 	sc->alc_buf_size = RX_BUF_SIZE_MAX;
 	CSR_WRITE_4(sc, ALC_RX_BUF_SIZE, sc->alc_buf_size);
 	paddr = sc->alc_rdata.alc_rr_ring_paddr;
 	/* Set Rx return descriptor base addresses. */
 	CSR_WRITE_4(sc, ALC_RRD0_HEAD_ADDR_LO, ALC_ADDR_LO(paddr));
 	if ((sc->alc_flags & ALC_FLAG_AR816X_FAMILY) == 0) {
 		/* We use one Rx return ring. */
 		CSR_WRITE_4(sc, ALC_RRD1_HEAD_ADDR_LO, 0);
 		CSR_WRITE_4(sc, ALC_RRD2_HEAD_ADDR_LO, 0);
 		CSR_WRITE_4(sc, ALC_RRD3_HEAD_ADDR_LO, 0);
 	}\
 	/* Set Rx return descriptor counter. */
 	CSR_WRITE_4(sc, ALC_RRD_RING_CNT,
 	    (ALC_RR_RING_CNT << RRD_RING_CNT_SHIFT) & RRD_RING_CNT_MASK);
 	paddr = sc->alc_rdata.alc_cmb_paddr;
 	CSR_WRITE_4(sc, ALC_CMB_BASE_ADDR_LO, ALC_ADDR_LO(paddr));
 	paddr = sc->alc_rdata.alc_smb_paddr;
 	CSR_WRITE_4(sc, ALC_SMB_BASE_ADDR_HI, ALC_ADDR_HI(paddr));
 	CSR_WRITE_4(sc, ALC_SMB_BASE_ADDR_LO, ALC_ADDR_LO(paddr));
 	if (sc->alc_ident->deviceid == PCI_PRODUCT_ATTANSIC_AR8152_B) {
 		/* Reconfigure SRAM - Vendor magic. */
 		CSR_WRITE_4(sc, ALC_SRAM_RX_FIFO_LEN, 0x000002A0);
 		CSR_WRITE_4(sc, ALC_SRAM_TX_FIFO_LEN, 0x00000100);
 @@ -3393,45 +3391,55 @@ alc_iff(struct alc_softc *sc)
 	uint32_t crc;
 	uint32_t mchash[2];
 	uint32_t rxcfg;
 	rxcfg = CSR_READ_4(sc, ALC_MAC_CFG);
 	rxcfg &= ~(MAC_CFG_ALLMULTI | MAC_CFG_BCAST | MAC_CFG_PROMISC);
 	ifp->if_flags &= ~IFF_ALLMULTI;
 	/*
 	 * Always accept broadcast frames.
 	 */
 	rxcfg |= MAC_CFG_BCAST;
-	if (ifp->if_flags & IFF_PROMISC || ec->ec_multicnt > 0) {
+	/* Program new filter. */
-		ifp->if_flags |= IFF_ALLMULTI;
+	if ((ifp->if_flags & IFF_PROMISC) != 0)
-		if (ifp->if_flags & IFF_PROMISC)
+		goto update;
 	memset(mchash, 0, sizeof(mchash));
 	ETHER_FIRST_MULTI(step, ec, enm);
 	while (enm != NULL) {
 		if (memcmp(enm->enm_addrlo, enm->enm_addrhi, ETHER_ADDR_LEN)) {
 			/* XXX Use ETHER_F_ALLMULTI in future. */
 			ifp->if_flags |= IFF_ALLMULTI;
 			ETHER_UNLOCK(ec);
 			goto update;
+		}
 		crc = ether_crc32_be(enm->enm_addrlo, ETHER_ADDR_LEN);
 		mchash[crc >> 31] |= 1 << ((crc >> 26) & 0x1f);
 		ETHER_NEXT_MULTI(step, enm);
+	}
 update:
 	if ((ifp->if_flags & (IFF_PROMISC | IFF_ALLMULTI)) != 0) {
 		if (ifp->if_flags & IFF_PROMISC) {
 			rxcfg |= MAC_CFG_PROMISC;
-		else
+			/* XXX Use ETHER_F_ALLMULTI in future. */
 			ifp->if_flags |= IFF_ALLMULTI;
 		} else
 			rxcfg |= MAC_CFG_ALLMULTI;
 		mchash[0] = mchash[1] = 0xFFFFFFFF;
 	} else {
 		/* Program new filter. */
 		memset(mchash, 0, sizeof(mchash));
 		ETHER_FIRST_MULTI(step, ec, enm);
 		while (enm != NULL) {
 			crc = ether_crc32_be(enm->enm_addrlo, ETHER_ADDR_LEN);
 			mchash[crc >> 31] |= 1 << ((crc >> 26) & 0x1f);
 			ETHER_NEXT_MULTI(step, enm);
+	}
 	CSR_WRITE_4(sc, ALC_MAR0, mchash[0]);
 	CSR_WRITE_4(sc, ALC_MAR1, mchash[1]);
 	CSR_WRITE_4(sc, ALC_MAC_CFG, rxcfg);
+}
 MODULE(MODULE_CLASS_DRIVER, if_alc, "pci");
 #ifdef _MODULE
 #include "ioconf.c"
 #endif
 static int
 if_alc_modcmd(modcmd_t cmd, void *opaque)

 @@ -1,14 +1,14 @@
-/*	$NetBSD: if_cas.c,v 1.26 2016/12/15 09:28:05 ozaki-r Exp $	*/
+/*	$NetBSD: if_cas.c,v 1.26.8.1 2019/12/05 16:50:54 bouyer Exp $	*/
 /*	$OpenBSD: if_cas.c,v 1.29 2009/11/29 16:19:38 kettenis Exp $	*/
 /*
+ *
  * Copyright (C) 2007 Mark Kettenis.
  * Copyright (C) 2001 Eduardo Horvath.
  * All rights reserved.
+ *
+ *
  * Redistribution and use in source and binary forms, with or without
  * modification, are permitted provided that the following conditions
  * are met:
  * 1. Redistributions of source code must retain the above copyright
 @@ -34,27 +34,27 @@
 /*
  * Driver for Sun Cassini ethernet controllers.
+ *
  * There are basically two variants of this chip: Cassini and
  * Cassini+.  We can distinguish between the two by revision: 0x10 and
  * up are Cassini+.  The most important difference is that Cassini+
  * has a second RX descriptor ring.  Cassini+ will not work without
  * configuring that second ring.  However, since we don't use it we
  * don't actually fill the descriptors, and only hand off the first
  * four to the chip.
  */
 #include <sys/cdefs.h>
-__KERNEL_RCSID(0, "$NetBSD: if_cas.c,v 1.26 2016/12/15 09:28:05 ozaki-r Exp $");
+__KERNEL_RCSID(0, "$NetBSD: if_cas.c,v 1.26.8.1 2019/12/05 16:50:54 bouyer Exp $");
 #ifndef _MODULE
 #include "opt_inet.h"
 #endif
 #include <sys/param.h>
 #include <sys/systm.h>
 #include <sys/callout.h>
 #include <sys/mbuf.h>
 #include <sys/syslog.h>
 #include <sys/malloc.h>
 #include <sys/kernel.h>
 #include <sys/socket.h>
 @@ -242,27 +242,27 @@ cas_pci_enaddr(struct cas_softc *sc, str
 	vpdoff = buf[PROMDATA_PTR_VPD] | (buf[PROMDATA_PTR_VPD + 1] << 8);
 	if (vpdoff < 0x1c)
 		goto fail;
 next:
 	bus_space_read_region_1(romt, romh, vpdoff, buf, sizeof(buf));
 	if (!PCI_VPDRES_ISLARGE(buf[0]))
 		goto fail;
 	res = (struct pci_vpd_largeres *)buf;
 	vpdoff += sizeof(*res);
 	len = ((res->vpdres_len_msb << 8) + res->vpdres_len_lsb);
-	switch(PCI_VPDRES_LARGE_NAME(res->vpdres_byte0)) {
+	switch (PCI_VPDRES_LARGE_NAME(res->vpdres_byte0)) {
 	case PCI_VPDRES_TYPE_IDENTIFIER_STRING:
 		/* Skip identifier string. */
 		vpdoff += len;
 		goto next;
 	case PCI_VPDRES_TYPE_VPD:
 		while (len > 0) {
 			bus_space_read_region_1(romt, romh, vpdoff,
 			     buf, sizeof(buf));
 			vpd = (struct pci_vpd *)buf;
 			vpdoff += sizeof(*vpd) + vpd->vpd_len;
 			len -= sizeof(*vpd) + vpd->vpd_len;
 @@ -286,27 +286,27 @@ next:
 			 * ...that's a byte array with the proper
 			 * length for a MAC address...
 			 */
 			if (desc[0] != 'B' || desc[1] != ETHER_ADDR_LEN)
 				continue;
 			desc += 2;
 			/*
 			 * ...named "local-mac-address".
 			 */
 			if (strcmp(desc, "local-mac-address") != 0)
 				continue;
 			desc += strlen("local-mac-address") + 1;
 			memcpy(enaddr, desc, ETHER_ADDR_LEN);
 			rv = 0;
+		}
 		break;
 	default:
 		goto fail;
+	}
  fail:
 	if (romsize != 0)
 		bus_space_unmap(romt, romh, romsize);
 @@ -413,27 +413,28 @@ cas_config(struct cas_softc *sc, const u
 	/* XXX should map this in with correct endianness */
 	if ((error = bus_dmamem_map(sc->sc_dmatag, &sc->sc_cdseg, sc->sc_cdnseg,
 	    sizeof(struct cas_control_data), (void **)&sc->sc_control_data,
 	    BUS_DMA_COHERENT)) != 0) {
 		aprint_error_dev(sc->sc_dev,
 		    "unable to map control data, error = %d\n", error);
 		cas_partial_detach(sc, CAS_ATT_1);
+	}
 	if ((error = bus_dmamap_create(sc->sc_dmatag,
 	    sizeof(struct cas_control_data), 1,
 	    sizeof(struct cas_control_data), 0, 0, &sc->sc_cddmamap)) != 0) {
 		aprint_error_dev(sc->sc_dev,
-		    "unable to create control data DMA map, error = %d\n", error);
+		    "unable to create control data DMA map, error = %d\n",
 		    error);
 		cas_partial_detach(sc, CAS_ATT_2);
+	}
 	if ((error = bus_dmamap_load(sc->sc_dmatag, sc->sc_cddmamap,
 	    sc->sc_control_data, sizeof(struct cas_control_data), NULL,
 )) != 0) {
 		aprint_error_dev(sc->sc_dev,
 		    "unable to load control data DMA map, error = %d\n",
 		    error);
 		cas_partial_detach(sc, CAS_ATT_3);
+	}
 	memset(sc->sc_control_data, 0, sizeof(struct cas_control_data));
 @@ -530,57 +531,57 @@ cas_config(struct cas_softc *sc, const u
 	mii->mii_writereg = cas_mii_writereg;
 	mii->mii_statchg = cas_mii_statchg;
 	ifmedia_init(&mii->mii_media, 0, cas_mediachange, cas_mediastatus);
 	sc->sc_ethercom.ec_mii = mii;
 	bus_space_write_4(sc->sc_memt, sc->sc_memh, CAS_MII_DATAPATH_MODE, 0);
 	cas_mifinit(sc);
 	if (sc->sc_mif_config & CAS_MIF_CONFIG_MDI1) {
 		sc->sc_mif_config |= CAS_MIF_CONFIG_PHY_SEL;
 		bus_space_write_4(sc->sc_memt, sc->sc_memh,
-	            CAS_MIF_CONFIG, sc->sc_mif_config);
+		    CAS_MIF_CONFIG, sc->sc_mif_config);
+	}
 	mii_attach(sc->sc_dev, mii, 0xffffffff, MII_PHY_ANY,
 	    MII_OFFSET_ANY, 0);
 	child = LIST_FIRST(&mii->mii_phys);
 	if (child == NULL &&
-	    sc->sc_mif_config & (CAS_MIF_CONFIG_MDI0|CAS_MIF_CONFIG_MDI1)) {
+	    sc->sc_mif_config & (CAS_MIF_CONFIG_MDI0 | CAS_MIF_CONFIG_MDI1)) {
 		/*
 		 * Try the external PCS SERDES if we didn't find any
 		 * MII devices.
 		 */
 		bus_space_write_4(sc->sc_memt, sc->sc_memh,
 		    CAS_MII_DATAPATH_MODE, CAS_MII_DATAPATH_SERDES);
 		bus_space_write_4(sc->sc_memt, sc->sc_memh,
 		     CAS_MII_CONFIG, CAS_MII_CONFIG_ENABLE);
 		mii->mii_readreg = cas_pcs_readreg;
 		mii->mii_writereg = cas_pcs_writereg;
 		mii_attach(sc->sc_dev, mii, 0xffffffff, MII_PHY_ANY,
 		    MII_OFFSET_ANY, MIIF_NOISOLATE);
+	}
 	child = LIST_FIRST(&mii->mii_phys);
 	if (child == NULL) {
 		/* No PHY attached */
-		ifmedia_add(&sc->sc_media, IFM_ETHER|IFM_MANUAL, 0, NULL);
+		ifmedia_add(&sc->sc_media, IFM_ETHER | IFM_MANUAL, 0, NULL);
-		ifmedia_set(&sc->sc_media, IFM_ETHER|IFM_MANUAL);
+		ifmedia_set(&sc->sc_media, IFM_ETHER | IFM_MANUAL);
 	} else {
 		/*
 		 * Walk along the list of attached MII devices and
 		 * establish an `MII instance' to `phy number'
 		 * mapping. We'll use this mapping in media change
 		 * requests to determine which phy to use to program
 		 * the MIF configuration register.
 		 */
 		for (; child != NULL; child = LIST_NEXT(child, mii_list)) {
 			/*
 			 * Note: we support just two PHYs: the built-in
 			 * internal device and an external on the MII
 			 * connector.
 @@ -591,27 +592,27 @@ cas_config(struct cas_softc *sc, const u
 				    " at phy %d, instance %d\n",
 				    device_xname(child->mii_dev),
 				    child->mii_phy, child->mii_inst);
 				continue;
+			}
 			sc->sc_phys[child->mii_inst] = child->mii_phy;
+		}
 		/*
 		 * XXX - we can really do the following ONLY if the
 		 * phy indeed has the auto negotiation capability!!
 		 */
-		ifmedia_set(&sc->sc_media, IFM_ETHER|IFM_AUTO);
+		ifmedia_set(&sc->sc_media, IFM_ETHER | IFM_AUTO);
+	}
 	/* claim 802.1q capability */
 	sc->sc_ethercom.ec_capabilities |= ETHERCAP_VLAN_MTU;
 	/* Attach the interface. */
 	if_attach(ifp);
 	if_deferred_start_init(ifp, NULL);
 	ether_ifattach(ifp, enaddr);
 	rnd_attach_source(&sc->rnd_source, device_xname(sc->sc_dev),
 			  RND_TYPE_NET, RND_FLAG_DEFAULT);
 @@ -964,47 +965,47 @@ cas_disable_tx(struct cas_softc *sc)
 int
 cas_meminit(struct cas_softc *sc)
+{
 	int i;
 	/*
 	 * Initialize the transmit descriptor ring.
 	 */
 	for (i = 0; i < CAS_NTXDESC; i++) {
 		sc->sc_txdescs[i].cd_flags = 0;
 		sc->sc_txdescs[i].cd_addr = 0;
+	}
 	CAS_CDTXSYNC(sc, 0, CAS_NTXDESC,
-	    BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE);
+	    BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
 	/*
 	 * Initialize the receive descriptor and receive job
 	 * descriptor rings.
 	 */
 	for (i = 0; i < CAS_NRXDESC; i++)
 		CAS_INIT_RXDESC(sc, i, i);
 	sc->sc_rxdptr = 0;
 	sc->sc_rxptr = 0;
 	/*
 	 * Initialize the receive completion ring.
 	 */
 	for (i = 0; i < CAS_NRXCOMP; i++) {
 		sc->sc_rxcomps[i].cc_word[0] = 0;
 		sc->sc_rxcomps[i].cc_word[1] = 0;
 		sc->sc_rxcomps[i].cc_word[2] = 0;
 		sc->sc_rxcomps[i].cc_word[3] = CAS_DMA_WRITE(CAS_RC3_OWN);
 		CAS_CDRXCSYNC(sc, i,
-		    BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE);
+		    BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
+	}
 	return (0);
+}
 int
 cas_ringsize(int sz)
+{
 	switch (sz) {
 	case 32:
 		return CAS_RING_SZ_32;
 	case 64:
 		return CAS_RING_SZ_64;
 @@ -1079,71 +1080,71 @@ cas_init(struct ifnet *ifp)
 	/* step 4. TX MAC registers & counters */
 	cas_init_regs(sc);
 	max_frame_size = ETHER_MAX_LEN + ETHER_VLAN_ENCAP_LEN;
 	v = (max_frame_size) | (0x2000 << 16) /* Burst size */;
 	bus_space_write_4(t, h, CAS_MAC_MAC_MAX_FRAME, v);
 	/* step 5. RX MAC registers & counters */
 	cas_iff(sc);
 	/* step 6 & 7. Program Descriptor Ring Base Addresses */
 	KASSERT((CAS_CDTXADDR(sc, 0) & 0x1fff) == 0);
 	bus_space_write_4(t, h, CAS_TX_RING_PTR_HI,
-	    (((uint64_t)CAS_CDTXADDR(sc,0)) >> 32));
+	    (((uint64_t)CAS_CDTXADDR(sc, 0)) >> 32));
 	bus_space_write_4(t, h, CAS_TX_RING_PTR_LO, CAS_CDTXADDR(sc, 0));
 	KASSERT((CAS_CDRXADDR(sc, 0) & 0x1fff) == 0);
 	bus_space_write_4(t, h, CAS_RX_DRING_PTR_HI,
-	    (((uint64_t)CAS_CDRXADDR(sc,0)) >> 32));
+	    (((uint64_t)CAS_CDRXADDR(sc, 0)) >> 32));
 	bus_space_write_4(t, h, CAS_RX_DRING_PTR_LO, CAS_CDRXADDR(sc, 0));
 	KASSERT((CAS_CDRXCADDR(sc, 0) & 0x1fff) == 0);
 	bus_space_write_4(t, h, CAS_RX_CRING_PTR_HI,
-	    (((uint64_t)CAS_CDRXCADDR(sc,0)) >> 32));
+	    (((uint64_t)CAS_CDRXCADDR(sc, 0)) >> 32));
 	bus_space_write_4(t, h, CAS_RX_CRING_PTR_LO, CAS_CDRXCADDR(sc, 0));
 	if (CAS_PLUS(sc)) {
 		KASSERT((CAS_CDRXADDR2(sc, 0) & 0x1fff) == 0);
 		bus_space_write_4(t, h, CAS_RX_DRING_PTR_HI2,
-		    (((uint64_t)CAS_CDRXADDR2(sc,0)) >> 32));
+		    (((uint64_t)CAS_CDRXADDR2(sc, 0)) >> 32));
 		bus_space_write_4(t, h, CAS_RX_DRING_PTR_LO2,
 		    CAS_CDRXADDR2(sc, 0));
+	}
 	/* step 8. Global Configuration & Interrupt Mask */
 	cas_estintr(sc, CAS_INTR_REG);
 	/* step 9. ETX Configuration: use mostly default values */
 	/* Enable DMA */
 	v = cas_ringsize(CAS_NTXDESC /*XXX*/) << 10;
 	bus_space_write_4(t, h, CAS_TX_CONFIG,
-	    v|CAS_TX_CONFIG_TXDMA_EN|(1<<24)|(1<<29));
+	    v | CAS_TX_CONFIG_TXDMA_EN | (1 << 24) | (1 << 29));
 	bus_space_write_4(t, h, CAS_TX_KICK, 0);
 	/* step 10. ERX Configuration */
 	/* Encode Receive Descriptor ring size */
 	v = cas_ringsize(CAS_NRXDESC) << CAS_RX_CONFIG_RXDRNG_SZ_SHIFT;
 	if (CAS_PLUS(sc))
 		v |= cas_ringsize(32) << CAS_RX_CONFIG_RXDRNG2_SZ_SHIFT;
 	/* Encode Receive Completion ring size */
 	v |= cas_cringsize(CAS_NRXCOMP) << CAS_RX_CONFIG_RXCRNG_SZ_SHIFT;
 	/* Enable DMA */
 	bus_space_write_4(t, h, CAS_RX_CONFIG,
-	    v|(2<<CAS_RX_CONFIG_FBOFF_SHFT)|CAS_RX_CONFIG_RXDMA_EN);
+	    v|(2<<CAS_RX_CONFIG_FBOFF_SHFT) | CAS_RX_CONFIG_RXDMA_EN);
 	/*
 	 * The following value is for an OFF Threshold of about 3/4 full
 	 * and an ON Threshold of 1/4 full.
 	 */
 	bus_space_write_4(t, h, CAS_RX_PAUSE_THRESH,
 	    (3 * sc->sc_rxfifosize / 256) |
 	    ((sc->sc_rxfifosize / 256) << 12));
 	bus_space_write_4(t, h, CAS_RX_BLANKING, (6 << 12) | 6);
 	/* step 11. Configure Media */
 	mii_ifmedia_change(&sc->sc_mii);
 @@ -1255,52 +1256,52 @@ cas_rint(struct cas_softc *sc)
+{
 	struct ifnet *ifp = &sc->sc_ethercom.ec_if;
 	bus_space_tag_t t = sc->sc_memt;
 	bus_space_handle_t h = sc->sc_memh;
 	struct cas_rxsoft *rxs;
 	struct mbuf *m;
 	u_int64_t word[4];
 	int len, off, idx;
 	int i, skip;
 	void *cp;
 	for (i = sc->sc_rxptr;; i = CAS_NEXTRX(i + skip)) {
 		CAS_CDRXCSYNC(sc, i,
-		    BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE);
+		    BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE);
 		word[0] = CAS_DMA_READ(sc->sc_rxcomps[i].cc_word[0]);
 		word[1] = CAS_DMA_READ(sc->sc_rxcomps[i].cc_word[1]);
 		word[2] = CAS_DMA_READ(sc->sc_rxcomps[i].cc_word[2]);
 		word[3] = CAS_DMA_READ(sc->sc_rxcomps[i].cc_word[3]);
 		/* Stop if the hardware still owns the descriptor. */
 		if ((word[0] & CAS_RC0_TYPE) == 0 || word[3] & CAS_RC3_OWN)
 			break;
 		len = CAS_RC1_HDR_LEN(word[1]);
 		if (len > 0) {
 			off = CAS_RC1_HDR_OFF(word[1]);
 			idx = CAS_RC1_HDR_IDX(word[1]);
 			rxs = &sc->sc_rxsoft[idx];
 			DPRINTF(sc, ("hdr at idx %d, off %d, len %d\n",
 			    idx, off, len));
 			bus_dmamap_sync(sc->sc_dmatag, rxs->rxs_dmamap, 0,
 			    rxs->rxs_dmamap->dm_mapsize, BUS_DMASYNC_POSTREAD);
 			cp = rxs->rxs_kva + off * 256 + ETHER_ALIGN;
 			m = m_devget(cp, len, 0, ifp, NULL);
 			if (word[0] & CAS_RC0_RELEASE_HDR)
 				cas_add_rxbuf(sc, idx);
 			if (m != NULL) {
 				/*
 				 * Pass this up to any BPF listeners, but only
 				 * pass it up the stack if its for us.
 				 */
 				m->m_pkthdr.csum_flags = 0;
 				if_percpuq_enqueue(ifp->if_percpuq, m);
 			} else
 				ifp->if_ierrors++;
 @@ -1339,27 +1340,27 @@ cas_rint(struct cas_softc *sc)
 		if (word[0] & CAS_RC0_SPLIT)
 			aprint_error_dev(sc->sc_dev, "split packet\n");
 		skip = CAS_RC0_SKIP(word[0]);
+	}
 	while (sc->sc_rxptr != i) {
 		sc->sc_rxcomps[sc->sc_rxptr].cc_word[0] = 0;
 		sc->sc_rxcomps[sc->sc_rxptr].cc_word[1] = 0;
 		sc->sc_rxcomps[sc->sc_rxptr].cc_word[2] = 0;
 		sc->sc_rxcomps[sc->sc_rxptr].cc_word[3] =
 		    CAS_DMA_WRITE(CAS_RC3_OWN);
 		CAS_CDRXCSYNC(sc, sc->sc_rxptr,
-		    BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE);
+		    BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
 		sc->sc_rxptr = CAS_NEXTRX(sc->sc_rxptr);
+	}
 	bus_space_write_4(t, h, CAS_RX_COMP_TAIL, sc->sc_rxptr);
 	DPRINTF(sc, ("cas_rint: done sc->rxptr %d, complete %d\n",
 		sc->sc_rxptr, bus_space_read_4(t, h, CAS_RX_COMPLETION)));
 	return (1);
+}
 /*
 @@ -1606,30 +1607,30 @@ cas_mii_statchg(struct ifnet *ifp)
 	bus_space_tag_t t = sc->sc_memt;
 	bus_space_handle_t mac = sc->sc_memh;
 	u_int32_t v;
 #ifdef CAS_DEBUG
 	if (sc->sc_debug)
 		printf("cas_mii_statchg: status change: phy = %d\n",
 		    sc->sc_phys[instance]);
 #endif
 	/* Set tx full duplex options */
 	bus_space_write_4(t, mac, CAS_MAC_TX_CONFIG, 0);
 	delay(10000); /* reg must be cleared and delay before changing. */
-	v = CAS_MAC_TX_ENA_IPG0|CAS_MAC_TX_NGU|CAS_MAC_TX_NGU_LIMIT|
+	v = CAS_MAC_TX_ENA_IPG0 | CAS_MAC_TX_NGU | CAS_MAC_TX_NGU_LIMIT |
 		CAS_MAC_TX_ENABLE;
 	if ((IFM_OPTIONS(sc->sc_mii.mii_media_active) & IFM_FDX) != 0) {
-		v |= CAS_MAC_TX_IGN_CARRIER|CAS_MAC_TX_IGN_COLLIS;
+		v |= CAS_MAC_TX_IGN_CARRIER | CAS_MAC_TX_IGN_COLLIS;
+	}
 	bus_space_write_4(t, mac, CAS_MAC_TX_CONFIG, v);
 	/* XIF Configuration */
 	v = CAS_MAC_XIF_TX_MII_ENA;
 	v |= CAS_MAC_XIF_LINK_LED;
 	/* MII needs echo disable if half duplex. */
 	if ((IFM_OPTIONS(sc->sc_mii.mii_media_active) & IFM_FDX) != 0)
 		/* turn on full duplex LED */
 		v |= CAS_MAC_XIF_FDPLX_LED;
 	else
 		/* half duplex -- disable echo */
 @@ -1665,27 +1666,27 @@ cas_pcs_readreg(device_t self, int phy,
 	case MII_BMCR:
 		reg = CAS_MII_CONTROL;
 		break;
 	case MII_BMSR:
 		reg = CAS_MII_STATUS;
 		break;
 	case MII_ANAR:
 		reg = CAS_MII_ANAR;
 		break;
 	case MII_ANLPAR:
 		reg = CAS_MII_ANLPAR;
 		break;
 	case MII_EXTSR:
-		return (EXTSR_1000XFDX|EXTSR_1000XHDX);
+		return (EXTSR_1000XFDX | EXTSR_1000XHDX);
 	default:
 		return (0);
+	}
 	return bus_space_read_4(t, pcs, reg);
+}
 void
 cas_pcs_writereg(device_t self, int phy, int reg, int val)
+{
 	struct cas_softc *sc = device_private(self);
 	bus_space_tag_t t = sc->sc_memt;
 	bus_space_handle_t pcs = sc->sc_memh;
 @@ -1826,35 +1827,35 @@ cas_estintr(struct cas_softc *sc, int wh
 			    "unable to establish interrupt");
 			if (intrstr != NULL)
 				aprint_error(" at %s", intrstr);
 			aprint_error("\n");
 			return false;
+		}
 		aprint_normal_dev(sc->sc_dev, "interrupting at %s\n", intrstr);
+	}
 	/* Interrupt register */
 	if (what & CAS_INTR_REG) {
 		bus_space_write_4(t, h, CAS_INTMASK,
-		    ~(CAS_INTR_TX_INTME|CAS_INTR_TX_EMPTY|
+		    ~(CAS_INTR_TX_INTME | CAS_INTR_TX_EMPTY |
-		    CAS_INTR_TX_TAG_ERR|
+		    CAS_INTR_TX_TAG_ERR |
-		    CAS_INTR_RX_DONE|CAS_INTR_RX_NOBUF|
+		    CAS_INTR_RX_DONE | CAS_INTR_RX_NOBUF |
-		    CAS_INTR_RX_TAG_ERR|
+		    CAS_INTR_RX_TAG_ERR |
-		    CAS_INTR_RX_COMP_FULL|CAS_INTR_PCS|
+		    CAS_INTR_RX_COMP_FULL | CAS_INTR_PCS |
-		    CAS_INTR_MAC_CONTROL|CAS_INTR_MIF|
+		    CAS_INTR_MAC_CONTROL | CAS_INTR_MIF |
 		    CAS_INTR_BERR));
 		bus_space_write_4(t, h, CAS_MAC_RX_MASK,
-		    CAS_MAC_RX_DONE|CAS_MAC_RX_FRAME_CNT);
+		    CAS_MAC_RX_DONE | CAS_MAC_RX_FRAME_CNT);
 		bus_space_write_4(t, h, CAS_MAC_TX_MASK, CAS_MAC_TX_XMIT_DONE);
 		bus_space_write_4(t, h, CAS_MAC_CONTROL_MASK, 0); /* XXXX */
+	}
 	return true;
+}
 bool
 cas_shutdown(device_t self, int howto)
+{
 	struct cas_softc *sc = device_private(self);
 	struct ifnet *ifp = &sc->sc_ethercom.ec_if;
 	cas_stop(ifp, 1);
 @@ -1869,70 +1870,80 @@ cas_iff(struct cas_softc *sc)
 	struct ethercom *ec = &sc->sc_ethercom;
 	struct ether_multi *enm;
 	struct ether_multistep step;
 	bus_space_tag_t t = sc->sc_memt;
 	bus_space_handle_t h = sc->sc_memh;
 	u_int32_t crc, hash[16], rxcfg;
 	int i;
 	rxcfg = bus_space_read_4(t, h, CAS_MAC_RX_CONFIG);
 	rxcfg &= ~(CAS_MAC_RX_HASH_FILTER | CAS_MAC_RX_PROMISCUOUS |
 	    CAS_MAC_RX_PROMISC_GRP);
 	ifp->if_flags &= ~IFF_ALLMULTI;
-	if (ifp->if_flags & IFF_PROMISC || ec->ec_multicnt > 0) {
+	if ((ifp->if_flags & IFF_PROMISC) != 0)
-		ifp->if_flags |= IFF_ALLMULTI;
+		goto update;
 		if (ifp->if_flags & IFF_PROMISC)
 			rxcfg |= CAS_MAC_RX_PROMISCUOUS;
 		else
 			rxcfg |= CAS_MAC_RX_PROMISC_GRP;
         } else {
 		/*
 		 * Set up multicast address filter by passing all multicast
 		 * addresses through a crc generator, and then using the
 		 * high order 8 bits as an index into the 256 bit logical
 		 * address filter.  The high order 4 bits selects the word,
 		 * while the other 4 bits select the bit within the word
 		 * (where bit 0 is the MSB).
 		 */
-		rxcfg |= CAS_MAC_RX_HASH_FILTER;
+	/*
 	 * Set up multicast address filter by passing all multicast
 	 * addresses through a crc generator, and then using the
 	 * high order 8 bits as an index into the 256 bit logical
 	 * address filter.  The high order 4 bits selects the word,
 	 * while the other 4 bits select the bit within the word
 	 * (where bit 0 is the MSB).
 	 */
-		/* Clear hash table */
+	/* Clear hash table */
-		for (i = 0; i < 16; i++)
+	for (i = 0; i < 16; i++)
-			hash[i] = 0;
+		hash[i] = 0;
 	ETHER_FIRST_MULTI(step, ec, enm);
 	while (enm != NULL) {
 		if (memcmp(enm->enm_addrlo, enm->enm_addrhi, ETHER_ADDR_LEN)) {
 			/* XXX Use ETHER_F_ALLMULTI in future. */
 			ifp->if_flags |= IFF_ALLMULTI;
 			ETHER_UNLOCK(ec);
 			goto update;
+		}
-		ETHER_FIRST_MULTI(step, ec, enm);
+		crc = ether_crc32_le(enm->enm_addrlo, ETHER_ADDR_LEN);
 		while (enm != NULL) {
                         crc = ether_crc32_le(enm->enm_addrlo,
                             ETHER_ADDR_LEN);
-                        /* Just want the 8 most significant bits. */
+		/* Just want the 8 most significant bits. */
-                        crc >>= 24;
+		crc >>= 24;
-                        /* Set the corresponding bit in the filter. */
+		/* Set the corresponding bit in the filter. */
-                        hash[crc >> 4] |= 1 << (15 - (crc & 15));
+		hash[crc >> 4] |= 1 << (15 - (crc & 15));
-			ETHER_NEXT_MULTI(step, enm);
+		ETHER_NEXT_MULTI(step, enm);
+	}
-		/* Now load the hash table into the chip (if we are using it) */
+	rxcfg |= CAS_MAC_RX_HASH_FILTER;
 		for (i = 0; i < 16; i++) {
-			bus_space_write_4(t, h,
+	/* Now load the hash table into the chip (if we are using it) */
-			    CAS_MAC_HASH0 + i * (CAS_MAC_HASH1 - CAS_MAC_HASH0),
+	for (i = 0; i < 16; i++) {
-			    hash[i]);
+		bus_space_write_4(t, h,
 		    CAS_MAC_HASH0 + i * (CAS_MAC_HASH1 - CAS_MAC_HASH0),
 		    hash[i]);
+	}
 update:
 	if ((ifp->if_flags & (IFF_PROMISC | IFF_ALLMULTI)) != 0) {
 		if (ifp->if_flags & IFF_PROMISC) {
 			rxcfg |= CAS_MAC_RX_PROMISCUOUS;
 			/* XXX Use ETHER_F_ALLMULTI in future. */
 			ifp->if_flags |= IFF_ALLMULTI;
 		} else
 			rxcfg |= CAS_MAC_RX_PROMISC_GRP;
+	}
 	bus_space_write_4(t, h, CAS_MAC_RX_CONFIG, rxcfg);
+}
 int
 cas_encap(struct cas_softc *sc, struct mbuf *mhead, u_int32_t *bixp)
+{
 	u_int64_t flags;
 	u_int32_t cur, frag, i;
 	bus_dmamap_t map;
 	cur = frag = *bixp;
 	map = sc->sc_txd[cur].sd_map;

 @@ -1,14 +1,14 @@
-/*	$NetBSD: if_ale.c,v 1.22.2.2 2019/11/06 10:04:47 martin Exp $	*/
+/*	$NetBSD: if_ale.c,v 1.22.2.3 2019/12/05 16:50:54 bouyer Exp $	*/
 /*-
  * Copyright (c) 2008, Pyun YongHyeon <yongari@FreeBSD.org>
  * All rights reserved.
+ *
  * Redistribution and use in source and binary forms, with or without
  * modification, are permitted provided that the following conditions
  * are met:
  * 1. Redistributions of source code must retain the above copyright
  *    notice unmodified, this list of conditions, and the following
  *    disclaimer.
  * 2. Redistributions in binary form must reproduce the above copyright
  *    notice, this list of conditions and the following disclaimer in the
 @@ -22,27 +22,27 @@
  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
  * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
  * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
  * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
  * SUCH DAMAGE.
+ *
  * $FreeBSD: src/sys/dev/ale/if_ale.c,v 1.3 2008/12/03 09:01:12 yongari Exp $
  */
 /* Driver for Atheros AR8121/AR8113/AR8114 PCIe Ethernet. */
 #include <sys/cdefs.h>
-__KERNEL_RCSID(0, "$NetBSD: if_ale.c,v 1.22.2.2 2019/11/06 10:04:47 martin Exp $");
+__KERNEL_RCSID(0, "$NetBSD: if_ale.c,v 1.22.2.3 2019/12/05 16:50:54 bouyer Exp $");
 #include "vlan.h"
 #include <sys/param.h>
 #include <sys/proc.h>
 #include <sys/endian.h>
 #include <sys/systm.h>
 #include <sys/types.h>
 #include <sys/sockio.h>
 #include <sys/mbuf.h>
 #include <sys/queue.h>
 #include <sys/kernel.h>
 #include <sys/device.h>
 @@ -1980,36 +1980,46 @@ ale_rxfilter(struct ale_softc *sc)
 	uint32_t crc;
 	uint32_t mchash[2];
 	uint32_t rxcfg;
 	rxcfg = CSR_READ_4(sc, ALE_MAC_CFG);
 	rxcfg &= ~(MAC_CFG_ALLMULTI | MAC_CFG_BCAST | MAC_CFG_PROMISC);
 	ifp->if_flags &= ~IFF_ALLMULTI;
 	/*
 	 * Always accept broadcast frames.
 	 */
 	rxcfg |= MAC_CFG_BCAST;
-	if (ifp->if_flags & IFF_PROMISC || ec->ec_multicnt > 0) {
+	/* Program new filter. */
-		ifp->if_flags |= IFF_ALLMULTI;
+	if ((ifp->if_flags & IFF_PROMISC) != 0)
-		if (ifp->if_flags & IFF_PROMISC)
+		goto update;
 	memset(mchash, 0, sizeof(mchash));
 	ETHER_FIRST_MULTI(step, ec, enm);
 	while (enm != NULL) {
 		if (memcmp(enm->enm_addrlo, enm->enm_addrhi, ETHER_ADDR_LEN)) {
 			/* XXX Use ETHER_F_ALLMULTI in future. */
 			ifp->if_flags |= IFF_ALLMULTI;
 			ETHER_UNLOCK(ec);
 			goto update;
+		}
 		crc = ether_crc32_be(enm->enm_addrlo, ETHER_ADDR_LEN);
 		mchash[crc >> 31] |= 1 << ((crc >> 26) & 0x1f);
 		ETHER_NEXT_MULTI(step, enm);
+	}
 update:
 	if ((ifp->if_flags & (IFF_PROMISC | IFF_ALLMULTI)) != 0) {
 		if (ifp->if_flags & IFF_PROMISC) {
 			rxcfg |= MAC_CFG_PROMISC;
-		else
+			/* XXX Use ETHER_F_ALLMULTI in future. */
 			ifp->if_flags |= IFF_ALLMULTI;
 		} else
 			rxcfg |= MAC_CFG_ALLMULTI;
 		mchash[0] = mchash[1] = 0xFFFFFFFF;
 	} else {
 		/* Program new filter. */
 		memset(mchash, 0, sizeof(mchash));
 		ETHER_FIRST_MULTI(step, ec, enm);
 		while (enm != NULL) {
 			crc = ether_crc32_be(enm->enm_addrlo, ETHER_ADDR_LEN);
 			mchash[crc >> 31] |= 1 << ((crc >> 26) & 0x1f);
 			ETHER_NEXT_MULTI(step, enm);
+	}
 	CSR_WRITE_4(sc, ALE_MAR0, mchash[0]);
 	CSR_WRITE_4(sc, ALE_MAR1, mchash[1]);
 	CSR_WRITE_4(sc, ALE_MAC_CFG, rxcfg);
+}