 @@ -1,38 +1,38 @@
-/* $NetBSD: piixpm.c,v 1.56 2019/12/23 15:41:34 thorpej Exp $ */
+/* $NetBSD: piixpm.c,v 1.57 2019/12/23 23:31:23 msaitoh Exp $ */
 /*	$OpenBSD: piixpm.c,v 1.39 2013/10/01 20:06:02 sf Exp $	*/
 /*
  * Copyright (c) 2005, 2006 Alexander Yurchenko <grange@openbsd.org>
+ *
  * Permission to use, copy, modify, and distribute this software for any
  * purpose with or without fee is hereby granted, provided that the above
  * copyright notice and this permission notice appear in all copies.
+ *
  * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
  * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
  * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
  * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
  * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
  * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
  * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
  */
 /*
  * Intel PIIX and compatible Power Management controller driver.
  */
 #include <sys/cdefs.h>
-__KERNEL_RCSID(0, "$NetBSD: piixpm.c,v 1.56 2019/12/23 15:41:34 thorpej Exp $");
+__KERNEL_RCSID(0, "$NetBSD: piixpm.c,v 1.57 2019/12/23 23:31:23 msaitoh Exp $");
 #include <sys/param.h>
 #include <sys/systm.h>
 #include <sys/device.h>
 #include <sys/kernel.h>
 #include <sys/mutex.h>
 #include <sys/proc.h>
 #include <sys/bus.h>
 #include <dev/pci/pcidevs.h>
 #include <dev/pci/pcireg.h>
 #include <dev/pci/pcivar.h>
 @@ -220,28 +220,26 @@ piixpm_attach(device_t parent, device_t
 	/*
 	 * Revision 0 and 1 are PIIX4, 2 is PIIX4E, 3 is PIIX4M.
 	 * PIIX4 and PIIX4E have a bug in the timer latch, see Errata #20
 	 * in the "Specification update" (document #297738).
 	 */
 	acpipmtimer_attach(self, sc->sc_pm_iot, sc->sc_pm_ioh, PIIX_PM_PMTMR,
 	    (PCI_REVISION(pa->pa_class) < 3) ? ACPIPMT_BADLATCH : 0);
 nopowermanagement:
 	/* SB800 rev 0x40+, AMD HUDSON and newer need special initialization */
 	if (PIIXPM_IS_FCHGRP(sc) || PIIXPM_IS_SB800GRP(sc)) {
 		if (piixpm_sb800_init(sc) == 0) {
 			sc->sc_numbusses = 4;
 			/* Read configuration */
 			conf = pci_conf_read(pa->pa_pc, pa->pa_tag,
 			    SB800_SMB_HOSTC);
 			DPRINTF(("%s: conf 0x%08x\n", device_xname(self),
 				conf));
 			usesmi = conf & SB800_SMB_HOSTC_SMI;
 			goto setintr;
+		}
 		aprint_normal_dev(self, "SMBus initialization failed\n");
 		return;
+	}
 @@ -389,26 +387,32 @@ piixpm_resume(device_t dv, const pmf_qua
  * Extract SMBus base address from SB800 Power Management (PM) registers.
  * The PM registers can be accessed either through indirect I/O (CD6/CD7) or
  * direct mapping if AcpiMMioDecodeEn is enabled. Since this function is only
  * called once it uses indirect I/O for simplicity.
  */
 static int
 piixpm_sb800_init(struct piixpm_softc *sc)
+{
 	bus_space_tag_t iot = sc->sc_iot;
 	bus_space_handle_t ioh;	/* indirect I/O handle */
 	uint16_t val, base_addr;
 	bool enabled;
 	if (PIIXPM_IS_KERNCZ(sc) ||
 	    (PIIXPM_IS_HUDSON(sc) && (sc->sc_rev >= 0x1f)))
 		sc->sc_numbusses = 2;
 	else
 		sc->sc_numbusses = 4;
 	/* Fetch SMB base address */
 	if (bus_space_map(iot,
 	    SB800_INDIRECTIO_BASE, SB800_INDIRECTIO_SIZE, 0, &ioh)) {
 		device_printf(sc->sc_dev, "couldn't map indirect I/O space\n");
 		return EBUSY;
+	}
 	if (PIIXPM_IS_FCHGRP(sc)) {
 		bus_space_write_1(iot, ioh, SB800_INDIRECTIO_INDEX,
 		    AMDFCH41_PM_DECODE_EN0);
 		val = bus_space_read_1(iot, ioh, SB800_INDIRECTIO_DATA);
 		enabled = val & AMDFCH41_SMBUS_EN;
 		if (!enabled)
 			return ENOENT;