 @@ -1,577 +1,579 @@
-/* $NetBSD: cpu.c,v 1.20.2.1 2019/10/23 19:14:19 martin Exp $ */
+/* $NetBSD: cpu.c,v 1.20.2.2 2019/12/29 09:40:59 martin Exp $ */
 /*
  * Copyright (c) 2017 Ryo Shimizu <ryo@nerv.org>
  * All rights reserved.
+ *
  * Redistribution and use in source and binary forms, with or without
  * modification, are permitted provided that the following conditions
  * are met:
  * 1. Redistributions of source code must retain the above copyright
  *    notice, this list of conditions and the following disclaimer.
  * 2. Redistributions in binary form must reproduce the above copyright
  *    notice, this list of conditions and the following disclaimer in the
  *    documentation and/or other materials provided with the distribution.
+ *
  * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
  * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
  * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
  * DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT,
  * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
  * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
  * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
  * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
  * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
  * POSSIBILITY OF SUCH DAMAGE.
  */
 #include <sys/cdefs.h>
-__KERNEL_RCSID(1, "$NetBSD: cpu.c,v 1.20.2.1 2019/10/23 19:14:19 martin Exp $");
+__KERNEL_RCSID(1, "$NetBSD: cpu.c,v 1.20.2.2 2019/12/29 09:40:59 martin Exp $");
 #include "locators.h"
 #include "opt_arm_debug.h"
 #include "opt_fdt.h"
 #include "opt_multiprocessor.h"
 #include <sys/param.h>
 #include <sys/systm.h>
 #include <sys/atomic.h>
 #include <sys/device.h>
 #include <sys/cpu.h>
 #include <sys/kmem.h>
 #include <sys/reboot.h>
 #include <sys/sysctl.h>
 #include <aarch64/armreg.h>
 #include <aarch64/cpu.h>
 #include <aarch64/cpufunc.h>
 #include <aarch64/machdep.h>
 #ifdef FDT
 #include <arm/fdt/arm_fdtvar.h>
 #endif
 #ifdef VERBOSE_INIT_ARM
 #define VPRINTF(...)	printf(__VA_ARGS__)
 #else
 #define VPRINTF(...)	__nothing
 #endif
 void cpu_attach(device_t, cpuid_t);
 static void identify_aarch64_model(uint32_t, char *, size_t);
 static void cpu_identify(device_t self, struct cpu_info *);
 static void cpu_identify1(device_t self, struct cpu_info *);
 static void cpu_identify2(device_t self, struct cpu_info *);
 static void cpu_setup_id(struct cpu_info *);
 static void cpu_setup_sysctl(device_t, struct cpu_info *);
 #ifdef MULTIPROCESSOR
 uint64_t cpu_mpidr[MAXCPUS];
 volatile u_int aarch64_cpu_mbox[howmany(MAXCPUS, sizeof(u_int))] __cacheline_aligned = { 0 };
 volatile u_int aarch64_cpu_hatched[howmany(MAXCPUS, sizeof(u_int))] __cacheline_aligned = { 0 };
 u_int arm_cpu_max = 1;
 static kmutex_t cpu_hatch_lock;
 #endif /* MULTIPROCESSOR */
 #ifdef MULTIPROCESSOR
 #define NCPUINFO	MAXCPUS
 #else
 #define NCPUINFO	1
 #endif /* MULTIPROCESSOR */
 /*
  * Our exported CPU info;
  * these will be refered from secondary cpus in the middle of hatching.
  */
 struct cpu_info cpu_info_store[NCPUINFO] = {
 	[0] = {
 		.ci_cpl = IPL_HIGH,
 		.ci_curlwp = &lwp0
+	}
 };
 struct cpu_info *cpu_info[NCPUINFO] __read_mostly = {
 	[0] = &cpu_info_store[0]
 };
 void
 cpu_attach(device_t dv, cpuid_t id)
+{
 	struct cpu_info *ci;
 	const int unit = device_unit(dv);
 	uint64_t mpidr;
 	if (unit == 0) {
 		ci = curcpu();
 		ci->ci_cpuid = id;
 		cpu_setup_id(ci);
 	} else {
 #ifdef MULTIPROCESSOR
 		if ((boothowto & RB_MD1) != 0) {
 			aprint_naive("\n");
 			aprint_normal(": multiprocessor boot disabled\n");
 			return;
+		}
 		KASSERT(unit < MAXCPUS);
 		ci = &cpu_info_store[unit];
 		ci->ci_cpl = IPL_HIGH;
 		ci->ci_cpuid = id;
 		// XXX big.LITTLE
 		ci->ci_data.cpu_cc_freq = cpu_info_store[0].ci_data.cpu_cc_freq;
 		/* ci_id is stored by own cpus when hatching */
 		cpu_info[ncpu] = ci;
 		if (cpu_hatched_p(unit) == 0) {
 			ci->ci_dev = dv;
 			dv->dv_private = ci;
 			ci->ci_index = -1;
 			aprint_naive(": disabled\n");
 			aprint_normal(": disabled (unresponsive)\n");
 			return;
+		}
 #else /* MULTIPROCESSOR */
 		aprint_naive(": disabled\n");
 		aprint_normal(": disabled (uniprocessor kernel)\n");
 		return;
 #endif /* MULTIPROCESSOR */
+	}
 	mpidr = ci->ci_id.ac_mpidr;
 	if (mpidr & MPIDR_MT) {
 		ci->ci_smt_id = __SHIFTOUT(mpidr, MPIDR_AFF0);
 		ci->ci_core_id = __SHIFTOUT(mpidr, MPIDR_AFF1);
 		ci->ci_package_id = __SHIFTOUT(mpidr, MPIDR_AFF2);
 	} else {
 		ci->ci_core_id = __SHIFTOUT(mpidr, MPIDR_AFF0);
 		ci->ci_package_id = __SHIFTOUT(mpidr, MPIDR_AFF1);
+	}
 	ci->ci_dev = dv;
 	dv->dv_private = ci;
 	cpu_identify(ci->ci_dev, ci);
 #ifdef MULTIPROCESSOR
 	if (unit != 0) {
 		mi_cpu_attach(ci);
 		return;
+	}
 #endif /* MULTIPROCESSOR */
 	set_cpufuncs();
 	fpu_attach(ci);
 	cpu_identify1(dv, ci);
 	aarch64_getcacheinfo();
 	aarch64_printcacheinfo(dv);
 	cpu_identify2(dv, ci);
 	cpu_setup_sysctl(dv, ci);
+}
 struct cpuidtab {
 	uint32_t cpu_partnum;
 	const char *cpu_name;
 	const char *cpu_class;
 	const char *cpu_architecture;
 };
 #define CPU_PARTMASK	(CPU_ID_IMPLEMENTOR_MASK | CPU_ID_PARTNO_MASK)
 const struct cpuidtab cpuids[] = {
 	{ CPU_ID_CORTEXA35R0 & CPU_PARTMASK, "Cortex-A35", "Cortex", "V8-A" },
 	{ CPU_ID_CORTEXA53R0 & CPU_PARTMASK, "Cortex-A53", "Cortex", "V8-A" },
 	{ CPU_ID_CORTEXA57R0 & CPU_PARTMASK, "Cortex-A57", "Cortex", "V8-A" },
 	{ CPU_ID_CORTEXA55R1 & CPU_PARTMASK, "Cortex-A55", "Cortex", "V8.2-A+" },
 	{ CPU_ID_CORTEXA65R0 & CPU_PARTMASK, "Cortex-A65", "Cortex", "V8.2-A+" },
 	{ CPU_ID_CORTEXA72R0 & CPU_PARTMASK, "Cortex-A72", "Cortex", "V8-A" },
 	{ CPU_ID_CORTEXA73R0 & CPU_PARTMASK, "Cortex-A73", "Cortex", "V8-A" },
 	{ CPU_ID_CORTEXA75R2 & CPU_PARTMASK, "Cortex-A75", "Cortex", "V8.2-A+" },
 	{ CPU_ID_CORTEXA76R3 & CPU_PARTMASK, "Cortex-A76", "Cortex", "V8.2-A+" },
 	{ CPU_ID_CORTEXA76AER1 & CPU_PARTMASK, "Cortex-A76AE", "Cortex", "V8.2-A+" },
 	{ CPU_ID_CORTEXA77R0 & CPU_PARTMASK, "Cortex-A77", "Cortex", "V8.2-A+" },
 	{ CPU_ID_EMAG8180 & CPU_PARTMASK, "Ampere eMAG", "Skylark", "V8-A" },
 	{ CPU_ID_NEOVERSEE1R1 & CPU_PARTMASK, "Neoverse E1", "Neoverse", "V8.2-A+" },
 	{ CPU_ID_NEOVERSEN1R3 & CPU_PARTMASK, "Neoverse N1", "Neoverse", "V8.2-A+" },
 	{ CPU_ID_THUNDERXRX, "Cavium ThunderX", "Cavium", "V8-A" },
 	{ CPU_ID_THUNDERX81XXRX, "Cavium ThunderX CN81XX", "Cavium", "V8-A" },
 	{ CPU_ID_THUNDERX83XXRX, "Cavium ThunderX CN83XX", "Cavium", "V8-A" },
 	{ CPU_ID_THUNDERX2RX, "Cavium ThunderX2", "Cavium", "V8.1-A" },
 };
 static void
 identify_aarch64_model(uint32_t cpuid, char *buf, size_t len)
+{
 	int i;
 	uint32_t cpupart, variant, revision;
 	cpupart = cpuid & CPU_PARTMASK;
 	variant = __SHIFTOUT(cpuid, CPU_ID_VARIANT_MASK);
 	revision = __SHIFTOUT(cpuid, CPU_ID_REVISION_MASK);
 	for (i = 0; i < __arraycount(cpuids); i++) {
 		if (cpupart == cpuids[i].cpu_partnum) {
 			snprintf(buf, len, "%s r%dp%d (%s %s core)",
 			    cpuids[i].cpu_name, variant, revision,
 			    cpuids[i].cpu_class,
 			    cpuids[i].cpu_architecture);
 			return;
+		}
+	}
 	snprintf(buf, len, "unknown CPU (ID = 0x%08x)", cpuid);
+}
 static void
 cpu_identify(device_t self, struct cpu_info *ci)
+{
 	char model[128];
 	identify_aarch64_model(ci->ci_id.ac_midr, model, sizeof(model));
 	if (ci->ci_index == 0)
 		cpu_setmodel("%s", model);
 	aprint_naive("\n");
 	aprint_normal(": %s\n", model);
 	aprint_normal_dev(ci->ci_dev, "package %lu, core %lu, smt %lu\n",
 	    ci->ci_package_id, ci->ci_core_id, ci->ci_smt_id);
+}
 static void
 cpu_identify1(device_t self, struct cpu_info *ci)
+{
 	uint32_t ctr, sctlr;	/* for cache */
 	/* SCTLR - System Control Register */
 	sctlr = reg_sctlr_el1_read();
 	if (sctlr & SCTLR_I)
 		aprint_normal_dev(self, "IC enabled");
 	else
 		aprint_normal_dev(self, "IC disabled");
 	if (sctlr & SCTLR_C)
 		aprint_normal(", DC enabled");
 	else
 		aprint_normal(", DC disabled");
 	if (sctlr & SCTLR_A)
 		aprint_normal(", Alignment check enabled\n");
 	else {
 		switch (sctlr & (SCTLR_SA | SCTLR_SA0)) {
 		case SCTLR_SA | SCTLR_SA0:
 			aprint_normal(
 			    ", EL0/EL1 stack Alignment check enabled\n");
 			break;
 		case SCTLR_SA:
 			aprint_normal(", EL1 stack Alignment check enabled\n");
 			break;
 		case SCTLR_SA0:
 			aprint_normal(", EL0 stack Alignment check enabled\n");
 			break;
 		case 0:
 			aprint_normal(", Alignment check disabled\n");
 			break;
+		}
+	}
 	/*
 	 * CTR - Cache Type Register
 	 */
 	ctr = reg_ctr_el0_read();
 	aprint_normal_dev(self, "Cache Writeback Granule %" PRIu64 "B,"
 	    " Exclusives Reservation Granule %" PRIu64 "B\n",
 	    __SHIFTOUT(ctr, CTR_EL0_CWG_LINE) * 4,
 	    __SHIFTOUT(ctr, CTR_EL0_ERG_LINE) * 4);
 	aprint_normal_dev(self, "Dcache line %ld, Icache line %ld\n",
 	    sizeof(int) << __SHIFTOUT(ctr, CTR_EL0_DMIN_LINE),
 	    sizeof(int) << __SHIFTOUT(ctr, CTR_EL0_IMIN_LINE));
+}
 /*
  * identify vfp, etc.
  */
 static void
 cpu_identify2(device_t self, struct cpu_info *ci)
+{
 	struct aarch64_sysctl_cpu_id *id = &ci->ci_id;
 	uint64_t dfr0;
 	if (!CPU_IS_PRIMARY(ci)) {
 		cpu_setup_id(ci);
 		cpu_setup_sysctl(self, ci);
+	}
 	dfr0 = reg_id_aa64dfr0_el1_read();
 	aprint_normal_dev(self, "revID=0x%" PRIx64, id->ac_revidr);
 	/* ID_AA64DFR0_EL1 */
 	switch (__SHIFTOUT(dfr0, ID_AA64DFR0_EL1_PMUVER)) {
 	case ID_AA64DFR0_EL1_PMUVER_V3:
 		aprint_normal(", PMCv3");
 		break;
 	case ID_AA64DFR0_EL1_PMUVER_NOV3:
 		aprint_normal(", PMC");
 		break;
+	}
 	/* ID_AA64MMFR0_EL1 */
 	switch (__SHIFTOUT(id->ac_aa64mmfr0, ID_AA64MMFR0_EL1_TGRAN4)) {
 	case ID_AA64MMFR0_EL1_TGRAN4_4KB:
 		aprint_normal(", 4k table");
 		break;
+	}
 	switch (__SHIFTOUT(id->ac_aa64mmfr0, ID_AA64MMFR0_EL1_TGRAN16)) {
 	case ID_AA64MMFR0_EL1_TGRAN16_16KB:
 		aprint_normal(", 16k table");
 		break;
+	}
 	switch (__SHIFTOUT(id->ac_aa64mmfr0, ID_AA64MMFR0_EL1_TGRAN64)) {
 	case ID_AA64MMFR0_EL1_TGRAN64_64KB:
 		aprint_normal(", 64k table");
 		break;
+	}
 	switch (__SHIFTOUT(id->ac_aa64mmfr0, ID_AA64MMFR0_EL1_ASIDBITS)) {
 	case ID_AA64MMFR0_EL1_ASIDBITS_8BIT:
 		aprint_normal(", 8bit ASID");
 		break;
 	case ID_AA64MMFR0_EL1_ASIDBITS_16BIT:
 		aprint_normal(", 16bit ASID");
 		break;
+	}
 	aprint_normal("\n");
 	aprint_normal_dev(self, "auxID=0x%" PRIx64, ci->ci_id.ac_aa64isar0);
 	/* PFR0 */
 	switch (__SHIFTOUT(id->ac_aa64pfr0, ID_AA64PFR0_EL1_GIC)) {
 	case ID_AA64PFR0_EL1_GIC_CPUIF_EN:
 		aprint_normal(", GICv3");
 		break;
+	}
 	switch (__SHIFTOUT(id->ac_aa64pfr0, ID_AA64PFR0_EL1_FP)) {
 	case ID_AA64PFR0_EL1_FP_IMPL:
 		aprint_normal(", FP");
 		break;
+	}
 	/* ISAR0 */
 	switch (__SHIFTOUT(id->ac_aa64isar0, ID_AA64ISAR0_EL1_CRC32)) {
 	case ID_AA64ISAR0_EL1_CRC32_CRC32X:
 		aprint_normal(", CRC32");
 		break;
+	}
 	switch (__SHIFTOUT(id->ac_aa64isar0, ID_AA64ISAR0_EL1_SHA1)) {
 	case ID_AA64ISAR0_EL1_SHA1_SHA1CPMHSU:
 		aprint_normal(", SHA1");
 		break;
+	}
 	switch (__SHIFTOUT(id->ac_aa64isar0, ID_AA64ISAR0_EL1_SHA2)) {
 	case ID_AA64ISAR0_EL1_SHA2_SHA256HSU:
 		aprint_normal(", SHA256");
 		break;
+	}
 	switch (__SHIFTOUT(id->ac_aa64isar0, ID_AA64ISAR0_EL1_AES)) {
 	case ID_AA64ISAR0_EL1_AES_AES:
 		aprint_normal(", AES");
 		break;
 	case ID_AA64ISAR0_EL1_AES_PMUL:
 		aprint_normal(", AES+PMULL");
 		break;
+	}
 	/* PFR0:AdvSIMD */
 	switch (__SHIFTOUT(id->ac_aa64pfr0, ID_AA64PFR0_EL1_ADVSIMD)) {
 	case ID_AA64PFR0_EL1_ADV_SIMD_IMPL:
 		aprint_normal(", NEON");
 		break;
+	}
 	/* MVFR0/MVFR1 */
 	switch (__SHIFTOUT(id->ac_mvfr0, MVFR0_FPROUND)) {
 	case MVFR0_FPROUND_ALL:
 		aprint_normal(", rounding");
 		break;
+	}
 	switch (__SHIFTOUT(id->ac_mvfr0, MVFR0_FPTRAP)) {
 	case MVFR0_FPTRAP_TRAP:
 		aprint_normal(", exceptions");
 		break;
+	}
 	switch (__SHIFTOUT(id->ac_mvfr1, MVFR1_FPDNAN)) {
 	case MVFR1_FPDNAN_NAN:
 		aprint_normal(", NaN propagation");
 		break;
+	}
 	switch (__SHIFTOUT(id->ac_mvfr1, MVFR1_FPFTZ)) {
 	case MVFR1_FPFTZ_DENORMAL:
 		aprint_normal(", denormals");
 		break;
+	}
 	switch (__SHIFTOUT(id->ac_mvfr0, MVFR0_SIMDREG)) {
 	case MVFR0_SIMDREG_16x64:
 		aprint_normal(", 16x64bitRegs");
 		break;
 	case MVFR0_SIMDREG_32x64:
 		aprint_normal(", 32x64bitRegs");
 		break;
+	}
 	switch (__SHIFTOUT(id->ac_mvfr1, MVFR1_SIMDFMAC)) {
 	case MVFR1_SIMDFMAC_FMAC:
 		aprint_normal(", Fused Multiply-Add");
 		break;
+	}
 	aprint_normal("\n");
+}
 /*
  * Fill in this CPUs id data.  Must be called from hatched cpus.
  */
 static void
 cpu_setup_id(struct cpu_info *ci)
+{
 	struct aarch64_sysctl_cpu_id *id = &ci->ci_id;
 	memset(id, 0, sizeof *id);
 	id->ac_midr      = reg_midr_el1_read();
 	id->ac_revidr    = reg_revidr_el1_read();
 	id->ac_mpidr     = reg_mpidr_el1_read();
 	id->ac_aa64dfr0  = reg_id_aa64dfr0_el1_read();
 	id->ac_aa64dfr1  = reg_id_aa64dfr1_el1_read();
 	id->ac_aa64isar0 = reg_id_aa64isar0_el1_read();
 	id->ac_aa64isar1 = reg_id_aa64isar1_el1_read();
 	id->ac_aa64mmfr0 = reg_id_aa64mmfr0_el1_read();
 	id->ac_aa64mmfr1 = reg_id_aa64mmfr1_el1_read();
 	/* Only in ARMv8.2. */
 	id->ac_aa64mmfr2 = 0 /* reg_id_aa64mmfr2_el1_read() */;
 	id->ac_mvfr0     = reg_mvfr0_el1_read();
 	id->ac_mvfr1     = reg_mvfr1_el1_read();
 	id->ac_mvfr2     = reg_mvfr2_el1_read();
 	/* Only in ARMv8.2. */
 	id->ac_aa64zfr0  = 0 /* reg_id_aa64zfr0_el1_read() */;
 	id->ac_aa64pfr0  = reg_id_aa64pfr0_el1_read();
 	id->ac_aa64pfr1  = reg_id_aa64pfr1_el1_read();
+}
 /*
  * setup the per-cpu sysctl tree.
  */
 static void
 cpu_setup_sysctl(device_t dv, struct cpu_info *ci)
+{
 	const struct sysctlnode *cpunode = NULL;
 	sysctl_createv(NULL, 0, NULL, &cpunode,
 		       CTLFLAG_PERMANENT,
 		       CTLTYPE_NODE, device_xname(dv), NULL,
 		       NULL, 0, NULL, 0,
 		       CTL_MACHDEP,
 		       CTL_CREATE, CTL_EOL);
 	if (cpunode == NULL)
 		return;
 	sysctl_createv(NULL, 0, &cpunode, NULL,
 		       CTLFLAG_PERMANENT,
 		       CTLTYPE_STRUCT, "cpu_id", NULL,
 		       NULL, 0, &ci->ci_id, sizeof(ci->ci_id),
 		       CTL_CREATE, CTL_EOL);
+}
 #ifdef MULTIPROCESSOR
 void
 cpu_boot_secondary_processors(void)
+{
 	u_int n, bit;
 	if ((boothowto & RB_MD1) != 0)
 		return;
 	mutex_init(&cpu_hatch_lock, MUTEX_DEFAULT, IPL_NONE);
 	VPRINTF("%s: starting secondary processors\n", __func__);
 	/* send mbox to have secondary processors do cpu_hatch() */
 	for (n = 0; n < __arraycount(aarch64_cpu_mbox); n++)
 		atomic_or_uint(&aarch64_cpu_mbox[n], aarch64_cpu_hatched[n]);
 	__asm __volatile ("sev; sev; sev");
 	/* wait all cpus have done cpu_hatch() */
 	for (n = 0; n < __arraycount(aarch64_cpu_mbox); n++) {
 		while (membar_consumer(), aarch64_cpu_mbox[n] & aarch64_cpu_hatched[n]) {
 			__asm __volatile ("wfe");
+		}
 		/* Add processors to kcpuset */
 		for (bit = 0; bit < 32; bit++) {
 			if (aarch64_cpu_hatched[n] & __BIT(bit))
 				kcpuset_set(kcpuset_attached, n * 32 + bit);
+		}
+	}
 	VPRINTF("%s: secondary processors hatched\n", __func__);
+}
 void
 cpu_hatch(struct cpu_info *ci)
+{
 	KASSERT(curcpu() == ci);
 	mutex_enter(&cpu_hatch_lock);
 	set_cpufuncs();
 	fpu_attach(ci);
 	cpu_identify1(ci->ci_dev, ci);
 	aarch64_getcacheinfo();
 	aarch64_printcacheinfo(ci->ci_dev);
 	cpu_identify2(ci->ci_dev, ci);
 	mutex_exit(&cpu_hatch_lock);
 	intr_cpu_init(ci);
 #ifdef FDT
 	arm_fdt_cpu_hatch(ci);
 #endif
 #ifdef MD_CPU_HATCH
 	MD_CPU_HATCH(ci);	/* for non-fdt arch? */
 #endif
 	/*
 	 * clear my bit of aarch64_cpu_mbox to tell cpu_boot_secondary_processors().
 	 * there are cpu0,1,2,3, and if cpu2 is unresponsive,
 	 * ci_index are each cpu0=0, cpu1=1, cpu2=undef, cpu3=2.
 	 * therefore we have to use device_unit instead of ci_index for mbox.
 	 */
 	const u_int off = device_unit(ci->ci_dev) / 32;
 	const u_int bit = device_unit(ci->ci_dev) % 32;
 	atomic_and_uint(&aarch64_cpu_mbox[off], ~__BIT(bit));
 	__asm __volatile ("sev; sev; sev");
+}
 bool
 cpu_hatched_p(u_int cpuindex)
+{
 	const u_int off = cpuindex / 32;
 	const u_int bit = cpuindex % 32;
 	membar_consumer();
 	return (aarch64_cpu_hatched[off] & __BIT(bit)) != 0;
+}
 #endif /* MULTIPROCESSOR */

 @@ -1,242 +1,244 @@
-/*	$NetBSD: cputypes.h,v 1.8 2019/07/16 10:37:12 jmcneill Exp $	*/
+/*	$NetBSD: cputypes.h,v 1.8.2.1 2019/12/29 09:40:59 martin Exp $	*/
 /*
  * Copyright (c) 1998, 2001 Ben Harris
  * Copyright (c) 1994-1996 Mark Brinicombe.
  * Copyright (c) 1994 Brini.
  * All rights reserved.
+ *
  * This code is derived from software written for Brini by Mark Brinicombe
+ *
  * Redistribution and use in source and binary forms, with or without
  * modification, are permitted provided that the following conditions
  * are met:
  * 1. Redistributions of source code must retain the above copyright
  *    notice, this list of conditions and the following disclaimer.
  * 2. Redistributions in binary form must reproduce the above copyright
  *    notice, this list of conditions and the following disclaimer in the
  *    documentation and/or other materials provided with the distribution.
  * 3. All advertising materials mentioning features or use of this software
  *    must display the following acknowledgement:
  *	This product includes software developed by Brini.
  * 4. The name of the company nor the name of the author may be used to
  *    endorse or promote products derived from this software without specific
  *    prior written permission.
+ *
  * THIS SOFTWARE IS PROVIDED BY BRINI ``AS IS'' AND ANY EXPRESS OR IMPLIED
  * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
  * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
  * IN NO EVENT SHALL BRINI OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
  * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
  * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
  * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
  * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
  * SUCH DAMAGE.
  */
 #ifndef _ARM_CPUTYPES_H_
 #define _ARM_CPUTYPES_H_
 /*
  * The CPU ID register is theoretically structured, but the definitions of
  * the fields keep changing.
  */
 /* The high-order byte is always the implementor */
 #define CPU_ID_IMPLEMENTOR_MASK	0xff000000
 #define CPU_ID_ARM_LTD		0x41000000 /* 'A' */
 #define CPU_ID_BROADCOM		0x42000000 /* 'B' */
 #define CPU_ID_CAVIUM		0x43000000 /* 'C' */
 #define CPU_ID_DEC		0x44000000 /* 'D' */
 #define CPU_ID_INFINEON		0x49000000 /* 'I' */
 #define CPU_ID_MOTOROLA		0x4d000000 /* 'M' */
 #define CPU_ID_NVIDIA		0x4e000000 /* 'N' */
 #define CPU_ID_APM		0x50000000 /* 'P' */
 #define CPU_ID_QUALCOMM		0x51000000 /* 'Q' */
 #define CPU_ID_SAMSUNG		0x53000000 /* 'S' */
 #define CPU_ID_TI		0x54000000 /* 'T' */
 #define CPU_ID_MARVELL		0x56000000 /* 'V' */
 #define CPU_ID_APPLE		0x61000000 /* 'a' */
 #define CPU_ID_FARADAY		0x66000000 /* 'f' */
 #define CPU_ID_INTEL		0x69000000 /* 'i' */
 /* How to decide what format the CPUID is in. */
 #define CPU_ID_ISOLD(x)		(((x) & 0x0000f000) == 0x00000000)
 #define CPU_ID_IS7(x)		(((x) & 0x0000f000) == 0x00007000)
 #define CPU_ID_ISNEW(x)		(!CPU_ID_ISOLD(x) && !CPU_ID_IS7(x))
 /* On ARM3 and ARM6, this byte holds the foundry ID. */
 #define CPU_ID_FOUNDRY_MASK	0x00ff0000
 #define CPU_ID_FOUNDRY_VLSI	0x00560000
 /* On ARM7 it holds the architecture and variant (sub-model) */
 #define CPU_ID_7ARCH_MASK	0x00800000
 #define CPU_ID_7ARCH_V3		0x00000000
 #define CPU_ID_7ARCH_V4T	0x00800000
 #define CPU_ID_7VARIANT_MASK	0x007f0000
 /* On more recent ARMs, it does the same, but in a different format */
 #define CPU_ID_ARCH_MASK	0x000f0000
 #define CPU_ID_ARCH_V3		0x00000000
 #define CPU_ID_ARCH_V4		0x00010000
 #define CPU_ID_ARCH_V4T		0x00020000
 #define CPU_ID_ARCH_V5		0x00030000
 #define CPU_ID_ARCH_V5T		0x00040000
 #define CPU_ID_ARCH_V5TE	0x00050000
 #define CPU_ID_ARCH_V5TEJ	0x00060000
 #define CPU_ID_ARCH_V6		0x00070000
 #define CPU_ID_VARIANT_MASK	0x00f00000
 /* Next three nybbles are part number */
 #define CPU_ID_PARTNO_MASK	0x0000fff0
 /* Intel XScale has sub fields in part number */
 #define CPU_ID_XSCALE_COREGEN_MASK	0x0000e000 /* core generation */
 #define CPU_ID_XSCALE_COREREV_MASK	0x00001c00 /* core revision */
 #define CPU_ID_XSCALE_PRODUCT_MASK	0x000003f0 /* product number */
 /* And finally, the revision number. */
 #define CPU_ID_REVISION_MASK	0x0000000f
 /* Individual CPUs are probably best IDed by everything but the revision. */
 #define CPU_ID_CPU_MASK		0xfffffff0
 /* Fake CPU IDs for ARMs without CP15 */
 #define CPU_ID_ARM2		0x41560200
 #define CPU_ID_ARM250		0x41560250
 /* Pre-ARM7 CPUs -- [15:12] == 0 */
 #define CPU_ID_ARM3		0x41560300
 #define CPU_ID_ARM600		0x41560600
 #define CPU_ID_ARM610		0x41560610
 #define CPU_ID_ARM620		0x41560620
 /* ARM7 CPUs -- [15:12] == 7 */
 #define CPU_ID_ARM700		0x41007000 /* XXX This is a guess. */
 #define CPU_ID_ARM710		0x41007100
 #define CPU_ID_ARM7500		0x41027100
 #define CPU_ID_ARM710A		0x41067100
 #define CPU_ID_ARM7500FE	0x41077100
 #define CPU_ID_ARM710T		0x41807100
 #define CPU_ID_ARM720T		0x41807200
 #define CPU_ID_ARM740T8K	0x41807400 /* XXX no MMU, 8KB cache */
 #define CPU_ID_ARM740T4K	0x41817400 /* XXX no MMU, 4KB cache */
 /* Post-ARM7 CPUs */
 #define CPU_ID_ARM810		0x41018100
 #define CPU_ID_ARM920T		0x41129200
 #define CPU_ID_ARM922T		0x41029220
 #define CPU_ID_ARM926EJS	0x41069260
 #define CPU_ID_ARM940T		0x41029400 /* XXX no MMU */
 #define CPU_ID_ARM946ES		0x41049460 /* XXX no MMU */
 #define CPU_ID_ARM966ES		0x41049660 /* XXX no MMU */
 #define CPU_ID_ARM966ESR1	0x41059660 /* XXX no MMU */
 #define CPU_ID_ARM1020E		0x4115a200 /* (AKA arm10 rev 1) */
 #define CPU_ID_ARM1022ES	0x4105a220
 #define CPU_ID_ARM1026EJS	0x4106a260
 #define CPU_ID_ARM11MPCORE	0x410fb020
 #define CPU_ID_ARM1136JS	0x4107b360
 #define CPU_ID_ARM1136JSR1	0x4117b360
 #define CPU_ID_ARM1156T2S	0x4107b560 /* MPU only */
 #define CPU_ID_ARM1176JZS	0x410fb760
 #define CPU_ID_ARM11_P(n)	((n & 0xff07f000) == 0x4107b000)
 /* ARMv7 CPUs */
 #define CPU_ID_CORTEXA5R0	0x410fc050
 #define CPU_ID_CORTEXA7R0	0x410fc070
 #define CPU_ID_CORTEXA8R1	0x411fc080
 #define CPU_ID_CORTEXA8R2	0x412fc080
 #define CPU_ID_CORTEXA8R3	0x413fc080
 #define CPU_ID_CORTEXA9R1	0x411fc090
 #define CPU_ID_CORTEXA9R2	0x412fc090
 #define CPU_ID_CORTEXA9R3	0x413fc090
 #define CPU_ID_CORTEXA9R4	0x414fc090
 #define CPU_ID_CORTEXA15R2	0x412fc0f0
 #define CPU_ID_CORTEXA15R3	0x413fc0f0
 #define CPU_ID_CORTEXA15R4	0x414fc0f0
 #define CPU_ID_CORTEXA17R1	0x411fc0e0
 /* ARMv8 CPUS */
 #define CPU_ID_CORTEXA32R1	0x411fd010
 #define CPU_ID_CORTEXA35R0	0x410fd040
 #define CPU_ID_CORTEXA35R1	0x411fd040
 #define CPU_ID_CORTEXA53R0	0x410fd030
 #define CPU_ID_CORTEXA55R1	0x411fd050
 #define CPU_ID_CORTEXA57R0	0x410fd070
 #define CPU_ID_CORTEXA57R1	0x411fd070
 #define CPU_ID_CORTEXA65R0	0x410fd060
 #define CPU_ID_CORTEXA72R0	0x410fd080
 #define CPU_ID_CORTEXA73R0	0x410fd090
 #define CPU_ID_CORTEXA75R2	0x412fd0a0
 #define CPU_ID_CORTEXA76AER1	0x411fd0e0
 #define CPU_ID_CORTEXA76R3	0x413fd0b0
 #define CPU_ID_NEOVERSEN1R3	0x413fd0c0
 #define CPU_ID_NEOVERSEE1R1	0x411fd4a0
 #define CPU_ID_CORTEXA77R0	0x410fd0d0
 #define CPU_ID_CORTEX_P(n)	((n & 0xff0fe000) == 0x410fc000)
 #define CPU_ID_CORTEX_A5_P(n)	((n & 0xff0ff0f0) == 0x410fc050)
 #define CPU_ID_CORTEX_A7_P(n)	((n & 0xff0ff0f0) == 0x410fc070)
 #define CPU_ID_CORTEX_A8_P(n)	((n & 0xff0ff0f0) == 0x410fc080)
 #define CPU_ID_CORTEX_A9_P(n)	((n & 0xff0ff0f0) == 0x410fc090)
 #define CPU_ID_CORTEX_A15_P(n)	((n & 0xff0ff0f0) == 0x410fc0f0)
 #define CPU_ID_CORTEX_A32_P(n)	((n & 0xff0ff0f0) == 0x410fd010)
 #define CPU_ID_CORTEX_A35_P(n)	((n & 0xff0ff0f0) == 0x410fd040)
 #define CPU_ID_CORTEX_A53_P(n)	((n & 0xff0ff0f0) == 0x410fd030)
 #define CPU_ID_CORTEX_A55_P(n)	((n & 0xff0ff0f0) == 0x410fd050)
 #define CPU_ID_CORTEX_A57_P(n)	((n & 0xff0ff0f0) == 0x410fd070)
 #define CPU_ID_CORTEX_A65_P(n)	((n & 0xff0ff0f0) == 0x410fd060)
 #define CPU_ID_CORTEX_A72_P(n)	((n & 0xff0ff0f0) == 0x410fd080)
 #define CPU_ID_CORTEX_A73_P(n)	((n & 0xff0ff0f0) == 0x410fd090)
 #define CPU_ID_CORTEX_A75_P(n)	((n & 0xff0ff0f0) == 0x410fd0a0)
 #define CPU_ID_CORTEX_A76_P(n)	((n & 0xff0ff0f0) == 0x410fd0b0)
 #define CPU_ID_CORTEX_A76AE_P(n) ((n & 0xff0ff0f0) == 0x410fd0e0)
 #define CPU_ID_CORTEX_A77_P(n)	((n & 0xff0ff0f0) == 0x410fd0f0)
 #define CPU_ID_THUNDERXRX	0x43000a10
 #define CPU_ID_THUNDERXP1d0	0x43000a10
 #define CPU_ID_THUNDERXP1d1	0x43000a11
 #define CPU_ID_THUNDERXP2d1	0x431f0a11
 #define CPU_ID_THUNDERX81XXRX	0x43000a20
 #define CPU_ID_THUNDERX83XXRX	0x43000a30
 #define CPU_ID_THUNDERX2RX	0x43000af0
 #define CPU_ID_SA110		0x4401a100
 #define CPU_ID_SA1100		0x4401a110
 #define CPU_ID_EMAG8180		0x503f0002
 #define CPU_ID_TI925T		0x54029250
 #define CPU_ID_MV88FR571_VD	0x56155710
 #define CPU_ID_MV88SV131	0x56251310
 #define CPU_ID_FA526		0x66015260
 #define CPU_ID_SA1110		0x6901b110
 #define CPU_ID_IXP1200		0x6901c120
 #define CPU_ID_80200		0x69052000
 #define CPU_ID_PXA250		0x69052100 /* sans core revision */
 #define CPU_ID_PXA210		0x69052120
 #define CPU_ID_PXA250A		0x69052100 /* 1st version Core */
 #define CPU_ID_PXA210A		0x69052120 /* 1st version Core */
 #define CPU_ID_PXA250B		0x69052900 /* 3rd version Core */
 #define CPU_ID_PXA210B		0x69052920 /* 3rd version Core */
 #define CPU_ID_PXA250C		0x69052d00 /* 4th version Core */
 #define CPU_ID_PXA210C		0x69052d20 /* 4th version Core */
 #define CPU_ID_PXA27X		0x69054110
 #define CPU_ID_80321_400	0x69052420
 #define CPU_ID_80321_600	0x69052430
 #define CPU_ID_80321_400_B0	0x69052c20
 #define CPU_ID_80321_600_B0	0x69052c30
 #define CPU_ID_80219_400	0x69052e20
 #define CPU_ID_80219_600	0x69052e30
 #define CPU_ID_IXP425_533	0x690541c0
 #define CPU_ID_IXP425_400	0x690541d0
 #define CPU_ID_IXP425_266	0x690541f0
 #define CPU_ID_MV88SV58XX_P(n)	((n & 0xff0fff00) == 0x560f5800)
 #define CPU_ID_MV88SV581X_V6	0x560f5810 /* Marvell Sheeva 88SV581x v6 Core */
 #define CPU_ID_MV88SV581X_V7	0x561f5810 /* Marvell Sheeva 88SV581x v7 Core */
 #define CPU_ID_MV88SV584X_V6	0x561f5840 /* Marvell Sheeva 88SV584x v6 Core */
 #define CPU_ID_MV88SV584X_V7	0x562f5840 /* Marvell Sheeva 88SV584x v7 Core */
 /* Marvell's CPUIDs with ARM ID in implementor field */
 #define CPU_ID_ARM_88SV581X_V6	0x410fb760 /* Marvell Sheeva 88SV581x v6 Core */
 #define CPU_ID_ARM_88SV581X_V7	0x413fc080 /* Marvell Sheeva 88SV581x v7 Core */
 #define CPU_ID_ARM_88SV584X_V6	0x410fb020 /* Marvell Sheeva 88SV584x v6 Core */
 #endif /* _ARM_CPUTYPES_H_ */