 @@ -1,61 +1,61 @@
-/*	$NetBSD: apc.c,v 1.1 2010/01/15 20:57:12 bouyer Exp $	*/
+/*	$NetBSD: apc.c,v 1.2 2019/12/30 22:13:46 ad Exp $	*/
 /*
  * Copyright (c) 2010 Manuel Bouyer.
+ *
  * Redistribution and use in source and binary forms, with or without
  * modification, are permitted provided that the following conditions
  * are met:
  * 1. Redistributions of source code must retain the above copyright
  *    notice, this list of conditions and the following disclaimer.
  * 2. Redistributions in binary form must reproduce the above copyright
  *    notice, this list of conditions and the following disclaimer in the
  *    documentation and/or other materials provided with the distribution.
+ *
  * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
  * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
  * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
  * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
  * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
  * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
  * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  */
 #include <sys/cdefs.h>
-__KERNEL_RCSID(0, "$NetBSD: apc.c,v 1.1 2010/01/15 20:57:12 bouyer Exp $");
+__KERNEL_RCSID(0, "$NetBSD: apc.c,v 1.2 2019/12/30 22:13:46 ad Exp $");
 /*
  * driver for the power management functions of the Aurora Personality Chip
  * on SPARCstation-4/5 and derivatives
  */
 #include <sys/param.h>
 #include <sys/systm.h>
 #include <sys/errno.h>
 #include <sys/device.h>
 #include <sys/bus.h>
 #include <machine/autoconf.h>
 #include <sparc/dev/apcreg.h>
 static int apcmatch(device_t, struct cfdata *, void *);
 static void apcattach(device_t, device_t, void *);
-static void apc_cpu_sleep(struct cpu_info *);
+static void apc_cpu_sleep(void);
 struct apc_softc {
 	device_t	sc_dev;
 	bus_space_tag_t	sc_bt;
 	bus_space_handle_t sc_bh;
 };
 struct apc_softc *apc = NULL;
 CFATTACH_DECL_NEW(apc, sizeof(struct apc_softc),
     apcmatch, apcattach, NULL, NULL);
 @@ -76,22 +76,22 @@ apcattach(device_t parent, device_t self
 	sc->sc_bt = sa->sa_bustag;
 	if (sbus_bus_map(sa->sa_bustag,
 	    sa->sa_slot, sa->sa_offset, APC_REG_SIZE, 0, &sc->sc_bh) != 0) {
 		aprint_error(": cannot map registers\n");
 		return;
+	}
 	aprint_normal("\n");
 	apc = sc;
 	curcpu()->idlespin = apc_cpu_sleep;
+}
 static void
-apc_cpu_sleep(struct cpu_info *ci)
+apc_cpu_sleep(void)
+{
 	uint8_t val;
 	if (apc == NULL)
 		return;
 	val = bus_space_read_1(apc->sc_bt, apc->sc_bh, APC_IDLE_REG);
 	bus_space_write_1(apc->sc_bt, apc->sc_bh, APC_IDLE_REG,
 	    val | APC_IDLE_REG_IDLE);
+}

 @@ -1,14 +1,14 @@
-/*	$NetBSD: clkctrl.c,v 1.5 2011/07/17 23:32:37 mrg Exp $	*/
+/*	$NetBSD: clkctrl.c,v 1.6 2019/12/30 22:13:47 ad Exp $	*/
 /*
  * Copyright (c) 2005 Michael Lorenz
+ *
  * Redistribution and use in source and binary forms, with or without
  * modification, are permitted provided that the following conditions
  * are met:
  * 1. Redistributions of source code must retain the above copyright
  *    notice, this list of conditions and the following disclaimer.
  * 2. Redistributions in binary form must reproduce the above copyright
  *    notice, this list of conditions and the following disclaimer in the
  *    documentation and/or other materials provided with the distribution.
+ *
 @@ -16,45 +16,45 @@
  * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
  * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
  * PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
  * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
  * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
  * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
  * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
  * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
  * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
  * POSSIBILITY OF SUCH DAMAGE.
  */
 #include <sys/cdefs.h>
-__KERNEL_RCSID(0, "$NetBSD: clkctrl.c,v 1.5 2011/07/17 23:32:37 mrg Exp $");
+__KERNEL_RCSID(0, "$NetBSD: clkctrl.c,v 1.6 2019/12/30 22:13:47 ad Exp $");
 #include <sys/param.h>
 #include <sys/systm.h>
 #include <sys/device.h>
 #include <sys/kernel.h>
 #include <machine/autoconf.h>
 #include <machine/cpu.h>
 #include <sparc/sparc/vaddrs.h>
 static int clkctrl_match(device_t, cfdata_t, void *);
 static void clkctrl_attach(device_t, device_t, void *);
 CFATTACH_DECL_NEW(clkctrl, 0,
      clkctrl_match, clkctrl_attach, NULL, NULL);
-static void tadpole_cpu_sleep(struct cpu_info *);
+static void tadpole_cpu_sleep(void);
 volatile uint8_t *clkctrl_reg = NULL;
 static int
 clkctrl_match(device_t parent, cfdata_t cf, void *aux)
+{
 	union obio_attach_args *uoba = aux;
 	if ((uoba->uoba_isobio4 != 0) || (clkctrl_reg != NULL))
 		return (0);
 	return (strcmp("clk-ctrl", uoba->uoba_sbus.sa_name) == 0);
+}
 @@ -81,19 +81,20 @@ clkctrl_attach(device_t parent, device_t
 	clkctrl_reg = (volatile uint8_t *)bus_space_vaddr(sa->sa_bustag, bh);
 #ifdef DEBUG
 	printf(" reg: %x", (uint32_t)clkctrl_reg);
 #endif
 	cur = curcpu();
 	cur->idlespin = tadpole_cpu_sleep;
 	printf("\n");
+}
 /* ARGSUSED */
 static void
-tadpole_cpu_sleep(struct cpu_info *ci)
+tadpole_cpu_sleep(void)
+{
 	if (clkctrl_reg == 0)
 		return;
 	*clkctrl_reg = 0;
+}

 @@ -1,14 +1,14 @@
-/*	$NetBSD: lock_stubs.s,v 1.12 2008/05/25 15:56:12 chs Exp $	*/
+/*	$NetBSD: lock_stubs.s,v 1.13 2019/12/30 22:13:47 ad Exp $	*/
 /*-
  * Copyright (c) 2002, 2007 The NetBSD Foundation, Inc.
  * All rights reserved.
+ *
  * This code is derived from software contributed to The NetBSD Foundation
  * by Jason R. Thorpe and Andrew Doran
+ *
  * Redistribution and use in source and binary forms, with or without
  * modification, are permitted provided that the following conditions
  * are met:
  * 1. Redistributions of source code must retain the above copyright
  *    notice, this list of conditions and the following disclaimer.
 @@ -112,76 +112,78 @@ ENTRY(mutex_exit)
 	 nop
 	ldub	[%o0 + MTX_LOCK], %o3		! get has-waiters indicator
 	tst	%o3				! has waiters?
 	bnz	_C_LABEL(mutex_wakeup)		! yes, hard case
 	 st	%g0, [%o0]			! and release lock
 	retl
 	 nop
 #if 0 /* does not work for MP yet */
 /*
  * void mutex_spin_enter(kmutex_t *);
  */
 ENTRY(mutex_spin_enter)
-	sethi	%hi(CPUINFO_VA), %o4
+	sethi	%hi(CPUINFO_VA+CPUINFO_MTX_COUNT), %o4
-	ld	[ %o4 + CPUINFO_MTX_COUNT ], %o5
+	ld	[ %o4 + %lo(CPUINFO_VA+CPUINFO_MTX_COUNT) ], %o5
 	sub	%o5, 1, %o1
-	st	%o1, [ %o4 + CPUINFO_MTX_COUNT ]
+	st	%o1, [ %o4 + %lo(CPUINFO_VA+CPUINFO_MTX_COUNT) ]
 	ldub	[ %o0 + MTX_IPL ], %o2
 	rd	%psr, %o1
 	sll	%o2, 8, %o2
 	and	%o1, PSR_PIL, %o3
 	cmp	%o3, %o2
 	bge	1f
 	 tst	%o5
 	andn	%o1, PSR_PIL, %o1
 	wr	%o2, %o1, %psr
 	nop
 	nop
 	nop
 	tst	%o5
 :
 	sethi	%hi(CPUINFO_VA+CPUINFO_MTX_OLDSPL), %o4
 	bz,a	2f
-	 st	%o3, [ %o4 + CPUINFO_MTX_OLDSPL ]
+	 st	%o3, [ %o4 + %lo(CPUINFO_VA+CPUINFO_MTX_OLDSPL) ]
 :
 #if defined(MULTIPROCESSOR) || defined(DIAGNOSTIC)
 	ldstub  [ %o0 + MTX_LOCK ], %o2
 	tst	%o2
 	bnz	_C_LABEL(mutex_spin_retry)
 	 nop
 #endif
 	retl
 	 nop
 /*
  * void mutex_spin_exit(kmutex_t *);
  */
 ENTRY(mutex_spin_exit)
 #if defined(DIAGNOSTIC)
 	ldub	[ %o0 + MTX_LOCK ], %o1
 	tst	%o1
 	bz	_C_LABEL(mutex_vector_exit)
 	 nop
 	clrb	[ %o0 + MTX_LOCK ]
 #elif defined(MULTIPROCESSOR)
 	clrb	[ %o0 + MTX_LOCK ]
 #endif
-	sethi	 %hi(CPUINFO_VA), %o2
+	sethi	 %hi(CPUINFO_VA+CPUINFO_MTX_OLDSPL), %o2
-	ld	[ %o2 + CPUINFO_MTX_OLDSPL ], %o3
+	ld	[ %o2 + %lo(CPUINFO_VA+CPUINFO_MTX_OLDSPL) ], %o3
-	ld	[ %o2 + CPUINFO_MTX_COUNT ], %o1
+	sethi	 %hi(CPUINFO_VA+CPUINFO_MTX_COUNT), %o2
 	ld	[ %o2 + %lo(CPUINFO_VA+CPUINFO_MTX_COUNT) ], %o1
 	addcc	%o1, 1, %o4
 	bnz	1f
-	 st	%o4, [ %o2 + CPUINFO_MTX_COUNT ]
+	 st	%o4, [ %o2 + %lo(CPUINFO_VA+CPUINFO_MTX_COUNT) ]
 	rd	%psr, %o1
 	andn	%o1, PSR_PIL, %o1
 	wr	%o3, %o1, %psr
 	nop
 	nop
 	nop
 :
 	retl
 	 nop
 #endif
 #endif	/* LOCKDEBUG */

 @@ -1,14 +1,14 @@
-/*	$NetBSD: locore.s,v 1.274 2019/06/07 00:18:26 mrg Exp $	*/
+/*	$NetBSD: locore.s,v 1.275 2019/12/30 22:13:47 ad Exp $	*/
 /*
  * Copyright (c) 1996 Paul Kranenburg
  * Copyright (c) 1996
  * 	The President and Fellows of Harvard College. All rights reserved.
  * Copyright (c) 1992, 1993
  *	The Regents of the University of California.  All rights reserved.
+ *
  * This software was developed by the Computer Systems Engineering group
  * at Lawrence Berkeley Laboratory under DARPA contract BG 91-66 and
  * contributed to Berkeley.
+ *
  * All advertising materials mentioning features or use of this software
 @@ -1944,30 +1944,31 @@ memfault_sun4c:
 	ld	[%sp + CCFSZ + 20], %g1	! restore g1 through g7
 	ldd	[%sp + CCFSZ + 24], %g2
 	ldd	[%sp + CCFSZ + 32], %g4
 	ldd	[%sp + CCFSZ + 40], %g6
 	wr	%l4, 0, %y		! restore y
 	b	return_from_trap
 	 wr	%l0, 0, %psr
 	/* NOTREACHED */
 #endif /* SUN4C */
 #if defined(SUN4M)
 _ENTRY(memfault_sun4m)
 memfault_sun4m:
-	sethi	%hi(CPUINFO_VA), %l4
+	sethi	%hi(CPUINFO_VA+CPUINFO_GETSYNCFLT), %l4
 	ld	[%l4 + %lo(CPUINFO_VA+CPUINFO_GETSYNCFLT)], %l5
 	sethi	%hi(CPUINFO_VA+CPUINFO_SYNCFLTDUMP), %l4
 	jmpl	%l5, %l7
-	 or	%l4, %lo(CPUINFO_SYNCFLTDUMP), %l4
+	 or	%l4, %lo(CPUINFO_VA+CPUINFO_SYNCFLTDUMP), %l4
 	TRAP_SETUP(-CCFSZ-80)
 	! tally fault (curcpu()->cpu_data.cpu_nfault++) (clobbers %o0,%o1,%o2)
 	INCR64(CPUINFO_VA + CPUINFO_NFAULT)
 	st	%g1, [%sp + CCFSZ + 20]	! save g1
 	rd	%y, %l4			! save y
 	std	%g2, [%sp + CCFSZ + 24]	! save g2, g3
 	std	%g4, [%sp + CCFSZ + 32]	! save g4, g5
 	std	%g6, [%sp + CCFSZ + 40]	! sneak in g6, g7
 	! retrieve sync fault status/address
 	sethi	%hi(CPUINFO_VA+CPUINFO_SYNCFLTDUMP), %o0
 @@ -2509,72 +2510,72 @@ softintr_common:
 	sll	%l3, 2, %l5
 	set	CPUINFO_VA + CPUINFO_SINTRCNT, %l4	! sintrcnt[intlev].ev_count++;
 	sll	%l3, EV_STRUCTSHIFT, %o2
 	ldd	[%l4 + %o2], %o0
 	std	%l2, [%sp + CCFSZ + 8]	! set up intrframe/clockframe
 	inccc   %o1
 	addx    %o0, 0, %o0
 	std	%o0, [%l4 + %o2]
 	set	_C_LABEL(sintrhand), %l4! %l4 = sintrhand[intlev];
 	ld	[%l4 + %l5], %l4
-	sethi	%hi(CPUINFO_VA), %o2
+	sethi	%hi(CPUINFO_VA+CPUINFO_IDEPTH), %o2
-	ld	[ %o2 + CPUINFO_IDEPTH ], %o3
+	ld	[ %o2 + %lo(CPUINFO_VA+CPUINFO_IDEPTH) ], %o3
 	inc	%o3
-	st	%o3, [ %o2 + CPUINFO_IDEPTH ]
+	st	%o3, [ %o2 + %lo(CPUINFO_VA+CPUINFO_IDEPTH) ]
 	b	3f
 	 st	%fp, [%sp + CCFSZ + 16]
 :	ld	[%l4 + IH_CLASSIPL], %o2 ! ih->ih_classipl
 	rd	%psr, %o3		!  (bits already shifted to PIL field)
 	andn	%o3, PSR_PIL, %o3	! %o3 = psr & ~PSR_PIL
 	wr	%o3, %o2, %psr		! splraise(ih->ih_classipl)
 	ld	[%l4 + IH_FUN], %o1
 	ld	[%l4 + IH_ARG], %o0
 	nop				! one more isns before touching ICC
 	tst	%o0
 	bz,a	2f
 	 add	%sp, CCFSZ, %o0
 :	jmpl	%o1, %o7		!	(void)(*ih->ih_fun)(...)
 	 ld	[%l4 + IH_NEXT], %l4	!	and ih = ih->ih_next
 :	tst	%l4			! while ih != NULL
 	bnz	1b
 	 nop
-	sethi	%hi(CPUINFO_VA), %o2
+	sethi	%hi(CPUINFO_VA+CPUINFO_IDEPTH), %o2
-	ld	[ %o2 + CPUINFO_IDEPTH ], %o3
+	ld	[ %o2 + %lo(CPUINFO_VA+CPUINFO_IDEPTH) ], %o3
 	dec	%o3
-	st	%o3, [ %o2 + CPUINFO_IDEPTH ]
+	st	%o3, [ %o2 + %lo(CPUINFO_VA+CPUINFO_IDEPTH) ]
 	mov	%l7, %g1
 	wr	%l6, 0, %y
 	ldd	[%sp + CCFSZ + 24], %g2
 	ldd	[%sp + CCFSZ + 32], %g4
 	ldd	[%sp + CCFSZ + 40], %g6
 	b	return_from_trap
 	 wr	%l0, 0, %psr
 	/*
 	 * _sparc_interrupt{44c,4m} is exported for paranoia checking
 	 * (see intr.c).
 	 */
 #if defined(SUN4M)
 _ENTRY(_C_LABEL(sparc_interrupt4m))
 #if !defined(MSIIEP)	/* "normal" sun4m */
-	sethi	%hi(CPUINFO_VA), %l6
+	sethi	%hi(CPUINFO_VA+CPUINFO_INTREG), %l6
-	ld	[%l6 + CPUINFO_INTREG], %l7
+	ld	[%l6 + %lo(CPUINFO_VA+CPUINFO_INTREG)], %l7
 	mov	1, %l4
 	ld	[%l7 + ICR_PI_PEND_OFFSET], %l5	! get pending interrupts
 	sll	%l4, %l3, %l4	! hw intr bits are in the lower halfword
 	btst	%l4, %l5	! has pending hw intr at this level?
 	bnz	sparc_interrupt_common
 	 nop
 	! both softint pending and clear bits are in upper halfwords of
 	! their respective registers so shift the test bit in %l4 up there
 	sll	%l4, 16, %l4
 	st	%l4, [%l7 + ICR_PI_CLR_OFFSET]	! ack soft intr
 @@ -2694,30 +2695,30 @@ sparc_interrupt_common:
 	sll	%l3, 2, %l5
 	set	CPUINFO_VA + CPUINFO_INTRCNT, %l4	! intrcnt[intlev].ev_count++;
 	sll	%l3, EV_STRUCTSHIFT, %o2
 	ldd	[%l4 + %o2], %o0
 	std	%l2, [%sp + CCFSZ + 8]	! set up intrframe/clockframe
 	inccc   %o1
 	addx    %o0, 0, %o0
 	std	%o0, [%l4 + %o2]
 	set	_C_LABEL(intrhand), %l4	! %l4 = intrhand[intlev];
 	ld	[%l4 + %l5], %l4
-	sethi	%hi(CPUINFO_VA), %o2
+	sethi	%hi(CPUINFO_VA+CPUINFO_IDEPTH), %o2
-	ld	[ %o2 + CPUINFO_IDEPTH ], %o3
+	ld	[ %o2 + %lo(CPUINFO_VA+CPUINFO_IDEPTH) ], %o3
 	inc	%o3
-	st	%o3, [ %o2 + CPUINFO_IDEPTH ]
+	st	%o3, [ %o2 + %lo(CPUINFO_VA+CPUINFO_IDEPTH) ]
 	b	3f
 	 st	%fp, [%sp + CCFSZ + 16]
 :	ld	[%l4 + IH_CLASSIPL], %o2 ! ih->ih_classipl
 	rd	%psr, %o3		!  (bits already shifted to PIL field)
 	andn	%o3, PSR_PIL, %o3	! %o3 = psr & ~PSR_PIL
 	wr	%o3, %o2, %psr		! splraise(ih->ih_classipl)
 	ld	[%l4 + IH_FUN], %o1
 	ld	[%l4 + IH_ARG], %o0
 	nop				! one more isns before touching ICC
 	tst	%o0
 	bz,a	2f
 @@ -2732,49 +2733,49 @@ sparc_interrupt_common:
 	 nop
 	/* Unhandled interrupts while cold cause IPL to be raised to `high' */
 	sethi	%hi(_C_LABEL(cold)), %o0
 	ld	[%o0 + %lo(_C_LABEL(cold))], %o0
 	tst	%o0			! if (cold) {
 	bnz,a	4f			!	splhigh();
 	 or	%l0, 0xf00, %l0		! } else
 	call	_C_LABEL(strayintr)	!	strayintr(&intrframe)
 	 add	%sp, CCFSZ, %o0
 	/* all done: restore registers and go return */
 :
-	sethi	%hi(CPUINFO_VA), %o2
+	sethi	%hi(CPUINFO_VA+CPUINFO_IDEPTH), %o2
-	ld	[ %o2 + CPUINFO_IDEPTH ], %o3
+	ld	[ %o2 + %lo(CPUINFO_VA+CPUINFO_IDEPTH) ], %o3
 	dec	%o3
-	st	%o3, [ %o2 + CPUINFO_IDEPTH ]
+	st	%o3, [ %o2 + %lo(CPUINFO_VA+CPUINFO_IDEPTH) ]
 	mov	%l7, %g1
 	wr	%l6, 0, %y
 	ldd	[%sp + CCFSZ + 24], %g2
 	ldd	[%sp + CCFSZ + 32], %g4
 	ldd	[%sp + CCFSZ + 40], %g6
 	b	return_from_trap
 	 wr	%l0, 0, %psr
 #if defined(MULTIPROCESSOR)
 /*
  * Level 14 software interrupt: fast IPI
  * <%l0,%l1,%l2> = <psr, pc, npc>
  * %l3 = int level
  * %l6 = &cpuinfo
  */
 lev14_softint:
-	sethi	%hi(CPUINFO_VA), %l7
+	sethi	%hi(CPUINFO_VA+CPUINFO_LEV14), %l7
-	ldd	[%l7 + CPUINFO_LEV14], %l4
+	ldd	[%l7 + %lo(CPUINFO_VA+CPUINFO_LEV14)], %l4
 	inccc	%l5
 	addx	%l4, %g0, %l4
 	std	%l4, [%l7 + CPUINFO_LEV14]
 	ld	[%l6 + CPUINFO_XMSG_TRAP], %l7
 #ifdef DIAGNOSTIC
 	tst	%l7
 	bz	sparc_interrupt4m_bogus
 	 nop
 #endif
 	jmp	%l7
 	 ld	[%l6 + CPUINFO_XMSG_ARG0], %l3	! prefetch 1st arg
 @@ -4951,33 +4952,33 @@ Lnosaveoldlwp:
 	 add	%o0, 4, %o1
 	st	%o0, [%l3 + TF_PC]	! store rewound %pc
 	st	%o1, [%l3 + TF_NPC]	! and %npc
 Lsw_noras:
 	ret
 	 restore			! return (oldlwp)
 /*
  * Call the idlespin() function if it exists, otherwise just return.
  */
 ENTRY(cpu_idle)
-	sethi	%hi(CPUINFO_VA), %o0
+	sethi	%hi(CPUINFO_VA+CPUINFO_IDLESPIN), %o0
-	ld	[%o0 + CPUINFO_IDLESPIN], %o1
+	ld	[%o0 + %lo(CPUINFO_VA+CPUINFO_IDLESPIN)], %o1
 	tst	%o1
 	bz	1f
 	 nop
 	jmp	%o1
-	 nop	! CPUINFO_VA is already in %o0
+	 nop
 :
 	retl
 	 nop
 /*
  * Snapshot the current process so that stack frames are up to date.
  * Only used just before a crash dump.
  */
 ENTRY(snapshot)
 	std	%o6, [%o0 + PCB_SP]	! save sp
 	rd	%psr, %o1		! save psr
 	st	%o1, [%o0 + PCB_PSR]
 @@ -5631,28 +5632,28 @@ Lkcerr:
  * savefpstate(struct fpstate *f);
  * ipi_savefpstate(struct fpstate *f);
+ *
  * Store the current FPU state.  The first `st %fsr' may cause a trap;
  * our trap handler knows how to recover (by `returning' to savefpcont).
+ *
  * The IPI version just deals with updating event counters first.
  */
 Lpanic_savefpstate:
 	.asciz	"cpu%d: NULL fpstate"
 	_ALIGN
 ENTRY(ipi_savefpstate)
-	sethi	%hi(CPUINFO_VA), %o5
+	sethi	%hi(CPUINFO_VA+CPUINFO_SAVEFPSTATE), %o5
-	ldd	[%o5 + CPUINFO_SAVEFPSTATE], %o2
+	ldd	[%o5 + %lo(CPUINFO_VA+CPUINFO_SAVEFPSTATE)], %o2
 	inccc   %o3
 	addx    %o2, 0, %o2
 	std	%o2, [%o5 + CPUINFO_SAVEFPSTATE]
 ENTRY(savefpstate)
 	cmp	%o0, 0
 	rd	%psr, %o1		! enable FP before we begin
 	set	PSR_EF, %o2
 	or	%o1, %o2, %o1
 	wr	%o1, 0, %psr
 	/* do some setup work while we wait for PSR_EF to turn on */
 	set	FSR_QNE, %o5		! QNE = 0x2000, too big for immediate
 	clr	%o3			! qsize = 0;
 @@ -5845,34 +5846,36 @@ _ENTRY(_C_LABEL(cypress_get_syncflt))
 	set	SRMMU_SFSR, %l5
 	lda	[%l5] ASI_SRMMU, %l5	! get sync fault status register
 	jmp	%l7 + 8			! return to caller
 	 st	%l5, [%l4]		! => dump.sfsr
 #if defined(MULTIPROCESSOR) && 0 /* notyet */
 /*
  * Read Synchronous Fault Status registers.
  * On entry: %o0 == &sfsr, %o1 == &sfar
  */
 _ENTRY(_C_LABEL(smp_get_syncflt))
 	save    %sp, -CCFSZ, %sp
-	sethi	%hi(CPUINFO_VA), %o4
+	sethi	%hi(CPUINFO_VA+CPUINFO_GETSYNCFLT), %o4
 	ld	[%l4 + %lo(CPUINFO_VA+CPUINFO_GETSYNCFLT)], %o5
 	clr	%l1
 	clr	%l3
 	sethi	%hi(CPUINFO_VA+CPUINFO_SYNCFLTDUMP), %o4
 	jmpl	%o5, %l7
-	 or	%o4, %lo(CPUINFO_SYNCFLTDUMP), %l4
+	 or	%o4, %lo(CPUINFO_VA+CPUINFO_SYNCFLTDUMP), %l4
 	! load values out of the dump
 	sethi	%hi(CPUINFO_VA+CPUINFO_SYNCFLTDUMP), %o4
 	ld	[%o4 + %lo(CPUINFO_VA+CPUINFO_SYNCFLTDUMP)], %o5
 	st	%o5, [%i0]
 	ld	[%o4 + %lo(CPUINFO_VA+CPUINFO_SYNCFLTDUMP+4)], %o5
 	st	%o5, [%i1]
 	ret
 	 restore
 #endif /* MULTIPROCESSOR */
 /*
  * Read Asynchronous Fault Status registers.
  * On entry: %o0 == &afsr, %o1 == &afar
  * Return 0 if async register are present.
  */

 @@ -1,14 +1,14 @@
-/*	$NetBSD: msiiep.c,v 1.47 2019/11/10 21:16:33 chs Exp $ */
+/*	$NetBSD: msiiep.c,v 1.48 2019/12/30 22:13:47 ad Exp $ */
 /*
  * Copyright (c) 2001 Valeriy E. Ushakov
  * All rights reserved.
+ *
  * Redistribution and use in source and binary forms, with or without
  * modification, are permitted provided that the following conditions
  * are met:
  * 1. Redistributions of source code must retain the above copyright
  *    notice, this list of conditions and the following disclaimer.
  * 2. Redistributions in binary form must reproduce the above copyright
  *    notice, this list of conditions and the following disclaimer in the
  *    documentation and/or other materials provided with the distribution.
 @@ -17,27 +17,27 @@
+ *
  * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
  * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
  * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
  * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
  * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
  * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
  * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  */
 #include <sys/cdefs.h>
-__KERNEL_RCSID(0, "$NetBSD: msiiep.c,v 1.47 2019/11/10 21:16:33 chs Exp $");
+__KERNEL_RCSID(0, "$NetBSD: msiiep.c,v 1.48 2019/12/30 22:13:47 ad Exp $");
 #include <sys/param.h>
 #include <sys/malloc.h>
 #include <sys/kernel.h>
 #include <sys/systm.h>
 #include <sys/device.h>
 #include <uvm/uvm.h>
 #define _SPARC_BUS_DMA_PRIVATE
 #include <sys/bus.h>
 #include <machine/autoconf.h>
 #include <machine/promlib.h>
 @@ -62,27 +62,27 @@ __KERNEL_RCSID(0, "$NetBSD: msiiep.c,v 1
  * but I'd rather insulate the rest of the source from ms-IIep quirks.
  */
 /*
  * "Stub" ms-IIep parent that knows how to attach various functions.
  */
 static int	msiiep_match(device_t, cfdata_t, void *);
 static void	msiiep_attach(device_t, device_t, void *);
 CFATTACH_DECL_NEW(msiiep, 0, msiiep_match, msiiep_attach, NULL, NULL);
 /* sleep in idle spin */
-static void	msiiep_cpu_sleep(struct cpu_info *);
+static void	msiiep_cpu_sleep(void);
 volatile uint32_t *msiiep_mid = NULL;
 /*
  * The real thing.
  */
 static int	mspcic_match(device_t, cfdata_t, void *);
 static void	mspcic_attach(device_t, device_t, void *);
 static int	mspcic_print(void *, const char *);
 CFATTACH_DECL_NEW(mspcic, sizeof(struct mspcic_softc),
     mspcic_match, mspcic_attach, NULL, NULL);
 @@ -231,27 +231,27 @@ msiiep_attach(device_t parent, device_t
 	msa.msa_ma = ma;
 	/* config timer/counter part of PCIC */
 	msa.msa_name = "timer";
 	config_found(self, &msa, NULL);
 	/* config PCI tree */
 	msa.msa_name = "pcic";
 	config_found(self, &msa, NULL);
+}
 /* ARGSUSED */
 void
-msiiep_cpu_sleep(struct cpu_info *ci)
+msiiep_cpu_sleep(void)
+{
 	uint32_t reg;
 	if (msiiep_mid == 0)
 		return;
 	reg = *msiiep_mid;
 	*msiiep_mid = (reg & MID_MASK) | MID_STANDBY;
+}
 /* ======================================================================
+ *
  *		      Real ms-IIep PCIC driver.

 @@ -1,14 +1,14 @@
-/*	$NetBSD: cpu.h,v 1.103 2019/12/01 15:34:45 ad Exp $ */
+/*	$NetBSD: cpu.h,v 1.104 2019/12/30 22:13:47 ad Exp $ */
 /*
  * Copyright (c) 1992, 1993
  *	The Regents of the University of California.  All rights reserved.
+ *
  * This software was developed by the Computer Systems Engineering group
  * at Lawrence Berkeley Laboratory under DARPA contract BG 91-66 and
  * contributed to Berkeley.
+ *
  * All advertising materials mentioning features or use of this software
  * must display the following acknowledgement:
  *	This product includes software developed by the University of
  *	California, Lawrence Berkeley Laboratory.
 @@ -364,27 +364,27 @@ struct cpu_info {
 	/* hardware-assisted block operation routines */
 	void		(*hwbcopy)(const void *from, void *to, size_t len);
 	void		(*hwbzero)(void *buf, size_t len);
 	/* routine to clear mbus-sbus buffers */
 	void		(*mbusflush)(void);
 #endif
 	/*
 	 * Memory error handler; parity errors, unhandled NMIs and other
 	 * unrecoverable faults end up here.
 	 */
 	void		(*memerr)(unsigned, u_int, u_int, struct trapframe *);
-	void		(*idlespin)(struct cpu_info *);
+	void		(*idlespin)(void);
 	/* Module Control Registers */
 	/*bus_space_handle_t*/ long ci_mbusport;
 	/*bus_space_handle_t*/ long ci_mxccregs;
 	u_int	ci_tt;			/* Last trap (if tracing) */
 	/*
 	 * Start/End VA's of this cpu_info region; we upload the other pages
 	 * in this region that aren't part of the cpu_info to uvm.
 	 */
 	vaddr_t	ci_free_sva1, ci_free_eva1, ci_free_sva2, ci_free_eva2;
 	struct evcnt ci_savefpstate;