 @@ -1,14 +1,14 @@
-#	$NetBSD: genassym.cf,v 1.79 2019/12/22 15:09:39 thorpej Exp $
+#	$NetBSD: genassym.cf,v 1.80 2019/12/30 23:32:29 thorpej Exp $
+#
 # Copyright (c) 1998, 2006, 2007, 2008 The NetBSD Foundation, Inc.
 # All rights reserved.
+#
 # This code is derived from software contributed to The NetBSD Foundation
 # by Charles M. Hannum, and by Andrew Doran.
+#
 # Redistribution and use in source and binary forms, with or without
 # modification, are permitted provided that the following conditions
 # are met:
 # 1. Redistributions of source code must retain the above copyright
 #    notice, this list of conditions and the following disclaimer.
 @@ -242,26 +242,27 @@ define	CPU_INFO_RSP0		offsetof(struct cp
 define	CPU_INFO_URSP0		offsetof(struct cpu_info, ci_svs_ursp0)
 define	CPU_INFO_KRSP0		offsetof(struct cpu_info, ci_svs_krsp0)
 endif
 define	CPU_INFO_NSYSCALL	offsetof(struct cpu_info, ci_data.cpu_nsyscall)
 define	CPU_INFO_NTRAP		offsetof(struct cpu_info, ci_data.cpu_ntrap)
 define	CPU_INFO_NINTR		offsetof(struct cpu_info, ci_data.cpu_nintr)
 define	CPU_INFO_CURPRIORITY	offsetof(struct cpu_info, ci_schedstate.spc_curpriority)
 define	CPU_INFO_GDT		offsetof(struct cpu_info, ci_gdt)
 define	CPU_INFO_ILEVEL		offsetof(struct cpu_info, ci_ilevel)
 define	CPU_INFO_IDEPTH		offsetof(struct cpu_info, ci_idepth)
 if !defined(XENPV)
 define	CPU_INFO_IPENDING	offsetof(struct cpu_info, ci_ipending)
 define	CPU_INFO_IMASKED	offsetof(struct cpu_info, ci_imasked)
 define	CPU_INFO_IMASK		offsetof(struct cpu_info, ci_imask)
 define	CPU_INFO_IUNMASK	offsetof(struct cpu_info, ci_iunmask)
 define	CPU_INFO_ISOURCES	offsetof(struct cpu_info, ci_isources)
 endif
 define	CPU_INFO_MTX_COUNT	offsetof(struct cpu_info, ci_mtx_count)
 define	CPU_INFO_MTX_OLDSPL	offsetof(struct cpu_info, ci_mtx_oldspl)
 define  CPU_INFO_CPUID		offsetof(struct cpu_info, ci_cpuid)
 define	CPU_INFO_ISTATE		offsetof(struct cpu_info, ci_istate)
 define	CPU_INFO_CC_SKEW	offsetof(struct cpu_info, ci_data.cpu_cc_skew)
 define	ACPI_SUSPEND_GDT	offsetof(struct cpu_info, ci_suspend_gdt)
 define	ACPI_SUSPEND_IDT	offsetof(struct cpu_info, ci_suspend_idt)
 define	ACPI_SUSPEND_TR		offsetof(struct cpu_info, ci_suspend_tr)

 @@ -1,14 +1,14 @@
-/*	$NetBSD: vector.S,v 1.72 2019/12/22 15:09:39 thorpej Exp $	*/
+/*	$NetBSD: vector.S,v 1.73 2019/12/30 23:32:29 thorpej Exp $	*/
 /*
  * Copyright (c) 1998, 2007, 2008 The NetBSD Foundation, Inc.
  * All rights reserved.
+ *
  * This code is derived from software contributed to The NetBSD Foundation
  * by Charles M. Hannum and by Andrew Doran.
+ *
  * Redistribution and use in source and binary forms, with or without
  * modification, are permitted provided that the following conditions
  * are met:
  * 1. Redistributions of source code must retain the above copyright
  *    notice, this list of conditions and the following disclaimer.
 @@ -382,53 +382,58 @@ IDTVEC(handle_ ## name ## num)						;\
 	movl	IS_MAXLEVEL(%r14),%ebx					;\
 	movl	CPUVAR(ILEVEL),%r13d					;\
 	cmpl	%ebx,%r13d						;\
 	jae	10f			/* currently masked; hold it */	;\
 	incq	CPUVAR(NINTR)		/* statistical info */		;\
 	incq	IS_EVCNT(%r14)						;\
 :									\
 	pushq	%r13			/* save for Xdoreti */		;\
 	movl	%ebx,CPUVAR(ILEVEL)					;\
 	sti								;\
 	incl	CPUVAR(IDEPTH)						;\
 	movq	IS_HANDLERS(%r14),%rbx					;\
 	cmpl	$0,IS_MASK_COUNT(%r14)	/* source currently masked? */	;\
-	jne	7f			/* yes, hold it */		;\
+	jne	12f			/* yes, hold it */		;\
 :									\
 	movl	IH_LEVEL(%rbx),%r12d					;\
 	cmpl	%r13d,%r12d						;\
 	jle	7f							;\
 	movq	%rsp,%rsi						;\
 	movq	IH_ARG(%rbx),%rdi					;\
 	movl	%r12d,CPUVAR(ILEVEL)					;\
 	call	*IH_FUN(%rbx)		/* call it */			;\
 	movq	IH_NEXT(%rbx),%rbx	/* next handler in chain */	;\
 	testq	%rbx,%rbx						;\
 	jnz	6b							;\
 :									\
 	cmpl	$0,IS_MASK_COUNT(%r14)	/* source now masked? */	;\
-	jne	7f			/* yes, deal */			;\
+	jne	12f			/* yes, deal */			;\
 	cli								;\
 	unmask(num)			/* unmask it in hardware */	;\
 	late_ack(num)							;\
 	sti								;\
 	jmp	_C_LABEL(Xdoreti)	/* lower spl and do ASTs */	;\
 :									\
 	cli								;\
 	orl	$(1 << num),CPUVAR(IPENDING)				;\
-	level_mask(num)							;\
+:	level_mask(num)							;\
 	late_ack(num)							;\
 	sti								;\
 	jmp	_C_LABEL(Xdoreti)	/* lower spl and do ASTs */	;\
 :									\
 	cli								;\
 	orl	$(1 << num),CPUVAR(IMASKED)				;\
 	btrl	$(num),CPUVAR(IPENDING)					;\
 	jmp	8b							;\
 :									\
 	cli								;\
 	orl	$(1 << num),CPUVAR(IPENDING)				;\
 	level_mask(num)							;\
 	late_ack(num)							;\
 	INTRFASTEXIT							;\
 :									\
 	unmask(num)							;\
 	late_ack(num)							;\
 	INTRFASTEXIT							;\
 IDTVEC_END(handle_ ## name ## num)					;\
 	TEXT_USER_BEGIN							;\
 IDTVEC(intr_ ## name ## num)						;\

 @@ -1,14 +1,14 @@
-#	$NetBSD: genassym.cf,v 1.116 2019/12/22 15:09:39 thorpej Exp $
+#	$NetBSD: genassym.cf,v 1.117 2019/12/30 23:32:29 thorpej Exp $
+#
 # Copyright (c) 1998, 2006, 2007, 2008 The NetBSD Foundation, Inc.
 # All rights reserved.
+#
 # This code is derived from software contributed to The NetBSD Foundation
 # by Charles M. Hannum, and by Andrew Doran.
+#
 # Redistribution and use in source and binary forms, with or without
 # modification, are permitted provided that the following conditions
 # are met:
 # 1. Redistributions of source code must retain the above copyright
 #    notice, this list of conditions and the following disclaimer.
 @@ -264,26 +264,27 @@ define	IOMAP_VALIDOFF		IOMAP_VALIDOFF
 define	CPU_INFO_NSYSCALL	offsetof(struct cpu_info, ci_data.cpu_nsyscall)
 define	CPU_INFO_NTRAP		offsetof(struct cpu_info, ci_data.cpu_ntrap)
 define	CPU_INFO_NINTR		offsetof(struct cpu_info, ci_data.cpu_nintr)
 define	CPU_INFO_CURPRIORITY	offsetof(struct cpu_info, ci_schedstate.spc_curpriority)
 define	CPU_INFO_CC_SKEW	offsetof(struct cpu_info, ci_data.cpu_cc_skew)
 define	CPU_INFO_VENDOR		offsetof(struct cpu_info, ci_vendor[0])
 define	CPU_INFO_SIGNATURE	offsetof(struct cpu_info, ci_signature)
 define	CPU_INFO_GDT		offsetof(struct cpu_info, ci_gdt)
 if !defined(XENPV)
 define	CPU_INFO_IPENDING	offsetof(struct cpu_info, ci_ipending)
 define	CPU_INFO_IMASKED	offsetof(struct cpu_info, ci_imasked)
 define	CPU_INFO_IMASK		offsetof(struct cpu_info, ci_imask)
 define	CPU_INFO_ISOURCES	offsetof(struct cpu_info, ci_isources)
 define	CPU_INFO_IUNMASK	offsetof(struct cpu_info, ci_iunmask)
 endif
 define	CPU_INFO_ILEVEL		offsetof(struct cpu_info, ci_ilevel)
 define	CPU_INFO_IDEPTH		offsetof(struct cpu_info, ci_idepth)
 define	CPU_INFO_MTX_COUNT	offsetof(struct cpu_info, ci_mtx_count)
 define	CPU_INFO_MTX_OLDSPL	offsetof(struct cpu_info, ci_mtx_oldspl)
 define	CPU_INFO_INTRSTACK	offsetof(struct cpu_info, ci_intrstack)
 define	CPU_INFO_ISTATE		offsetof(struct cpu_info, ci_istate)
 define	ACPI_SUSPEND_GDT	offsetof(struct cpu_info, ci_suspend_gdt)
 define	ACPI_SUSPEND_IDT	offsetof(struct cpu_info, ci_suspend_idt)

 @@ -1,14 +1,14 @@
-/*	$NetBSD: vector.S,v 1.84 2019/12/22 15:09:39 thorpej Exp $	*/
+/*	$NetBSD: vector.S,v 1.85 2019/12/30 23:32:29 thorpej Exp $	*/
 /*
  * Copyright 2002 (c) Wasabi Systems, Inc.
  * All rights reserved.
+ *
  * Written by Frank van der Linden for Wasabi Systems, Inc.
+ *
  * Redistribution and use in source and binary forms, with or without
  * modification, are permitted provided that the following conditions
  * are met:
  * 1. Redistributions of source code must retain the above copyright
  *    notice, this list of conditions and the following disclaimer.
  * 2. Redistributions in binary form must reproduce the above copyright
 @@ -55,27 +55,27 @@
  * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
  * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
  * PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
  * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
  * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
  * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
  * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
  * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
  * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
  * POSSIBILITY OF SUCH DAMAGE.
  */
 #include <machine/asm.h>
-__KERNEL_RCSID(0, "$NetBSD: vector.S,v 1.84 2019/12/22 15:09:39 thorpej Exp $");
+__KERNEL_RCSID(0, "$NetBSD: vector.S,v 1.85 2019/12/30 23:32:29 thorpej Exp $");
 #include "opt_ddb.h"
 #include "opt_multiprocessor.h"
 #include "opt_xen.h"
 #include "opt_dtrace.h"
 #include <machine/i8259.h>
 #include <machine/i82093reg.h>
 #include <machine/i82489reg.h>
 #include <machine/frameasm.h>
 #include <machine/segments.h>
 #include <machine/specialreg.h>
 #include <machine/trap.h>
 @@ -399,51 +399,56 @@ IDTVEC(intr_ ## name ## num)						;\
 	jae	10f			/* currently masked; hold it */	;\
 	addl	$1,CPUVAR(NINTR)	/* statistical info */		;\
 	adcl	$0,CPUVAR(NINTR)+4					;\
 	addl	$1,IS_EVCNTLO(%ebp)	/* inc event counter */		;\
 	adcl	$0,IS_EVCNTHI(%ebp)					;\
 :									\
 	pushl	%esi			/* if_ppi */			;\
 	movl	%ebx,CPUVAR(ILEVEL)					;\
 	/* switch stack if necessary, and push a ptr to our intrframe */ \
 	IDEPTH_INCR							;\
 	sti								;\
 	movl	IS_HANDLERS(%ebp),%ebx					;\
 	cmpl	$0,IS_MASK_COUNT(%ebp)	/* source currently masked? */	;\
-	jne	7f			/* yes, hold it */		;\
+	jne	12f			/* yes, hold it */		;\
 :									\
 	movl	IH_LEVEL(%ebx),%edi					;\
 	cmpl	%esi,%edi						;\
 	jle	7f							;\
 	pushl	IH_ARG(%ebx)						;\
 	movl	IH_FUN(%ebx),%eax					;\
 	movl	%edi,CPUVAR(ILEVEL)					;\
 	movl	IH_NEXT(%ebx),%ebx	/* next handler in chain */	;\
 	call	*%eax			/* call it */			;\
 	addl	$4,%esp			/* toss the arg */		;\
 	testl	%ebx,%ebx						;\
 	jnz	6b							;\
 	cmpl	$0,IS_MASK_COUNT(%ebp)	/* source now masked? */	;\
-	jne	7f			/* yes, deal */			;\
+	jne	12f			/* yes, deal */			;\
 	cli								;\
 	unmask(num)			/* unmask it in hardware */	;\
 	late_ack(num)							;\
 	jmp	_C_LABEL(Xdoreti)	/* lower spl and do ASTs */	;\
 :									\
 	cli								;\
 	orl	$(1 << num),CPUVAR(IPENDING)				;\
-	level_mask(num)							;\
+:	level_mask(num)							;\
 	late_ack(num)							;\
 	jmp	_C_LABEL(Xdoreti)	/* lower spl and do ASTs */	;\
 :									\
 	cli								;\
 	orl	$(1 << num),CPUVAR(IMASKED)				;\
 	btrl	$(num),CPUVAR(IPENDING)					;\
 	jmp	8b							;\
 :									\
 	orl	$(1 << num),CPUVAR(IPENDING)				;\
 	level_mask(num)							;\
 	late_ack(num)							;\
 	INTRFASTEXIT							;\
 :									\
 	pushl	%esp			/* for unmask */		;\
 	unmask(num)							;\
 	late_ack(num)							;\
 	addl	$4,%esp							;\
 	INTRFASTEXIT							;\
 IDTVEC_END(intr_ ## name ## num)

 @@ -1,14 +1,14 @@
-/*	$NetBSD: cpu.h,v 1.115 2019/12/01 15:34:46 ad Exp $	*/
+/*	$NetBSD: cpu.h,v 1.116 2019/12/30 23:32:29 thorpej Exp $	*/
 /*
  * Copyright (c) 1990 The Regents of the University of California.
  * All rights reserved.
+ *
  * This code is derived from software contributed to Berkeley by
  * William Jolitz.
+ *
  * Redistribution and use in source and binary forms, with or without
  * modification, are permitted provided that the following conditions
  * are met:
  * 1. Redistributions of source code must retain the above copyright
  *    notice, this list of conditions and the following disclaimer.
 @@ -139,29 +139,31 @@ struct cpu_info {
 	struct intrsource *ci_xsources[NIPL];
 	uint32_t	ci_xmask[NIPL];
 	uint32_t	ci_xunmask[NIPL];
 	uint32_t	ci_xpending; /* XEN doesn't use the cmpxchg8 path */
 #endif
 	volatile int	ci_mtx_count;	/* Negative count of spin mutexes */
 	volatile int	ci_mtx_oldspl;	/* Old SPL at this ci_idepth */
 	/* The following must be aligned for cmpxchg8b. */
 	struct {
 		uint32_t	ipending;
 		int		ilevel;
 		uint32_t	imasked;
 	} ci_istate __aligned(8);
 #define ci_ipending	ci_istate.ipending
 #define	ci_ilevel	ci_istate.ilevel
 #define	ci_imasked	ci_istate.imasked
 	int		ci_idepth;
 	void *		ci_intrstack;
 	uint32_t	ci_imask[NIPL];
 	uint32_t	ci_iunmask[NIPL];
 	uint32_t	ci_signature;	/* X86 cpuid type (cpuid.1.%eax) */
 	uint32_t	ci_vendor[4];	/* vendor string */
 	uint32_t	ci_max_cpuid;	/* cpuid.0:%eax */
 	uint32_t	ci_max_ext_cpuid; /* cpuid.80000000:%eax */
 	volatile uint32_t	ci_lapic_counter;
 	uint32_t	ci_feat_val[8]; /* X86 CPUID feature bits */
 			/* [0] basic features cpuid.1:%edx

 @@ -1,14 +1,14 @@
-/*	$NetBSD: intr.c,v 1.149 2019/12/22 16:50:03 ad Exp $	*/
+/*	$NetBSD: intr.c,v 1.150 2019/12/30 23:32:30 thorpej Exp $	*/
 /*
  * Copyright (c) 2007, 2008, 2009, 2019 The NetBSD Foundation, Inc.
  * All rights reserved.
+ *
  * This code is derived from software contributed to The NetBSD Foundation
  * by Andrew Doran, and by Jason R. Thorpe.
+ *
  * Redistribution and use in source and binary forms, with or without
  * modification, are permitted provided that the following conditions
  * are met:
  * 1. Redistributions of source code must retain the above copyright
  *    notice, this list of conditions and the following disclaimer.
 @@ -123,27 +123,27 @@
  * ARE DISCLAIMED.  IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
  * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
  * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
  * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
  * SUCH DAMAGE.
+ *
  *	@(#)isa.c	7.2 (Berkeley) 5/13/91
  */
 #include <sys/cdefs.h>
-__KERNEL_RCSID(0, "$NetBSD: intr.c,v 1.149 2019/12/22 16:50:03 ad Exp $");
+__KERNEL_RCSID(0, "$NetBSD: intr.c,v 1.150 2019/12/30 23:32:30 thorpej Exp $");
 #include "opt_intrdebug.h"
 #include "opt_multiprocessor.h"
 #include "opt_acpi.h"
 #include <sys/param.h>
 #include <sys/systm.h>
 #include <sys/kernel.h>
 #include <sys/syslog.h>
 #include <sys/device.h>
 #include <sys/kmem.h>
 #include <sys/proc.h>
 #include <sys/errno.h>
 @@ -1042,29 +1042,44 @@ intr_mask_xcall(void *arg1, void *arg2)
 	if (mask) {
 		source->is_mask_count++;
 		KASSERT(source->is_mask_count != 0);
 		if (source->is_mask_count == 1) {
 			(*pic->pic_hwmask)(pic, ih->ih_pin);
+		}
 	} else {
 		KASSERT(source->is_mask_count != 0);
 		if (--source->is_mask_count == 0) {
 			/*
 			 * If this interrupt source is being moved, don't
 			 * unmask it at the hw.
 			 */
-			if (! source->is_distribute_pending)
+			if (! source->is_distribute_pending) {
 				(*pic->pic_hwunmask)(pic, ih->ih_pin);
 			force_pending = true;
 			/*
 			 * For level-sensitive interrupts, the hardware
 			 * will let us know.  For everything else, we
 			 * need to explicitly handle interrupts that
 			 * happened when when the source was masked.
 			 */
 			const uint32_t bit = (1U << ih->ih_slot);
 			if (ci->ci_imasked & bit) {
 				ci->ci_imasked &= ~bit;
 				if (source->is_type != IST_LEVEL) {
 					ci->ci_ipending |= bit;
 					force_pending = true;
+				}
+			}
+		}
+	}
 	/* Re-enable interrupts. */
 	x86_write_psl(psl);
 	if (force_pending) {
 		/* Force processing of any pending interrupts. */
 		splx(splhigh());
+	}
+}
 static void