 @@ -1,14 +1,14 @@
-/*	$NetBSD: pci_subr.c,v 1.218 2019/12/11 07:33:55 msaitoh Exp $	*/
+/*	$NetBSD: pci_subr.c,v 1.219 2020/01/17 02:08:25 msaitoh Exp $	*/
 /*
  * Copyright (c) 1997 Zubin D. Dittia.  All rights reserved.
  * Copyright (c) 1995, 1996, 1998, 2000
  *	Christopher G. Demetriou.  All rights reserved.
  * Copyright (c) 1994 Charles M. Hannum.  All rights reserved.
+ *
  * Redistribution and use in source and binary forms, with or without
  * modification, are permitted provided that the following conditions
  * are met:
  * 1. Redistributions of source code must retain the above copyright
  *    notice, this list of conditions and the following disclaimer.
  * 2. Redistributions in binary form must reproduce the above copyright
 @@ -30,27 +30,27 @@
  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
  * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  */
 /*
  * PCI autoconfiguration support functions.
+ *
  * Note: This file is also built into a userland library (libpci).
  * Pay attention to this when you make modifications.
  */
 #include <sys/cdefs.h>
-__KERNEL_RCSID(0, "$NetBSD: pci_subr.c,v 1.218 2019/12/11 07:33:55 msaitoh Exp $");
+__KERNEL_RCSID(0, "$NetBSD: pci_subr.c,v 1.219 2020/01/17 02:08:25 msaitoh Exp $");
 #ifdef _KERNEL_OPT
 #include "opt_pci.h"
 #endif
 #include <sys/param.h>
 #ifdef _KERNEL
 #include <sys/systm.h>
 #include <sys/intr.h>
 #include <sys/module.h>
 #else
 #include <pci.h>
 @@ -2854,151 +2854,158 @@ pci_conf_print_aer_cap(const pcireg_t *r
 		reg = regs[o2i(extcapoff + PCI_AER_ERRSRC_ID)];
 		printf("    Error Source Identification register: 0x%08x\n",
 		    reg);
 		pci_conf_print_aer_cap_errsrc_id(reg);
 		break;
+	}
 	if (tlp_prefix_log) {
 		reg = regs[o2i(extcapoff + PCI_AER_TLP_PREFIX_LOG)];
 		printf("    TLP Prefix Log register: 0x%08x\n", reg);
+	}
+}
 /*
  * Helper function to print the arbitration phase register.
+ *
  * phases: Number of phases in the arbitration tables.
  * arbsize: Number of bits in each phase.
  * indent: Add more two spaces if it's true.
  */
 static void
 pci_conf_print_vc_cap_arbtab(const pcireg_t *regs, int off, const char *name,
-    pcireg_t parbsel, int parbsize)
+    const int phases, int arbsize, bool indent)
+{
 	pcireg_t reg;
-	int num = 16 << parbsel;
+	int num_per_reg = 32 / arbsize;
 	int num_per_reg = sizeof(pcireg_t) / parbsize;
 	int i, j;
-	/* First, dump the table */
+	printf("%s    %s Arbitration Table:\n", indent ? "  " : "", name);
-	for (i = 0; i < num; i += num_per_reg) {
+	for (i = 0; i < phases; i += num_per_reg) {
-		reg = regs[o2i(off + i / num_per_reg)];
+		reg = regs[o2i(off + (sizeof(uint32_t) * (i / num_per_reg)))];
-		printf("    %s Arbitration Table: 0x%08x\n", name, reg);
+		for (j = 0; j < num_per_reg; j++) {
 			printf("%s      Phase[%d]: 0x%x\n", indent ? "  " : "",
-	/* And then, decode each entry */
+			    i + j,
-	for (i = 0; i < num; i += num_per_reg) {
+			    (uint32_t)(reg & __BITS(arbsize - 1, 0)));
-		reg = regs[o2i(off + i / num_per_reg)];
+			reg >>= arbsize;
 		for (j = 0; j < num_per_reg; j++)
 			printf("      Phase[%d]: %d\n", j, reg);
+	}
+}
 /* For VC, bit 4-7 are reserved. For Port, bit 6-7 are reserved */
 static const int arb_phases[8] = {0, 32, 64, 128, 128, 256, 0, 0 };
 static void
 pci_conf_print_vc_cap(const pcireg_t *regs, int extcapoff)
+{
 	pcireg_t reg, n;
-	int parbtab, parbsize;
+	int arbtab, parbsize;
-	pcireg_t parbsel;
+	pcireg_t arbsel;
 	int varbtab, varbsize;
 	pcireg_t varbsel;
 	int i, count;
 	printf("\n  Virtual Channel Register\n");
 	reg = regs[o2i(extcapoff + PCI_VC_CAP1)];
 	printf("    Port VC Capability register 1: 0x%08x\n", reg);
 	count = __SHIFTOUT(reg, PCI_VC_CAP1_EXT_COUNT);
 	printf("      Extended VC Count: %d\n", count);
 	n = __SHIFTOUT(reg, PCI_VC_CAP1_LOWPRI_EXT_COUNT);
 	printf("      Low Priority Extended VC Count: %u\n", n);
 	n = __SHIFTOUT(reg, PCI_VC_CAP1_REFCLK);
 	printf("      Reference Clock: %s\n",
 	    (n == PCI_VC_CAP1_REFCLK_100NS) ? "100ns" : "unknown");
 	parbsize = 1 << __SHIFTOUT(reg, PCI_VC_CAP1_PORT_ARB_TABLE_SIZE);
 	printf("      Port Arbitration Table Entry Size: %dbit\n", parbsize);
 	reg = regs[o2i(extcapoff + PCI_VC_CAP2)];
 	printf("    Port VC Capability register 2: 0x%08x\n", reg);
 	onoff("Hardware fixed arbitration scheme",
 	    reg, PCI_VC_CAP2_ARB_CAP_HW_FIXED_SCHEME);
 	onoff("WRR arbitration with 32 phases",
 	    reg, PCI_VC_CAP2_ARB_CAP_WRR_32);
 	onoff("WRR arbitration with 64 phases",
 	    reg, PCI_VC_CAP2_ARB_CAP_WRR_64);
 	onoff("WRR arbitration with 128 phases",
 	    reg, PCI_VC_CAP2_ARB_CAP_WRR_128);
-	varbtab = __SHIFTOUT(reg, PCI_VC_CAP2_ARB_TABLE_OFFSET);
+	arbtab = __SHIFTOUT(reg, PCI_VC_CAP2_ARB_TABLE_OFFSET);
-	printf("      VC Arbitration Table Offset: 0x%x\n", varbtab);
+	printf("      VC Arbitration Table Offset: 0x%x\n", arbtab);
 	reg = regs[o2i(extcapoff + PCI_VC_CONTROL)] & 0xffff;
 	printf("    Port VC Control register: 0x%04x\n", reg);
-	varbsel = __SHIFTOUT(reg, PCI_VC_CONTROL_VC_ARB_SELECT);
+	arbsel = __SHIFTOUT(reg, PCI_VC_CONTROL_VC_ARB_SELECT);
-	printf("      VC Arbitration Select: 0x%x\n", varbsel);
+	printf("      VC Arbitration Select: 0x%x\n", arbsel);
 	reg = regs[o2i(extcapoff + PCI_VC_STATUS)] >> 16;
 	printf("    Port VC Status register: 0x%04x\n", reg);
 	onoff("VC Arbitration Table Status",
 	    reg, PCI_VC_STATUS_LOAD_VC_ARB_TABLE);
 	if ((arbtab != 0) && (arbsel != 0))
 		pci_conf_print_vc_cap_arbtab(regs, extcapoff + (arbtab * 16),
 		    "VC", arb_phases[arbsel], 4, false);
 	for (i = 0; i < count + 1; i++) {
 		reg = regs[o2i(extcapoff + PCI_VC_RESOURCE_CAP(i))];
 		printf("    VC number %d\n", i);
 		printf("      VC Resource Capability Register: 0x%08x\n", reg);
 		onoff("  Non-configurable Hardware fixed arbitration scheme",
 		    reg, PCI_VC_RESOURCE_CAP_PORT_ARB_CAP_HW_FIXED_SCHEME);
 		onoff("  WRR arbitration with 32 phases",
 		    reg, PCI_VC_RESOURCE_CAP_PORT_ARB_CAP_WRR_32);
 		onoff("  WRR arbitration with 64 phases",
 		    reg, PCI_VC_RESOURCE_CAP_PORT_ARB_CAP_WRR_64);
 		onoff("  WRR arbitration with 128 phases",
 		    reg, PCI_VC_RESOURCE_CAP_PORT_ARB_CAP_WRR_128);
 		onoff("  Time-based WRR arbitration with 128 phases",
 		    reg, PCI_VC_RESOURCE_CAP_PORT_ARB_CAP_TWRR_128);
 		onoff("  WRR arbitration with 256 phases",
 		    reg, PCI_VC_RESOURCE_CAP_PORT_ARB_CAP_WRR_256);
 		onoff("  Advanced Packet Switching",
 		    reg, PCI_VC_RESOURCE_CAP_ADV_PKT_SWITCH);
 		onoff("  Reject Snoop Transaction",
 		    reg, PCI_VC_RESOURCE_CAP_REJCT_SNOOP_TRANS);
 		n = __SHIFTOUT(reg, PCI_VC_RESOURCE_CAP_MAX_TIME_SLOTS) + 1;
 		printf("        Maximum Time Slots: %d\n", n);
-		parbtab = reg >> PCI_VC_RESOURCE_CAP_PORT_ARB_TABLE_OFFSET_S;
+		arbtab = __SHIFTOUT(reg,
 		    PCI_VC_RESOURCE_CAP_PORT_ARB_TABLE_OFFSET);
 		printf("        Port Arbitration Table offset: 0x%02x\n",
-		    parbtab);
+		    arbtab);
 		reg = regs[o2i(extcapoff + PCI_VC_RESOURCE_CTL(i))];
 		printf("      VC Resource Control Register: 0x%08x\n", reg);
 		printf("        TC/VC Map: 0x%02x\n",
 		    (pcireg_t)__SHIFTOUT(reg, PCI_VC_RESOURCE_CTL_TCVC_MAP));
 		/*
 		 * The load Port Arbitration Table bit is used to update
 		 * the Port Arbitration logic and it's always 0 on read, so
 		 * we don't print it.
 		 */
-		parbsel = __SHIFTOUT(reg, PCI_VC_RESOURCE_CTL_PORT_ARB_SELECT);
+		arbsel = __SHIFTOUT(reg, PCI_VC_RESOURCE_CTL_PORT_ARB_SELECT);
-		printf("        Port Arbitration Select: 0x%x\n", parbsel);
+		printf("        Port Arbitration Select: 0x%x\n", arbsel);
 		n = __SHIFTOUT(reg, PCI_VC_RESOURCE_CTL_VC_ID);
 		printf("        VC ID: %d\n", n);
 		onoff("  VC Enable", reg, PCI_VC_RESOURCE_CTL_VC_ENABLE);
 		reg = regs[o2i(extcapoff + PCI_VC_RESOURCE_STA(i))] >> 16;
 		printf("      VC Resource Status Register: 0x%08x\n", reg);
 		onoff("  Port Arbitration Table Status",
 		    reg, PCI_VC_RESOURCE_STA_PORT_ARB_TABLE);
 		onoff("  VC Negotiation Pending",
 		    reg, PCI_VC_RESOURCE_STA_VC_NEG_PENDING);
-		if ((parbtab != 0) && (parbsel != 0))
+		if ((arbtab != 0) && (arbsel != 0))
-			pci_conf_print_vc_cap_arbtab(regs, extcapoff + parbtab,
+			pci_conf_print_vc_cap_arbtab(regs,
-			    "Port", parbsel, parbsize);
+			    extcapoff + (arbtab * 16),
 			    "Port", arb_phases[arbsel], parbsize, true);
+	}
 	varbsize = 8;
 	if ((varbtab != 0) && (varbsel != 0))
 		pci_conf_print_vc_cap_arbtab(regs, extcapoff + varbtab,
 		    "  VC", varbsel, varbsize);
+}
 /*
  * Print Power limit. This encoding is the same among the following registers:
  *  - The Captured Slot Power Limit in the PCIe Device Capability Register.
  *  - The Slot Power Limit in the PCIe Slot Capability Register.
  *  - The Base Power in the Data register of Power Budgeting capability.
  */
 static void
 pci_conf_print_pcie_power(uint8_t base, unsigned int scale)
+{
 	unsigned int sdiv = 1;