 @@ -1,2132 +1,2163 @@
-/*	$NetBSD: rtl8169.c,v 1.159 2019/05/30 02:32:18 msaitoh Exp $	*/
+/*	$NetBSD: rtl8169.c,v 1.159.2.1 2020/01/28 11:12:30 martin Exp $	*/
 /*
  * Copyright (c) 1997, 1998-2003
  *	Bill Paul <wpaul@windriver.com>.  All rights reserved.
+ *
  * Redistribution and use in source and binary forms, with or without
  * modification, are permitted provided that the following conditions
  * are met:
  * 1. Redistributions of source code must retain the above copyright
  *    notice, this list of conditions and the following disclaimer.
  * 2. Redistributions in binary form must reproduce the above copyright
  *    notice, this list of conditions and the following disclaimer in the
  *    documentation and/or other materials provided with the distribution.
  * 3. All advertising materials mentioning features or use of this software
  *    must display the following acknowledgement:
  *	This product includes software developed by Bill Paul.
  * 4. Neither the name of the author nor the names of any co-contributors
  *    may be used to endorse or promote products derived from this software
  *    without specific prior written permission.
+ *
  * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND
  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
  * ARE DISCLAIMED.  IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD
  * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
  * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
  * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
  * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
  * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
  * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
  * THE POSSIBILITY OF SUCH DAMAGE.
  */
 #include <sys/cdefs.h>
-__KERNEL_RCSID(0, "$NetBSD: rtl8169.c,v 1.159 2019/05/30 02:32:18 msaitoh Exp $");
+__KERNEL_RCSID(0, "$NetBSD: rtl8169.c,v 1.159.2.1 2020/01/28 11:12:30 martin Exp $");
 /* $FreeBSD: /repoman/r/ncvs/src/sys/dev/re/if_re.c,v 1.20 2004/04/11 20:34:08 ru Exp $ */
 /*
  * RealTek 8139C+/8169/8169S/8168/8110S PCI NIC driver
+ *
  * Written by Bill Paul <wpaul@windriver.com>
  * Senior Networking Software Engineer
  * Wind River Systems
  */
 /*
  * This driver is designed to support RealTek's next generation of
  * 10/100 and 10/100/1000 PCI ethernet controllers. There are currently
  * six devices in this family: the RTL8139C+, the RTL8169, the RTL8169S,
  * RTL8110S, the RTL8168 and the RTL8111.
+ *
  * The 8139C+ is a 10/100 ethernet chip. It is backwards compatible
  * with the older 8139 family, however it also supports a special
  * C+ mode of operation that provides several new performance enhancing
  * features. These include:
+ *
  *	o Descriptor based DMA mechanism. Each descriptor represents
  *	  a single packet fragment. Data buffers may be aligned on
  *	  any byte boundary.
+ *
  *	o 64-bit DMA
+ *
  *	o TCP/IP checksum offload for both RX and TX
+ *
  *	o High and normal priority transmit DMA rings
+ *
  *	o VLAN tag insertion and extraction
+ *
  *	o TCP large send (segmentation offload)
+ *
  * Like the 8139, the 8139C+ also has a built-in 10/100 PHY. The C+
  * programming API is fairly straightforward. The RX filtering, EEPROM
  * access and PHY access is the same as it is on the older 8139 series
  * chips.
+ *
  * The 8169 is a 64-bit 10/100/1000 gigabit ethernet MAC. It has almost the
  * same programming API and feature set as the 8139C+ with the following
  * differences and additions:
+ *
  *	o 1000Mbps mode
+ *
  *	o Jumbo frames
+ *
  *	o GMII and TBI ports/registers for interfacing with copper
  *	  or fiber PHYs
+ *
  *      o RX and TX DMA rings can have up to 1024 descriptors
  *        (the 8139C+ allows a maximum of 64)
+ *
  *	o Slight differences in register layout from the 8139C+
+ *
  * The TX start and timer interrupt registers are at different locations
  * on the 8169 than they are on the 8139C+. Also, the status word in the
  * RX descriptor has a slightly different bit layout. The 8169 does not
  * have a built-in PHY. Most reference boards use a Marvell 88E1000 'Alaska'
  * copper gigE PHY.
+ *
  * The 8169S/8110S 10/100/1000 devices have built-in copper gigE PHYs
  * (the 'S' stands for 'single-chip'). These devices have the same
  * programming API as the older 8169, but also have some vendor-specific
  * registers for the on-board PHY. The 8110S is a LAN-on-motherboard
  * part designed to be pin-compatible with the RealTek 8100 10/100 chip.
+ *
  * This driver takes advantage of the RX and TX checksum offload and
  * VLAN tag insertion/extraction features. It also implements TX
  * interrupt moderation using the timer interrupt registers, which
  * significantly reduces TX interrupt load. There is also support
  * for jumbo frames, however the 8169/8169S/8110S can not transmit
  * jumbo frames larger than 7.5K, so the max MTU possible with this
  * driver is 7500 bytes.
  */
 #include <sys/param.h>
 #include <sys/endian.h>
 #include <sys/systm.h>
 #include <sys/sockio.h>
 #include <sys/mbuf.h>
 #include <sys/malloc.h>
 #include <sys/kernel.h>
 #include <sys/socket.h>
 #include <sys/device.h>
 #include <net/if.h>
 #include <net/if_arp.h>
 #include <net/if_dl.h>
 #include <net/if_ether.h>
 #include <net/if_media.h>
 #include <net/if_vlanvar.h>
 #include <netinet/in_systm.h>	/* XXX for IP_MAXPACKET */
 #include <netinet/in.h>		/* XXX for IP_MAXPACKET */
 #include <netinet/ip.h>		/* XXX for IP_MAXPACKET */
 #include <net/bpf.h>
 #include <sys/rndsource.h>
 #include <sys/bus.h>
 #include <dev/mii/mii.h>
 #include <dev/mii/miivar.h>
 #include <dev/ic/rtl81x9reg.h>
 #include <dev/ic/rtl81x9var.h>
 #include <dev/ic/rtl8169var.h>
 static inline void re_set_bufaddr(struct re_desc *, bus_addr_t);
 static int re_newbuf(struct rtk_softc *, int, struct mbuf *);
 static int re_rx_list_init(struct rtk_softc *);
 static int re_tx_list_init(struct rtk_softc *);
 static void re_rxeof(struct rtk_softc *);
 static void re_txeof(struct rtk_softc *);
 static void re_tick(void *);
 static void re_start(struct ifnet *);
 static int re_ioctl(struct ifnet *, u_long, void *);
 static int re_init(struct ifnet *);
 static void re_stop(struct ifnet *, int);
 static void re_watchdog(struct ifnet *);
 static int re_enable(struct rtk_softc *);
 static void re_disable(struct rtk_softc *);
 static int re_gmii_readreg(device_t, int, int, uint16_t *);
 static int re_gmii_writereg(device_t, int, int, uint16_t);
 static int re_miibus_readreg(device_t, int, int, uint16_t *);
 static int re_miibus_writereg(device_t, int, int, uint16_t);
 static void re_miibus_statchg(struct ifnet *);
 static void re_reset(struct rtk_softc *);
 static inline void
 re_set_bufaddr(struct re_desc *d, bus_addr_t addr)
+{
 	d->re_bufaddr_lo = htole32((uint32_t)addr);
 	if (sizeof(bus_addr_t) == sizeof(uint64_t))
 		d->re_bufaddr_hi = htole32((uint64_t)addr >> 32);
 	else
 		d->re_bufaddr_hi = 0;
+}
 static int
 re_gmii_readreg(device_t dev, int phy, int reg, uint16_t *val)
+{
 	struct rtk_softc *sc = device_private(dev);
 	uint32_t data;
 	int i;
 	if (phy != 7)
 		return -1;
 	/* Let the rgephy driver read the GMEDIASTAT register */
 	if (reg == RTK_GMEDIASTAT) {
 		*val = CSR_READ_1(sc, RTK_GMEDIASTAT);
 		return 0;
+	}
 	CSR_WRITE_4(sc, RTK_PHYAR, reg << 16);
 	DELAY(1000);
 	for (i = 0; i < RTK_TIMEOUT; i++) {
 		data = CSR_READ_4(sc, RTK_PHYAR);
 		if (data & RTK_PHYAR_BUSY)
 			break;
 		DELAY(100);
+	}
 	if (i == RTK_TIMEOUT) {
 		printf("%s: PHY read failed\n", device_xname(sc->sc_dev));
 		return ETIMEDOUT;
+	}
 	*val = data & RTK_PHYAR_PHYDATA;
 	return 0;
+}
 static int
 re_gmii_writereg(device_t dev, int phy, int reg, uint16_t val)
+{
 	struct rtk_softc *sc = device_private(dev);
 	uint32_t data;
 	int i;
 	CSR_WRITE_4(sc, RTK_PHYAR, (reg << 16) |
 	    (val & RTK_PHYAR_PHYDATA) | RTK_PHYAR_BUSY);
 	DELAY(1000);
 	for (i = 0; i < RTK_TIMEOUT; i++) {
 		data = CSR_READ_4(sc, RTK_PHYAR);
 		if (!(data & RTK_PHYAR_BUSY))
 			break;
 		DELAY(100);
+	}
 	if (i == RTK_TIMEOUT) {
 		printf("%s: PHY write reg %x <- %hx failed\n",
 		    device_xname(sc->sc_dev), reg, val);
 		return ETIMEDOUT;
+	}
 	return 0;
+}
 static int
 re_miibus_readreg(device_t dev, int phy, int reg, uint16_t *val)
+{
 	struct rtk_softc *sc = device_private(dev);
 	uint16_t re8139_reg = 0;
 	int s, rv = 0;
 	s = splnet();
 	if ((sc->sc_quirk & RTKQ_8139CPLUS) == 0) {
 		rv = re_gmii_readreg(dev, phy, reg, val);
 		splx(s);
 		return rv;
+	}
 	/* Pretend the internal PHY is only at address 0 */
 	if (phy) {
 		splx(s);
 		return -1;
+	}
 	switch (reg) {
 	case MII_BMCR:
 		re8139_reg = RTK_BMCR;
 		break;
 	case MII_BMSR:
 		re8139_reg = RTK_BMSR;
 		break;
 	case MII_ANAR:
 		re8139_reg = RTK_ANAR;
 		break;
 	case MII_ANER:
 		re8139_reg = RTK_ANER;
 		break;
 	case MII_ANLPAR:
 		re8139_reg = RTK_LPAR;
 		break;
 	case MII_PHYIDR1:
 	case MII_PHYIDR2:
 		*val = 0;
 		splx(s);
 		return 0;
 	/*
 	 * Allow the rlphy driver to read the media status
 	 * register. If we have a link partner which does not
 	 * support NWAY, this is the register which will tell
 	 * us the results of parallel detection.
 	 */
 	case RTK_MEDIASTAT:
 		*val = CSR_READ_1(sc, RTK_MEDIASTAT);
 		splx(s);
 		return 0;
 	default:
 		printf("%s: bad phy register\n", device_xname(sc->sc_dev));
 		splx(s);
 		return -1;
+	}
 	*val = CSR_READ_2(sc, re8139_reg);
 	if ((sc->sc_quirk & RTKQ_8139CPLUS) != 0 && re8139_reg == RTK_BMCR) {
 		/* 8139C+ has different bit layout. */
 		*val &= ~(BMCR_LOOP | BMCR_ISO);
+	}
 	splx(s);
 	return 0;
+}
 static int
 re_miibus_writereg(device_t dev, int phy, int reg, uint16_t val)
+{
 	struct rtk_softc *sc = device_private(dev);
 	uint16_t re8139_reg = 0;
 	int s, rv;
 	s = splnet();
 	if ((sc->sc_quirk & RTKQ_8139CPLUS) == 0) {
 		rv = re_gmii_writereg(dev, phy, reg, val);
 		splx(s);
 		return rv;
+	}
 	/* Pretend the internal PHY is only at address 0 */
 	if (phy) {
 		splx(s);
 		return -1;
+	}
 	switch (reg) {
 	case MII_BMCR:
 		re8139_reg = RTK_BMCR;
 		if ((sc->sc_quirk & RTKQ_8139CPLUS) != 0) {
 			/* 8139C+ has different bit layout. */
 			val &= ~(BMCR_LOOP | BMCR_ISO);
+		}
 		break;
 	case MII_BMSR:
 		re8139_reg = RTK_BMSR;
 		break;
 	case MII_ANAR:
 		re8139_reg = RTK_ANAR;
 		break;
 	case MII_ANER:
 		re8139_reg = RTK_ANER;
 		break;
 	case MII_ANLPAR:
 		re8139_reg = RTK_LPAR;
 		break;
 	case MII_PHYIDR1:
 	case MII_PHYIDR2:
 		splx(s);
 		return 0;
 		break;
 	default:
 		printf("%s: bad phy register\n", device_xname(sc->sc_dev));
 		splx(s);
 		return -1;
+	}
 	CSR_WRITE_2(sc, re8139_reg, val);
 	splx(s);
 	return 0;
+}
 static void
 re_miibus_statchg(struct ifnet *ifp)
+{
 	return;
+}
 static void
 re_reset(struct rtk_softc *sc)
+{
 	int i;
 	CSR_WRITE_1(sc, RTK_COMMAND, RTK_CMD_RESET);
 	for (i = 0; i < RTK_TIMEOUT; i++) {
 		DELAY(10);
 		if ((CSR_READ_1(sc, RTK_COMMAND) & RTK_CMD_RESET) == 0)
 			break;
+	}
 	if (i == RTK_TIMEOUT)
 		printf("%s: reset never completed!\n",
 		    device_xname(sc->sc_dev));
 	/*
 	 * NB: Realtek-supplied FreeBSD driver does this only for MACFG_3,
 	 *     but also says "Rtl8169s sigle chip detected".
 	 */
 	if ((sc->sc_quirk & RTKQ_MACLDPS) != 0)
 		CSR_WRITE_1(sc, RTK_LDPS, 1);
+}
 /*
  * The following routine is designed to test for a defect on some
  * 32-bit 8169 cards. Some of these NICs have the REQ64# and ACK64#
  * lines connected to the bus, however for a 32-bit only card, they
  * should be pulled high. The result of this defect is that the
  * NIC will not work right if you plug it into a 64-bit slot: DMA
  * operations will be done with 64-bit transfers, which will fail
  * because the 64-bit data lines aren't connected.
+ *
  * There's no way to work around this (short of talking a soldering
  * iron to the board), however we can detect it. The method we use
  * here is to put the NIC into digital loopback mode, set the receiver
  * to promiscuous mode, and then try to send a frame. We then compare
  * the frame data we sent to what was received. If the data matches,
  * then the NIC is working correctly, otherwise we know the user has
  * a defective NIC which has been mistakenly plugged into a 64-bit PCI
  * slot. In the latter case, there's no way the NIC can work correctly,
  * so we print out a message on the console and abort the device attach.
  */
 int
 re_diag(struct rtk_softc *sc)
+{
 	struct ifnet *ifp = &sc->ethercom.ec_if;
 	struct mbuf *m0;
 	struct ether_header *eh;
 	struct re_rxsoft *rxs;
 	struct re_desc *cur_rx;
 	bus_dmamap_t dmamap;
 	uint16_t status;
 	uint32_t rxstat;
 	int total_len, i, s, error = 0;
 	static const uint8_t dst[] = { 0x00, 'h', 'e', 'l', 'l', 'o' };
 	static const uint8_t src[] = { 0x00, 'w', 'o', 'r', 'l', 'd' };
 	/* Allocate a single mbuf */
 	MGETHDR(m0, M_DONTWAIT, MT_DATA);
 	if (m0 == NULL)
 		return ENOBUFS;
 	/*
 	 * Initialize the NIC in test mode. This sets the chip up
 	 * so that it can send and receive frames, but performs the
 	 * following special functions:
 	 * - Puts receiver in promiscuous mode
 	 * - Enables digital loopback mode
 	 * - Leaves interrupts turned off
 	 */
 	ifp->if_flags |= IFF_PROMISC;
 	sc->re_testmode = 1;
 	re_init(ifp);
 	re_stop(ifp, 0);
 	DELAY(100000);
 	re_init(ifp);
 	/* Put some data in the mbuf */
 	eh = mtod(m0, struct ether_header *);
 	memcpy(eh->ether_dhost, &dst, ETHER_ADDR_LEN);
 	memcpy(eh->ether_shost, &src, ETHER_ADDR_LEN);
 	eh->ether_type = htons(ETHERTYPE_IP);
 	m0->m_pkthdr.len = m0->m_len = ETHER_MIN_LEN - ETHER_CRC_LEN;
 	/*
 	 * Queue the packet, start transmission.
 	 */
 	CSR_WRITE_2(sc, RTK_ISR, 0xFFFF);
 	s = splnet();
 	IF_ENQUEUE(&ifp->if_snd, m0);
 	re_start(ifp);
 	splx(s);
 	m0 = NULL;
 	/* Wait for it to propagate through the chip */
 	DELAY(100000);
 	for (i = 0; i < RTK_TIMEOUT; i++) {
 		status = CSR_READ_2(sc, RTK_ISR);
 		if ((status & (RTK_ISR_TIMEOUT_EXPIRED | RTK_ISR_RX_OK)) ==
 		    (RTK_ISR_TIMEOUT_EXPIRED | RTK_ISR_RX_OK))
 			break;
 		DELAY(10);
+	}
 	if (i == RTK_TIMEOUT) {
 		aprint_error_dev(sc->sc_dev,
 		    "diagnostic failed, failed to receive packet "
 		    "in loopback mode\n");
 		error = EIO;
 		goto done;
+	}
 	/*
 	 * The packet should have been dumped into the first
 	 * entry in the RX DMA ring. Grab it from there.
 	 */
 	rxs = &sc->re_ldata.re_rxsoft[0];
 	dmamap = rxs->rxs_dmamap;
 	bus_dmamap_sync(sc->sc_dmat, dmamap, 0, dmamap->dm_mapsize,
 	    BUS_DMASYNC_POSTREAD);
 	bus_dmamap_unload(sc->sc_dmat, dmamap);
 	m0 = rxs->rxs_mbuf;
 	rxs->rxs_mbuf = NULL;
 	eh = mtod(m0, struct ether_header *);
 	RE_RXDESCSYNC(sc, 0, BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE);
 	cur_rx = &sc->re_ldata.re_rx_list[0];
 	rxstat = le32toh(cur_rx->re_cmdstat);
 	total_len = rxstat & sc->re_rxlenmask;
 	if (total_len != ETHER_MIN_LEN) {
 		aprint_error_dev(sc->sc_dev,
 		    "diagnostic failed, received short packet\n");
 		error = EIO;
 		goto done;
+	}
 	/* Test that the received packet data matches what we sent. */
 	if (memcmp(&eh->ether_dhost, &dst, ETHER_ADDR_LEN) ||
 	    memcmp(&eh->ether_shost, &src, ETHER_ADDR_LEN) ||
 	    ntohs(eh->ether_type) != ETHERTYPE_IP) {
 		aprint_error_dev(sc->sc_dev, "WARNING, DMA FAILURE!\n"
 		    "expected TX data: %s/%s/0x%x\n"
 		    "received RX data: %s/%s/0x%x\n"
 		    "You may have a defective 32-bit NIC plugged "
 		    "into a 64-bit PCI slot.\n"
 		    "Please re-install the NIC in a 32-bit slot "
 		    "for proper operation.\n"
 		    "Read the re(4) man page for more details.\n" ,
 		    ether_sprintf(dst),  ether_sprintf(src), ETHERTYPE_IP,
 		    ether_sprintf(eh->ether_dhost),
 		    ether_sprintf(eh->ether_shost), ntohs(eh->ether_type));
 		error = EIO;
+	}
  done:
 	/* Turn interface off, release resources */
 	sc->re_testmode = 0;
 	ifp->if_flags &= ~IFF_PROMISC;
 	re_stop(ifp, 0);
 	if (m0 != NULL)
 		m_freem(m0);
 	return error;
+}
 /*
  * Attach the interface. Allocate softc structures, do ifmedia
  * setup and ethernet/BPF attach.
  */
 void
 re_attach(struct rtk_softc *sc)
+{
 	uint8_t eaddr[ETHER_ADDR_LEN];
 	struct ifnet *ifp;
 	struct mii_data *mii = &sc->mii;
 	int error = 0, i;
 	if ((sc->sc_quirk & RTKQ_8139CPLUS) == 0) {
 		uint32_t hwrev;
 		/* Revision of 8169/8169S/8110s in bits 30..26, 23 */
 		hwrev = CSR_READ_4(sc, RTK_TXCFG) & RTK_TXCFG_HWREV;
 		switch (hwrev) {
 		case RTK_HWREV_8169:
 			sc->sc_quirk |= RTKQ_8169NONS;
 			break;
 		case RTK_HWREV_8169S:
 		case RTK_HWREV_8110S:
 		case RTK_HWREV_8169_8110SB:
 		case RTK_HWREV_8169_8110SBL:
 		case RTK_HWREV_8169_8110SC:
 			sc->sc_quirk |= RTKQ_MACLDPS;
 			break;
 		case RTK_HWREV_8168_SPIN1:
 		case RTK_HWREV_8168_SPIN2:
 		case RTK_HWREV_8168_SPIN3:
 			sc->sc_quirk |= RTKQ_MACSTAT;
 			break;
 		case RTK_HWREV_8168C:
 		case RTK_HWREV_8168C_SPIN2:
 		case RTK_HWREV_8168CP:
 		case RTK_HWREV_8168D:
 		case RTK_HWREV_8168DP:
 			sc->sc_quirk |= RTKQ_DESCV2 | RTKQ_NOEECMD |
 			    RTKQ_MACSTAT | RTKQ_CMDSTOP;
 			/*
 			 * From FreeBSD driver:
+			 *
 			 * These (8168/8111) controllers support jumbo frame
 			 * but it seems that enabling it requires touching
 			 * additional magic registers. Depending on MAC
 			 * revisions some controllers need to disable
 			 * checksum offload. So disable jumbo frame until
 			 * I have better idea what it really requires to
 			 * make it support.
 			 * RTL8168C/CP : supports up to 6KB jumbo frame.
 			 * RTL8111C/CP : supports up to 9KB jumbo frame.
 			 */
 			sc->sc_quirk |= RTKQ_NOJUMBO;
 			break;
 		case RTK_HWREV_8168E:
 		case RTK_HWREV_8168H:
 		case RTK_HWREV_8168H_SPIN1:
 			sc->sc_quirk |= RTKQ_DESCV2 | RTKQ_NOEECMD |
 			    RTKQ_MACSTAT | RTKQ_CMDSTOP | RTKQ_PHYWAKE_PM |
 			    RTKQ_NOJUMBO;
 			break;
 		case RTK_HWREV_8168H:
 		case RTK_HWREV_8168FP:
 			sc->sc_quirk |= RTKQ_DESCV2 | RTKQ_NOEECMD |
 			    RTKQ_MACSTAT | RTKQ_CMDSTOP | RTKQ_PHYWAKE_PM |
 			    RTKQ_NOJUMBO | RTKQ_RXDV_GATED | RTKQ_TXRXEN_LATER;
 			break;
 		case RTK_HWREV_8168E_VL:
 		case RTK_HWREV_8168F:
 		case RTK_HWREV_8411:
 			sc->sc_quirk |= RTKQ_DESCV2 | RTKQ_NOEECMD |
 			    RTKQ_MACSTAT | RTKQ_CMDSTOP | RTKQ_NOJUMBO;
 			break;
 		case RTK_HWREV_8168EP:
 		case RTK_HWREV_8168G:
 		case RTK_HWREV_8168G_SPIN1:
 		case RTK_HWREV_8168G_SPIN2:
 		case RTK_HWREV_8168G_SPIN4:
 			sc->sc_quirk |= RTKQ_DESCV2 | RTKQ_NOEECMD |
 			    RTKQ_MACSTAT | RTKQ_CMDSTOP | RTKQ_NOJUMBO |
 			    RTKQ_RXDV_GATED;
 			break;
 		case RTK_HWREV_8100E:
 		case RTK_HWREV_8100E_SPIN2:
 		case RTK_HWREV_8101E:
 			sc->sc_quirk |= RTKQ_NOJUMBO;
 			break;
 		case RTK_HWREV_8102E:
 		case RTK_HWREV_8102EL:
-		case RTK_HWREV_8103E:
+		case RTK_HWREV_8102EL_SPIN1:
 			sc->sc_quirk |= RTKQ_DESCV2 | RTKQ_NOEECMD |
 			    RTKQ_MACSTAT | RTKQ_CMDSTOP | RTKQ_NOJUMBO;
 			break;
 		case RTK_HWREV_8103E:
 			sc->sc_quirk |= RTKQ_DESCV2 | RTKQ_NOEECMD |
 			    RTKQ_MACSTAT | RTKQ_CMDSTOP;
 			break;
 		case RTK_HWREV_8401E:
 		case RTK_HWREV_8105E:
 		case RTK_HWREV_8105E_SPIN1:
 		case RTK_HWREV_8106E:
 			sc->sc_quirk |= RTKQ_PHYWAKE_PM |
 			    RTKQ_DESCV2 | RTKQ_NOEECMD | RTKQ_MACSTAT |
 			    RTKQ_CMDSTOP;
 			break;
 		case RTK_HWREV_8402:
 			sc->sc_quirk |= RTKQ_PHYWAKE_PM |
 			    RTKQ_DESCV2 | RTKQ_NOEECMD | RTKQ_MACSTAT |
 			    RTKQ_CMDSTOP; /* CMDSTOP_WAIT_TXQ */
 			break;
 		default:
 			aprint_normal_dev(sc->sc_dev,
 			    "Unknown revision (0x%08x)\n", hwrev);
 			/* assume the latest features */
 			sc->sc_quirk |= RTKQ_DESCV2 | RTKQ_NOEECMD;
 			sc->sc_quirk |= RTKQ_NOJUMBO;
+		}
 		/* Set RX length mask */
 		sc->re_rxlenmask = RE_RDESC_STAT_GFRAGLEN;
 		sc->re_ldata.re_tx_desc_cnt = RE_TX_DESC_CNT_8169;
 	} else {
 		sc->sc_quirk |= RTKQ_NOJUMBO;
 		/* Set RX length mask */
 		sc->re_rxlenmask = RE_RDESC_STAT_FRAGLEN;
 		sc->re_ldata.re_tx_desc_cnt = RE_TX_DESC_CNT_8139;
+	}
 	/* Reset the adapter. */
 	re_reset(sc);
 	/*
 	 * RTL81x9 chips automatically read EEPROM to init MAC address,
 	 * and some NAS override its MAC address per own configuration,
 	 * so no need to explicitely read EEPROM and set ID registers.
 	 */
 #ifdef RE_USE_EECMD
 	if ((sc->sc_quirk & RTKQ_NOEECMD) != 0) {
 		/*
 		 * Get station address from ID registers.
 		 */
 		for (i = 0; i < ETHER_ADDR_LEN; i++)
 			eaddr[i] = CSR_READ_1(sc, RTK_IDR0 + i);
 	} else {
 		uint16_t val;
 		int addr_len;
 		/*
 		 * Get station address from the EEPROM.
 		 */
 		if (rtk_read_eeprom(sc, RTK_EE_ID, RTK_EEADDR_LEN1) == 0x8129)
 			addr_len = RTK_EEADDR_LEN1;
 		else
 			addr_len = RTK_EEADDR_LEN0;
 		/*
 		 * Get station address from the EEPROM.
 		 */
 		for (i = 0; i < ETHER_ADDR_LEN / 2; i++) {
 			val = rtk_read_eeprom(sc, RTK_EE_EADDR0 + i, addr_len);
 			eaddr[(i * 2) + 0] = val & 0xff;
 			eaddr[(i * 2) + 1] = val >> 8;
+		}
+	}
 #else
 	/*
 	 * Get station address from ID registers.
 	 */
 	for (i = 0; i < ETHER_ADDR_LEN; i++)
 		eaddr[i] = CSR_READ_1(sc, RTK_IDR0 + i);
 #endif
 	/* Take PHY out of power down mode. */
 	if ((sc->sc_quirk & RTKQ_PHYWAKE_PM) != 0)
 		CSR_WRITE_1(sc, RTK_PMCH, CSR_READ_1(sc, RTK_PMCH) | 0x80);
 	aprint_normal_dev(sc->sc_dev, "Ethernet address %s\n",
 	    ether_sprintf(eaddr));
 	if (sc->re_ldata.re_tx_desc_cnt >
 	    PAGE_SIZE / sizeof(struct re_desc)) {
 		sc->re_ldata.re_tx_desc_cnt =
 		    PAGE_SIZE / sizeof(struct re_desc);
+	}
 	aprint_verbose_dev(sc->sc_dev, "using %d tx descriptors\n",
 	    sc->re_ldata.re_tx_desc_cnt);
 	KASSERT(RE_NEXT_TX_DESC(sc, RE_TX_DESC_CNT(sc) - 1) == 0);
 	/* Allocate DMA'able memory for the TX ring */
 	if ((error = bus_dmamem_alloc(sc->sc_dmat, RE_TX_LIST_SZ(sc),
 	    RE_RING_ALIGN, 0, &sc->re_ldata.re_tx_listseg, 1,
 	    &sc->re_ldata.re_tx_listnseg, BUS_DMA_NOWAIT)) != 0) {
 		aprint_error_dev(sc->sc_dev,
 		    "can't allocate tx listseg, error = %d\n", error);
 		goto fail_0;
+	}
 	/* Load the map for the TX ring. */
 	if ((error = bus_dmamem_map(sc->sc_dmat, &sc->re_ldata.re_tx_listseg,
 	    sc->re_ldata.re_tx_listnseg, RE_TX_LIST_SZ(sc),
 	    (void **)&sc->re_ldata.re_tx_list,
 	    BUS_DMA_COHERENT | BUS_DMA_NOWAIT)) != 0) {
 		aprint_error_dev(sc->sc_dev,
 		    "can't map tx list, error = %d\n", error);
 		goto fail_1;
+	}
 	memset(sc->re_ldata.re_tx_list, 0, RE_TX_LIST_SZ(sc));
 	if ((error = bus_dmamap_create(sc->sc_dmat, RE_TX_LIST_SZ(sc), 1,
 	    RE_TX_LIST_SZ(sc), 0, 0,
 	    &sc->re_ldata.re_tx_list_map)) != 0) {
 		aprint_error_dev(sc->sc_dev,
 		    "can't create tx list map, error = %d\n", error);
 		goto fail_2;
+	}
 	if ((error = bus_dmamap_load(sc->sc_dmat,
 	    sc->re_ldata.re_tx_list_map, sc->re_ldata.re_tx_list,
 	    RE_TX_LIST_SZ(sc), NULL, BUS_DMA_NOWAIT)) != 0) {
 		aprint_error_dev(sc->sc_dev,
 		    "can't load tx list, error = %d\n", error);
 		goto fail_3;
+	}
 	/* Create DMA maps for TX buffers */
 	for (i = 0; i < RE_TX_QLEN; i++) {
 		error = bus_dmamap_create(sc->sc_dmat,
 		    round_page(IP_MAXPACKET),
 		    RE_TX_DESC_CNT(sc), RE_TDESC_CMD_FRAGLEN,
 , 0, &sc->re_ldata.re_txq[i].txq_dmamap);
 		if (error) {
 			aprint_error_dev(sc->sc_dev,
 			    "can't create DMA map for TX\n");
 			goto fail_4;
+		}
+	}
 	/* Allocate DMA'able memory for the RX ring */
 	/* XXX see also a comment about RE_RX_DMAMEM_SZ in rtl81x9var.h */
 	if ((error = bus_dmamem_alloc(sc->sc_dmat,
 	    RE_RX_DMAMEM_SZ, RE_RING_ALIGN, 0, &sc->re_ldata.re_rx_listseg, 1,
 	    &sc->re_ldata.re_rx_listnseg, BUS_DMA_NOWAIT)) != 0) {
 		aprint_error_dev(sc->sc_dev,
 		    "can't allocate rx listseg, error = %d\n", error);
 		goto fail_4;
+	}
 	/* Load the map for the RX ring. */
 	if ((error = bus_dmamem_map(sc->sc_dmat, &sc->re_ldata.re_rx_listseg,
 	    sc->re_ldata.re_rx_listnseg, RE_RX_DMAMEM_SZ,
 	    (void **)&sc->re_ldata.re_rx_list,
 	    BUS_DMA_COHERENT | BUS_DMA_NOWAIT)) != 0) {
 		aprint_error_dev(sc->sc_dev,
 		    "can't map rx list, error = %d\n", error);
 		goto fail_5;
+	}
 	memset(sc->re_ldata.re_rx_list, 0, RE_RX_DMAMEM_SZ);
 	if ((error = bus_dmamap_create(sc->sc_dmat,
 	    RE_RX_DMAMEM_SZ, 1, RE_RX_DMAMEM_SZ, 0, 0,
 	    &sc->re_ldata.re_rx_list_map)) != 0) {
 		aprint_error_dev(sc->sc_dev,
 		    "can't create rx list map, error = %d\n", error);
 		goto fail_6;
+	}
 	if ((error = bus_dmamap_load(sc->sc_dmat,
 	    sc->re_ldata.re_rx_list_map, sc->re_ldata.re_rx_list,
 	    RE_RX_DMAMEM_SZ, NULL, BUS_DMA_NOWAIT)) != 0) {
 		aprint_error_dev(sc->sc_dev,
 		    "can't load rx list, error = %d\n", error);
 		goto fail_7;
+	}
 	/* Create DMA maps for RX buffers */
 	for (i = 0; i < RE_RX_DESC_CNT; i++) {
 		error = bus_dmamap_create(sc->sc_dmat, MCLBYTES, 1, MCLBYTES,
 , 0, &sc->re_ldata.re_rxsoft[i].rxs_dmamap);
 		if (error) {
 			aprint_error_dev(sc->sc_dev,
 			    "can't create DMA map for RX\n");
 			goto fail_8;
+		}
+	}
 	/*
 	 * Record interface as attached. From here, we should not fail.
 	 */
 	sc->sc_flags |= RTK_ATTACHED;
 	ifp = &sc->ethercom.ec_if;
 	ifp->if_softc = sc;
 	strlcpy(ifp->if_xname, device_xname(sc->sc_dev), IFNAMSIZ);
 	ifp->if_mtu = ETHERMTU;
 	ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST;
 	ifp->if_ioctl = re_ioctl;
 	sc->ethercom.ec_capabilities |=
 	    ETHERCAP_VLAN_MTU | ETHERCAP_VLAN_HWTAGGING;
 	ifp->if_start = re_start;
 	ifp->if_stop = re_stop;
 	/*
 	 * IFCAP_CSUM_IPv4_Tx on re(4) is broken for small packets,
 	 * so we have a workaround to handle the bug by padding
 	 * such packets manually.
 	 */
 	ifp->if_capabilities |=
 	    IFCAP_CSUM_IPv4_Tx | IFCAP_CSUM_IPv4_Rx |
 	    IFCAP_CSUM_TCPv4_Tx | IFCAP_CSUM_TCPv4_Rx |
 	    IFCAP_CSUM_UDPv4_Tx | IFCAP_CSUM_UDPv4_Rx |
 	    IFCAP_TSOv4;
 	ifp->if_watchdog = re_watchdog;
 	ifp->if_init = re_init;
 	ifp->if_snd.ifq_maxlen = RE_IFQ_MAXLEN;
 	ifp->if_capenable = ifp->if_capabilities;
 	IFQ_SET_READY(&ifp->if_snd);
 	callout_init(&sc->rtk_tick_ch, 0);
 	/* Do MII setup */
 	mii->mii_ifp = ifp;
 	mii->mii_readreg = re_miibus_readreg;
 	mii->mii_writereg = re_miibus_writereg;
 	mii->mii_statchg = re_miibus_statchg;
 	sc->ethercom.ec_mii = mii;
 	ifmedia_init(&mii->mii_media, IFM_IMASK, ether_mediachange,
 	    ether_mediastatus);
 	mii_attach(sc->sc_dev, mii, 0xffffffff, MII_PHY_ANY,
 	    MII_OFFSET_ANY, 0);
 	ifmedia_set(&mii->mii_media, IFM_ETHER | IFM_AUTO);
 	/*
 	 * Call MI attach routine.
 	 */
 	if_attach(ifp);
 	if_deferred_start_init(ifp, NULL);
 	ether_ifattach(ifp, eaddr);
 	rnd_attach_source(&sc->rnd_source, device_xname(sc->sc_dev),
 	    RND_TYPE_NET, RND_FLAG_DEFAULT);
 	if (pmf_device_register(sc->sc_dev, NULL, NULL))
 		pmf_class_network_register(sc->sc_dev, ifp);
 	else
 		aprint_error_dev(sc->sc_dev,
 		    "couldn't establish power handler\n");
 	return;
  fail_8:
 	/* Destroy DMA maps for RX buffers. */
 	for (i = 0; i < RE_RX_DESC_CNT; i++)
 		if (sc->re_ldata.re_rxsoft[i].rxs_dmamap != NULL)
 			bus_dmamap_destroy(sc->sc_dmat,
 			    sc->re_ldata.re_rxsoft[i].rxs_dmamap);
 	/* Free DMA'able memory for the RX ring. */
 	bus_dmamap_unload(sc->sc_dmat, sc->re_ldata.re_rx_list_map);
  fail_7:
 	bus_dmamap_destroy(sc->sc_dmat, sc->re_ldata.re_rx_list_map);
  fail_6:
 	bus_dmamem_unmap(sc->sc_dmat,
 	    (void *)sc->re_ldata.re_rx_list, RE_RX_DMAMEM_SZ);
  fail_5:
 	bus_dmamem_free(sc->sc_dmat,
 	    &sc->re_ldata.re_rx_listseg, sc->re_ldata.re_rx_listnseg);
  fail_4:
 	/* Destroy DMA maps for TX buffers. */
 	for (i = 0; i < RE_TX_QLEN; i++)
 		if (sc->re_ldata.re_txq[i].txq_dmamap != NULL)
 			bus_dmamap_destroy(sc->sc_dmat,
 			    sc->re_ldata.re_txq[i].txq_dmamap);
 	/* Free DMA'able memory for the TX ring. */
 	bus_dmamap_unload(sc->sc_dmat, sc->re_ldata.re_tx_list_map);
  fail_3:
 	bus_dmamap_destroy(sc->sc_dmat, sc->re_ldata.re_tx_list_map);
  fail_2:
 	bus_dmamem_unmap(sc->sc_dmat,
 	    (void *)sc->re_ldata.re_tx_list, RE_TX_LIST_SZ(sc));
  fail_1:
 	bus_dmamem_free(sc->sc_dmat,
 	    &sc->re_ldata.re_tx_listseg, sc->re_ldata.re_tx_listnseg);
  fail_0:
 	return;
+}
 /*
  * re_activate:
  *     Handle device activation/deactivation requests.
  */
 int
 re_activate(device_t self, enum devact act)
+{
 	struct rtk_softc *sc = device_private(self);
 	switch (act) {
 	case DVACT_DEACTIVATE:
 		if_deactivate(&sc->ethercom.ec_if);
 		return 0;
 	default:
 		return EOPNOTSUPP;
+	}
+}
 /*
  * re_detach:
  *     Detach a rtk interface.
  */
 int
 re_detach(struct rtk_softc *sc)
+{
 	struct ifnet *ifp = &sc->ethercom.ec_if;
 	int i;
 	/*
 	 * Succeed now if there isn't any work to do.
 	 */
 	if ((sc->sc_flags & RTK_ATTACHED) == 0)
 		return 0;
 	/* Unhook our tick handler. */
 	callout_stop(&sc->rtk_tick_ch);
 	/* Detach all PHYs. */
 	mii_detach(&sc->mii, MII_PHY_ANY, MII_OFFSET_ANY);
 	/* Delete all remaining media. */
 	ifmedia_delete_instance(&sc->mii.mii_media, IFM_INST_ANY);
 	rnd_detach_source(&sc->rnd_source);
 	ether_ifdetach(ifp);
 	if_detach(ifp);
 	/* Destroy DMA maps for RX buffers. */
 	for (i = 0; i < RE_RX_DESC_CNT; i++)
 		if (sc->re_ldata.re_rxsoft[i].rxs_dmamap != NULL)
 			bus_dmamap_destroy(sc->sc_dmat,
 			    sc->re_ldata.re_rxsoft[i].rxs_dmamap);
 	/* Free DMA'able memory for the RX ring. */
 	bus_dmamap_unload(sc->sc_dmat, sc->re_ldata.re_rx_list_map);
 	bus_dmamap_destroy(sc->sc_dmat, sc->re_ldata.re_rx_list_map);
 	bus_dmamem_unmap(sc->sc_dmat,
 	    (void *)sc->re_ldata.re_rx_list, RE_RX_DMAMEM_SZ);
 	bus_dmamem_free(sc->sc_dmat,
 	    &sc->re_ldata.re_rx_listseg, sc->re_ldata.re_rx_listnseg);
 	/* Destroy DMA maps for TX buffers. */
 	for (i = 0; i < RE_TX_QLEN; i++)
 		if (sc->re_ldata.re_txq[i].txq_dmamap != NULL)
 			bus_dmamap_destroy(sc->sc_dmat,
 			    sc->re_ldata.re_txq[i].txq_dmamap);
 	/* Free DMA'able memory for the TX ring. */
 	bus_dmamap_unload(sc->sc_dmat, sc->re_ldata.re_tx_list_map);
 	bus_dmamap_destroy(sc->sc_dmat, sc->re_ldata.re_tx_list_map);
 	bus_dmamem_unmap(sc->sc_dmat,
 	    (void *)sc->re_ldata.re_tx_list, RE_TX_LIST_SZ(sc));
 	bus_dmamem_free(sc->sc_dmat,
 	    &sc->re_ldata.re_tx_listseg, sc->re_ldata.re_tx_listnseg);
 	pmf_device_deregister(sc->sc_dev);
 	/* we don't want to run again */
 	sc->sc_flags &= ~RTK_ATTACHED;
 	return 0;
+}
 /*
  * re_enable:
  *     Enable the RTL81X9 chip.
  */
 static int
 re_enable(struct rtk_softc *sc)
+{
 	if (RTK_IS_ENABLED(sc) == 0 && sc->sc_enable != NULL) {
 		if ((*sc->sc_enable)(sc) != 0) {
 			printf("%s: device enable failed\n",
 			    device_xname(sc->sc_dev));
 			return EIO;
+		}
 		sc->sc_flags |= RTK_ENABLED;
+	}
 	return 0;
+}
 /*
  * re_disable:
  *     Disable the RTL81X9 chip.
  */
 static void
 re_disable(struct rtk_softc *sc)
+{
 	if (RTK_IS_ENABLED(sc) && sc->sc_disable != NULL) {
 		(*sc->sc_disable)(sc);
 		sc->sc_flags &= ~RTK_ENABLED;
+	}
+}
 static int
 re_newbuf(struct rtk_softc *sc, int idx, struct mbuf *m)
+{
 	struct mbuf *n = NULL;
 	bus_dmamap_t map;
 	struct re_desc *d;
 	struct re_rxsoft *rxs;
 	uint32_t cmdstat;
 	int error;
 	if (m == NULL) {
 		MGETHDR(n, M_DONTWAIT, MT_DATA);
 		if (n == NULL)
 			return ENOBUFS;
 		MCLGET(n, M_DONTWAIT);
 		if ((n->m_flags & M_EXT) == 0) {
 			m_freem(n);
 			return ENOBUFS;
+		}
 		m = n;
 	} else
 		m->m_data = m->m_ext.ext_buf;
 	/*
 	 * Initialize mbuf length fields and fixup
 	 * alignment so that the frame payload is
 	 * longword aligned.
 	 */
 	m->m_len = m->m_pkthdr.len = MCLBYTES - RE_ETHER_ALIGN;
 	m->m_data += RE_ETHER_ALIGN;
 	rxs = &sc->re_ldata.re_rxsoft[idx];
 	map = rxs->rxs_dmamap;
 	error = bus_dmamap_load_mbuf(sc->sc_dmat, map, m,
 	    BUS_DMA_READ|BUS_DMA_NOWAIT);
 	if (error)
 		goto out;
 	bus_dmamap_sync(sc->sc_dmat, map, 0, map->dm_mapsize,
 	    BUS_DMASYNC_PREREAD);
 	d = &sc->re_ldata.re_rx_list[idx];
 #ifdef DIAGNOSTIC
 	RE_RXDESCSYNC(sc, idx, BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE);
 	cmdstat = le32toh(d->re_cmdstat);
 	RE_RXDESCSYNC(sc, idx, BUS_DMASYNC_PREREAD);
 	if (cmdstat & RE_RDESC_STAT_OWN) {
 		panic("%s: tried to map busy RX descriptor",
 		    device_xname(sc->sc_dev));
+	}
 #endif
 	rxs->rxs_mbuf = m;
 	d->re_vlanctl = 0;
 	cmdstat = map->dm_segs[0].ds_len;
 	if (idx == (RE_RX_DESC_CNT - 1))
 		cmdstat |= RE_RDESC_CMD_EOR;
 	re_set_bufaddr(d, map->dm_segs[0].ds_addr);
 	d->re_cmdstat = htole32(cmdstat);
 	RE_RXDESCSYNC(sc, idx, BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE);
 	cmdstat |= RE_RDESC_CMD_OWN;
 	d->re_cmdstat = htole32(cmdstat);
 	RE_RXDESCSYNC(sc, idx, BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE);
 	return 0;
  out:
 	if (n != NULL)
 		m_freem(n);
 	return ENOMEM;
+}
 static int
 re_tx_list_init(struct rtk_softc *sc)
+{
 	int i;
 	memset(sc->re_ldata.re_tx_list, 0, RE_TX_LIST_SZ(sc));
 	for (i = 0; i < RE_TX_QLEN; i++) {
 		sc->re_ldata.re_txq[i].txq_mbuf = NULL;
+	}
 	bus_dmamap_sync(sc->sc_dmat,
 	    sc->re_ldata.re_tx_list_map, 0,
 	    sc->re_ldata.re_tx_list_map->dm_mapsize,
 	    BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE);
 	sc->re_ldata.re_txq_prodidx = 0;
 	sc->re_ldata.re_txq_considx = 0;
 	sc->re_ldata.re_txq_free = RE_TX_QLEN;
 	sc->re_ldata.re_tx_free = RE_TX_DESC_CNT(sc);
 	sc->re_ldata.re_tx_nextfree = 0;
 	return 0;
+}
 static int
 re_rx_list_init(struct rtk_softc *sc)
+{
 	int i;
 	memset(sc->re_ldata.re_rx_list, 0, RE_RX_LIST_SZ);
 	for (i = 0; i < RE_RX_DESC_CNT; i++) {
 		if (re_newbuf(sc, i, NULL) == ENOBUFS)
 			return ENOBUFS;
+	}
 	sc->re_ldata.re_rx_prodidx = 0;
 	sc->re_head = sc->re_tail = NULL;
 	return 0;
+}
 /*
  * RX handler for C+ and 8169. For the gigE chips, we support
  * the reception of jumbo frames that have been fragmented
  * across multiple 2K mbuf cluster buffers.
  */
 static void
 re_rxeof(struct rtk_softc *sc)
+{
 	struct mbuf *m;
 	struct ifnet *ifp;
 	int i, total_len;
 	struct re_desc *cur_rx;
 	struct re_rxsoft *rxs;
 	uint32_t rxstat, rxvlan;
 	ifp = &sc->ethercom.ec_if;
 	for (i = sc->re_ldata.re_rx_prodidx;; i = RE_NEXT_RX_DESC(sc, i)) {
 		cur_rx = &sc->re_ldata.re_rx_list[i];
 		RE_RXDESCSYNC(sc, i,
 		    BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE);
 		rxstat = le32toh(cur_rx->re_cmdstat);
 		rxvlan = le32toh(cur_rx->re_vlanctl);
 		RE_RXDESCSYNC(sc, i, BUS_DMASYNC_PREREAD);
 		if ((rxstat & RE_RDESC_STAT_OWN) != 0) {
 			break;
+		}
 		total_len = rxstat & sc->re_rxlenmask;
 		rxs = &sc->re_ldata.re_rxsoft[i];
 		m = rxs->rxs_mbuf;
 		/* Invalidate the RX mbuf and unload its map */
 		bus_dmamap_sync(sc->sc_dmat,
 		    rxs->rxs_dmamap, 0, rxs->rxs_dmamap->dm_mapsize,
 		    BUS_DMASYNC_POSTREAD);
 		bus_dmamap_unload(sc->sc_dmat, rxs->rxs_dmamap);
 		if ((rxstat & RE_RDESC_STAT_EOF) == 0) {
 			m->m_len = MCLBYTES - RE_ETHER_ALIGN;
 			if (sc->re_head == NULL)
 				sc->re_head = sc->re_tail = m;
 			else {
 				m_remove_pkthdr(m);
 				sc->re_tail->m_next = m;
 				sc->re_tail = m;
+			}
 			re_newbuf(sc, i, NULL);
 			continue;
+		}
 		/*
 		 * NOTE: for the 8139C+, the frame length field
 		 * is always 12 bits in size, but for the gigE chips,
 		 * it is 13 bits (since the max RX frame length is 16K).
 		 * Unfortunately, all 32 bits in the status word
 		 * were already used, so to make room for the extra
 		 * length bit, RealTek took out the 'frame alignment
 		 * error' bit and shifted the other status bits
 		 * over one slot. The OWN, EOR, FS and LS bits are
 		 * still in the same places. We have already extracted
 		 * the frame length and checked the OWN bit, so rather
 		 * than using an alternate bit mapping, we shift the
 		 * status bits one space to the right so we can evaluate
 		 * them using the 8169 status as though it was in the
 		 * same format as that of the 8139C+.
 		 */
 		if ((sc->sc_quirk & RTKQ_8139CPLUS) == 0)
 			rxstat >>= 1;
 		if (__predict_false((rxstat & RE_RDESC_STAT_RXERRSUM) != 0)) {
 #ifdef RE_DEBUG
 			printf("%s: RX error (rxstat = 0x%08x)",
 			    device_xname(sc->sc_dev), rxstat);
 			if (rxstat & RE_RDESC_STAT_FRALIGN)
 				printf(", frame alignment error");
 			if (rxstat & RE_RDESC_STAT_BUFOFLOW)
 				printf(", out of buffer space");
 			if (rxstat & RE_RDESC_STAT_FIFOOFLOW)
 				printf(", FIFO overrun");
 			if (rxstat & RE_RDESC_STAT_GIANT)
 				printf(", giant packet");
 			if (rxstat & RE_RDESC_STAT_RUNT)
 				printf(", runt packet");
 			if (rxstat & RE_RDESC_STAT_CRCERR)
 				printf(", CRC error");
 			printf("\n");
 #endif
 			ifp->if_ierrors++;
 			/*
 			 * If this is part of a multi-fragment packet,
 			 * discard all the pieces.
 			 */
 			if (sc->re_head != NULL) {
 				m_freem(sc->re_head);
 				sc->re_head = sc->re_tail = NULL;
+			}
 			re_newbuf(sc, i, m);
 			continue;
+		}
 		/*
 		 * If allocating a replacement mbuf fails,
 		 * reload the current one.
 		 */
 		if (__predict_false(re_newbuf(sc, i, NULL) != 0)) {
 			ifp->if_ierrors++;
 			if (sc->re_head != NULL) {
 				m_freem(sc->re_head);
 				sc->re_head = sc->re_tail = NULL;
+			}
 			re_newbuf(sc, i, m);
 			continue;
+		}
 		if (sc->re_head != NULL) {
 			m->m_len = total_len % (MCLBYTES - RE_ETHER_ALIGN);
 			/*
 			 * Special case: if there's 4 bytes or less
 			 * in this buffer, the mbuf can be discarded:
 			 * the last 4 bytes is the CRC, which we don't
 			 * care about anyway.
 			 */
 			if (m->m_len <= ETHER_CRC_LEN) {
 				sc->re_tail->m_len -=
 				    (ETHER_CRC_LEN - m->m_len);
 				m_freem(m);
 			} else {
 				m->m_len -= ETHER_CRC_LEN;
 				m_remove_pkthdr(m);
 				sc->re_tail->m_next = m;
+			}
 			m = sc->re_head;
 			sc->re_head = sc->re_tail = NULL;
 			m->m_pkthdr.len = total_len - ETHER_CRC_LEN;
 		} else
 			m->m_pkthdr.len = m->m_len =
 			    (total_len - ETHER_CRC_LEN);
 		m_set_rcvif(m, ifp);
 		/* Do RX checksumming */
 		if ((sc->sc_quirk & RTKQ_DESCV2) == 0) {
 			/* Check IP header checksum */
 			if ((rxstat & RE_RDESC_STAT_PROTOID) != 0) {
 				m->m_pkthdr.csum_flags |= M_CSUM_IPv4;
 				if (rxstat & RE_RDESC_STAT_IPSUMBAD)
 					m->m_pkthdr.csum_flags |=
 					    M_CSUM_IPv4_BAD;
 				/* Check TCP/UDP checksum */
 				if (RE_TCPPKT(rxstat)) {
 					m->m_pkthdr.csum_flags |= M_CSUM_TCPv4;
 					if (rxstat & RE_RDESC_STAT_TCPSUMBAD)
 						m->m_pkthdr.csum_flags |=
 						    M_CSUM_TCP_UDP_BAD;
 				} else if (RE_UDPPKT(rxstat)) {
 					m->m_pkthdr.csum_flags |= M_CSUM_UDPv4;
 					if (rxstat & RE_RDESC_STAT_UDPSUMBAD) {
 						/*
 						 * XXX: 8139C+ thinks UDP csum
 						 * 0xFFFF is bad, force software
 						 * calculation.
 						 */
 						if (sc->sc_quirk & RTKQ_8139CPLUS)
 							m->m_pkthdr.csum_flags
 							    &= ~M_CSUM_UDPv4;
 						else
 							m->m_pkthdr.csum_flags
 							    |= M_CSUM_TCP_UDP_BAD;
+					}
+				}
+			}
 		} else {
 			/* Check IPv4 header checksum */
 			if ((rxvlan & RE_RDESC_VLANCTL_IPV4) != 0) {
 				m->m_pkthdr.csum_flags |= M_CSUM_IPv4;
 				if (rxstat & RE_RDESC_STAT_IPSUMBAD)
 					m->m_pkthdr.csum_flags |=
 					    M_CSUM_IPv4_BAD;
 				/* Check TCPv4/UDPv4 checksum */
 				if (RE_TCPPKT(rxstat)) {
 					m->m_pkthdr.csum_flags |= M_CSUM_TCPv4;
 					if (rxstat & RE_RDESC_STAT_TCPSUMBAD)
 						m->m_pkthdr.csum_flags |=
 						    M_CSUM_TCP_UDP_BAD;
 				} else if (RE_UDPPKT(rxstat)) {
 					m->m_pkthdr.csum_flags |= M_CSUM_UDPv4;
 					if (rxstat & RE_RDESC_STAT_UDPSUMBAD)
 						m->m_pkthdr.csum_flags |=
 						    M_CSUM_TCP_UDP_BAD;
+				}
+			}
 			/* XXX Check TCPv6/UDPv6 checksum? */
+		}
 		if (rxvlan & RE_RDESC_VLANCTL_TAG) {
 			vlan_set_tag(m,
 			     bswap16(rxvlan & RE_RDESC_VLANCTL_DATA));
+		}
 		if_percpuq_enqueue(ifp->if_percpuq, m);
+	}
 	sc->re_ldata.re_rx_prodidx = i;
+}
 static void
 re_txeof(struct rtk_softc *sc)
+{
 	struct ifnet *ifp;
 	struct re_txq *txq;
 	uint32_t txstat;
 	int idx, descidx;
 	ifp = &sc->ethercom.ec_if;
 	for (idx = sc->re_ldata.re_txq_considx;
 	    sc->re_ldata.re_txq_free < RE_TX_QLEN;
 	    idx = RE_NEXT_TXQ(sc, idx), sc->re_ldata.re_txq_free++) {
 		txq = &sc->re_ldata.re_txq[idx];
 		KASSERT(txq->txq_mbuf != NULL);
 		descidx = txq->txq_descidx;
 		RE_TXDESCSYNC(sc, descidx,
 		    BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE);
 		txstat =
 		    le32toh(sc->re_ldata.re_tx_list[descidx].re_cmdstat);
 		RE_TXDESCSYNC(sc, descidx, BUS_DMASYNC_PREREAD);
 		KASSERT((txstat & RE_TDESC_CMD_EOF) != 0);
 		if (txstat & RE_TDESC_CMD_OWN) {
 			break;
+		}
 		sc->re_ldata.re_tx_free += txq->txq_nsegs;
 		KASSERT(sc->re_ldata.re_tx_free <= RE_TX_DESC_CNT(sc));
 		bus_dmamap_sync(sc->sc_dmat, txq->txq_dmamap,
 , txq->txq_dmamap->dm_mapsize, BUS_DMASYNC_POSTWRITE);
 		bus_dmamap_unload(sc->sc_dmat, txq->txq_dmamap);
 		m_freem(txq->txq_mbuf);
 		txq->txq_mbuf = NULL;
 		if (txstat & (RE_TDESC_STAT_EXCESSCOL | RE_TDESC_STAT_COLCNT))
 			ifp->if_collisions++;
 		if (txstat & RE_TDESC_STAT_TXERRSUM)
 			ifp->if_oerrors++;
 		else
 			ifp->if_opackets++;
+	}
 	sc->re_ldata.re_txq_considx = idx;
 	if (sc->re_ldata.re_txq_free > RE_NTXDESC_RSVD)
 		ifp->if_flags &= ~IFF_OACTIVE;
 	/*
 	 * If not all descriptors have been released reaped yet,
 	 * reload the timer so that we will eventually get another
 	 * interrupt that will cause us to re-enter this routine.
 	 * This is done in case the transmitter has gone idle.
 	 */
 	if (sc->re_ldata.re_txq_free < RE_TX_QLEN) {
 		if ((sc->sc_quirk & RTKQ_IM_HW) == 0)
 			CSR_WRITE_4(sc, RTK_TIMERCNT, 1);
 		if ((sc->sc_quirk & RTKQ_PCIE) != 0) {
 			/*
 			 * Some chips will ignore a second TX request
 			 * issued while an existing transmission is in
 			 * progress. If the transmitter goes idle but
 			 * there are still packets waiting to be sent,
 			 * we need to restart the channel here to flush
 			 * them out. This only seems to be required with
 			 * the PCIe devices.
 			 */
 			CSR_WRITE_1(sc, RTK_GTXSTART, RTK_TXSTART_START);
+		}
 	} else
 		ifp->if_timer = 0;
+}
 static void
 re_tick(void *arg)
+{
 	struct rtk_softc *sc = arg;
 	int s;
 	/* XXX: just return for 8169S/8110S with rev 2 or newer phy */
 	s = splnet();
 	mii_tick(&sc->mii);
 	splx(s);
 	callout_reset(&sc->rtk_tick_ch, hz, re_tick, sc);
+}
 int
 re_intr(void *arg)
+{
 	struct rtk_softc *sc = arg;
 	struct ifnet *ifp;
 	uint16_t status;
 	int handled = 0;
 	if (!device_has_power(sc->sc_dev))
 		return 0;
 	ifp = &sc->ethercom.ec_if;
 	if ((ifp->if_flags & IFF_UP) == 0)
 		return 0;
 	const uint16_t status_mask = (sc->sc_quirk & RTKQ_IM_HW) ?
 	    RTK_INTRS_IM_HW : RTK_INTRS_CPLUS;
 	for (;;) {
 		status = CSR_READ_2(sc, RTK_ISR);
 		/* If the card has gone away the read returns 0xffff. */
 		if (status == 0xffff)
 			break;
 		if (status) {
 			handled = 1;
 			CSR_WRITE_2(sc, RTK_ISR, status);
+		}
 		if ((status & status_mask) == 0)
 			break;
 		if (status & (RTK_ISR_RX_OK | RTK_ISR_RX_ERR))
 			re_rxeof(sc);
 		if (status & (RTK_ISR_TIMEOUT_EXPIRED | RTK_ISR_TX_ERR |
 		    RTK_ISR_TX_DESC_UNAVAIL | RTK_ISR_TX_OK))
 			re_txeof(sc);
 		if (status & RTK_ISR_SYSTEM_ERR) {
 			re_init(ifp);
+		}
 		if (status & RTK_ISR_LINKCHG) {
 			callout_stop(&sc->rtk_tick_ch);
 			re_tick(sc);
+		}
+	}
 	if (handled)
 		if_schedule_deferred_start(ifp);
 	rnd_add_uint32(&sc->rnd_source, status);
 	return handled;
+}
 /*
  * Main transmit routine for C+ and gigE NICs.
  */
 static void
 re_start(struct ifnet *ifp)
+{
 	struct rtk_softc *sc;
 	struct mbuf *m;
 	bus_dmamap_t map;
 	struct re_txq *txq;
 	struct re_desc *d;
 	uint32_t cmdstat, re_flags, vlanctl;
 	int ofree, idx, error, nsegs, seg;
 	int startdesc, curdesc, lastdesc;
 	bool pad;
 	sc = ifp->if_softc;
 	ofree = sc->re_ldata.re_txq_free;
 	for (idx = sc->re_ldata.re_txq_prodidx;; idx = RE_NEXT_TXQ(sc, idx)) {
 		IFQ_POLL(&ifp->if_snd, m);
 		if (m == NULL)
 			break;
 		if (sc->re_ldata.re_txq_free == 0 ||
 		    sc->re_ldata.re_tx_free == 0) {
 			/* no more free slots left */
 			ifp->if_flags |= IFF_OACTIVE;
 			break;
+		}
 		/*
 		 * Set up checksum offload. Note: checksum offload bits must
 		 * appear in all descriptors of a multi-descriptor transmit
 		 * attempt. (This is according to testing done with an 8169
 		 * chip. I'm not sure if this is a requirement or a bug.)
 		 */
 		vlanctl = 0;
 		if ((m->m_pkthdr.csum_flags & M_CSUM_TSOv4) != 0) {
 			uint32_t segsz = m->m_pkthdr.segsz;
 			if ((sc->sc_quirk & RTKQ_DESCV2) == 0) {
 				re_flags = RE_TDESC_CMD_LGSEND |
 				    (segsz << RE_TDESC_CMD_MSSVAL_SHIFT);
 			} else {
 				re_flags = RE_TDESC_CMD_LGSEND_V4;
 				vlanctl |=
 				    (segsz << RE_TDESC_VLANCTL_MSSVAL_SHIFT);
+			}
 		} else {
 			/*
 			 * set RE_TDESC_CMD_IPCSUM if any checksum offloading
 			 * is requested.  otherwise, RE_TDESC_CMD_TCPCSUM/
 			 * RE_TDESC_CMD_UDPCSUM doesn't make effects.
 			 */
 			re_flags = 0;
 			if ((m->m_pkthdr.csum_flags &
 			    (M_CSUM_IPv4 | M_CSUM_TCPv4 | M_CSUM_UDPv4))
 			    != 0) {
 				if ((sc->sc_quirk & RTKQ_DESCV2) == 0) {
 					re_flags |= RE_TDESC_CMD_IPCSUM;
 					if (m->m_pkthdr.csum_flags &
 					    M_CSUM_TCPv4) {
 						re_flags |=
 						    RE_TDESC_CMD_TCPCSUM;
 					} else if (m->m_pkthdr.csum_flags &
 					    M_CSUM_UDPv4) {
 						re_flags |=
 						    RE_TDESC_CMD_UDPCSUM;
+					}
 				} else {
 					vlanctl |= RE_TDESC_VLANCTL_IPCSUM;
 					if (m->m_pkthdr.csum_flags &
 					    M_CSUM_TCPv4) {
 						vlanctl |=
 						    RE_TDESC_VLANCTL_TCPCSUM;
 					} else if (m->m_pkthdr.csum_flags &
 					    M_CSUM_UDPv4) {
 						vlanctl |=
 						    RE_TDESC_VLANCTL_UDPCSUM;
+					}
+				}
+			}
+		}
 		txq = &sc->re_ldata.re_txq[idx];
 		map = txq->txq_dmamap;
 		error = bus_dmamap_load_mbuf(sc->sc_dmat, map, m,
 		    BUS_DMA_WRITE|BUS_DMA_NOWAIT);
 		if (__predict_false(error)) {
 			/* XXX try to defrag if EFBIG? */
 			printf("%s: can't map mbuf (error %d)\n",
 			    device_xname(sc->sc_dev), error);
 			IFQ_DEQUEUE(&ifp->if_snd, m);
 			m_freem(m);
 			ifp->if_oerrors++;
 			continue;
+		}
 		nsegs = map->dm_nsegs;
 		pad = false;
 		if (__predict_false(m->m_pkthdr.len <= RE_IP4CSUMTX_PADLEN &&
 		    (re_flags & RE_TDESC_CMD_IPCSUM) != 0 &&
 		    (sc->sc_quirk & RTKQ_DESCV2) == 0)) {
 			pad = true;
 			nsegs++;
+		}
 		if (nsegs > sc->re_ldata.re_tx_free) {
 			/*
 			 * Not enough free descriptors to transmit this packet.
 			 */
 			ifp->if_flags |= IFF_OACTIVE;
 			bus_dmamap_unload(sc->sc_dmat, map);
 			break;
+		}
 		IFQ_DEQUEUE(&ifp->if_snd, m);
 		/*
 		 * Make sure that the caches are synchronized before we
 		 * ask the chip to start DMA for the packet data.
 		 */
 		bus_dmamap_sync(sc->sc_dmat, map, 0, map->dm_mapsize,
 		    BUS_DMASYNC_PREWRITE);
 		/*
 		 * Set up hardware VLAN tagging. Note: vlan tag info must
 		 * appear in all descriptors of a multi-descriptor
 		 * transmission attempt.
 		 */
 		if (vlan_has_tag(m))
 			vlanctl |= bswap16(vlan_get_tag(m)) |
 			    RE_TDESC_VLANCTL_TAG;
 		/*
 		 * Map the segment array into descriptors.
 		 * Note that we set the start-of-frame and
 		 * end-of-frame markers for either TX or RX,
 		 * but they really only have meaning in the TX case.
 		 * (In the RX case, it's the chip that tells us
 		 *  where packets begin and end.)
 		 * We also keep track of the end of the ring
 		 * and set the end-of-ring bits as needed,
 		 * and we set the ownership bits in all except
 		 * the very first descriptor. (The caller will
 		 * set this descriptor later when it start
 		 * transmission or reception.)
 		 */
 		curdesc = startdesc = sc->re_ldata.re_tx_nextfree;
 		lastdesc = -1;
 		for (seg = 0; seg < map->dm_nsegs;
 		    seg++, curdesc = RE_NEXT_TX_DESC(sc, curdesc)) {
 			d = &sc->re_ldata.re_tx_list[curdesc];
 #ifdef DIAGNOSTIC
 			RE_TXDESCSYNC(sc, curdesc,
 			    BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE);
 			cmdstat = le32toh(d->re_cmdstat);
 			RE_TXDESCSYNC(sc, curdesc, BUS_DMASYNC_PREREAD);
 			if (cmdstat & RE_TDESC_STAT_OWN) {
 				panic("%s: tried to map busy TX descriptor",
 				    device_xname(sc->sc_dev));
+			}
 #endif
 			d->re_vlanctl = htole32(vlanctl);
 			re_set_bufaddr(d, map->dm_segs[seg].ds_addr);
 			cmdstat = re_flags | map->dm_segs[seg].ds_len;
 			if (seg == 0)
 				cmdstat |= RE_TDESC_CMD_SOF;
 			else
 				cmdstat |= RE_TDESC_CMD_OWN;
 			if (curdesc == (RE_TX_DESC_CNT(sc) - 1))
 				cmdstat |= RE_TDESC_CMD_EOR;
 			if (seg == nsegs - 1) {
 				cmdstat |= RE_TDESC_CMD_EOF;
 				lastdesc = curdesc;
+			}
 			d->re_cmdstat = htole32(cmdstat);
 			RE_TXDESCSYNC(sc, curdesc,
 			    BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE);
+		}
 		if (__predict_false(pad)) {
 			d = &sc->re_ldata.re_tx_list[curdesc];
 			d->re_vlanctl = htole32(vlanctl);
 			re_set_bufaddr(d, RE_TXPADDADDR(sc));
 			cmdstat = re_flags |
 			    RE_TDESC_CMD_OWN | RE_TDESC_CMD_EOF |
 			    (RE_IP4CSUMTX_PADLEN + 1 - m->m_pkthdr.len);
 			if (curdesc == (RE_TX_DESC_CNT(sc) - 1))
 				cmdstat |= RE_TDESC_CMD_EOR;
 			d->re_cmdstat = htole32(cmdstat);
 			RE_TXDESCSYNC(sc, curdesc,
 			    BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE);
 			lastdesc = curdesc;
 			curdesc = RE_NEXT_TX_DESC(sc, curdesc);
+		}
 		KASSERT(lastdesc != -1);
 		/* Transfer ownership of packet to the chip. */
 		sc->re_ldata.re_tx_list[startdesc].re_cmdstat |=
 		    htole32(RE_TDESC_CMD_OWN);
 		RE_TXDESCSYNC(sc, startdesc,
 		    BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE);
 		/* update info of TX queue and descriptors */
 		txq->txq_mbuf = m;
 		txq->txq_descidx = lastdesc;
 		txq->txq_nsegs = nsegs;
 		sc->re_ldata.re_txq_free--;
 		sc->re_ldata.re_tx_free -= nsegs;
 		sc->re_ldata.re_tx_nextfree = curdesc;
 		/*
 		 * If there's a BPF listener, bounce a copy of this frame
 		 * to him.
 		 */
 		bpf_mtap(ifp, m, BPF_D_OUT);
+	}
 	if (sc->re_ldata.re_txq_free < ofree) {
 		/*
 		 * TX packets are enqueued.
 		 */
 		sc->re_ldata.re_txq_prodidx = idx;
 		/*
 		 * Start the transmitter to poll.
+		 *
 		 * RealTek put the TX poll request register in a different
 		 * location on the 8169 gigE chip. I don't know why.
 		 */
 		if ((sc->sc_quirk & RTKQ_8139CPLUS) != 0)
 			CSR_WRITE_1(sc, RTK_TXSTART, RTK_TXSTART_START);
 		else
 			CSR_WRITE_1(sc, RTK_GTXSTART, RTK_TXSTART_START);
 		if ((sc->sc_quirk & RTKQ_IM_HW) == 0) {
 			/*
 			 * Use the countdown timer for interrupt moderation.
 			 * 'TX done' interrupts are disabled. Instead, we reset
 			 * the countdown timer, which will begin counting until
 			 * it hits the value in the TIMERINT register, and then
 			 * trigger an interrupt. Each time we write to the
 			 * TIMERCNT register, the timer count is reset to 0.
 			 */
 			CSR_WRITE_4(sc, RTK_TIMERCNT, 1);
+		}
 		/*
 		 * Set a timeout in case the chip goes out to lunch.
 		 */
 		ifp->if_timer = 5;
+	}
+}
 static int
 re_init(struct ifnet *ifp)
+{
 	struct rtk_softc *sc = ifp->if_softc;
 	uint32_t rxcfg = 0;
 	uint16_t cfg;
 	int error;
 #ifdef RE_USE_EECMD
 	const uint8_t *enaddr;
 	uint32_t reg;
 #endif
 	if ((error = re_enable(sc)) != 0)
 		goto out;
 	/*
 	 * Cancel pending I/O and free all RX/TX buffers.
 	 */
 	re_stop(ifp, 0);
 	re_reset(sc);
 	/*
 	 * Enable C+ RX and TX mode, as well as VLAN stripping and
 	 * RX checksum offload. We must configure the C+ register
 	 * before all others.
 	 */
 	cfg = RE_CPLUSCMD_PCI_MRW;
 	/*
 	 * XXX: For old 8169 set bit 14.
 	 *      For 8169S/8110S and above, do not set bit 14.
 	 */
 	if ((sc->sc_quirk & RTKQ_8169NONS) != 0)
 		cfg |= (0x1 << 14);
 	if ((sc->ethercom.ec_capenable & ETHERCAP_VLAN_HWTAGGING) != 0)
 		cfg |= RE_CPLUSCMD_VLANSTRIP;
 	if ((ifp->if_capenable & (IFCAP_CSUM_IPv4_Rx |
 	     IFCAP_CSUM_TCPv4_Rx | IFCAP_CSUM_UDPv4_Rx)) != 0)
 		cfg |= RE_CPLUSCMD_RXCSUM_ENB;
 	if ((sc->sc_quirk & RTKQ_MACSTAT) != 0) {
 		cfg |= RE_CPLUSCMD_MACSTAT_DIS;
 		cfg |= RE_CPLUSCMD_TXENB;
 	} else
 		cfg |= RE_CPLUSCMD_RXENB | RE_CPLUSCMD_TXENB;
 	CSR_WRITE_2(sc, RTK_CPLUS_CMD, cfg);
 	/* XXX: from Realtek-supplied Linux driver. Wholly undocumented. */
 	if ((sc->sc_quirk & RTKQ_8139CPLUS) == 0) {
 		if ((sc->sc_quirk & RTKQ_IM_HW) == 0) {
 			CSR_WRITE_2(sc, RTK_IM, 0x0000);
 		} else {
 			CSR_WRITE_2(sc, RTK_IM, 0x5151);
+		}
+	}
 	DELAY(10000);
 #ifdef RE_USE_EECMD
 	/*
 	 * Init our MAC address.  Even though the chipset
 	 * documentation doesn't mention it, we need to enter "Config
 	 * register write enable" mode to modify the ID registers.
 	 */
 	CSR_WRITE_1(sc, RTK_EECMD, RTK_EEMODE_WRITECFG);
 	enaddr = CLLADDR(ifp->if_sadl);
 	reg = enaddr[0] | (enaddr[1] << 8) |
 	    (enaddr[2] << 16) | (enaddr[3] << 24);
 	CSR_WRITE_4(sc, RTK_IDR0, reg);
 	reg = enaddr[4] | (enaddr[5] << 8);
 	CSR_WRITE_4(sc, RTK_IDR4, reg);
 	CSR_WRITE_1(sc, RTK_EECMD, RTK_EEMODE_OFF);
 #endif
 	/*
 	 * For C+ mode, initialize the RX descriptors and mbufs.
 	 */
 	re_rx_list_init(sc);
 	re_tx_list_init(sc);
 	/*
 	 * Load the addresses of the RX and TX lists into the chip.
 	 */
 	CSR_WRITE_4(sc, RTK_RXLIST_ADDR_HI,
 	    RE_ADDR_HI(sc->re_ldata.re_rx_list_map->dm_segs[0].ds_addr));
 	CSR_WRITE_4(sc, RTK_RXLIST_ADDR_LO,
 	    RE_ADDR_LO(sc->re_ldata.re_rx_list_map->dm_segs[0].ds_addr));
 	CSR_WRITE_4(sc, RTK_TXLIST_ADDR_HI,
 	    RE_ADDR_HI(sc->re_ldata.re_tx_list_map->dm_segs[0].ds_addr));
 	CSR_WRITE_4(sc, RTK_TXLIST_ADDR_LO,
 	    RE_ADDR_LO(sc->re_ldata.re_tx_list_map->dm_segs[0].ds_addr));
 	if (sc->sc_quirk & RTKQ_RXDV_GATED) {
 		CSR_WRITE_4(sc, RTK_MISC,
 		    CSR_READ_4(sc, RTK_MISC) & ~RTK_MISC_RXDV_GATED_EN);
+	}
 	/*
 	 * Enable transmit and receive.
 	 */
-	CSR_WRITE_1(sc, RTK_COMMAND, RTK_CMD_TX_ENB | RTK_CMD_RX_ENB);
+	if ((sc->sc_quirk & RTKQ_TXRXEN_LATER) == 0)
 		CSR_WRITE_1(sc, RTK_COMMAND, RTK_CMD_TX_ENB | RTK_CMD_RX_ENB);
 	/*
 	 * Set the initial TX and RX configuration.
 	 */
 	if (sc->re_testmode && (sc->sc_quirk & RTKQ_8169NONS) != 0) {
 		/* test mode is needed only for old 8169 */
 		CSR_WRITE_4(sc, RTK_TXCFG,
 		    RE_TXCFG_CONFIG | RTK_LOOPTEST_ON);
 	} else
 		CSR_WRITE_4(sc, RTK_TXCFG, RE_TXCFG_CONFIG);
 	CSR_WRITE_1(sc, RTK_EARLY_TX_THRESH, 16);
 	CSR_WRITE_4(sc, RTK_RXCFG, RE_RXCFG_CONFIG);
 	/* Set the individual bit to receive frames for this host only. */
 	rxcfg = CSR_READ_4(sc, RTK_RXCFG);
 	rxcfg |= RTK_RXCFG_RX_INDIV;
 	/* If we want promiscuous mode, set the allframes bit. */
 	if (ifp->if_flags & IFF_PROMISC)
 		rxcfg |= RTK_RXCFG_RX_ALLPHYS;
 	else
 		rxcfg &= ~RTK_RXCFG_RX_ALLPHYS;
 	CSR_WRITE_4(sc, RTK_RXCFG, rxcfg);
 	/*
 	 * Set capture broadcast bit to capture broadcast frames.
 	 */
 	if (ifp->if_flags & IFF_BROADCAST)
 		rxcfg |= RTK_RXCFG_RX_BROAD;
 	else
 		rxcfg &= ~RTK_RXCFG_RX_BROAD;
 	CSR_WRITE_4(sc, RTK_RXCFG, rxcfg);
 	/*
 	 * Program the multicast filter, if necessary.
 	 */
 	rtk_setmulti(sc);
 	/*
 	 * some chips require to enable TX/RX *AFTER* TX/RX configuration
 	 */
 	if ((sc->sc_quirk & RTKQ_TXRXEN_LATER) != 0)
 		CSR_WRITE_1(sc, RTK_COMMAND, RTK_CMD_TX_ENB | RTK_CMD_RX_ENB);
 	/*
 	 * Enable interrupts.
 	 */
 	if (sc->re_testmode)
 		CSR_WRITE_2(sc, RTK_IMR, 0);
 	else if ((sc->sc_quirk & RTKQ_IM_HW) != 0)
 		CSR_WRITE_2(sc, RTK_IMR, RTK_INTRS_IM_HW);
 	else
 		CSR_WRITE_2(sc, RTK_IMR, RTK_INTRS_CPLUS);
 	/* Start RX/TX process. */
 	CSR_WRITE_4(sc, RTK_MISSEDPKT, 0);
 #ifdef notdef
 	/* Enable receiver and transmitter. */
 	CSR_WRITE_1(sc, RTK_COMMAND, RTK_CMD_TX_ENB | RTK_CMD_RX_ENB);
 #endif
 	/*
 	 * Initialize the timer interrupt register so that
 	 * a timer interrupt will be generated once the timer
 	 * reaches a certain number of ticks. The timer is
 	 * reloaded on each transmit. This gives us TX interrupt
 	 * moderation, which dramatically improves TX frame rate.
 	 */
 	unsigned defer;		/* timer interval / ns */
 	unsigned period;	/* busclock period / ns */
 	/*
 	 * Maximum frame rate
 	 * 1500 byte PDU -> 81274 Hz
 	 *   46 byte PDU -> 1488096 Hz
+	 *
 	 * Deferring interrupts by up to 128us needs descriptors for
 	 * 1500 byte PDU -> 10.4 frames
 	 *   46 byte PDU -> 190.4 frames
+	 *
 	 */
 	defer = 128000;
 	if ((sc->sc_quirk & RTKQ_IM_HW) != 0) {
 		period = 1;
 		defer = 0;
 	} else if ((sc->sc_quirk & RTKQ_PCIE) != 0) {
 		period = 8;
 	} else {
 		switch (CSR_READ_1(sc, RTK_CFG2_BUSFREQ) & 0x7) {
 		case RTK_BUSFREQ_33MHZ:
 			period = 30;
 			break;
 		case RTK_BUSFREQ_66MHZ:
 			period = 15;
 			break;
 		default:
 			/* lowest possible clock */
 			period = 60;
 			break;
+		}
+	}
 	/* Timer Interrupt register address varies */
 	uint16_t re8139_reg;
 	if ((sc->sc_quirk & RTKQ_8139CPLUS) != 0)
 		re8139_reg = RTK_TIMERINT;
 	else
 		re8139_reg = RTK_TIMERINT_8169;
 	CSR_WRITE_4(sc, re8139_reg, defer / period);
 	if ((sc->sc_quirk & RTKQ_8139CPLUS) == 0) {
 		/*
 		 * For 8169 gigE NICs, set the max allowed RX packet
 		 * size so we can receive jumbo frames.
 		 */
 		CSR_WRITE_2(sc, RTK_MAXRXPKTLEN, 16383);
+	}
 	if (sc->re_testmode)
 		return 0;
 	CSR_WRITE_1(sc, RTK_CFG1, RTK_CFG1_DRVLOAD);
 	ifp->if_flags |= IFF_RUNNING;
 	ifp->if_flags &= ~IFF_OACTIVE;
 	callout_reset(&sc->rtk_tick_ch, hz, re_tick, sc);
  out:
 	if (error) {
 		ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE);
 		ifp->if_timer = 0;
 		printf("%s: interface not running\n",
 		    device_xname(sc->sc_dev));
+	}
 	return error;
+}
 static int
 re_ioctl(struct ifnet *ifp, u_long command, void *data)
+{
 	struct rtk_softc *sc = ifp->if_softc;
 	struct ifreq *ifr = data;
 	int s, error = 0;
 	s = splnet();
 	switch (command) {
 	case SIOCSIFMTU:
 		/*
 		 * Disable jumbo frames if it's not supported.
 		 */
 		if ((sc->sc_quirk & RTKQ_NOJUMBO) != 0 &&
 		    ifr->ifr_mtu > ETHERMTU) {
 			error = EINVAL;
 			break;
+		}
 		if (ifr->ifr_mtu < ETHERMIN || ifr->ifr_mtu > ETHERMTU_JUMBO)
 			error = EINVAL;
 		else if ((error = ifioctl_common(ifp, command, data)) ==
 		    ENETRESET)
 			error = 0;
 		break;
 	default:
 		if ((error = ether_ioctl(ifp, command, data)) != ENETRESET)
 			break;
 		error = 0;
 		if (command == SIOCSIFCAP)
 			error = (*ifp->if_init)(ifp);
 		else if (command != SIOCADDMULTI && command != SIOCDELMULTI)
+			;
 		else if (ifp->if_flags & IFF_RUNNING)
 			rtk_setmulti(sc);
 		break;
+	}
 	splx(s);
 	return error;
+}
 static void
 re_watchdog(struct ifnet *ifp)
+{
 	struct rtk_softc *sc;
 	int s;
 	sc = ifp->if_softc;
 	s = splnet();
 	printf("%s: watchdog timeout\n", device_xname(sc->sc_dev));
 	ifp->if_oerrors++;
 	re_txeof(sc);
 	re_rxeof(sc);
 	re_init(ifp);
 	splx(s);
+}
 /*
  * Stop the adapter and free any mbufs allocated to the
  * RX and TX lists.
  */
 static void
 re_stop(struct ifnet *ifp, int disable)
+{
 	int i;
 	struct rtk_softc *sc = ifp->if_softc;
 	callout_stop(&sc->rtk_tick_ch);
 	mii_down(&sc->mii);
 	if ((sc->sc_quirk & RTKQ_CMDSTOP) != 0)
 		CSR_WRITE_1(sc, RTK_COMMAND, RTK_CMD_STOPREQ | RTK_CMD_TX_ENB |
 		    RTK_CMD_RX_ENB);
 	else
 		CSR_WRITE_1(sc, RTK_COMMAND, 0x00);
 	DELAY(1000);
 	CSR_WRITE_2(sc, RTK_IMR, 0x0000);
 	CSR_WRITE_2(sc, RTK_ISR, 0xFFFF);
 	if (sc->re_head != NULL) {
 		m_freem(sc->re_head);
 		sc->re_head = sc->re_tail = NULL;
+	}
 	/* Free the TX list buffers. */
 	for (i = 0; i < RE_TX_QLEN; i++) {
 		if (sc->re_ldata.re_txq[i].txq_mbuf != NULL) {
 			bus_dmamap_unload(sc->sc_dmat,
 			    sc->re_ldata.re_txq[i].txq_dmamap);
 			m_freem(sc->re_ldata.re_txq[i].txq_mbuf);
 			sc->re_ldata.re_txq[i].txq_mbuf = NULL;
+		}
+	}
 	/* Free the RX list buffers. */
 	for (i = 0; i < RE_RX_DESC_CNT; i++) {
 		if (sc->re_ldata.re_rxsoft[i].rxs_mbuf != NULL) {
 			bus_dmamap_unload(sc->sc_dmat,
 			    sc->re_ldata.re_rxsoft[i].rxs_dmamap);
 			m_freem(sc->re_ldata.re_rxsoft[i].rxs_mbuf);
 			sc->re_ldata.re_rxsoft[i].rxs_mbuf = NULL;
+		}
+	}
 	if (disable)
 		re_disable(sc);
 	ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE);
 	ifp->if_timer = 0;
+}

 @@ -1,1515 +1,1515 @@
-/*	$NetBSD: rtl81x9.c,v 1.106 2019/05/28 07:41:48 msaitoh Exp $	*/
+/*	$NetBSD: rtl81x9.c,v 1.106.2.1 2020/01/28 11:12:30 martin Exp $	*/
 /*
  * Copyright (c) 1997, 1998
  *	Bill Paul <wpaul@ctr.columbia.edu>.  All rights reserved.
+ *
  * Redistribution and use in source and binary forms, with or without
  * modification, are permitted provided that the following conditions
  * are met:
  * 1. Redistributions of source code must retain the above copyright
  *    notice, this list of conditions and the following disclaimer.
  * 2. Redistributions in binary form must reproduce the above copyright
  *    notice, this list of conditions and the following disclaimer in the
  *    documentation and/or other materials provided with the distribution.
  * 3. All advertising materials mentioning features or use of this software
  *    must display the following acknowledgement:
  *	This product includes software developed by Bill Paul.
  * 4. Neither the name of the author nor the names of any co-contributors
  *    may be used to endorse or promote products derived from this software
  *    without specific prior written permission.
+ *
  * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND
  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
  * ARE DISCLAIMED.  IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD
  * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
  * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
  * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
  * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
  * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
  * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
  * THE POSSIBILITY OF SUCH DAMAGE.
+ *
  *	FreeBSD Id: if_rl.c,v 1.17 1999/06/19 20:17:37 wpaul Exp
  */
 /*
  * RealTek 8129/8139 PCI NIC driver
+ *
  * Supports several extremely cheap PCI 10/100 adapters based on
  * the RealTek chipset. Datasheets can be obtained from
  * www.realtek.com.tw.
+ *
  * Written by Bill Paul <wpaul@ctr.columbia.edu>
  * Electrical Engineering Department
  * Columbia University, New York City
  */
 /*
  * The RealTek 8139 PCI NIC redefines the meaning of 'low end.' This is
  * probably the worst PCI ethernet controller ever made, with the possible
  * exception of the FEAST chip made by SMC. The 8139 supports bus-master
  * DMA, but it has a terrible interface that nullifies any performance
  * gains that bus-master DMA usually offers.
+ *
  * For transmission, the chip offers a series of four TX descriptor
  * registers. Each transmit frame must be in a contiguous buffer, aligned
  * on a longword (32-bit) boundary. This means we almost always have to
  * do mbuf copies in order to transmit a frame, except in the unlikely
  * case where a) the packet fits into a single mbuf, and b) the packet
  * is 32-bit aligned within the mbuf's data area. The presence of only
  * four descriptor registers means that we can never have more than four
  * packets queued for transmission at any one time.
+ *
  * Reception is not much better. The driver has to allocate a single large
  * buffer area (up to 64K in size) into which the chip will DMA received
  * frames. Because we don't know where within this region received packets
  * will begin or end, we have no choice but to copy data from the buffer
  * area into mbufs in order to pass the packets up to the higher protocol
  * levels.
+ *
  * It's impossible given this rotten design to really achieve decent
  * performance at 100Mbps, unless you happen to have a 400MHz PII or
  * some equally overmuscled CPU to drive it.
+ *
  * On the bright side, the 8139 does have a built-in PHY, although
  * rather than using an MDIO serial interface like most other NICs, the
  * PHY registers are directly accessible through the 8139's register
  * space. The 8139 supports autonegotiation, as well as a 64-bit multicast
  * filter.
+ *
  * The 8129 chip is an older version of the 8139 that uses an external PHY
  * chip. The 8129 has a serial MDIO interface for accessing the MII where
  * the 8139 lets you directly access the on-board PHY registers. We need
  * to select which interface to use depending on the chip type.
  */
 #include <sys/cdefs.h>
-__KERNEL_RCSID(0, "$NetBSD: rtl81x9.c,v 1.106 2019/05/28 07:41:48 msaitoh Exp $");
+__KERNEL_RCSID(0, "$NetBSD: rtl81x9.c,v 1.106.2.1 2020/01/28 11:12:30 martin Exp $");
 #include <sys/param.h>
 #include <sys/systm.h>
 #include <sys/callout.h>
 #include <sys/device.h>
 #include <sys/sockio.h>
 #include <sys/mbuf.h>
 #include <sys/malloc.h>
 #include <sys/kernel.h>
 #include <sys/socket.h>
 #include <net/if.h>
 #include <net/if_arp.h>
 #include <net/if_ether.h>
 #include <net/if_dl.h>
 #include <net/if_media.h>
 #include <net/bpf.h>
 #include <sys/rndsource.h>
 #include <sys/bus.h>
 #include <machine/endian.h>
 #include <dev/mii/mii.h>
 #include <dev/mii/miivar.h>
 #include <dev/ic/rtl81x9reg.h>
 #include <dev/ic/rtl81x9var.h>
 static void rtk_reset(struct rtk_softc *);
 static void rtk_rxeof(struct rtk_softc *);
 static void rtk_txeof(struct rtk_softc *);
 static void rtk_start(struct ifnet *);
 static int rtk_ioctl(struct ifnet *, u_long, void *);
 static int rtk_init(struct ifnet *);
 static void rtk_stop(struct ifnet *, int);
 static void rtk_watchdog(struct ifnet *);
 static void rtk_eeprom_putbyte(struct rtk_softc *, int, int);
 static void rtk_mii_sync(struct rtk_softc *);
 static void rtk_mii_send(struct rtk_softc *, uint32_t, int);
 static int rtk_mii_readreg(struct rtk_softc *, struct rtk_mii_frame *);
 static int rtk_mii_writereg(struct rtk_softc *, struct rtk_mii_frame *);
 static int rtk_phy_readreg(device_t, int, int, uint16_t *);
 static int rtk_phy_writereg(device_t, int, int, uint16_t);
 static void rtk_phy_statchg(struct ifnet *);
 static void rtk_tick(void *);
 static int rtk_enable(struct rtk_softc *);
 static void rtk_disable(struct rtk_softc *);
 static void rtk_list_tx_init(struct rtk_softc *);
 #define EE_SET(x)					\
 	CSR_WRITE_1(sc, RTK_EECMD,			\
 		CSR_READ_1(sc, RTK_EECMD) | (x))
 #define EE_CLR(x)					\
 	CSR_WRITE_1(sc, RTK_EECMD,			\
 		CSR_READ_1(sc, RTK_EECMD) & ~(x))
 #define EE_DELAY()	DELAY(100)
 #define ETHER_PAD_LEN (ETHER_MIN_LEN - ETHER_CRC_LEN)
 /*
  * Send a read command and address to the EEPROM, check for ACK.
  */
 static void
 rtk_eeprom_putbyte(struct rtk_softc *sc, int addr, int addr_len)
+{
 	int d, i;
 	d = (RTK_EECMD_READ << addr_len) | addr;
 	/*
 	 * Feed in each bit and stobe the clock.
 	 */
 	for (i = RTK_EECMD_LEN + addr_len; i > 0; i--) {
 		if (d & (1 << (i - 1))) {
 			EE_SET(RTK_EE_DATAIN);
 		} else {
 			EE_CLR(RTK_EE_DATAIN);
+		}
 		EE_DELAY();
 		EE_SET(RTK_EE_CLK);
 		EE_DELAY();
 		EE_CLR(RTK_EE_CLK);
 		EE_DELAY();
+	}
+}
 /*
  * Read a word of data stored in the EEPROM at address 'addr.'
  */
 uint16_t
 rtk_read_eeprom(struct rtk_softc *sc, int addr, int addr_len)
+{
 	uint16_t word;
 	int i;
 	/* Enter EEPROM access mode. */
 	CSR_WRITE_1(sc, RTK_EECMD, RTK_EEMODE_PROGRAM);
 	EE_DELAY();
 	EE_SET(RTK_EE_SEL);
 	/*
 	 * Send address of word we want to read.
 	 */
 	rtk_eeprom_putbyte(sc, addr, addr_len);
 	/*
 	 * Start reading bits from EEPROM.
 	 */
 	word = 0;
 	for (i = 16; i > 0; i--) {
 		EE_SET(RTK_EE_CLK);
 		EE_DELAY();
 		if (CSR_READ_1(sc, RTK_EECMD) & RTK_EE_DATAOUT)
 			word |= 1 << (i - 1);
 		EE_CLR(RTK_EE_CLK);
 		EE_DELAY();
+	}
 	/* Turn off EEPROM access mode. */
 	CSR_WRITE_1(sc, RTK_EECMD, RTK_EEMODE_OFF);
 	return word;
+}
 /*
  * MII access routines are provided for the 8129, which
  * doesn't have a built-in PHY. For the 8139, we fake things
  * up by diverting rtk_phy_readreg()/rtk_phy_writereg() to the
  * direct access PHY registers.
  */
 #define MII_SET(x)					\
 	CSR_WRITE_1(sc, RTK_MII,			\
 		CSR_READ_1(sc, RTK_MII) | (x))
 #define MII_CLR(x)					\
 	CSR_WRITE_1(sc, RTK_MII,			\
 		CSR_READ_1(sc, RTK_MII) & ~(x))
 /*
  * Sync the PHYs by setting data bit and strobing the clock 32 times.
  */
 static void
 rtk_mii_sync(struct rtk_softc *sc)
+{
 	int i;
 	MII_SET(RTK_MII_DIR | RTK_MII_DATAOUT);
 	for (i = 0; i < 32; i++) {
 		MII_SET(RTK_MII_CLK);
 		DELAY(1);
 		MII_CLR(RTK_MII_CLK);
 		DELAY(1);
+	}
+}
 /*
  * Clock a series of bits through the MII.
  */
 static void
 rtk_mii_send(struct rtk_softc *sc, uint32_t bits, int cnt)
+{
 	int i;
 	MII_CLR(RTK_MII_CLK);
 	for (i = cnt; i > 0; i--) {
 		if (bits & (1 << (i - 1))) {
 			MII_SET(RTK_MII_DATAOUT);
 		} else {
 			MII_CLR(RTK_MII_DATAOUT);
+		}
 		DELAY(1);
 		MII_CLR(RTK_MII_CLK);
 		DELAY(1);
 		MII_SET(RTK_MII_CLK);
+	}
+}
 /*
  * Read an PHY register through the MII.
  */
 static int
 rtk_mii_readreg(struct rtk_softc *sc, struct rtk_mii_frame *frame)
+{
 	int i, ack, s, rv = 0;
 	s = splnet();
 	/*
 	 * Set up frame for RX.
 	 */
 	frame->mii_stdelim = RTK_MII_STARTDELIM;
 	frame->mii_opcode = RTK_MII_READOP;
 	frame->mii_turnaround = 0;
 	frame->mii_data = 0;
 	CSR_WRITE_2(sc, RTK_MII, 0);
 	/*
 	 * Turn on data xmit.
 	 */
 	MII_SET(RTK_MII_DIR);
 	rtk_mii_sync(sc);
 	/*
 	 * Send command/address info.
 	 */
 	rtk_mii_send(sc, frame->mii_stdelim, 2);
 	rtk_mii_send(sc, frame->mii_opcode, 2);
 	rtk_mii_send(sc, frame->mii_phyaddr, 5);
 	rtk_mii_send(sc, frame->mii_regaddr, 5);
 	/* Idle bit */
 	MII_CLR((RTK_MII_CLK | RTK_MII_DATAOUT));
 	DELAY(1);
 	MII_SET(RTK_MII_CLK);
 	DELAY(1);
 	/* Turn off xmit. */
 	MII_CLR(RTK_MII_DIR);
 	/* Check for ack */
 	MII_CLR(RTK_MII_CLK);
 	DELAY(1);
 	ack = CSR_READ_2(sc, RTK_MII) & RTK_MII_DATAIN;
 	MII_SET(RTK_MII_CLK);
 	DELAY(1);
 	/*
 	 * Now try reading data bits. If the ack failed, we still
 	 * need to clock through 16 cycles to keep the PHY(s) in sync.
 	 */
 	if (ack) {
 		for (i = 0; i < 16; i++) {
 			MII_CLR(RTK_MII_CLK);
 			DELAY(1);
 			MII_SET(RTK_MII_CLK);
 			DELAY(1);
+		}
 		rv = -1;
 		goto fail;
+	}
 	for (i = 16; i > 0; i--) {
 		MII_CLR(RTK_MII_CLK);
 		DELAY(1);
 		if (!ack) {
 			if (CSR_READ_2(sc, RTK_MII) & RTK_MII_DATAIN)
 				frame->mii_data |= 1 << (i - 1);
 			DELAY(1);
+		}
 		MII_SET(RTK_MII_CLK);
 		DELAY(1);
+	}
  fail:
 	MII_CLR(RTK_MII_CLK);
 	DELAY(1);
 	MII_SET(RTK_MII_CLK);
 	DELAY(1);
 	splx(s);
 	return rv;
+}
 /*
  * Write to a PHY register through the MII.
  */
 static int
 rtk_mii_writereg(struct rtk_softc *sc, struct rtk_mii_frame *frame)
+{
 	int s;
 	s = splnet();
 	/*
 	 * Set up frame for TX.
 	 */
 	frame->mii_stdelim = RTK_MII_STARTDELIM;
 	frame->mii_opcode = RTK_MII_WRITEOP;
 	frame->mii_turnaround = RTK_MII_TURNAROUND;
 	/*
 	 * Turn on data output.
 	 */
 	MII_SET(RTK_MII_DIR);
 	rtk_mii_sync(sc);
 	rtk_mii_send(sc, frame->mii_stdelim, 2);
 	rtk_mii_send(sc, frame->mii_opcode, 2);
 	rtk_mii_send(sc, frame->mii_phyaddr, 5);
 	rtk_mii_send(sc, frame->mii_regaddr, 5);
 	rtk_mii_send(sc, frame->mii_turnaround, 2);
 	rtk_mii_send(sc, frame->mii_data, 16);
 	/* Idle bit. */
 	MII_SET(RTK_MII_CLK);
 	DELAY(1);
 	MII_CLR(RTK_MII_CLK);
 	DELAY(1);
 	/*
 	 * Turn off xmit.
 	 */
 	MII_CLR(RTK_MII_DIR);
 	splx(s);
 	return 0;
+}
 static int
 rtk_phy_readreg(device_t self, int phy, int reg, uint16_t *val)
+{
 	struct rtk_softc *sc = device_private(self);
 	struct rtk_mii_frame frame;
 	int rv;
 	int rtk8139_reg;
 	if ((sc->sc_quirk & RTKQ_8129) == 0) {
 		if (phy != 7)
 			return -1;
 		switch (reg) {
 		case MII_BMCR:
 			rtk8139_reg = RTK_BMCR;
 			break;
 		case MII_BMSR:
 			rtk8139_reg = RTK_BMSR;
 			break;
 		case MII_ANAR:
 			rtk8139_reg = RTK_ANAR;
 			break;
 		case MII_ANER:
 			rtk8139_reg = RTK_ANER;
 			break;
 		case MII_ANLPAR:
 			rtk8139_reg = RTK_LPAR;
 			break;
 		case MII_PHYIDR1:
 		case MII_PHYIDR2:
 			*val = 0;
 			return 0;
 		default:
 #if 0
 			printf("%s: bad phy register\n", device_xname(self));
 #endif
 			return -1;
+		}
 		*val = CSR_READ_2(sc, rtk8139_reg);
 		return 0;
+	}
 	memset(&frame, 0, sizeof(frame));
 	frame.mii_phyaddr = phy;
 	frame.mii_regaddr = reg;
 	rv = rtk_mii_readreg(sc, &frame);
 	*val = frame.mii_data;
 	return rv;
+}
 static int
 rtk_phy_writereg(device_t self, int phy, int reg, uint16_t val)
+{
 	struct rtk_softc *sc = device_private(self);
 	struct rtk_mii_frame frame;
 	int rtk8139_reg;
 	if ((sc->sc_quirk & RTKQ_8129) == 0) {
 		if (phy != 7)
 			return -1;
 		switch (reg) {
 		case MII_BMCR:
 			rtk8139_reg = RTK_BMCR;
 			break;
 		case MII_BMSR:
 			rtk8139_reg = RTK_BMSR;
 			break;
 		case MII_ANAR:
 			rtk8139_reg = RTK_ANAR;
 			break;
 		case MII_ANER:
 			rtk8139_reg = RTK_ANER;
 			break;
 		case MII_ANLPAR:
 			rtk8139_reg = RTK_LPAR;
 			break;
 		default:
 #if 0
 			printf("%s: bad phy register\n", device_xname(self));
 #endif
 			return -1;
+		}
 		CSR_WRITE_2(sc, rtk8139_reg, val);
 		return 0;
+	}
 	memset(&frame, 0, sizeof(frame));
 	frame.mii_phyaddr = phy;
 	frame.mii_regaddr = reg;
 	frame.mii_data = val;
 	return rtk_mii_writereg(sc, &frame);
+}
 static void
 rtk_phy_statchg(struct ifnet *ifp)
+{
 	/* Nothing to do. */
+}
 #define	rtk_calchash(addr) \
 	(ether_crc32_be((addr), ETHER_ADDR_LEN) >> 26)
 /*
  * Program the 64-bit multicast hash filter.
  */
 void
 rtk_setmulti(struct rtk_softc *sc)
+{
 	struct ethercom *ec = &sc->ethercom;
 	struct ifnet *ifp = &ec->ec_if;
 	uint32_t hashes[2] = { 0, 0 };
 	uint32_t rxfilt;
 	struct ether_multi *enm;
 	struct ether_multistep step;
 	int h, mcnt;
 	rxfilt = CSR_READ_4(sc, RTK_RXCFG);
 	if (ifp->if_flags & IFF_PROMISC) {
  allmulti:
 		ifp->if_flags |= IFF_ALLMULTI;
 		rxfilt |= RTK_RXCFG_RX_MULTI;
 		CSR_WRITE_4(sc, RTK_RXCFG, rxfilt);
 		CSR_WRITE_4(sc, RTK_MAR0, 0xFFFFFFFF);
 		CSR_WRITE_4(sc, RTK_MAR4, 0xFFFFFFFF);
 		return;
+	}
 	/* first, zot all the existing hash bits */
 	CSR_WRITE_4(sc, RTK_MAR0, 0);
 	CSR_WRITE_4(sc, RTK_MAR4, 0);
 	/* now program new ones */
 	ETHER_LOCK(ec);
 	ETHER_FIRST_MULTI(step, ec, enm);
 	mcnt = 0;
 	while (enm != NULL) {
 		if (memcmp(enm->enm_addrlo, enm->enm_addrhi,
 		    ETHER_ADDR_LEN) != 0) {
 			ETHER_UNLOCK(ec);
 			goto allmulti;
+		}
 		h = rtk_calchash(enm->enm_addrlo);
 		if (h < 32)
-			hashes[0] |= (1 << h);
+			hashes[0] |= __BIT(h);
 		else
-			hashes[1] |= (1 << (h - 32));
+			hashes[1] |= __BIT(h - 32);
 		mcnt++;
 		ETHER_NEXT_MULTI(step, enm);
+	}
 	ETHER_UNLOCK(ec);
 	ifp->if_flags &= ~IFF_ALLMULTI;
 	if (mcnt)
 		rxfilt |= RTK_RXCFG_RX_MULTI;
 	else
 		rxfilt &= ~RTK_RXCFG_RX_MULTI;
 	CSR_WRITE_4(sc, RTK_RXCFG, rxfilt);
 	/*
 	 * For some unfathomable reason, RealTek decided to reverse
 	 * the order of the multicast hash registers in the PCI Express
 	 * parts. This means we have to write the hash pattern in reverse
 	 * order for those devices.
 	 */
 	if ((sc->sc_quirk & RTKQ_PCIE) != 0) {
 		CSR_WRITE_4(sc, RTK_MAR0, bswap32(hashes[1]));
 		CSR_WRITE_4(sc, RTK_MAR4, bswap32(hashes[0]));
 	} else {
 		CSR_WRITE_4(sc, RTK_MAR0, hashes[0]);
 		CSR_WRITE_4(sc, RTK_MAR4, hashes[1]);
+	}
+}
 void
 rtk_reset(struct rtk_softc *sc)
+{
 	int i;
 	CSR_WRITE_1(sc, RTK_COMMAND, RTK_CMD_RESET);
 	for (i = 0; i < RTK_TIMEOUT; i++) {
 		DELAY(10);
 		if ((CSR_READ_1(sc, RTK_COMMAND) & RTK_CMD_RESET) == 0)
 			break;
+	}
 	if (i == RTK_TIMEOUT)
 		printf("%s: reset never completed!\n",
 		    device_xname(sc->sc_dev));
+}
 /*
  * Attach the interface. Allocate softc structures, do ifmedia
  * setup and ethernet/BPF attach.
  */
 void
 rtk_attach(struct rtk_softc *sc)
+{
 	device_t self = sc->sc_dev;
 	struct ifnet *ifp;
 	struct mii_data * const mii = &sc->mii;
 	struct rtk_tx_desc *txd;
 	uint16_t val;
 	uint8_t eaddr[ETHER_ADDR_LEN];
 	int error;
 	int i, addr_len;
 	callout_init(&sc->rtk_tick_ch, 0);
 	/*
 	 * Check EEPROM type 9346 or 9356.
 	 */
 	if (rtk_read_eeprom(sc, RTK_EE_ID, RTK_EEADDR_LEN1) == 0x8129)
 		addr_len = RTK_EEADDR_LEN1;
 	else
 		addr_len = RTK_EEADDR_LEN0;
 	/*
 	 * Get station address.
 	 */
 	val = rtk_read_eeprom(sc, RTK_EE_EADDR0, addr_len);
 	eaddr[0] = val & 0xff;
 	eaddr[1] = val >> 8;
 	val = rtk_read_eeprom(sc, RTK_EE_EADDR1, addr_len);
 	eaddr[2] = val & 0xff;
 	eaddr[3] = val >> 8;
 	val = rtk_read_eeprom(sc, RTK_EE_EADDR2, addr_len);
 	eaddr[4] = val & 0xff;
 	eaddr[5] = val >> 8;
 	if ((error = bus_dmamem_alloc(sc->sc_dmat,
 	    RTK_RXBUFLEN + 16, PAGE_SIZE, 0, &sc->sc_dmaseg, 1, &sc->sc_dmanseg,
 	    BUS_DMA_NOWAIT)) != 0) {
 		aprint_error_dev(self,
 		    "can't allocate recv buffer, error = %d\n", error);
 		goto fail_0;
+	}
 	if ((error = bus_dmamem_map(sc->sc_dmat, &sc->sc_dmaseg, sc->sc_dmanseg,
 	    RTK_RXBUFLEN + 16, (void **)&sc->rtk_rx_buf,
 	    BUS_DMA_NOWAIT | BUS_DMA_COHERENT)) != 0) {
 		aprint_error_dev(self,
 		    "can't map recv buffer, error = %d\n", error);
 		goto fail_1;
+	}
 	if ((error = bus_dmamap_create(sc->sc_dmat,
 	    RTK_RXBUFLEN + 16, 1, RTK_RXBUFLEN + 16, 0, BUS_DMA_NOWAIT,
 	    &sc->recv_dmamap)) != 0) {
 		aprint_error_dev(self,
 		    "can't create recv buffer DMA map, error = %d\n", error);
 		goto fail_2;
+	}
 	if ((error = bus_dmamap_load(sc->sc_dmat, sc->recv_dmamap,
 	    sc->rtk_rx_buf, RTK_RXBUFLEN + 16,
 	    NULL, BUS_DMA_READ | BUS_DMA_NOWAIT)) != 0) {
 		aprint_error_dev(self,
 		    "can't load recv buffer DMA map, error = %d\n", error);
 		goto fail_3;
+	}
 	for (i = 0; i < RTK_TX_LIST_CNT; i++) {
 		txd = &sc->rtk_tx_descs[i];
 		if ((error = bus_dmamap_create(sc->sc_dmat,
 		    MCLBYTES, 1, MCLBYTES, 0, BUS_DMA_NOWAIT,
 		    &txd->txd_dmamap)) != 0) {
 			aprint_error_dev(self,
 			    "can't create snd buffer DMA map, error = %d\n",
 			    error);
 			goto fail_4;
+		}
 		txd->txd_txaddr = RTK_TXADDR0 + (i * 4);
 		txd->txd_txstat = RTK_TXSTAT0 + (i * 4);
+	}
 	SIMPLEQ_INIT(&sc->rtk_tx_free);
 	SIMPLEQ_INIT(&sc->rtk_tx_dirty);
 	/*
 	 * From this point forward, the attachment cannot fail. A failure
 	 * before this releases all resources thar may have been
 	 * allocated.
 	 */
 	sc->sc_flags |= RTK_ATTACHED;
 	/* Reset the adapter. */
 	rtk_reset(sc);
 	aprint_normal_dev(self, "Ethernet address %s\n", ether_sprintf(eaddr));
 	ifp = &sc->ethercom.ec_if;
 	ifp->if_softc = sc;
 	strcpy(ifp->if_xname, device_xname(self));
 	ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST;
 	ifp->if_ioctl = rtk_ioctl;
 	ifp->if_start = rtk_start;
 	ifp->if_watchdog = rtk_watchdog;
 	ifp->if_init = rtk_init;
 	ifp->if_stop = rtk_stop;
 	IFQ_SET_READY(&ifp->if_snd);
 	/*
 	 * Do ifmedia setup.
 	 */
 	mii->mii_ifp = ifp;
 	mii->mii_readreg = rtk_phy_readreg;
 	mii->mii_writereg = rtk_phy_writereg;
 	mii->mii_statchg = rtk_phy_statchg;
 	sc->ethercom.ec_mii = mii;
 	ifmedia_init(&mii->mii_media, IFM_IMASK, ether_mediachange,
 	    ether_mediastatus);
 	mii_attach(self, mii, 0xffffffff, MII_PHY_ANY, MII_OFFSET_ANY, 0);
 	/* Choose a default media. */
 	if (LIST_FIRST(&mii->mii_phys) == NULL) {
 		ifmedia_add(&mii->mii_media, IFM_ETHER | IFM_NONE, 0, NULL);
 		ifmedia_set(&mii->mii_media, IFM_ETHER | IFM_NONE);
 	} else
 		ifmedia_set(&mii->mii_media, IFM_ETHER | IFM_AUTO);
 	/*
 	 * Call MI attach routines.
 	 */
 	if_attach(ifp);
 	if_deferred_start_init(ifp, NULL);
 	ether_ifattach(ifp, eaddr);
 	rnd_attach_source(&sc->rnd_source, device_xname(self),
 	    RND_TYPE_NET, RND_FLAG_DEFAULT);
 	return;
  fail_4:
 	for (i = 0; i < RTK_TX_LIST_CNT; i++) {
 		txd = &sc->rtk_tx_descs[i];
 		if (txd->txd_dmamap != NULL)
 			bus_dmamap_destroy(sc->sc_dmat, txd->txd_dmamap);
+	}
  fail_3:
 	bus_dmamap_destroy(sc->sc_dmat, sc->recv_dmamap);
  fail_2:
 	bus_dmamem_unmap(sc->sc_dmat, sc->rtk_rx_buf,
 	    RTK_RXBUFLEN + 16);
  fail_1:
 	bus_dmamem_free(sc->sc_dmat, &sc->sc_dmaseg, sc->sc_dmanseg);
  fail_0:
 	return;
+}
 /*
  * Initialize the transmit descriptors.
  */
 static void
 rtk_list_tx_init(struct rtk_softc *sc)
+{
 	struct rtk_tx_desc *txd;
 	int i;
 	while ((txd = SIMPLEQ_FIRST(&sc->rtk_tx_dirty)) != NULL)
 		SIMPLEQ_REMOVE_HEAD(&sc->rtk_tx_dirty, txd_q);
 	while ((txd = SIMPLEQ_FIRST(&sc->rtk_tx_free)) != NULL)
 		SIMPLEQ_REMOVE_HEAD(&sc->rtk_tx_free, txd_q);
 	for (i = 0; i < RTK_TX_LIST_CNT; i++) {
 		txd = &sc->rtk_tx_descs[i];
 		CSR_WRITE_4(sc, txd->txd_txaddr, 0);
 		SIMPLEQ_INSERT_TAIL(&sc->rtk_tx_free, txd, txd_q);
+	}
+}
 /*
  * rtk_activate:
  *     Handle device activation/deactivation requests.
  */
 int
 rtk_activate(device_t self, enum devact act)
+{
 	struct rtk_softc *sc = device_private(self);
 	switch (act) {
 	case DVACT_DEACTIVATE:
 		if_deactivate(&sc->ethercom.ec_if);
 		return 0;
 	default:
 		return EOPNOTSUPP;
+	}
+}
 /*
  * rtk_detach:
  *     Detach a rtk interface.
  */
 int
 rtk_detach(struct rtk_softc *sc)
+{
 	struct ifnet *ifp = &sc->ethercom.ec_if;
 	struct rtk_tx_desc *txd;
 	int i;
 	/*
 	 * Succeed now if there isn't any work to do.
 	 */
 	if ((sc->sc_flags & RTK_ATTACHED) == 0)
 		return 0;
 	/* Unhook our tick handler. */
 	callout_stop(&sc->rtk_tick_ch);
 	/* Detach all PHYs. */
 	mii_detach(&sc->mii, MII_PHY_ANY, MII_OFFSET_ANY);
 	/* Delete all remaining media. */
 	ifmedia_delete_instance(&sc->mii.mii_media, IFM_INST_ANY);
 	rnd_detach_source(&sc->rnd_source);
 	ether_ifdetach(ifp);
 	if_detach(ifp);
 	for (i = 0; i < RTK_TX_LIST_CNT; i++) {
 		txd = &sc->rtk_tx_descs[i];
 		if (txd->txd_dmamap != NULL)
 			bus_dmamap_destroy(sc->sc_dmat, txd->txd_dmamap);
+	}
 	bus_dmamap_destroy(sc->sc_dmat, sc->recv_dmamap);
 	bus_dmamem_unmap(sc->sc_dmat, sc->rtk_rx_buf,
 	    RTK_RXBUFLEN + 16);
 	bus_dmamem_free(sc->sc_dmat, &sc->sc_dmaseg, sc->sc_dmanseg);
 	/* we don't want to run again */
 	sc->sc_flags &= ~RTK_ATTACHED;
 	return 0;
+}
 /*
  * rtk_enable:
  *     Enable the RTL81X9 chip.
  */
 int
 rtk_enable(struct rtk_softc *sc)
+{
 	if (RTK_IS_ENABLED(sc) == 0 && sc->sc_enable != NULL) {
 		if ((*sc->sc_enable)(sc) != 0) {
 			printf("%s: device enable failed\n",
 			    device_xname(sc->sc_dev));
 			return EIO;
+		}
 		sc->sc_flags |= RTK_ENABLED;
+	}
 	return 0;
+}
 /*
  * rtk_disable:
  *     Disable the RTL81X9 chip.
  */
 void
 rtk_disable(struct rtk_softc *sc)
+{
 	if (RTK_IS_ENABLED(sc) && sc->sc_disable != NULL) {
 		(*sc->sc_disable)(sc);
 		sc->sc_flags &= ~RTK_ENABLED;
+	}
+}
 /*
  * A frame has been uploaded: pass the resulting mbuf chain up to
  * the higher level protocols.
+ *
  * You know there's something wrong with a PCI bus-master chip design.
+ *
  * The receive operation is badly documented in the datasheet, so I'll
  * attempt to document it here. The driver provides a buffer area and
  * places its base address in the RX buffer start address register.
  * The chip then begins copying frames into the RX buffer. Each frame
  * is preceded by a 32-bit RX status word which specifies the length
  * of the frame and certain other status bits. Each frame (starting with
  * the status word) is also 32-bit aligned. The frame length is in the
  * first 16 bits of the status word; the lower 15 bits correspond with
  * the 'rx status register' mentioned in the datasheet.
+ *
  * Note: to make the Alpha happy, the frame payload needs to be aligned
  * on a 32-bit boundary. To achieve this, we copy the data to mbuf
  * shifted forward 2 bytes.
  */
 static void
 rtk_rxeof(struct rtk_softc *sc)
+{
 	struct mbuf *m;
 	struct ifnet *ifp;
 	uint8_t *rxbufpos, *dst;
 	u_int total_len, wrap;
 	uint32_t rxstat;
 	uint16_t cur_rx, new_rx;
 	uint16_t limit;
 	uint16_t rx_bytes, max_bytes;
 	ifp = &sc->ethercom.ec_if;
 	cur_rx = (CSR_READ_2(sc, RTK_CURRXADDR) + 16) % RTK_RXBUFLEN;
 	/* Do not try to read past this point. */
 	limit = CSR_READ_2(sc, RTK_CURRXBUF) % RTK_RXBUFLEN;
 	if (limit < cur_rx)
 		max_bytes = (RTK_RXBUFLEN - cur_rx) + limit;
 	else
 		max_bytes = limit - cur_rx;
 	rx_bytes = 0;
 	while ((CSR_READ_1(sc, RTK_COMMAND) & RTK_CMD_EMPTY_RXBUF) == 0) {
 		rxbufpos = sc->rtk_rx_buf + cur_rx;
 		bus_dmamap_sync(sc->sc_dmat, sc->recv_dmamap, cur_rx,
 		    RTK_RXSTAT_LEN, BUS_DMASYNC_POSTREAD);
 		rxstat = le32toh(*(uint32_t *)rxbufpos);
 		bus_dmamap_sync(sc->sc_dmat, sc->recv_dmamap, cur_rx,
 		    RTK_RXSTAT_LEN, BUS_DMASYNC_PREREAD);
 		/*
 		 * Here's a totally undocumented fact for you. When the
 		 * RealTek chip is in the process of copying a packet into
 		 * RAM for you, the length will be 0xfff0. If you spot a
 		 * packet header with this value, you need to stop. The
 		 * datasheet makes absolutely no mention of this and
 		 * RealTek should be shot for this.
 		 */
 		total_len = rxstat >> 16;
 		if (total_len == RTK_RXSTAT_UNFINISHED)
 			break;
 		if ((rxstat & RTK_RXSTAT_RXOK) == 0 ||
 		    total_len < ETHER_MIN_LEN ||
 		    total_len > (MCLBYTES - RTK_ETHER_ALIGN)) {
 			ifp->if_ierrors++;
 			/*
 			 * submitted by:[netbsd-pcmcia:00484]
 			 *	Takahiro Kambe <taca@sky.yamashina.kyoto.jp>
 			 * obtain from:
 			 *     FreeBSD if_rl.c rev 1.24->1.25
+			 *
 			 */
 #if 0
 			if (rxstat & (RTK_RXSTAT_BADSYM | RTK_RXSTAT_RUNT |
 			    RTK_RXSTAT_GIANT | RTK_RXSTAT_CRCERR |
 			    RTK_RXSTAT_ALIGNERR)) {
 				CSR_WRITE_2(sc, RTK_COMMAND, RTK_CMD_TX_ENB);
 				CSR_WRITE_2(sc, RTK_COMMAND,
 				    RTK_CMD_TX_ENB | RTK_CMD_RX_ENB);
 				CSR_WRITE_4(sc, RTK_RXCFG, RTK_RXCFG_CONFIG);
 				CSR_WRITE_4(sc, RTK_RXADDR,
 				    sc->recv_dmamap->dm_segs[0].ds_addr);
 				cur_rx = 0;
+			}
 			break;
 #else
 			rtk_init(ifp);
 			return;
 #endif
+		}
 		/* No errors; receive the packet. */
 		rx_bytes += total_len + RTK_RXSTAT_LEN;
 		/*
 		 * Avoid trying to read more bytes than we know
 		 * the chip has prepared for us.
 		 */
 		if (rx_bytes > max_bytes)
 			break;
 		/*
 		 * Skip the status word, wrapping around to the beginning
 		 * of the Rx area, if necessary.
 		 */
 		cur_rx = (cur_rx + RTK_RXSTAT_LEN) % RTK_RXBUFLEN;
 		rxbufpos = sc->rtk_rx_buf + cur_rx;
 		/*
 		 * Compute the number of bytes at which the packet
 		 * will wrap to the beginning of the ring buffer.
 		 */
 		wrap = RTK_RXBUFLEN - cur_rx;
 		/*
 		 * Compute where the next pending packet is.
 		 */
 		if (total_len > wrap)
 			new_rx = total_len - wrap;
 		else
 			new_rx = cur_rx + total_len;
 		/* Round up to 32-bit boundary. */
 		new_rx = roundup2(new_rx, sizeof(uint32_t)) % RTK_RXBUFLEN;
 		/*
 		 * The RealTek chip includes the CRC with every
 		 * incoming packet; trim it off here.
 		 */
 		total_len -= ETHER_CRC_LEN;
 		/*
 		 * Now allocate an mbuf (and possibly a cluster) to hold
 		 * the packet. Note we offset the packet 2 bytes so that
 		 * data after the Ethernet header will be 4-byte aligned.
 		 */
 		MGETHDR(m, M_DONTWAIT, MT_DATA);
 		if (m == NULL) {
 			printf("%s: unable to allocate Rx mbuf\n",
 			    device_xname(sc->sc_dev));
 			ifp->if_ierrors++;
 			goto next_packet;
+		}
 		if (total_len > (MHLEN - RTK_ETHER_ALIGN)) {
 			MCLGET(m, M_DONTWAIT);
 			if ((m->m_flags & M_EXT) == 0) {
 				printf("%s: unable to allocate Rx cluster\n",
 				    device_xname(sc->sc_dev));
 				ifp->if_ierrors++;
 				m_freem(m);
 				m = NULL;
 				goto next_packet;
+			}
+		}
 		m->m_data += RTK_ETHER_ALIGN;	/* for alignment */
 		m_set_rcvif(m, ifp);
 		m->m_pkthdr.len = m->m_len = total_len;
 		dst = mtod(m, void *);
 		/*
 		 * If the packet wraps, copy up to the wrapping point.
 		 */
 		if (total_len > wrap) {
 			bus_dmamap_sync(sc->sc_dmat, sc->recv_dmamap,
 			    cur_rx, wrap, BUS_DMASYNC_POSTREAD);
 			memcpy(dst, rxbufpos, wrap);
 			bus_dmamap_sync(sc->sc_dmat, sc->recv_dmamap,
 			    cur_rx, wrap, BUS_DMASYNC_PREREAD);
 			cur_rx = 0;
 			rxbufpos = sc->rtk_rx_buf;
 			total_len -= wrap;
 			dst += wrap;
+		}
 		/*
 		 * ...and now the rest.
 		 */
 		bus_dmamap_sync(sc->sc_dmat, sc->recv_dmamap,
 		    cur_rx, total_len, BUS_DMASYNC_POSTREAD);
 		memcpy(dst, rxbufpos, total_len);
 		bus_dmamap_sync(sc->sc_dmat, sc->recv_dmamap,
 		    cur_rx, total_len, BUS_DMASYNC_PREREAD);
  next_packet:
 		CSR_WRITE_2(sc, RTK_CURRXADDR, (new_rx - 16) % RTK_RXBUFLEN);
 		cur_rx = new_rx;
 		if (m == NULL)
 			continue;
 		/* pass it on. */
 		if_percpuq_enqueue(ifp->if_percpuq, m);
+	}
+}
 /*
  * A frame was downloaded to the chip. It's safe for us to clean up
  * the list buffers.
  */
 static void
 rtk_txeof(struct rtk_softc *sc)
+{
 	struct ifnet *ifp;
 	struct rtk_tx_desc *txd;
 	uint32_t txstat;
 	ifp = &sc->ethercom.ec_if;
 	/*
 	 * Go through our tx list and free mbufs for those
 	 * frames that have been uploaded.
 	 */
 	while ((txd = SIMPLEQ_FIRST(&sc->rtk_tx_dirty)) != NULL) {
 		txstat = CSR_READ_4(sc, txd->txd_txstat);
 		if ((txstat & (RTK_TXSTAT_TX_OK |
 		    RTK_TXSTAT_TX_UNDERRUN | RTK_TXSTAT_TXABRT)) == 0)
 			break;
 		SIMPLEQ_REMOVE_HEAD(&sc->rtk_tx_dirty, txd_q);
 		bus_dmamap_sync(sc->sc_dmat, txd->txd_dmamap, 0,
 		    txd->txd_dmamap->dm_mapsize, BUS_DMASYNC_POSTWRITE);
 		bus_dmamap_unload(sc->sc_dmat, txd->txd_dmamap);
 		m_freem(txd->txd_mbuf);
 		txd->txd_mbuf = NULL;
 		ifp->if_collisions += (txstat & RTK_TXSTAT_COLLCNT) >> 24;
 		if (txstat & RTK_TXSTAT_TX_OK)
 			ifp->if_opackets++;
 		else {
 			ifp->if_oerrors++;
 			/*
 			 * Increase Early TX threshold if underrun occurred.
 			 * Increase step 64 bytes.
 			 */
 			if (txstat & RTK_TXSTAT_TX_UNDERRUN) {
 #ifdef DEBUG
 				printf("%s: transmit underrun;",
 				    device_xname(sc->sc_dev));
 #endif
 				if (sc->sc_txthresh < RTK_TXTH_MAX) {
 					sc->sc_txthresh += 2;
 #ifdef DEBUG
 					printf(" new threshold: %d bytes",
 					    sc->sc_txthresh * 32);
 #endif
+				}
 #ifdef DEBUG
 				printf("\n");
 #endif
+			}
 			if (txstat & (RTK_TXSTAT_TXABRT | RTK_TXSTAT_OUTOFWIN))
 				CSR_WRITE_4(sc, RTK_TXCFG, RTK_TXCFG_CONFIG);
+		}
 		SIMPLEQ_INSERT_TAIL(&sc->rtk_tx_free, txd, txd_q);
 		ifp->if_flags &= ~IFF_OACTIVE;
+	}
 	/* Clear the timeout timer if there is no pending packet. */
 	if (SIMPLEQ_EMPTY(&sc->rtk_tx_dirty))
 		ifp->if_timer = 0;
+}
 int
 rtk_intr(void *arg)
+{
 	struct rtk_softc *sc;
 	struct ifnet *ifp;
 	uint16_t status;
 	int handled;
 	sc = arg;
 	ifp = &sc->ethercom.ec_if;
 	if (!device_has_power(sc->sc_dev))
 		return 0;
 	/* Disable interrupts. */
 	CSR_WRITE_2(sc, RTK_IMR, 0x0000);
 	handled = 0;
 	for (;;) {
 		status = CSR_READ_2(sc, RTK_ISR);
 		if (status == 0xffff)
 			break; /* Card is gone... */
 		if (status)
 			CSR_WRITE_2(sc, RTK_ISR, status);
 		if ((status & RTK_INTRS) == 0)
 			break;
 		handled = 1;
 		if (status & RTK_ISR_RX_OK)
 			rtk_rxeof(sc);
 		if (status & RTK_ISR_RX_ERR)
 			rtk_rxeof(sc);
 		if (status & (RTK_ISR_TX_OK | RTK_ISR_TX_ERR))
 			rtk_txeof(sc);
 		if (status & RTK_ISR_SYSTEM_ERR) {
 			rtk_reset(sc);
 			rtk_init(ifp);
+		}
+	}
 	/* Re-enable interrupts. */
 	CSR_WRITE_2(sc, RTK_IMR, RTK_INTRS);
 	if_schedule_deferred_start(ifp);
 	rnd_add_uint32(&sc->rnd_source, status);
 	return handled;
+}
 /*
  * Main transmit routine.
  */
 static void
 rtk_start(struct ifnet *ifp)
+{
 	struct rtk_softc *sc;
 	struct rtk_tx_desc *txd;
 	struct mbuf *m_head, *m_new;
 	int error, len;
 	sc = ifp->if_softc;
 	while ((txd = SIMPLEQ_FIRST(&sc->rtk_tx_free)) != NULL) {
 		IFQ_POLL(&ifp->if_snd, m_head);
 		if (m_head == NULL)
 			break;
 		m_new = NULL;
 		/*
 		 * Load the DMA map.  If this fails, the packet didn't
 		 * fit in one DMA segment, and we need to copy.  Note,
 		 * the packet must also be aligned.
 		 * if the packet is too small, copy it too, so we're sure
 		 * so have enough room for the pad buffer.
 		 */
 		if ((mtod(m_head, uintptr_t) & 3) != 0 ||
 		    m_head->m_pkthdr.len < ETHER_PAD_LEN ||
 		    bus_dmamap_load_mbuf(sc->sc_dmat, txd->txd_dmamap,
 			m_head, BUS_DMA_WRITE | BUS_DMA_NOWAIT) != 0) {
 			MGETHDR(m_new, M_DONTWAIT, MT_DATA);
 			if (m_new == NULL) {
 				printf("%s: unable to allocate Tx mbuf\n",
 				    device_xname(sc->sc_dev));
 				break;
+			}
 			if (m_head->m_pkthdr.len > MHLEN) {
 				MCLGET(m_new, M_DONTWAIT);
 				if ((m_new->m_flags & M_EXT) == 0) {
 					printf("%s: unable to allocate Tx "
 					    "cluster\n",
 					    device_xname(sc->sc_dev));
 					m_freem(m_new);
 					break;
+				}
+			}
 			m_copydata(m_head, 0, m_head->m_pkthdr.len,
 			    mtod(m_new, void *));
 			m_new->m_pkthdr.len = m_new->m_len =
 			    m_head->m_pkthdr.len;
 			if (m_head->m_pkthdr.len < ETHER_PAD_LEN) {
 				memset(
 				    mtod(m_new, char *) + m_head->m_pkthdr.len,
 , ETHER_PAD_LEN - m_head->m_pkthdr.len);
 				m_new->m_pkthdr.len = m_new->m_len =
 				    ETHER_PAD_LEN;
+			}
 			error = bus_dmamap_load_mbuf(sc->sc_dmat,
 			    txd->txd_dmamap, m_new,
 			    BUS_DMA_WRITE | BUS_DMA_NOWAIT);
 			if (error) {
 				printf("%s: unable to load Tx buffer, "
 				    "error = %d\n",
 				    device_xname(sc->sc_dev), error);
 				break;
+			}
+		}
 		IFQ_DEQUEUE(&ifp->if_snd, m_head);
 		/*
 		 * If there's a BPF listener, bounce a copy of this frame
 		 * to him.
 		 */
 		bpf_mtap(ifp, m_head, BPF_D_OUT);
 		if (m_new != NULL) {
 			m_freem(m_head);
 			m_head = m_new;
+		}
 		txd->txd_mbuf = m_head;
 		SIMPLEQ_REMOVE_HEAD(&sc->rtk_tx_free, txd_q);
 		SIMPLEQ_INSERT_TAIL(&sc->rtk_tx_dirty, txd, txd_q);
 		/*
 		 * Transmit the frame.
 		 */
 		bus_dmamap_sync(sc->sc_dmat,
 		    txd->txd_dmamap, 0, txd->txd_dmamap->dm_mapsize,
 		    BUS_DMASYNC_PREWRITE);
 		len = txd->txd_dmamap->dm_segs[0].ds_len;
 		CSR_WRITE_4(sc, txd->txd_txaddr,
 		    txd->txd_dmamap->dm_segs[0].ds_addr);
 		CSR_WRITE_4(sc, txd->txd_txstat,
 		    RTK_TXSTAT_THRESH(sc->sc_txthresh) | len);
 		/*
 		 * Set a timeout in case the chip goes out to lunch.
 		 */
 		ifp->if_timer = 5;
+	}
 	/*
 	 * We broke out of the loop because all our TX slots are
 	 * full. Mark the NIC as busy until it drains some of the
 	 * packets from the queue.
 	 */
 	if (SIMPLEQ_EMPTY(&sc->rtk_tx_free))
 		ifp->if_flags |= IFF_OACTIVE;
+}
 static int
 rtk_init(struct ifnet *ifp)
+{
 	struct rtk_softc *sc = ifp->if_softc;
 	int error, i;
 	uint32_t rxcfg;
 	if ((error = rtk_enable(sc)) != 0)
 		goto out;
 	/*
 	 * Cancel pending I/O.
 	 */
 	rtk_stop(ifp, 0);
 	/* Init our MAC address */
 	for (i = 0; i < ETHER_ADDR_LEN; i++) {
 		CSR_WRITE_1(sc, RTK_IDR0 + i, CLLADDR(ifp->if_sadl)[i]);
+	}
 	/* Init the RX buffer pointer register. */
 	bus_dmamap_sync(sc->sc_dmat, sc->recv_dmamap, 0,
 	    sc->recv_dmamap->dm_mapsize, BUS_DMASYNC_PREREAD);
 	CSR_WRITE_4(sc, RTK_RXADDR, sc->recv_dmamap->dm_segs[0].ds_addr);
 	/* Init TX descriptors. */
 	rtk_list_tx_init(sc);
 	/* Init Early TX threshold. */
 	sc->sc_txthresh = RTK_TXTH_256;
 	/*
 	 * Enable transmit and receive.
 	 */
 	CSR_WRITE_1(sc, RTK_COMMAND, RTK_CMD_TX_ENB | RTK_CMD_RX_ENB);
 	/*
 	 * Set the initial TX and RX configuration.
 	 */
 	CSR_WRITE_4(sc, RTK_TXCFG, RTK_TXCFG_CONFIG);
 	CSR_WRITE_4(sc, RTK_RXCFG, RTK_RXCFG_CONFIG);
 	/* Set the individual bit to receive frames for this host only. */
 	rxcfg = CSR_READ_4(sc, RTK_RXCFG);
 	rxcfg |= RTK_RXCFG_RX_INDIV;
 	/* If we want promiscuous mode, set the allframes bit. */
 	if (ifp->if_flags & IFF_PROMISC) {
 		rxcfg |= RTK_RXCFG_RX_ALLPHYS;
 		CSR_WRITE_4(sc, RTK_RXCFG, rxcfg);
 	} else {
 		rxcfg &= ~RTK_RXCFG_RX_ALLPHYS;
 		CSR_WRITE_4(sc, RTK_RXCFG, rxcfg);
+	}
 	/*
 	 * Set capture broadcast bit to capture broadcast frames.
 	 */
 	if (ifp->if_flags & IFF_BROADCAST) {
 		rxcfg |= RTK_RXCFG_RX_BROAD;
 		CSR_WRITE_4(sc, RTK_RXCFG, rxcfg);
 	} else {
 		rxcfg &= ~RTK_RXCFG_RX_BROAD;
 		CSR_WRITE_4(sc, RTK_RXCFG, rxcfg);
+	}
 	/*
 	 * Program the multicast filter, if necessary.
 	 */
 	rtk_setmulti(sc);
 	/*
 	 * Enable interrupts.
 	 */
 	CSR_WRITE_2(sc, RTK_IMR, RTK_INTRS);
 	/* Start RX/TX process. */
 	CSR_WRITE_4(sc, RTK_MISSEDPKT, 0);
 	/* Enable receiver and transmitter. */
 	CSR_WRITE_1(sc, RTK_COMMAND, RTK_CMD_TX_ENB | RTK_CMD_RX_ENB);
 	CSR_WRITE_1(sc, RTK_CFG1, RTK_CFG1_DRVLOAD | RTK_CFG1_FULLDUPLEX);
 	/*
 	 * Set current media.
 	 */
 	if ((error = ether_mediachange(ifp)) != 0)
 		goto out;
 	ifp->if_flags |= IFF_RUNNING;
 	ifp->if_flags &= ~IFF_OACTIVE;
 	callout_reset(&sc->rtk_tick_ch, hz, rtk_tick, sc);
  out:
 	if (error) {
 		ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE);
 		ifp->if_timer = 0;
 		printf("%s: interface not running\n", device_xname(sc->sc_dev));
+	}
 	return error;
+}
 static int
 rtk_ioctl(struct ifnet *ifp, u_long command, void *data)
+{
 	struct rtk_softc *sc = ifp->if_softc;
 	int s, error;
 	s = splnet();
 	error = ether_ioctl(ifp, command, data);
 	if (error == ENETRESET) {
 		if (ifp->if_flags & IFF_RUNNING) {
 			/*
 			 * Multicast list has changed.  Set the
 			 * hardware filter accordingly.
 			 */
 			rtk_setmulti(sc);
+		}
 		error = 0;
+	}
 	splx(s);
 	return error;
+}
 static void
 rtk_watchdog(struct ifnet *ifp)
+{
 	struct rtk_softc *sc;
 	sc = ifp->if_softc;
 	printf("%s: watchdog timeout\n", device_xname(sc->sc_dev));
 	ifp->if_oerrors++;
 	rtk_txeof(sc);
 	rtk_rxeof(sc);
 	rtk_init(ifp);
+}
 /*
  * Stop the adapter and free any mbufs allocated to the
  * RX and TX lists.
  */
 static void
 rtk_stop(struct ifnet *ifp, int disable)
+{
 	struct rtk_softc *sc = ifp->if_softc;
 	struct rtk_tx_desc *txd;
 	callout_stop(&sc->rtk_tick_ch);
 	mii_down(&sc->mii);
 	CSR_WRITE_1(sc, RTK_COMMAND, 0x00);
 	CSR_WRITE_2(sc, RTK_IMR, 0x0000);
 	/*
 	 * Free the TX list buffers.
 	 */
 	while ((txd = SIMPLEQ_FIRST(&sc->rtk_tx_dirty)) != NULL) {
 		SIMPLEQ_REMOVE_HEAD(&sc->rtk_tx_dirty, txd_q);
 		bus_dmamap_unload(sc->sc_dmat, txd->txd_dmamap);
 		m_freem(txd->txd_mbuf);
 		txd->txd_mbuf = NULL;
 		CSR_WRITE_4(sc, txd->txd_txaddr, 0);
+	}
 	if (disable)
 		rtk_disable(sc);
 	ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE);
 	ifp->if_timer = 0;
+}
 static void
 rtk_tick(void *arg)
+{
 	struct rtk_softc *sc = arg;
 	int s;
 	s = splnet();
 	mii_tick(&sc->mii);
 	splx(s);
 	callout_reset(&sc->rtk_tick_ch, hz, rtk_tick, sc);
+}

 @@ -1,610 +1,619 @@
-/*	$NetBSD: rtl81x9reg.h,v 1.50 2019/04/05 23:46:04 uwe Exp $	*/
+/*	$NetBSD: rtl81x9reg.h,v 1.50.4.1 2020/01/28 11:12:30 martin Exp $	*/
 /*
  * Copyright (c) 1997, 1998
  *	Bill Paul <wpaul@ctr.columbia.edu>.  All rights reserved.
+ *
  * Redistribution and use in source and binary forms, with or without
  * modification, are permitted provided that the following conditions
  * are met:
  * 1. Redistributions of source code must retain the above copyright
  *    notice, this list of conditions and the following disclaimer.
  * 2. Redistributions in binary form must reproduce the above copyright
  *    notice, this list of conditions and the following disclaimer in the
  *    documentation and/or other materials provided with the distribution.
  * 3. All advertising materials mentioning features or use of this software
  *    must display the following acknowledgement:
  *	This product includes software developed by Bill Paul.
  * 4. Neither the name of the author nor the names of any co-contributors
  *    may be used to endorse or promote products derived from this software
  *    without specific prior written permission.
+ *
  * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND
  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
  * ARE DISCLAIMED.  IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD
  * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
  * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
  * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
  * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
  * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
  * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
  * THE POSSIBILITY OF SUCH DAMAGE.
+ *
  *	FreeBSD Id: if_rlreg.h,v 1.9 1999/06/20 18:56:09 wpaul Exp
  */
 /*
  * RealTek 8129/8139 register offsets
  */
 #define RTK_IDR0	0x0000		/* ID register 0 (station addr) */
 #define RTK_IDR1	0x0001		/* Must use 32-bit accesses (?) */
 #define RTK_IDR2	0x0002
 #define RTK_IDR3	0x0003
 #define RTK_IDR4	0x0004
 #define RTK_IDR5	0x0005
 					/* 0006-0007 reserved */
 #define RTK_MAR0	0x0008		/* Multicast hash table */
 #define RTK_MAR1	0x0009
 #define RTK_MAR2	0x000A
 #define RTK_MAR3	0x000B
 #define RTK_MAR4	0x000C
 #define RTK_MAR5	0x000D
 #define RTK_MAR6	0x000E
 #define RTK_MAR7	0x000F
 #define RTK_TXSTAT0	0x0010		/* status of TX descriptor 0 */
 #define RTK_TXSTAT1	0x0014		/* status of TX descriptor 1 */
 #define RTK_TXSTAT2	0x0018		/* status of TX descriptor 2 */
 #define RTK_TXSTAT3	0x001C		/* status of TX descriptor 3 */
 #define RTK_TXADDR0	0x0020		/* address of TX descriptor 0 */
 #define RTK_TXADDR1	0x0024		/* address of TX descriptor 1 */
 #define RTK_TXADDR2	0x0028		/* address of TX descriptor 2 */
 #define RTK_TXADDR3	0x002C		/* address of TX descriptor 3 */
 #define RTK_RXADDR		0x0030	/* RX ring start address */
 #define RTK_RX_EARLY_BYTES	0x0034	/* RX early byte count */
 #define RTK_RX_EARLY_STAT	0x0036	/* RX early status */
 #define RTK_COMMAND	0x0037		/* command register */
 #define RTK_CURRXADDR	0x0038		/* current address of packet read */
 #define RTK_CURRXBUF	0x003A		/* current RX buffer address */
 #define RTK_IMR		0x003C		/* interrupt mask register */
 #define RTK_ISR		0x003E		/* interrupt status register */
 #define RTK_TXCFG	0x0040		/* transmit config */
 #define RTK_RXCFG	0x0044		/* receive config */
 #define RTK_TIMERCNT	0x0048		/* timer count register */
 #define RTK_MISSEDPKT	0x004C		/* missed packet counter */
 #define RTK_EECMD	0x0050		/* EEPROM command register */
 #define RTK_CFG0	0x0051		/* config register #0 */
 #define RTK_CFG1	0x0052		/* config register #1 */
 					/* 0053-0057 reserved */
 #define RTK_MEDIASTAT	0x0058		/* media status register (8139) */
 					/* 0059-005A reserved */
 #define RTK_MII		0x005A		/* 8129 chip only */
 #define RTK_HALTCLK	0x005B
 #define RTK_MULTIINTR	0x005C		/* multiple interrupt */
 #define RTK_PCIREV	0x005E		/* PCI revision value */
 					/* 005F reserved */
 #define RTK_TXSTAT_ALL	0x0060		/* TX status of all descriptors */
 /* Direct PHY access registers only available on 8139 */
 #define RTK_BMCR	0x0062		/* PHY basic mode control */
 #define RTK_BMSR	0x0064		/* PHY basic mode status */
 #define RTK_ANAR	0x0066		/* PHY autoneg advert */
 #define RTK_LPAR	0x0068		/* PHY link partner ability */
 #define RTK_ANER	0x006A		/* PHY autoneg expansion */
 #define RTK_DISCCNT	0x006C		/* disconnect counter */
 #define RTK_FALSECAR	0x006E		/* false carrier counter */
 #define RTK_NWAYTST	0x0070		/* NWAY test register */
 #define RTK_RX_ER	0x0072		/* RX_ER counter */
 #define RTK_CSCFG	0x0074		/* CS configuration register */
 /*
  * When operating in special C+ mode, some of the registers in an
  * 8139C+ chip have different definitions. These are also used for
  * the 8169 gigE chip.
  */
 #define RTK_DUMPSTATS_LO	0x0010	/* counter dump command register */
 #define RTK_DUMPSTATS_HI	0x0014	/* counter dump command register */
 #define RTK_TXLIST_ADDR_LO	0x0020	/* 64 bits, 256 byte alignment */
 #define RTK_TXLIST_ADDR_HI	0x0024	/* 64 bits, 256 byte alignment */
 #define RTK_TXLIST_ADDR_HPRIO_LO	0x0028	/* 64 bits, 256 byte aligned */
 #define RTK_TXLIST_ADDR_HPRIO_HI	0x002C	/* 64 bits, 256 byte aligned */
 #define RTK_CFG2		0x0053
 #define RTK_TIMERINT		0x0054	/* interrupt on timer expire */
 #define RTK_TXSTART		0x00D9	/* 8 bits */
 #define RTK_CPLUS_CMD		0x00E0	/* 16 bits */
 #define RTK_RXLIST_ADDR_LO	0x00E4	/* 64 bits, 256 byte alignment */
 #define RTK_RXLIST_ADDR_HI	0x00E8	/* 64 bits, 256 byte alignment */
 #define RTK_EARLY_TX_THRESH	0x00EC	/* 8 bits */
 /*
  * Registers specific to the 8169 gigE chip
  */
 #define RTK_GTXSTART		0x0038	/* 8 bits */
 #define RTK_TIMERINT_8169	0x0058	/* different offset than 8139 */
 #define RTK_PHYAR		0x0060
 #define RTK_CSIDR		0x0064
 #define RTK_CSIAR		0x0068
 #define RTK_TBI_LPAR		0x006A
 #define RTK_GMEDIASTAT		0x006C	/* 8 bits */
 #define RTK_PMCH		0x006F	/* 8 bits */
 #define RTK_EPHYAR		0x0080
 #define RTK_LDPS		0x0082	/* Link Down Power Saving */
 #define RTK_DBG_REG		0x00D1
 #define RTK_MAXRXPKTLEN		0x00DA	/* 16 bits, chip multiplies by 8 */
 #define RTK_IM			0x00E2
 #define RTK_MISC		0x00F0
 /*
  * TX config register bits
  */
 #define RTK_TXCFG_CLRABRT	0x00000001	/* retransmit aborted pkt */
 #define RTK_TXCFG_MAXDMA	0x00000700	/* max DMA burst size */
 #define RTK_TXCFG_CRCAPPEND	0x00010000	/* CRC append (0 = yes) */
 #define RTK_TXCFG_LOOPBKTST	0x00060000	/* loopback test */
 #define RTK_TXCFG_IFG2		0x00080000	/* 8169 only */
 #define RTK_TXCFG_IFG		0x03000000	/* interframe gap */
 #define RTK_TXCFG_HWREV		0x7CC00000
-#define RTK_LOOPTEST_OFF		0x00000000
+#define RTK_LOOPTEST_OFF	0x00000000
 #define RTK_LOOPTEST_ON		0x00020000
 #define RTK_LOOPTEST_ON_CPLUS	0x00060000
 /* Known revision codes. */
 #define RTK_HWREV_8169		0x00000000
 #define RTK_HWREV_8110S		0x00800000
 #define RTK_HWREV_8169S		0x04000000
 #define RTK_HWREV_8169_8110SB	0x10000000
 #define RTK_HWREV_8169_8110SC	0x18000000
 #define RTK_HWREV_8401E		0x24000000
 #define RTK_HWREV_8102EL	0x24800000
-#define RTK_HWREV_8103E		0x24C00000
+#define RTK_HWREV_8102EL_SPIN1	0x24C00000
 #define RTK_HWREV_8168D		0x28000000
 #define RTK_HWREV_8168DP	0x28800000
 #define RTK_HWREV_8168E		0x2C000000
 #define RTK_HWREV_8168E_VL	0x2C800000
 #define RTK_HWREV_8168_SPIN1	0x30000000
 #define RTK_HWREV_8168G		0x4c000000
 #define RTK_HWREV_8168G_SPIN1	0x4c100000
 #define RTK_HWREV_8168G_SPIN2	0x50900000
 #define RTK_HWREV_8168G_SPIN4	0x5c800000
 #define RTK_HWREV_8168GU	0x50800000
 #define RTK_HWREV_8100E		0x30800000
 #define RTK_HWREV_8101E		0x34000000
 #define RTK_HWREV_8102E		0x34800000
 #define RTK_HWREV_8103E		0x34c00000
 #define RTK_HWREV_8168_SPIN2	0x38000000
 #define RTK_HWREV_8168_SPIN3	0x38400000
 #define RTK_HWREV_8100E_SPIN2	0x38800000
 #define RTK_HWREV_8168C		0x3C000000
 #define RTK_HWREV_8168C_SPIN2	0x3C400000
 #define RTK_HWREV_8168CP	0x3C800000
 #define RTK_HWREV_8105E		0x40800000
 #define RTK_HWREV_8105E_SPIN1	0x40C00000
 #define RTK_HWREV_8402		0x44000000
 #define RTK_HWREV_8106E		0x44800000
 #define RTK_HWREV_8168F		0x48000000
 #define RTK_HWREV_8411		0x48800000
 #define RTK_HWREV_8168G		0x4c000000
 #define RTK_HWREV_8168G_SPIN1	0x4c100000
 #define RTK_HWREV_8168EP	0x50000000
 #define RTK_HWREV_8168GU	0x50800000
 #define RTK_HWREV_8168G_SPIN2	0x50900000
 #define RTK_HWREV_8168H		0x54000000
 #define RTK_HWREV_8168H_SPIN1	0x54100000
 #define RTK_HWREV_8168FP	0x54800000
 #define RTK_HWREV_8168G_SPIN4	0x5c800000
 #define RTK_HWREV_8139		0x60000000
 #define RTK_HWREV_8139A		0x70000000
 #define RTK_HWREV_8139AG	0x70800000
 #define RTK_HWREV_8139B		0x78000000
 #define RTK_HWREV_8130		0x7C000000
 #define RTK_HWREV_8139C		0x74000000
 #define RTK_HWREV_8139D		0x74400000
 #define RTK_HWREV_8139CPLUS	0x74800000
 #define RTK_HWREV_8101		0x74c00000
 #define RTK_HWREV_8139B		0x78000000
 #define RTK_HWREV_8100		0x78800000
 #define RTK_HWREV_8130		0x7C000000
 #define RTK_HWREV_8169_8110SBL	0x7cc00000
 #define RTK_TXDMA_16BYTES	0x00000000
 #define RTK_TXDMA_32BYTES	0x00000100
 #define RTK_TXDMA_64BYTES	0x00000200
 #define RTK_TXDMA_128BYTES	0x00000300
 #define RTK_TXDMA_256BYTES	0x00000400
 #define RTK_TXDMA_512BYTES	0x00000500
 #define RTK_TXDMA_1024BYTES	0x00000600
 #define RTK_TXDMA_2048BYTES	0x00000700
 /*
  * Transmit descriptor status register bits.
  */
 #define RTK_TXSTAT_LENMASK	0x00001FFF
 #define RTK_TXSTAT_OWN		0x00002000
 #define RTK_TXSTAT_TX_UNDERRUN	0x00004000
 #define RTK_TXSTAT_TX_OK	0x00008000
 #define RTK_TXSTAT_EARLY_THRESH	0x003F0000
 #define RTK_TXSTAT_COLLCNT	0x0F000000
 #define RTK_TXSTAT_CARR_HBEAT	0x10000000
 #define RTK_TXSTAT_OUTOFWIN	0x20000000
 #define RTK_TXSTAT_TXABRT	0x40000000
 #define RTK_TXSTAT_CARRLOSS	0x80000000
 #define RTK_TXSTAT_THRESH(x)	(((x) << 16) & RTK_TXSTAT_EARLY_THRESH)
 #define RTK_TXTH_256		8	/* (x) * 32 bytes */
 #define RTK_TXTH_1536		48
 /* MISC register */
 #define	RTK_MISC_TXPLA_RST	__BIT(29)
 #define	RTK_MISC_DISABLE_LAN_EN	__BIT(23)	/* Enable GPIO pin */
 #define	RTK_MISC_PWM_EN		__BIT(22)
 #define	RTK_MISC_RXDV_GATED_EN	__BIT(19)
 #define	RTK_MISC_EARLY_TALLY_EN	__BIT(16)
 /*
  * Interrupt status register bits.
  */
 #define RTK_ISR_RX_OK		0x0001
 #define RTK_ISR_RX_ERR		0x0002
 #define RTK_ISR_TX_OK		0x0004
 #define RTK_ISR_TX_ERR		0x0008
 #define RTK_ISR_RX_OVERRUN	0x0010
 #define RTK_ISR_PKT_UNDERRUN	0x0020
 #define RTK_ISR_LINKCHG		0x0020	/* 8169 only */
 #define RTK_ISR_FIFO_OFLOW	0x0040	/* 8139 only */
 #define RTK_ISR_TX_DESC_UNAVAIL	0x0080	/* C+ only */
 #define RTK_ISR_SWI		0x0100	/* C+ only */
 #define RTK_ISR_CABLE_LEN_CHGD	0x2000
 #define RTK_ISR_PCS_TIMEOUT	0x4000	/* 8129 only */
 #define RTK_ISR_TIMEOUT_EXPIRED	0x4000
 #define RTK_ISR_SYSTEM_ERR	0x8000
 #define RTK_INTRS	\
 	(RTK_ISR_TX_OK|RTK_ISR_RX_OK|RTK_ISR_RX_ERR|RTK_ISR_TX_ERR|	\
 	RTK_ISR_RX_OVERRUN|RTK_ISR_PKT_UNDERRUN|RTK_ISR_FIFO_OFLOW|	\
 	RTK_ISR_PCS_TIMEOUT|RTK_ISR_SYSTEM_ERR)
 #define RTK_INTRS_CPLUS	\
 	(RTK_ISR_RX_OK|RTK_ISR_RX_ERR|RTK_ISR_TX_ERR|			\
 	RTK_ISR_RX_OVERRUN|RTK_ISR_PKT_UNDERRUN|RTK_ISR_FIFO_OFLOW|	\
 	RTK_ISR_PCS_TIMEOUT|RTK_ISR_SYSTEM_ERR|RTK_ISR_TIMEOUT_EXPIRED)
 #define RTK_INTRS_IM_HW	\
 	(RTK_INTRS_CPLUS|RTK_ISR_TX_OK)
 /*
  * Media status register. (8139 only)
  */
 #define RTK_MEDIASTAT_RXPAUSE	0x01
 #define RTK_MEDIASTAT_TXPAUSE	0x02
 #define RTK_MEDIASTAT_LINK	0x04
 #define RTK_MEDIASTAT_SPEED10	0x08
 #define RTK_MEDIASTAT_RXFLOWCTL	0x40	/* duplex mode */
 #define RTK_MEDIASTAT_TXFLOWCTL	0x80	/* duplex mode */
 /*
  * Receive config register.
  */
 #define RTK_RXCFG_RX_ALLPHYS	0x00000001	/* accept all nodes */
 #define RTK_RXCFG_RX_INDIV	0x00000002	/* match filter */
 #define RTK_RXCFG_RX_MULTI	0x00000004	/* accept all multicast */
 #define RTK_RXCFG_RX_BROAD	0x00000008	/* accept all broadcast */
 #define RTK_RXCFG_RX_RUNT	0x00000010
 #define RTK_RXCFG_RX_ERRPKT	0x00000020
 #define RTK_RXCFG_WRAP		0x00000080
 #define RTK_RXCFG_MAXDMA	0x00000700
 #define RTK_RXCFG_BUFSZ		0x00001800
 #define RTK_RXCFG_FIFOTHRESH	0x0000E000
 #define RTK_RXCFG_EARLYTHRESH	0x07000000
 #define RTK_RXDMA_16BYTES	0x00000000
 #define RTK_RXDMA_32BYTES	0x00000100
 #define RTK_RXDMA_64BYTES	0x00000200
 #define RTK_RXDMA_128BYTES	0x00000300
 #define RTK_RXDMA_256BYTES	0x00000400
 #define RTK_RXDMA_512BYTES	0x00000500
 #define RTK_RXDMA_1024BYTES	0x00000600
 #define RTK_RXDMA_UNLIMITED	0x00000700
 #define RTK_RXBUF_8		0x00000000
 #define RTK_RXBUF_16		0x00000800
 #define RTK_RXBUF_32		0x00001000
 #define RTK_RXBUF_64		0x00001800
 #define RTK_RXBUF_LEN(x)	(1 << (((x) >> 11) + 13))
 #define RTK_RXFIFO_16BYTES	0x00000000
 #define RTK_RXFIFO_32BYTES	0x00002000
 #define RTK_RXFIFO_64BYTES	0x00004000
 #define RTK_RXFIFO_128BYTES	0x00006000
 #define RTK_RXFIFO_256BYTES	0x00008000
 #define RTK_RXFIFO_512BYTES	0x0000A000
 #define RTK_RXFIFO_1024BYTES	0x0000C000
 #define RTK_RXFIFO_NOTHRESH	0x0000E000
 /*
  * Bits in RX status header (included with RX'ed packet
  * in ring buffer).
  */
 #define RTK_RXSTAT_RXOK		0x00000001
 #define RTK_RXSTAT_ALIGNERR	0x00000002
 #define RTK_RXSTAT_CRCERR	0x00000004
 #define RTK_RXSTAT_GIANT	0x00000008
 #define RTK_RXSTAT_RUNT		0x00000010
 #define RTK_RXSTAT_BADSYM	0x00000020
 #define RTK_RXSTAT_BROAD	0x00002000
 #define RTK_RXSTAT_INDIV	0x00004000
 #define RTK_RXSTAT_MULTI	0x00008000
 #define RTK_RXSTAT_LENMASK	0xFFFF0000
 #define RTK_RXSTAT_UNFINISHED	0xFFF0		/* DMA still in progress */
 /*
  * Command register.
  */
 #define RTK_CMD_EMPTY_RXBUF	0x0001
 #define RTK_CMD_TX_ENB		0x0004
 #define RTK_CMD_RX_ENB		0x0008
 #define RTK_CMD_RESET		0x0010
 #define RTK_CMD_STOPREQ		0x0080
 /*
  * EEPROM control register
  */
 #define RTK_EE_DATAOUT		0x01	/* Data out */
 #define RTK_EE_DATAIN		0x02	/* Data in */
 #define RTK_EE_CLK		0x04	/* clock */
 #define RTK_EE_SEL		0x08	/* chip select */
 #define RTK_EE_MODE		(0x40|0x80)
 #define RTK_EEMODE_OFF		0x00
 #define RTK_EEMODE_AUTOLOAD	0x40
 #define RTK_EEMODE_PROGRAM	0x80
 #define RTK_EEMODE_WRITECFG	(0x80|0x40)
 /* 9346/9356 EEPROM commands */
 #define RTK_EEADDR_LEN0		6	/* 9346 */
 #define RTK_EEADDR_LEN1		8	/* 9356 */
 #define RTK_EECMD_LEN		4
 #define RTK_EECMD_WRITE		0x5	/* 0101b */
 #define RTK_EECMD_READ		0x6	/* 0110b */
 #define RTK_EECMD_ERASE		0x7	/* 0111b */
 #define RTK_EE_ID		0x00
 #define RTK_EE_PCI_VID		0x01
 #define RTK_EE_PCI_DID		0x02
 /* Location of station address inside EEPROM */
 #define RTK_EE_EADDR0		0x07
 #define RTK_EE_EADDR1		0x08
 #define RTK_EE_EADDR2		0x09
 /*
  * MII register (8129 only)
  */
 #define RTK_MII_CLK		0x01
 #define RTK_MII_DATAIN		0x02
 #define RTK_MII_DATAOUT		0x04
 #define RTK_MII_DIR		0x80	/* 0 == input, 1 == output */
 /*
  * Config 0 register
  */
 #define RTK_CFG0_ROM0		0x01
 #define RTK_CFG0_ROM1		0x02
 #define RTK_CFG0_ROM2		0x04
 #define RTK_CFG0_PL0		0x08
 #define RTK_CFG0_PL1		0x10
 #define RTK_CFG0_10MBPS		0x20	/* 10 Mbps internal mode */
 #define RTK_CFG0_PCS		0x40
 #define RTK_CFG0_SCR		0x80
 /*
  * Config 1 register
  */
 #define RTK_CFG1_PWRDWN		0x01
 #define RTK_CFG1_SLEEP		0x02
 #define RTK_CFG1_IOMAP		0x04
 #define RTK_CFG1_MEMMAP		0x08
 #define RTK_CFG1_RSVD		0x10
 #define RTK_CFG1_DRVLOAD	0x20
 #define RTK_CFG1_LED0		0x40
 #define RTK_CFG1_FULLDUPLEX	0x40	/* 8129 only */
 #define RTK_CFG1_LED1		0x80
 /*
  * 8139C+ register definitions
  */
 /* RTK_DUMPSTATS_LO register */
 #define RTK_DUMPSTATS_START	0x00000008
 /* Transmit start register */
 #define RTK_TXSTART_SWI		0x01	/* generate TX interrupt */
 #define RTK_TXSTART_START	0x40	/* start normal queue transmit */
 #define RTK_TXSTART_HPRIO_START	0x80	/* start hi prio queue transmit */
 /*
  * Config 2 register, 8139C+/8169/8169S/8110S only
  */
 #define RTK_CFG2_BUSFREQ	0x07
 #define RTK_CFG2_BUSWIDTH	0x08
 #define RTK_CFG2_AUXPWRSTS	0x10
 #define RTK_BUSFREQ_33MHZ	0x00
 #define RTK_BUSFREQ_66MHZ	0x01
 #define RTK_BUSWIDTH_32BITS	0x00
 #define RTK_BUSWIDTH_64BITS	0x08
 /* C+ mode command register */
 #define RE_CPLUSCMD_TXENB	0x0001	/* enable C+ transmit mode */
 #define RE_CPLUSCMD_RXENB	0x0002	/* enable C+ receive mode */
 #define RE_CPLUSCMD_PCI_MRW	0x0008	/* enable PCI multi-read/write */
 #define RE_CPLUSCMD_PCI_DAC	0x0010	/* PCI dual-address cycle only */
 #define RE_CPLUSCMD_RXCSUM_ENB	0x0020	/* enable RX checksum offload */
 #define RE_CPLUSCMD_VLANSTRIP	0x0040	/* enable VLAN tag stripping */
 #define RE_CPLUSCMD_MACSTAT_DIS	0x0080	/* 8168B/C/CP */
 #define RE_CPLUSCMD_ASF		0x0100	/* 8168C/CP */
 #define RE_CPLUSCMD_DBG_SEL	0x0200	/* 8168C/CP */
 #define RE_CPLUSCMD_FORCE_TXFC	0x0400	/* 8168C/CP */
 #define RE_CPLUSCMD_FORCE_RXFC	0x0800	/* 8168C/CP */
 #define RE_CPLUSCMD_FORCE_HDPX	0x1000	/* 8168C/CP */
 #define RE_CPLUSCMD_NORMAL_MODE	0x2000	/* 8168C/CP */
 #define RE_CPLUSCMD_DBG_ENB	0x4000	/* 8168C/CP */
 #define RE_CPLUSCMD_BIST_ENB	0x8000	/* 8168C/CP */
 /* C+ early transmit threshold */
 #define RTK_EARLYTXTHRESH_CNT	0x003F	/* byte count times 8 */
 /*
  * Gigabit PHY access register (8169 only)
  */
 #define RTK_PHYAR_PHYDATA	0x0000FFFF
 #define RTK_PHYAR_PHYREG		0x001F0000
 #define RTK_PHYAR_BUSY		0x80000000
 /*
  * Gigabit media status (8169 only)
  */
 #define RTK_GMEDIASTAT_FDX	0x01	/* full duplex */
 #define RTK_GMEDIASTAT_LINK	0x02	/* link up */
 #define RTK_GMEDIASTAT_10MBPS	0x04	/* 10mps link */
 #define RTK_GMEDIASTAT_100MBPS	0x08	/* 100mbps link */
 #define RTK_GMEDIASTAT_1000MBPS	0x10	/* gigE link */
 #define RTK_GMEDIASTAT_RXFLOW	0x20	/* RX flow control on */
 #define RTK_GMEDIASTAT_TXFLOW	0x40	/* TX flow control on */
 #define RTK_GMEDIASTAT_TBI	0x80	/* TBI enabled */
 #define RTK_TX_EARLYTHRESH	((256 / 32) << 16)
 #define RTK_RX_FIFOTHRESH	RTK_RXFIFO_256BYTES
 #define RTK_RX_MAXDMA		RTK_RXDMA_256BYTES
 #define RTK_TX_MAXDMA		RTK_TXDMA_256BYTES
 #define RTK_RXCFG_CONFIG	(RTK_RX_FIFOTHRESH|RTK_RX_MAXDMA|RTK_RX_BUF_SZ)
 #define RTK_TXCFG_CONFIG	(RTK_TXCFG_IFG|RTK_TX_MAXDMA)
 #define RE_RX_FIFOTHRESH	RTK_RXFIFO_NOTHRESH
 #define RE_RX_MAXDMA		RTK_RXDMA_UNLIMITED
 #define RE_TX_MAXDMA		RTK_TXDMA_2048BYTES
 #define RE_RXCFG_CONFIG		(RE_RX_FIFOTHRESH|RE_RX_MAXDMA|RTK_RX_BUF_SZ)
 #define RE_TXCFG_CONFIG		(RTK_TXCFG_IFG|RE_TX_MAXDMA)
 /*
  * RX/TX descriptor definition. When large send mode is enabled, the
  * lower 11 bits of the TX rtk_cmd word are used to hold the MSS, and
  * the checksum offload bits are disabled. The structure layout is
  * the same for RX and TX descriptors
  */
 struct re_desc {
 	volatile uint32_t	re_cmdstat;
 	volatile uint32_t	re_vlanctl;
 	volatile uint32_t	re_bufaddr_lo;
 	volatile uint32_t	re_bufaddr_hi;
 };
 #define RE_TDESC_CMD_FRAGLEN	0x0000FFFF
 #define RE_TDESC_CMD_TCPCSUM	0x00010000	/* TCP checksum enable */
 #define RE_TDESC_CMD_UDPCSUM	0x00020000	/* UDP checksum enable */
 #define RE_TDESC_CMD_IPCSUM	0x00040000	/* IP header checksum enable */
 #define RE_TDESC_CMD_MSSVAL	0x07FF0000	/* Large send MSS value */
 #define RE_TDESC_CMD_MSSVAL_SHIFT 16		/* Shift of the above */
 #define RE_TDESC_CMD_LGSEND	0x08000000	/* TCP large send enb */
 #define RE_TDESC_CMD_EOF	0x10000000	/* end of frame marker */
 #define RE_TDESC_CMD_SOF	0x20000000	/* start of frame marker */
 #define RE_TDESC_CMD_EOR	0x40000000	/* end of ring marker */
 #define RE_TDESC_CMD_OWN	0x80000000	/* chip owns descriptor */
 #define RE_TDESC_CMD_LGTCPHO	0x01fc0000	/* DESCV2 TCP hdr off lg send */
 #define RE_TDESC_CMD_LGTCPHO_SHIFT 18
 #define RE_TDESC_CMD_LGSEND_V4	0x04000000	/* DESCV2 TCPv4 large send en */
 #define RE_TDESC_CMD_LGSEND_V6	0x02000000	/* DESCV2 TCPv6 large send en */
 #define RE_TDESC_VLANCTL_TAG	0x00020000	/* Insert VLAN tag */
 #define RE_TDESC_VLANCTL_DATA	0x0000FFFF	/* TAG data */
 #define RE_TDESC_VLANCTL_UDPCSUM 0x80000000	/* DESCV2 UDP cksum enable */
 #define RE_TDESC_VLANCTL_TCPCSUM 0x40000000	/* DESCV2 TCP cksum enable */
 #define RE_TDESC_VLANCTL_IPCSUM	0x20000000	/* DESCV2 IP hdr cksum enable */
 #define RE_TDESC_VLANCTL_MSSVAL	0x0ffc0000	/* DESCV2 large send MSS val */
 #define RE_TDESC_VLANCTL_MSSVAL_SHIFT 18
 /*
  * Error bits are valid only on the last descriptor of a frame
  * (i.e. RE_TDESC_CMD_EOF == 1)
  */
 #define RE_TDESC_STAT_COLCNT	0x000F0000	/* collision count */
 #define RE_TDESC_STAT_EXCESSCOL	0x00100000	/* excessive collisions */
 #define RE_TDESC_STAT_LINKFAIL	0x00200000	/* link faulure */
 #define RE_TDESC_STAT_OWINCOL	0x00400000	/* out-of-window collision */
 #define RE_TDESC_STAT_TXERRSUM	0x00800000	/* transmit error summary */
 #define RE_TDESC_STAT_UNDERRUN	0x02000000	/* TX underrun occurred */
 #define RE_TDESC_STAT_OWN	0x80000000
 /*
  * RX descriptor cmd/vlan definitions
  */
 #define RE_RDESC_CMD_EOR	0x40000000
 #define RE_RDESC_CMD_OWN	0x80000000
 #define RE_RDESC_CMD_BUFLEN	0x00001FFF
 #define RE_RDESC_STAT_OWN	0x80000000
 #define RE_RDESC_STAT_EOR	0x40000000
 #define RE_RDESC_STAT_SOF	0x20000000
 #define RE_RDESC_STAT_EOF	0x10000000
 #define RE_RDESC_STAT_FRALIGN	0x08000000	/* frame alignment error */
 #define RE_RDESC_STAT_MCAST	0x04000000	/* multicast pkt received */
 #define RE_RDESC_STAT_UCAST	0x02000000	/* unicast pkt received */
 #define RE_RDESC_STAT_BCAST	0x01000000	/* broadcast pkt received */
 #define RE_RDESC_STAT_BUFOFLOW	0x00800000	/* out of buffer space */
 #define RE_RDESC_STAT_FIFOOFLOW	0x00400000	/* FIFO overrun */
 #define RE_RDESC_STAT_GIANT	0x00200000	/* pkt > 4096 bytes */
 #define RE_RDESC_STAT_RXERRSUM	0x00100000	/* RX error summary */
 #define RE_RDESC_STAT_RUNT	0x00080000	/* runt packet received */
 #define RE_RDESC_STAT_CRCERR	0x00040000	/* CRC error */
 #define RE_RDESC_STAT_PROTOID	0x00030000	/* Protocol type */
 #define RE_RDESC_STAT_IPSUMBAD	0x00008000	/* IP header checksum bad */
 #define RE_RDESC_STAT_UDPSUMBAD	0x00004000	/* UDP checksum bad */
 #define RE_RDESC_STAT_TCPSUMBAD	0x00002000	/* TCP checksum bad */
 #define RE_RDESC_STAT_FRAGLEN	0x00001FFF	/* RX'ed frame/frag len */
 #define RE_RDESC_STAT_GFRAGLEN	0x00003FFF	/* RX'ed frame/frag len */
 #define RE_RDESC_VLANCTL_TAG	0x00010000	/* VLAN tag available
 						   (re_vlandata valid)*/
 #define RE_RDESC_VLANCTL_DATA	0x0000FFFF	/* TAG data */
 #define RE_RDESC_VLANCTL_IPV6	0x80000000	/* DESCV2 IPV6 packet */
 #define RE_RDESC_VLANCTL_IPV4	0x40000000	/* DESCV2 IPV4 packet */
 #define RE_PROTOID_NONIP	0x00000000
 #define RE_PROTOID_TCPIP	0x00010000
 #define RE_PROTOID_UDPIP	0x00020000
 #define RE_PROTOID_IP		0x00030000
 #define RE_TCPPKT(x)		(((x) & RE_RDESC_STAT_PROTOID) == \
 				 RE_PROTOID_TCPIP)
 #define RE_UDPPKT(x)		(((x) & RE_RDESC_STAT_PROTOID) == \
 				 RE_PROTOID_UDPIP)
 #define RE_ADDR_LO(y)		((uint64_t)(y) & 0xFFFFFFFF)
 #define RE_ADDR_HI(y)		((uint64_t)(y) >> 32)
 /*
  * Statistics counter structure (8139C+ and 8169 only)
  */
 struct re_stats {
 	uint32_t		re_tx_pkts_lo;
 	uint32_t		re_tx_pkts_hi;
 	uint32_t		re_tx_errs_lo;
 	uint32_t		re_tx_errs_hi;
 	uint32_t		re_tx_errs;
 	uint16_t		re_missed_pkts;
 	uint16_t		re_rx_framealign_errs;
 	uint32_t		re_tx_onecoll;
 	uint32_t		re_tx_multicolls;
 	uint32_t		re_rx_ucasts_hi;
 	uint32_t		re_rx_ucasts_lo;
 	uint32_t		re_rx_bcasts_lo;
 	uint32_t		re_rx_bcasts_hi;
 	uint32_t		re_rx_mcasts;
 	uint16_t		re_tx_aborts;
 	uint16_t		re_rx_underruns;
 };
 #define RE_IFQ_MAXLEN		512
 #define RE_JUMBO_FRAMELEN	ETHER_MAX_LEN_JUMBO
 #define RE_JUMBO_MTU		ETHERMTU_JUMBO