Tue Jan 28 17:23:30 2020 UTC ()
More definitions.


(maxv)
diff -r1.30 -r1.31 src/sys/arch/aarch64/include/armreg.h
cvs diff -r1.30 -r1.31 src/sys/arch/aarch64/include/armreg.h (expand / switch to unified diff)

--- src/sys/arch/aarch64/include/armreg.h 2019/12/28 00:22:08 1.30
+++ src/sys/arch/aarch64/include/armreg.h 2020/01/28 17:23:30 1.31
@@ -1,14 +1,14 @@ @@ -1,14 +1,14 @@
1/* $NetBSD: armreg.h,v 1.30 2019/12/28 00:22:08 rjs Exp $ */ 1/* $NetBSD: armreg.h,v 1.31 2020/01/28 17:23:30 maxv Exp $ */
2 2
3/*- 3/*-
4 * Copyright (c) 2014 The NetBSD Foundation, Inc. 4 * Copyright (c) 2014 The NetBSD Foundation, Inc.
5 * All rights reserved. 5 * All rights reserved.
6 * 6 *
7 * This code is derived from software contributed to The NetBSD Foundation 7 * This code is derived from software contributed to The NetBSD Foundation
8 * by Matt Thomas of 3am Software Foundry. 8 * by Matt Thomas of 3am Software Foundry.
9 * 9 *
10 * Redistribution and use in source and binary forms, with or without 10 * Redistribution and use in source and binary forms, with or without
11 * modification, are permitted provided that the following conditions 11 * modification, are permitted provided that the following conditions
12 * are met: 12 * are met:
13 * 1. Redistributions of source code must retain the above copyright 13 * 1. Redistributions of source code must retain the above copyright
14 * notice, this list of conditions and the following disclaimer. 14 * notice, this list of conditions and the following disclaimer.
@@ -219,26 +219,65 @@ AARCH64REG_READ_INLINE(id_aa64isar0_el1) @@ -219,26 +219,65 @@ AARCH64REG_READ_INLINE(id_aa64isar0_el1)
219#define ID_AA64ISAR0_EL1_CRC32_CRC32X 1 219#define ID_AA64ISAR0_EL1_CRC32_CRC32X 1
220#define ID_AA64ISAR0_EL1_SHA2 __BITS(15,12) 220#define ID_AA64ISAR0_EL1_SHA2 __BITS(15,12)
221#define ID_AA64ISAR0_EL1_SHA2_NONE 0 221#define ID_AA64ISAR0_EL1_SHA2_NONE 0
222#define ID_AA64ISAR0_EL1_SHA2_SHA256HSU 1 222#define ID_AA64ISAR0_EL1_SHA2_SHA256HSU 1
223#define ID_AA64ISAR0_EL1_SHA1 __BITS(11,8) 223#define ID_AA64ISAR0_EL1_SHA1 __BITS(11,8)
224#define ID_AA64ISAR0_EL1_SHA1_NONE 0 224#define ID_AA64ISAR0_EL1_SHA1_NONE 0
225#define ID_AA64ISAR0_EL1_SHA1_SHA1CPMHSU 1 225#define ID_AA64ISAR0_EL1_SHA1_SHA1CPMHSU 1
226#define ID_AA64ISAR0_EL1_AES __BITS(7,4) 226#define ID_AA64ISAR0_EL1_AES __BITS(7,4)
227#define ID_AA64ISAR0_EL1_AES_NONE 0 227#define ID_AA64ISAR0_EL1_AES_NONE 0
228#define ID_AA64ISAR0_EL1_AES_AES 1 228#define ID_AA64ISAR0_EL1_AES_AES 1
229#define ID_AA64ISAR0_EL1_AES_PMUL 2 229#define ID_AA64ISAR0_EL1_AES_PMUL 2
230 230
231AARCH64REG_READ_INLINE(id_aa64isar1_el1) 231AARCH64REG_READ_INLINE(id_aa64isar1_el1)
 232
 233#define ID_AA64ISAR1_EL1_SPECRES __BITS(43,40)
 234#define ID_AA64ISAR1_EL1_SPECRES_NONE 0
 235#define ID_AA64ISAR1_EL1_SPECRES_SUPPORTED 1
 236#define ID_AA64ISAR1_EL1_SB __BITS(39,36)
 237#define ID_AA64ISAR1_EL1_SB_NONE 0
 238#define ID_AA64ISAR1_EL1_SB_SUPPORTED 1
 239#define ID_AA64ISAR1_EL1_FRINTTS __BITS(35,32)
 240#define ID_AA64ISAR1_EL1_FRINTTS_NONE 0
 241#define ID_AA64ISAR1_EL1_FRINTTS_SUPPORTED 1
 242#define ID_AA64ISAR1_EL1_GPI __BITS(31,28)
 243#define ID_AA64ISAR1_EL1_GPI_NONE 0
 244#define ID_AA64ISAR1_EL1_GPI_SUPPORTED 1
 245#define ID_AA64ISAR1_EL1_GPA __BITS(27,24)
 246#define ID_AA64ISAR1_EL1_GPA_NONE 0
 247#define ID_AA64ISAR1_EL1_GPA_QARMA 1
 248#define ID_AA64ISAR1_EL1_LRCPC __BITS(23,20)
 249#define ID_AA64ISAR1_EL1_LRCPC_NONE 0
 250#define ID_AA64ISAR1_EL1_LRCPC_PR 1
 251#define ID_AA64ISAR1_EL1_LRCPC_PR_UR 2
 252#define ID_AA64ISAR1_EL1_FCMA __BITS(19,16)
 253#define ID_AA64ISAR1_EL1_FCMA_NONE 0
 254#define ID_AA64ISAR1_EL1_FCMA_SUPPORTED 1
 255#define ID_AA64ISAR1_EL1_JSCVT __BITS(15,12)
 256#define ID_AA64ISAR1_EL1_JSCVT_NONE 0
 257#define ID_AA64ISAR1_EL1_JSCVT_SUPPORTED 1
 258#define ID_AA64ISAR1_EL1_API __BITS(11,8)
 259#define ID_AA64ISAR1_EL1_API_NONE 0
 260#define ID_AA64ISAR1_EL1_API_SUPPORTED 1
 261#define ID_AA64ISAR1_EL1_API_ENHANCED 2
 262#define ID_AA64ISAR1_EL1_APA __BITS(7,4)
 263#define ID_AA64ISAR1_EL1_APA_NONE 0
 264#define ID_AA64ISAR1_EL1_APA_QARMA 1
 265#define ID_AA64ISAR1_EL1_APA_QARMA_ENH 2
 266#define ID_AA64ISAR1_EL1_DPB __BITS(3,0)
 267#define ID_AA64ISAR1_EL1_DPB_NONE 0
 268#define ID_AA64ISAR1_EL1_DPB_CVAP 1
 269#define ID_AA64ISAR1_EL1_DPB_CVAP_CVADP 2
 270
232AARCH64REG_READ_INLINE(id_aa64mmfr0_el1) 271AARCH64REG_READ_INLINE(id_aa64mmfr0_el1)
233 272
234#define ID_AA64MMFR0_EL1_TGRAN4 __BITS(31,28) 273#define ID_AA64MMFR0_EL1_TGRAN4 __BITS(31,28)
235#define ID_AA64MMFR0_EL1_TGRAN4_4KB 0 274#define ID_AA64MMFR0_EL1_TGRAN4_4KB 0
236#define ID_AA64MMFR0_EL1_TGRAN4_NONE 15 275#define ID_AA64MMFR0_EL1_TGRAN4_NONE 15
237#define ID_AA64MMFR0_EL1_TGRAN64 __BITS(24,27) 276#define ID_AA64MMFR0_EL1_TGRAN64 __BITS(24,27)
238#define ID_AA64MMFR0_EL1_TGRAN64_64KB 0 277#define ID_AA64MMFR0_EL1_TGRAN64_64KB 0
239#define ID_AA64MMFR0_EL1_TGRAN64_NONE 15 278#define ID_AA64MMFR0_EL1_TGRAN64_NONE 15
240#define ID_AA64MMFR0_EL1_TGRAN16 __BITS(20,23) 279#define ID_AA64MMFR0_EL1_TGRAN16 __BITS(20,23)
241#define ID_AA64MMFR0_EL1_TGRAN16_NONE 0 280#define ID_AA64MMFR0_EL1_TGRAN16_NONE 0
242#define ID_AA64MMFR0_EL1_TGRAN16_16KB 1 281#define ID_AA64MMFR0_EL1_TGRAN16_16KB 1
243#define ID_AA64MMFR0_EL1_BIGENDEL0 __BITS(16,19) 282#define ID_AA64MMFR0_EL1_BIGENDEL0 __BITS(16,19)
244#define ID_AA64MMFR0_EL1_BIGENDEL0_NONE 0 283#define ID_AA64MMFR0_EL1_BIGENDEL0_NONE 0
@@ -250,31 +289,126 @@ AARCH64REG_READ_INLINE(id_aa64mmfr0_el1) @@ -250,31 +289,126 @@ AARCH64REG_READ_INLINE(id_aa64mmfr0_el1)
250#define ID_AA64MMFR0_EL1_BIGEND_NONE 0 289#define ID_AA64MMFR0_EL1_BIGEND_NONE 0
251#define ID_AA64MMFR0_EL1_BIGEND_MIX 1 290#define ID_AA64MMFR0_EL1_BIGEND_MIX 1
252#define ID_AA64MMFR0_EL1_ASIDBITS __BITS(4,7) 291#define ID_AA64MMFR0_EL1_ASIDBITS __BITS(4,7)
253#define ID_AA64MMFR0_EL1_ASIDBITS_8BIT 0 292#define ID_AA64MMFR0_EL1_ASIDBITS_8BIT 0
254#define ID_AA64MMFR0_EL1_ASIDBITS_16BIT 2 293#define ID_AA64MMFR0_EL1_ASIDBITS_16BIT 2
255#define ID_AA64MMFR0_EL1_PARANGE __BITS(0,3) 294#define ID_AA64MMFR0_EL1_PARANGE __BITS(0,3)
256#define ID_AA64MMFR0_EL1_PARANGE_4G 0 295#define ID_AA64MMFR0_EL1_PARANGE_4G 0
257#define ID_AA64MMFR0_EL1_PARANGE_64G 1 296#define ID_AA64MMFR0_EL1_PARANGE_64G 1
258#define ID_AA64MMFR0_EL1_PARANGE_1T 2 297#define ID_AA64MMFR0_EL1_PARANGE_1T 2
259#define ID_AA64MMFR0_EL1_PARANGE_4T 3 298#define ID_AA64MMFR0_EL1_PARANGE_4T 3
260#define ID_AA64MMFR0_EL1_PARANGE_16T 4 299#define ID_AA64MMFR0_EL1_PARANGE_16T 4
261#define ID_AA64MMFR0_EL1_PARANGE_256T 5 300#define ID_AA64MMFR0_EL1_PARANGE_256T 5
262 301
263AARCH64REG_READ_INLINE2(a72_cpuactlr_el1, s3_1_c15_c2_0) 
264AARCH64REG_READ_INLINE(id_aa64mmfr1_el1) 302AARCH64REG_READ_INLINE(id_aa64mmfr1_el1)
 303
 304#define ID_AA64MMFR1_EL1_XNX __BITS(31,28)
 305#define ID_AA64MMFR1_EL1_XNX_NONE 0
 306#define ID_AA64MMFR1_EL1_XNX_SUPPORTED 1
 307#define ID_AA64MMFR1_EL1_SPECSEI __BITS(27,24)
 308#define ID_AA64MMFR1_EL1_SPECSEI_NONE 0
 309#define ID_AA64MMFR1_EL1_SPECSEI_EXTINT 1
 310#define ID_AA64MMFR1_EL1_PAN __BITS(23,20)
 311#define ID_AA64MMFR1_EL1_PAN_NONE 0
 312#define ID_AA64MMFR1_EL1_PAN_SUPPORTED 1
 313#define ID_AA64MMFR1_EL1_PAN_S1E1 2
 314#define ID_AA64MMFR1_EL1_LO __BITS(19,16)
 315#define ID_AA64MMFR1_EL1_LO_NONE 0
 316#define ID_AA64MMFR1_EL1_LO_SUPPORTED 1
 317#define ID_AA64MMFR1_EL1_HPDS __BITS(15,12)
 318#define ID_AA64MMFR1_EL1_HPDS_NONE 0
 319#define ID_AA64MMFR1_EL1_HPDS_SUPPORTED 1
 320#define ID_AA64MMFR1_EL1_HPDS_EXTRA_PTD 2
 321#define ID_AA64MMFR1_EL1_VH __BITS(11,8)
 322#define ID_AA64MMFR1_EL1_VH_NONE 0
 323#define ID_AA64MMFR1_EL1_VH_SUPPORTED 1
 324#define ID_AA64MMFR1_EL1_VMIDBITS __BITS(7,4)
 325#define ID_AA64MMFR1_EL1_VMIDBITS_8BIT 0
 326#define ID_AA64MMFR1_EL1_VMIDBITS_16BIT 2
 327#define ID_AA64MMFR1_EL1_HAFDBS __BITS(3,0)
 328#define ID_AA64MMFR1_EL1_HAFDBS_NONE 0
 329#define ID_AA64MMFR1_EL1_HAFDBS_A 1
 330#define ID_AA64MMFR1_EL1_HAFDBS_AD 2
 331
265AARCH64REG_READ_INLINE(id_aa64mmfr2_el1) 332AARCH64REG_READ_INLINE(id_aa64mmfr2_el1)
 333
 334#define ID_AA64MMFR2_EL1_E0PD __BITS(63,60)
 335#define ID_AA64MMFR2_EL1_E0PD_NONE 0
 336#define ID_AA64MMFR2_EL1_E0PD_SUPPORTED 1
 337#define ID_AA64MMFR2_EL1_EVT __BITS(59,56)
 338#define ID_AA64MMFR2_EL1_EVT_NONE 0
 339#define ID_AA64MMFR2_EL1_EVT_TO_TI 1
 340#define ID_AA64MMFR2_EL1_EVT_TO_TI_TTL 2
 341#define ID_AA64MMFR2_EL1_BBM __BITS(55,52)
 342#define ID_AA64MMFR2_EL1_BBM_L0 0
 343#define ID_AA64MMFR2_EL1_BBM_L1 1
 344#define ID_AA64MMFR2_EL1_BBM_L2 2
 345#define ID_AA64MMFR2_EL1_TTL __BITS(51,48)
 346#define ID_AA64MMFR2_EL1_TTL_NONE 0
 347#define ID_AA64MMFR2_EL1_TTL_SUPPORTED 1
 348#define ID_AA64MMFR2_EL1_FWB __BITS(43,40)
 349#define ID_AA64MMFR2_EL1_FWB_NONE 0
 350#define ID_AA64MMFR2_EL1_FWB_SUPPORTED 1
 351#define ID_AA64MMFR2_EL1_IDS __BITS(39,36)
 352#define ID_AA64MMFR2_EL1_IDS_0X0 0
 353#define ID_AA64MMFR2_EL1_IDS_0X18 1
 354#define ID_AA64MMFR2_EL1_AT __BITS(35,32)
 355#define ID_AA64MMFR2_EL1_AT_NONE 0
 356#define ID_AA64MMFR2_EL1_AT_16BIT 1
 357#define ID_AA64MMFR2_EL1_ST __BITS(31,28)
 358#define ID_AA64MMFR2_EL1_ST_39 0
 359#define ID_AA64MMFR2_EL1_ST_48 1
 360#define ID_AA64MMFR2_EL1_NV __BITS(27,24)
 361#define ID_AA64MMFR2_EL1_NV_NONE 0
 362#define ID_AA64MMFR2_EL1_NV_HCR 1
 363#define ID_AA64MMFR2_EL1_NV_HCR_VNCR 2
 364#define ID_AA64MMFR2_EL1_CCIDX __BITS(23,20)
 365#define ID_AA64MMFR2_EL1_CCIDX_32BIT 0
 366#define ID_AA64MMFR2_EL1_CCIDX_64BIT 1
 367#define ID_AA64MMFR2_EL1_VARANGE __BITS(19,16)
 368#define ID_AA64MMFR2_EL1_VARANGE_48BIT 0
 369#define ID_AA64MMFR2_EL1_VARANGE_52BIT 1
 370#define ID_AA64MMFR2_EL1_IESB __BITS(15,12)
 371#define ID_AA64MMFR2_EL1_IESB_NONE 0
 372#define ID_AA64MMFR2_EL1_IESB_SUPPORTED 1
 373#define ID_AA64MMFR2_EL1_LSM __BITS(11,8)
 374#define ID_AA64MMFR2_EL1_LSM_NONE 0
 375#define ID_AA64MMFR2_EL1_LSM_SUPPORTED 1
 376#define ID_AA64MMFR2_EL1_UAO __BITS(7,4)
 377#define ID_AA64MMFR2_EL1_UAO_NONE 0
 378#define ID_AA64MMFR2_EL1_UAO_SUPPORTED 1
 379#define ID_AA64MMFR2_EL1_CNP __BITS(3,0)
 380#define ID_AA64MMFR2_EL1_CNP_NONE 0
 381#define ID_AA64MMFR2_EL1_CNP_SUPPORTED 1
 382
 383AARCH64REG_READ_INLINE2(a72_cpuactlr_el1, s3_1_c15_c2_0)
266AARCH64REG_READ_INLINE(id_aa64pfr0_el1) 384AARCH64REG_READ_INLINE(id_aa64pfr0_el1)
267AARCH64REG_READ_INLINE(id_aa64pfr1_el1) 385AARCH64REG_READ_INLINE(id_aa64pfr1_el1)
 386
 387#define ID_AA64PFR1_EL1_RASFRAC __BITS(15,12)
 388#define ID_AA64PFR1_EL1_RASFRAC_NORMAL 0
 389#define ID_AA64PFR1_EL1_RASFRAC_EXTRA 1
 390#define ID_AA64PFR1_EL1_MTE __BITS(11,8)
 391#define ID_AA64PFR1_EL1_MTE_NONE 0
 392#define ID_AA64PFR1_EL1_MTE_PARTIAL 1
 393#define ID_AA64PFR1_EL1_MTE_SUPPORTED 2
 394#define ID_AA64PFR1_EL1_SSBS __BITS(7,4)
 395#define ID_AA64PFR1_EL1_SSBS_NONE 0
 396#define ID_AA64PFR1_EL1_SSBS_SUPPORTED 1
 397#define ID_AA64PFR1_EL1_SSBS_MSR_MRS 2
 398#define ID_AA64PFR1_EL1_BT __BITS(3,0)
 399#define ID_AA64PFR1_EL1_BT_NONE 0
 400#define ID_AA64PFR1_EL1_BT_SUPPORTED 1
 401
268AARCH64REG_READ_INLINE(id_aa64zfr0_el1) 402AARCH64REG_READ_INLINE(id_aa64zfr0_el1)
269AARCH64REG_READ_INLINE(id_pfr1_el1) 403AARCH64REG_READ_INLINE(id_pfr1_el1)
270AARCH64REG_READ_INLINE(isr_el1) 404AARCH64REG_READ_INLINE(isr_el1)
271AARCH64REG_READ_INLINE(midr_el1) 405AARCH64REG_READ_INLINE(midr_el1)
272AARCH64REG_READ_INLINE(mpidr_el1) 406AARCH64REG_READ_INLINE(mpidr_el1)
273 407
274#define MIDR_EL1_IMPL __BITS(31,24) // Implementor 408#define MIDR_EL1_IMPL __BITS(31,24) // Implementor
275#define MIDR_EL1_VARIANT __BITS(23,20) // CPU Variant 409#define MIDR_EL1_VARIANT __BITS(23,20) // CPU Variant
276#define MIDR_EL1_ARCH __BITS(19,16) // Architecture 410#define MIDR_EL1_ARCH __BITS(19,16) // Architecture
277#define MIDR_EL1_PARTNUM __BITS(15,4) // PartNum 411#define MIDR_EL1_PARTNUM __BITS(15,4) // PartNum
278#define MIDR_EL1_REVISION __BITS(3,0) // Revision 412#define MIDR_EL1_REVISION __BITS(3,0) // Revision
279 413
280#define MPIDR_AFF3 __BITS(32,39) 414#define MPIDR_AFF3 __BITS(32,39)