 @@ -1,14 +1,14 @@
-/*	$NetBSD: aarch64.c,v 1.7 2019/05/09 07:38:44 mrg Exp $	*/
+/*	$NetBSD: aarch64.c,v 1.8 2020/01/28 17:36:42 maxv Exp $	*/
 /*
  * Copyright (c) 2018 Ryo Shimizu <ryo@nerv.org>
  * All rights reserved.
+ *
  * Redistribution and use in source and binary forms, with or without
  * modification, are permitted provided that the following conditions
  * are met:
  * 1. Redistributions of source code must retain the above copyright
  *    notice, this list of conditions and the following disclaimer.
  * 2. Redistributions in binary form must reproduce the above copyright
  *    notice, this list of conditions and the following disclaimer in the
  *    documentation and/or other materials provided with the distribution.
 @@ -19,27 +19,27 @@
  * DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT,
  * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
  * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
  * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
  * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
  * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
  * POSSIBILITY OF SUCH DAMAGE.
  */
 #include <sys/cdefs.h>
 #ifndef lint
-__RCSID("$NetBSD: aarch64.c,v 1.7 2019/05/09 07:38:44 mrg Exp $");
+__RCSID("$NetBSD: aarch64.c,v 1.8 2020/01/28 17:36:42 maxv Exp $");
 #endif /* no lint */
 #include <sys/types.h>
 #include <sys/cpuio.h>
 #include <sys/sysctl.h>
 #include <stdio.h>
 #include <stdbool.h>
 #include <stdlib.h>
 #include <string.h>
 #include <inttypes.h>
 #include <err.h>
 #include <arm/cputypes.h>
 @@ -148,26 +148,61 @@ struct fieldinfo id_aa64pfr0_fieldinfo[]
 			[15] = "No Advanced SIMD"
+		}
 	},
+	{
 		.bitpos = 24, .bitwidth = 4, .name = "GIC",
 		.info = (const char *[16]) { /* 16=4bit */
 			[0] = "No GIC",
 			[1] = "GICv3"
+		}
 	},
 	{ .bitwidth = 0 }	/* end of table */
 };
 /* ID_AA64PFR1_EL1 - AArch64 Processor Feature Register 1 */
 struct fieldinfo id_aa64pfr1_fieldinfo[] = {
+	{
 		.bitpos = 0, .bitwidth = 4, .name = "BT",
 		.info = (const char *[16]) { /* 16=4bit */
 			[0] = "Branch Target Identification not implemented",
 			[1] = "Branch Target Identification implemented",
+		}
 	},
+	{
 		.bitpos = 4, .bitwidth = 4, .name = "SSBS",
 		.info = (const char *[16]) { /* 16=4bit */
 			[0] = "Speculative Store Bypassing control not implemented",
 			[1] = "Speculative Store Bypassing control implemented",
 			[2] = "Speculative Store Bypassing control implemented, plus MSR/MRS"
+		}
 	},
+	{
 		.bitpos = 8, .bitwidth = 4, .name = "MTE",
 		.info = (const char *[16]) { /* 16=4bit */
 			[0] = "Tagged Memory Extension not implemented",
 			[1] = "Tagged Memory Extension implemented, EL0 only",
 			[2] = "Tagged Memory Extension implemented"
+		}
 	},
+	{
 		.bitpos = 12, .bitwidth = 4, .name = "RAS_frac",
 		.info = (const char *[16]) { /* 16=4bit */
 			[0] = "Regular RAS",
 			[1] = "RAS plus registers",
+		}
 	},
 	{ .bitwidth = 0 }	/* end of table */
 };
 /* ID_AA64ISAR0_EL1 - AArch64 Instruction Set Attribute Register 0 */
 struct fieldinfo id_aa64isar0_fieldinfo[] = {
+	{
 		.bitpos = 4, .bitwidth = 4, .name = "AES",
 		.info = (const char *[16]) { /* 16=4bit */
 			[0] = "No AES",
 			[1] = "AESE/AESD/AESMC/AESIMC",
 			[2] = "AESE/AESD/AESMC/AESIMC+PMULL/PMULL2"
+		}
 	},
+	{
 		.bitpos = 8, .bitwidth = 4, .name = "SHA1",
 		.info = (const char *[16]) { /* 16=4bit */
 @@ -248,26 +283,90 @@ struct fieldinfo id_aa64mmfr0_fieldinfo[
 			[15] = "No 64KB granule"
+		}
 	},
+	{
 		.bitpos = 28, .bitwidth = 4, .name = "TGran4",
 		.info = (const char *[16]) { /* 16=4bit */
 			[0] = "4KB granule",
 			[15] = "No 4KB granule"
+		}
 	},
 	{ .bitwidth = 0 }	/* end of table */
 };
 /* ID_AA64MMFR1_EL1 - AArch64 Memory Model Feature Register 1 */
 struct fieldinfo id_aa64mmfr1_fieldinfo[] = {
+	{
 		.bitpos = 0, .bitwidth = 4, .name = "HAFDBS",
 		.info = (const char *[16]) { /* 16=4bit */
 			[0] = "Access and Dirty flags not supported",
 			[1] = "Access flag supported",
 			[2] = "Access and Dirty flags supported",
+		}
 	},
+	{
 		.bitpos = 4, .bitwidth = 4, .name = "VMIDBits",
 		.info = (const char *[16]) { /* 16=4bit */
 			[0] = "8bits",
 			[2] = "16bits"
+		}
 	},
+	{
 		.bitpos = 8, .bitwidth = 4, .name = "VH",
 		.info = (const char *[16]) { /* 16=4bit */
 			[0] = "Virtualization Host Extensions not supported",
 			[1] = "Virtualization Host Extensions supported",
+		}
 	},
+	{
 		.bitpos = 12, .bitwidth = 4, .name = "HPDS",
 		.info = (const char *[16]) { /* 16=4bit */
 			[0] = "Disabling of hierarchical controls not supported",
 			[1] = "Disabling of hierarchical controls supported",
 			[2] = "Disabling of hierarchical controls supported, plus PTD"
+		}
 	},
+	{
 		.bitpos = 16, .bitwidth = 4, .name = "LO",
 		.info = (const char *[16]) { /* 16=4bit */
 			[0] = "LORegions not supported",
 			[1] = "LORegions supported"
+		}
 	},
+	{
 		.bitpos = 20, .bitwidth = 4, .name = "PAN",
 		.info = (const char *[16]) { /* 16=4bit */
 			[0] = "PAN not supported",
 			[1] = "PAN supported",
 			[2] = "PAN supported, and instructions supported"
+		}
 	},
+	{
 		.bitpos = 24, .bitwidth = 4, .name = "SpecSEI",
 		.info = (const char *[16]) { /* 16=4bit */
 			[0] = "SError interrupt not supported",
 			[1] = "SError interrupt supported"
+		}
 	},
+	{
 		.bitpos = 28, .bitwidth = 4, .name = "XNX",
 		.info = (const char *[16]) { /* 16=4bit */
 			[0] = "Distinction between EL0 and EL1 XN control at stage 2 not supported",
 			[1] = "Distinction between EL0 and EL1 XN control at stage 2 supported"
+		}
 	},
 	{ .bitwidth = 0 }	/* end of table */
 };
 /* ID_AA64DFR0_EL1 - AArch64 Debug Feature Register 0 */
 struct fieldinfo id_aa64dfr0_fieldinfo[] = {
+	{
 		.bitpos = 0, .bitwidth = 4, .name = "DebugVer",
 		.info = (const char *[16]) { /* 16=4bit */
 			[6] = "v8-A debug architecture"
+		}
 	},
+	{
 		.bitpos = 4, .bitwidth = 4, .name = "TraceVer",
 		.info = (const char *[16]) { /* 16=4bit */
 			[0] = "Trace supported",
 			[1] = "Trace not supported"
 @@ -600,28 +699,32 @@ identifycpu(int fd, const char *cpuname)
 		printf("%s: MVFR1_EL1: 0x%08"PRIx32"\n",
 		    cpuname, id->ac_mvfr1);
 		printf("%s: MVFR2_EL1: 0x%08"PRIx32"\n",
 		    cpuname, id->ac_mvfr2);
+	}
 	identify_midr(cpuname, id->ac_midr);
 	identify_revidr(cpuname, id->ac_revidr);
 	identify_mpidr(cpuname, id->ac_mpidr);
 	print_fieldinfo(cpuname, "isa features 0",
 	    id_aa64isar0_fieldinfo, id->ac_aa64isar0);
 	print_fieldinfo(cpuname, "memory model 0",
 	    id_aa64mmfr0_fieldinfo, id->ac_aa64mmfr0);
 	print_fieldinfo(cpuname, "memory model 1",
 	    id_aa64mmfr1_fieldinfo, id->ac_aa64mmfr1);
 	print_fieldinfo(cpuname, "processor feature 0",
 	    id_aa64pfr0_fieldinfo, id->ac_aa64pfr0);
 	print_fieldinfo(cpuname, "processor feature 1",
 	    id_aa64pfr1_fieldinfo, id->ac_aa64pfr1);
 	identify_dfr0(cpuname, id->ac_aa64dfr0);
 	print_fieldinfo(cpuname, "media and VFP features 0",
 	    mvfr0_fieldinfo, id->ac_mvfr0);
 	print_fieldinfo(cpuname, "media and VFP features 1",
 	    mvfr1_fieldinfo, id->ac_mvfr1);
 	print_fieldinfo(cpuname, "media and VFP features 2",
 	    mvfr2_fieldinfo, id->ac_mvfr2);
+}
 bool
 identifycpu_bind(void)
+{