 @@ -1,1513 +1,1513 @@
-/* $NetBSD: bwfm.c,v 1.19 2019/12/27 09:22:20 msaitoh Exp $ */
+/* $NetBSD: bwfm.c,v 1.20 2020/01/29 14:14:55 thorpej Exp $ */
 /* $OpenBSD: bwfm.c,v 1.5 2017/10/16 22:27:16 patrick Exp $ */
 /*
  * Copyright (c) 2010-2016 Broadcom Corporation
  * Copyright (c) 2016,2017 Patrick Wildt <patrick@blueri.se>
+ *
  * Permission to use, copy, modify, and/or distribute this software for any
  * purpose with or without fee is hereby granted, provided that the above
  * copyright notice and this permission notice appear in all copies.
+ *
  * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
  * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
  * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
  * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
  * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
  * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
  * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
  */
 #include <sys/param.h>
 #include <sys/systm.h>
 #include <sys/buf.h>
 #include <sys/kernel.h>
 #include <sys/device.h>
 #include <sys/queue.h>
 #include <sys/socket.h>
 #include <sys/kmem.h>
 #include <sys/workqueue.h>
 #include <sys/pcq.h>
 #include <net/bpf.h>
 #include <net/if.h>
 #include <net/if_dl.h>
 #include <net/if_media.h>
 #include <net/if_ether.h>
 #include <netinet/in.h>
 #include <net80211/ieee80211_var.h>
 #include <dev/ic/bwfmvar.h>
 #include <dev/ic/bwfmreg.h>
 /* #define BWFM_DEBUG */
 #ifdef BWFM_DEBUG
 #define DPRINTF(x)	do { if (bwfm_debug > 0) printf x; } while (0)
 #define DPRINTFN(n, x)	do { if (bwfm_debug >= (n)) printf x; } while (0)
 static int bwfm_debug = 1;
 #else
 #define DPRINTF(x)	do { ; } while (0)
 #define DPRINTFN(n, x)	do { ; } while (0)
 #endif
 #define DEVNAME(sc)	device_xname((sc)->sc_dev)
 void	 bwfm_start(struct ifnet *);
 int	 bwfm_init(struct ifnet *);
 void	 bwfm_stop(struct ifnet *, int);
 void	 bwfm_watchdog(struct ifnet *);
 int	 bwfm_ioctl(struct ifnet *, u_long, void *);
 int	 bwfm_media_change(struct ifnet *);
 int	 bwfm_send_mgmt(struct ieee80211com *, struct ieee80211_node *,
 	     int, int);
 void	 bwfm_recv_mgmt(struct ieee80211com *, struct mbuf *,
 	     struct ieee80211_node *, int, int, uint32_t);
 int	 bwfm_key_set(struct ieee80211com *, const struct ieee80211_key *,
 	     const uint8_t *);
 int	 bwfm_key_delete(struct ieee80211com *, const struct ieee80211_key *);
 int	 bwfm_newstate(struct ieee80211com *, enum ieee80211_state, int);
 void	 bwfm_newstate_cb(struct bwfm_softc *, struct bwfm_cmd_newstate *);
 void	 bwfm_newassoc(struct ieee80211_node *, int);
 void	 bwfm_task(struct work *, void *);
 int	 bwfm_chip_attach(struct bwfm_softc *);
 int	 bwfm_chip_detach(struct bwfm_softc *, int);
 struct bwfm_core *bwfm_chip_get_core(struct bwfm_softc *, int);
 struct bwfm_core *bwfm_chip_get_pmu(struct bwfm_softc *);
 int	 bwfm_chip_ai_isup(struct bwfm_softc *, struct bwfm_core *);
 void	 bwfm_chip_ai_disable(struct bwfm_softc *, struct bwfm_core *,
 	     uint32_t, uint32_t);
 void	 bwfm_chip_ai_reset(struct bwfm_softc *, struct bwfm_core *,
 	     uint32_t, uint32_t, uint32_t);
 void	 bwfm_chip_dmp_erom_scan(struct bwfm_softc *);
 int	 bwfm_chip_dmp_get_regaddr(struct bwfm_softc *, uint32_t *,
 	     uint32_t *, uint32_t *);
 int	 bwfm_chip_cr4_set_active(struct bwfm_softc *, const uint32_t);
 void	 bwfm_chip_cr4_set_passive(struct bwfm_softc *);
 int	 bwfm_chip_ca7_set_active(struct bwfm_softc *, const uint32_t);
 void	 bwfm_chip_ca7_set_passive(struct bwfm_softc *);
 int	 bwfm_chip_cm3_set_active(struct bwfm_softc *);
 void	 bwfm_chip_cm3_set_passive(struct bwfm_softc *);
 void	 bwfm_chip_socram_ramsize(struct bwfm_softc *, struct bwfm_core *);
 void	 bwfm_chip_sysmem_ramsize(struct bwfm_softc *, struct bwfm_core *);
 void	 bwfm_chip_tcm_ramsize(struct bwfm_softc *, struct bwfm_core *);
 void	 bwfm_chip_tcm_rambase(struct bwfm_softc *);
 int	 bwfm_proto_bcdc_query_dcmd(struct bwfm_softc *, int,
 	     int, char *, size_t *);
 int	 bwfm_proto_bcdc_set_dcmd(struct bwfm_softc *, int,
 	     int, char *, size_t);
 int	 bwfm_fwvar_cmd_get_data(struct bwfm_softc *, int, void *, size_t);
 int	 bwfm_fwvar_cmd_set_data(struct bwfm_softc *, int, void *, size_t);
 int	 bwfm_fwvar_cmd_get_int(struct bwfm_softc *, int, uint32_t *);
 int	 bwfm_fwvar_cmd_set_int(struct bwfm_softc *, int, uint32_t);
 int	 bwfm_fwvar_var_get_data(struct bwfm_softc *, const char *, void *, size_t);
 int	 bwfm_fwvar_var_set_data(struct bwfm_softc *, const char *, void *, size_t);
 int	 bwfm_fwvar_var_get_int(struct bwfm_softc *, const char *, uint32_t *);
 int	 bwfm_fwvar_var_set_int(struct bwfm_softc *, const char *, uint32_t);
 struct ieee80211_channel *bwfm_bss2chan(struct bwfm_softc *, struct bwfm_bss_info *);
 void	 bwfm_scan(struct bwfm_softc *);
 void	 bwfm_connect(struct bwfm_softc *);
 void	 bwfm_get_sta_info(struct bwfm_softc *, struct ifmediareq *);
 void	 bwfm_rx(struct bwfm_softc *, struct mbuf *);
 void	 bwfm_rx_event(struct bwfm_softc *, struct mbuf *);
 void	 bwfm_rx_event_cb(struct bwfm_softc *, struct mbuf *);
 void	 bwfm_scan_node(struct bwfm_softc *, struct bwfm_bss_info *, size_t);
 uint8_t bwfm_2ghz_channels[] = {
 , 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13,
 };
 uint8_t bwfm_5ghz_channels[] = {
 , 36, 38, 40, 42, 44, 46, 48, 52, 56, 60, 64, 100, 104, 108, 112,
 , 120, 124, 128, 132, 136, 140, 144, 149, 153, 157, 161, 165,
 };
 struct bwfm_proto_ops bwfm_proto_bcdc_ops = {
 	.proto_query_dcmd = bwfm_proto_bcdc_query_dcmd,
 	.proto_set_dcmd = bwfm_proto_bcdc_set_dcmd,
 };
 void
 bwfm_attach(struct bwfm_softc *sc)
+{
 	struct ieee80211com *ic = &sc->sc_ic;
 	struct ifnet *ifp = &sc->sc_if;
 	struct bwfm_task *t;
 	char fw_version[BWFM_DCMD_SMLEN];
 	uint32_t bandlist[3];
 	uint32_t tmp;
 	int i, j, error;
 	error = workqueue_create(&sc->sc_taskq, DEVNAME(sc),
 	    bwfm_task, sc, PRI_NONE, IPL_NET, 0);
 	if (error != 0) {
 		printf("%s: could not create workqueue\n", DEVNAME(sc));
 		return;
+	}
 	sc->sc_freetask = pcq_create(BWFM_TASK_COUNT, KM_SLEEP);
 	for (i = 0; i < BWFM_TASK_COUNT; i++) {
 		t = &sc->sc_task[i];
 		t->t_sc = sc;
 		pcq_put(sc->sc_freetask, t);
+	}
 	/* Stop the device in case it was previously initialized */
 	bwfm_fwvar_cmd_set_int(sc, BWFM_C_DOWN, 1);
 	if (bwfm_fwvar_cmd_get_int(sc, BWFM_C_GET_VERSION, &tmp)) {
 		printf("%s: could not read io type\n", DEVNAME(sc));
 		return;
 	} else
 		sc->sc_io_type = tmp;
 	if (bwfm_fwvar_var_get_data(sc, "cur_etheraddr", ic->ic_myaddr,
 	    sizeof(ic->ic_myaddr))) {
 		printf("%s: could not read mac address\n", DEVNAME(sc));
 		return;
+	}
 	memset(fw_version, 0, sizeof(fw_version));
 	if (bwfm_fwvar_var_get_data(sc, "ver", fw_version, sizeof(fw_version)) == 0)
 		printf("%s: %s", DEVNAME(sc), fw_version);
 	printf("%s: address %s\n", DEVNAME(sc), ether_sprintf(ic->ic_myaddr));
 	ic->ic_ifp = ifp;
 	ic->ic_phytype = IEEE80211_T_OFDM;
 	ic->ic_opmode = IEEE80211_M_STA;
 	ic->ic_state = IEEE80211_S_INIT;
 	ic->ic_caps =
 	    IEEE80211_C_WEP |
 	    IEEE80211_C_TKIP |
 	    IEEE80211_C_AES |
 	    IEEE80211_C_AES_CCM |
 #if notyet
 	    IEEE80211_C_MONITOR |		/* monitor mode supported */
 	    IEEE80211_C_IBSS |
 	    IEEE80211_C_TXPMGT |
 	    IEEE80211_C_WME |
 #endif
 	    IEEE80211_C_SHSLOT |		/* short slot time supported */
 	    IEEE80211_C_SHPREAMBLE |		/* short preamble supported */
 	    IEEE80211_C_WPA |			/* 802.11i */
 	    /* IEEE80211_C_WPA_4WAY */0;		/* WPA 4-way handshake in hw */
 	/* IBSS channel undefined for now. */
 	ic->ic_ibss_chan = &ic->ic_channels[0];
 	if (bwfm_fwvar_cmd_get_data(sc, BWFM_C_GET_BANDLIST, bandlist,
 	    sizeof(bandlist))) {
 		printf("%s: couldn't get supported band list\n", DEVNAME(sc));
 		return;
+	}
 	const u_int nbands = le32toh(bandlist[0]);
 	for (i = 1; i <= MIN(nbands, __arraycount(bandlist) - 1); i++) {
 		switch (le32toh(bandlist[i])) {
 		case BWFM_BAND_2G:
 			ic->ic_sup_rates[IEEE80211_MODE_11B] = ieee80211_std_rateset_11b;
 			ic->ic_sup_rates[IEEE80211_MODE_11G] = ieee80211_std_rateset_11g;
 			for (j = 0; j < __arraycount(bwfm_2ghz_channels); j++) {
 				uint8_t chan = bwfm_2ghz_channels[j];
 				ic->ic_channels[chan].ic_freq =
 				    ieee80211_ieee2mhz(chan, IEEE80211_CHAN_2GHZ);
 				ic->ic_channels[chan].ic_flags =
 				    IEEE80211_CHAN_CCK | IEEE80211_CHAN_OFDM |
 				    IEEE80211_CHAN_DYN | IEEE80211_CHAN_2GHZ;
+			}
 			break;
 		case BWFM_BAND_5G:
 			ic->ic_sup_rates[IEEE80211_MODE_11A] = ieee80211_std_rateset_11a;
 			for (j = 0; j < __arraycount(bwfm_5ghz_channels); j++) {
 				uint8_t chan = bwfm_5ghz_channels[j];
 				ic->ic_channels[chan].ic_freq =
 				    ieee80211_ieee2mhz(chan, IEEE80211_CHAN_5GHZ);
 				ic->ic_channels[chan].ic_flags =
 				    IEEE80211_CHAN_A;
+			}
 			break;
+		}
+	}
 	ifp->if_softc = sc;
 	ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST;
 	ifp->if_init = bwfm_init;
 	ifp->if_ioctl = bwfm_ioctl;
 	ifp->if_start = bwfm_start;
 	ifp->if_stop = bwfm_stop;
 	ifp->if_watchdog = bwfm_watchdog;
 	IFQ_SET_READY(&ifp->if_snd);
 	memcpy(ifp->if_xname, DEVNAME(sc), IFNAMSIZ);
 	error = if_initialize(ifp);
 	if (error != 0) {
 		printf("%s: if_initialize failed(%d)\n", DEVNAME(sc), error);
 		pcq_destroy(sc->sc_freetask);
 		workqueue_destroy(sc->sc_taskq);
 		return; /* Error */
+	}
 	ieee80211_ifattach(ic);
 	ifp->if_percpuq = if_percpuq_create(ifp);
 	if_deferred_start_init(ifp, NULL);
 	if_register(ifp);
 	sc->sc_newstate = ic->ic_newstate;
 	ic->ic_newstate = bwfm_newstate;
 	ic->ic_newassoc = bwfm_newassoc;
 	ic->ic_send_mgmt = bwfm_send_mgmt;
 	ic->ic_recv_mgmt = bwfm_recv_mgmt;
 	ic->ic_crypto.cs_key_set = bwfm_key_set;
 	ic->ic_crypto.cs_key_delete = bwfm_key_delete;
 	ieee80211_media_init(ic, bwfm_media_change, ieee80211_media_status);
 	ieee80211_announce(ic);
 	sc->sc_if_attached = true;
+}
 int
 bwfm_detach(struct bwfm_softc *sc, int flags)
+{
 	struct ieee80211com *ic = &sc->sc_ic;
 	struct ifnet *ifp = ic->ic_ifp;
 	if (sc->sc_if_attached) {
 		bpf_detach(ifp);
 		ieee80211_ifdetach(ic);
 		if_detach(ifp);
+	}
 	if (sc->sc_taskq)
 		workqueue_destroy(sc->sc_taskq);
 	if (sc->sc_freetask)
 		pcq_destroy(sc->sc_freetask);
 	return 0;
+}
 void
 bwfm_start(struct ifnet *ifp)
+{
 	struct bwfm_softc *sc = ifp->if_softc;
 	struct ieee80211com *ic = &sc->sc_ic;
 	struct mbuf *m;
 	int error;
 	if ((ifp->if_flags & (IFF_RUNNING | IFF_OACTIVE)) != IFF_RUNNING)
 		return;
 	/* TODO: return if no link? */
 	for (;;) {
 		/* Discard management packets (fw handles this for us) */
 		IF_DEQUEUE(&ic->ic_mgtq, m);
 		if (m != NULL) {
 			m_freem(m);
 			continue;
+		}
 		if (sc->sc_bus_ops->bs_txcheck(sc)) {
 			ifp->if_flags |= IFF_OACTIVE;
 			break;
+		}
 		IFQ_DEQUEUE(&ifp->if_snd, m);
 		if (m == NULL)
 			break;
 		error = sc->sc_bus_ops->bs_txdata(sc, &m);
 		if (error == ENOBUFS) {
 			IF_PREPEND(&ifp->if_snd, m);
 			ifp->if_flags |= IFF_OACTIVE;
 			break;
+		}
 		if (error != 0) {
-			ifp->if_oerrors++;
+			if_statinc(ifp, if_oerrors);
 			m_freem(m);
 			continue;
+		}
 		bpf_mtap(ifp, m, BPF_D_OUT);
+	}
+}
 int
 bwfm_init(struct ifnet *ifp)
+{
 	struct bwfm_softc *sc = ifp->if_softc;
 	struct ieee80211com *ic = &sc->sc_ic;
 	uint8_t evmask[BWFM_EVENT_MASK_LEN];
 	struct bwfm_join_pref_params join_pref[2];
 	int pm;
 	if (bwfm_fwvar_var_set_int(sc, "mpc", 1)) {
 		printf("%s: could not set mpc\n", DEVNAME(sc));
 		return EIO;
+	}
 	/* Select target by RSSI (boost on 5GHz) */
 	join_pref[0].type = BWFM_JOIN_PREF_RSSI_DELTA;
 	join_pref[0].len = 2;
 	join_pref[0].rssi_gain = BWFM_JOIN_PREF_RSSI_BOOST;
 	join_pref[0].band = BWFM_JOIN_PREF_BAND_5G;
 	join_pref[1].type = BWFM_JOIN_PREF_RSSI;
 	join_pref[1].len = 2;
 	join_pref[1].rssi_gain = 0;
 	join_pref[1].band = 0;
 	if (bwfm_fwvar_var_set_data(sc, "join_pref", join_pref,
 	    sizeof(join_pref))) {
 		printf("%s: could not set join pref\n", DEVNAME(sc));
 		return EIO;
+	}
 	memset(evmask, 0, sizeof(evmask));
 #define	ENABLE_EVENT(e)		evmask[(e) / 8] |= 1 << ((e) % 8)
 	/* Events used to drive the state machine */
 	switch (ic->ic_opmode) {
 	case IEEE80211_M_STA:
 		ENABLE_EVENT(BWFM_E_IF);
 		ENABLE_EVENT(BWFM_E_LINK);
 		ENABLE_EVENT(BWFM_E_AUTH);
 		ENABLE_EVENT(BWFM_E_ASSOC);
 		ENABLE_EVENT(BWFM_E_DEAUTH);
 		ENABLE_EVENT(BWFM_E_DISASSOC);
 		ENABLE_EVENT(BWFM_E_SET_SSID);
 		ENABLE_EVENT(BWFM_E_ESCAN_RESULT);
 		break;
 #ifndef IEEE80211_STA_ONLY
 	case IEEE80211_M_HOSTAP:
 		ENABLE_EVENT(BWFM_E_AUTH_IND);
 		ENABLE_EVENT(BWFM_E_ASSOC_IND);
 		ENABLE_EVENT(BWFM_E_REASSOC_IND);
 		ENABLE_EVENT(BWFM_E_DEAUTH_IND);
 		ENABLE_EVENT(BWFM_E_DISASSOC_IND);
 		ENABLE_EVENT(BWFM_E_ESCAN_RESULT);
 		ENABLE_EVENT(BWFM_E_ESCAN_RESULT);
 		break;
 #endif
 	default:
 		break;
+	}
 #undef	ENABLE_EVENT
 #ifdef BWFM_DEBUG
 	memset(evmask, 0xff, sizeof(evmask));
 #endif
 	if (bwfm_fwvar_var_set_data(sc, "event_msgs", evmask, sizeof(evmask))) {
 		printf("%s: could not set event mask\n", DEVNAME(sc));
 		return EIO;
+	}
 	if (bwfm_fwvar_cmd_set_int(sc, BWFM_C_SET_SCAN_CHANNEL_TIME,
 	    BWFM_DEFAULT_SCAN_CHANNEL_TIME)) {
 		printf("%s: could not set scan channel time\n", DEVNAME(sc));
 		return EIO;
+	}
 	if (bwfm_fwvar_cmd_set_int(sc, BWFM_C_SET_SCAN_UNASSOC_TIME,
 	    BWFM_DEFAULT_SCAN_UNASSOC_TIME)) {
 		printf("%s: could not set scan unassoc time\n", DEVNAME(sc));
 		return EIO;
+	}
 	if (bwfm_fwvar_cmd_set_int(sc, BWFM_C_SET_SCAN_PASSIVE_TIME,
 	    BWFM_DEFAULT_SCAN_PASSIVE_TIME)) {
 		printf("%s: could not set scan passive time\n", DEVNAME(sc));
 		return EIO;
+	}
         /*
          * Use CAM (constantly awake) when we are running as AP
          * otherwise use fast power saving.
          */
 	pm = BWFM_PM_FAST_PS;
 #ifndef IEEE80211_STA_ONLY
 	if (ic->ic_opmode == IEEE80211_M_HOSTAP)
 		pm = BWFM_PM_CAM;
 #endif
 	if (bwfm_fwvar_cmd_set_int(sc, BWFM_C_SET_PM, pm)) {
 		printf("%s: could not set power\n", DEVNAME(sc));
 		return EIO;
+	}
 	bwfm_fwvar_var_set_int(sc, "txbf", 1);
 	bwfm_fwvar_cmd_set_int(sc, BWFM_C_UP, 0);
 	bwfm_fwvar_cmd_set_int(sc, BWFM_C_SET_INFRA, 1);
 	bwfm_fwvar_cmd_set_int(sc, BWFM_C_SET_AP, 0);
 	/* Disable all offloading (ARP, NDP, TCP/UDP cksum). */
 	bwfm_fwvar_var_set_int(sc, "arp_ol", 0);
 	bwfm_fwvar_var_set_int(sc, "arpoe", 0);
 	bwfm_fwvar_var_set_int(sc, "ndoe", 0);
 	bwfm_fwvar_var_set_int(sc, "toe", 0);
 	/* Accept all multicast frames. */
 	bwfm_fwvar_var_set_int(sc, "allmulti", 1);
 	/* Setup promiscuous mode */
 	bwfm_fwvar_cmd_set_int(sc, BWFM_C_SET_PROMISC,
 	    (ifp->if_flags & IFF_PROMISC) ? 1 : 0);
 	/*
 	 * Tell the firmware supplicant that we are going to handle the
 	 * WPA handshake ourselves.
 	 */
 	bwfm_fwvar_var_set_int(sc, "sup_wpa", 0);
 	ifp->if_flags |= IFF_RUNNING;
 	ifp->if_flags &= ~IFF_OACTIVE;
 	if (ic->ic_opmode != IEEE80211_M_MONITOR) {
 		if (ic->ic_roaming != IEEE80211_ROAMING_MANUAL)
 			ieee80211_new_state(ic, IEEE80211_S_SCAN, -1);
 	} else {
 		ieee80211_new_state(ic, IEEE80211_S_RUN, -1);
+	}
 	return 0;
+}
 void
 bwfm_stop(struct ifnet *ifp, int disable)
+{
 	struct bwfm_softc *sc = ifp->if_softc;
 	struct ieee80211com *ic = &sc->sc_ic;
 	struct bwfm_join_params join;
 	sc->sc_tx_timer = 0;
 	ifp->if_timer = 0;
 	ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE);
 	memset(&join, 0, sizeof(join));
 	bwfm_fwvar_cmd_set_data(sc, BWFM_C_SET_SSID, &join, sizeof(join));
 	bwfm_fwvar_cmd_set_int(sc, BWFM_C_DOWN, 1);
 	bwfm_fwvar_cmd_set_int(sc, BWFM_C_SET_PM, 0);
 	bwfm_fwvar_cmd_set_int(sc, BWFM_C_SET_AP, 0);
 	bwfm_fwvar_cmd_set_int(sc, BWFM_C_SET_INFRA, 0);
 	bwfm_fwvar_cmd_set_int(sc, BWFM_C_UP, 1);
 	bwfm_fwvar_cmd_set_int(sc, BWFM_C_SET_PM, BWFM_PM_FAST_PS);
 	ieee80211_new_state(ic, IEEE80211_S_INIT, -1);
 	if (sc->sc_bus_ops->bs_stop)
 		sc->sc_bus_ops->bs_stop(sc);
+}
 void
 bwfm_watchdog(struct ifnet *ifp)
+{
 	struct bwfm_softc *sc = ifp->if_softc;
 	struct ieee80211com *ic = &sc->sc_ic;
 	ifp->if_timer = 0;
 	if (sc->sc_tx_timer > 0) {
 		if (--sc->sc_tx_timer == 0) {
 			printf("%s: device timeout\n", DEVNAME(sc));
-			ifp->if_oerrors++;
+			if_statinc(ifp, if_oerrors);
 			return;
+		}
 		ifp->if_timer = 1;
+	}
 	ieee80211_watchdog(ic);
+}
 int
 bwfm_ioctl(struct ifnet *ifp, u_long cmd, void *data)
+{
 	struct bwfm_softc *sc = ifp->if_softc;
 	struct ieee80211com *ic = &sc->sc_ic;
 	int s, error = 0;
 	s = splnet();
 	switch (cmd) {
 	case SIOCSIFFLAGS:
 		if ((error = ifioctl_common(ifp, cmd, data)) != 0)
 			break;
 		switch (ifp->if_flags & (IFF_UP | IFF_RUNNING)) {
 		case IFF_UP | IFF_RUNNING:
 			break;
 		case IFF_UP:
 			bwfm_init(ifp);
 			break;
 		case IFF_RUNNING:
 			bwfm_stop(ifp, 1);
 			break;
 		case 0:
 			break;
+		}
 		break;
 	case SIOCADDMULTI:
 	case SIOCDELMULTI:
 		if ((error = ether_ioctl(ifp, cmd, data)) == ENETRESET) {
 			/* setup multicast filter, etc */
 			error = 0;
+		}
 		break;
 	case SIOCGIFMEDIA:
 		error = ieee80211_ioctl(ic, cmd, data);
 		if (error == 0 && ic->ic_state == IEEE80211_S_RUN)
 			bwfm_get_sta_info(sc, (struct ifmediareq *)data);
 		break;
 	default:
 		error = ieee80211_ioctl(ic, cmd, data);
+	}
 	if (error == ENETRESET) {
 		if ((ifp->if_flags & IFF_UP) != 0 &&
 		    (ifp->if_flags & IFF_RUNNING) != 0 &&
 		    ic->ic_roaming != IEEE80211_ROAMING_MANUAL) {
 			bwfm_init(ifp);
+		}
 		error = 0;
+	}
 	splx(s);
 	return error;
+}
 int
 bwfm_send_mgmt(struct ieee80211com *ic, struct ieee80211_node *ni,
     int type, int arg)
+{
 	return 0;
+}
 void
 bwfm_recv_mgmt(struct ieee80211com *ic, struct mbuf *m0,
     struct ieee80211_node *ni, int subtype, int rssi, uint32_t rstamp)
+{
+}
 int
 bwfm_key_set(struct ieee80211com *ic, const struct ieee80211_key *wk,
     const uint8_t mac[IEEE80211_ADDR_LEN])
+{
 	struct bwfm_softc *sc = ic->ic_ifp->if_softc;
 	struct bwfm_task *t;
 	t = pcq_get(sc->sc_freetask);
 	if (t == NULL) {
 		printf("%s: no free tasks\n", DEVNAME(sc));
 		return 0;
+	}
 	t->t_cmd = BWFM_TASK_KEY_SET;
 	t->t_key.key = wk;
 	memcpy(t->t_key.mac, mac, sizeof(t->t_key.mac));
 	workqueue_enqueue(sc->sc_taskq, (struct work *)t, NULL);
 	return 1;
+}
 static void
 bwfm_key_set_cb(struct bwfm_softc *sc, struct bwfm_cmd_key *ck)
+{
 	const struct ieee80211_key *wk = ck->key;
 	const uint8_t *mac = ck->mac;
 	struct bwfm_wsec_key wsec_key;
 	uint32_t wsec_enable, wsec;
 	bool ext_key;
 #ifdef BWFM_DEBUG
 	printf("key_set: key cipher %s len %d: ", wk->wk_cipher->ic_name, wk->wk_keylen);
 	for (int j = 0; j < sizeof(wk->wk_key); j++)
 		printf("%02x", wk->wk_key[j]);
 #endif
 	if ((wk->wk_flags & IEEE80211_KEY_GROUP) == 0 &&
 	    wk->wk_cipher->ic_cipher != IEEE80211_CIPHER_WEP) {
 		ext_key = true;
 	} else {
 		ext_key = false;
+	}
 #ifdef BWFM_DEBUG
 	printf(", ext_key = %d", ext_key);
 	printf(", mac = %02x:%02x:%02x:%02x:%02x:%02x",
 	    mac[0], mac[1], mac[2], mac[3], mac[4], mac[5]);
 	printf("\n");
 #endif
 	memset(&wsec_key, 0, sizeof(wsec_key));
 	if (ext_key && !IEEE80211_IS_MULTICAST(mac))
 		memcpy(wsec_key.ea, mac, sizeof(wsec_key.ea));
 	wsec_key.index = htole32(wk->wk_keyix);
 	wsec_key.len = htole32(wk->wk_keylen);
 	memcpy(wsec_key.data, wk->wk_key, sizeof(wsec_key.data));
 	if (!ext_key)
 		wsec_key.flags = htole32(BWFM_WSEC_PRIMARY_KEY);
 	switch (wk->wk_cipher->ic_cipher) {
 	case IEEE80211_CIPHER_WEP:
 		if (wk->wk_keylen == 5)
 			wsec_key.algo = htole32(BWFM_CRYPTO_ALGO_WEP1);
 		else if (wk->wk_keylen == 13)
 			wsec_key.algo = htole32(BWFM_CRYPTO_ALGO_WEP128);
 		else
 			return;
 		wsec_enable = BWFM_WSEC_WEP;
 		break;
 	case IEEE80211_CIPHER_TKIP:
 		wsec_key.algo = htole32(BWFM_CRYPTO_ALGO_TKIP);
 		wsec_enable = BWFM_WSEC_TKIP;
 		break;
 	case IEEE80211_CIPHER_AES_CCM:
 		wsec_key.algo = htole32(BWFM_CRYPTO_ALGO_AES_CCM);
 		wsec_enable = BWFM_WSEC_AES;
 		break;
 	default:
 		printf("%s: %s: cipher %s not supported\n", DEVNAME(sc),
 		    __func__, wk->wk_cipher->ic_name);
 		return;
+	}
 	if (bwfm_fwvar_var_set_data(sc, "wsec_key", &wsec_key, sizeof(wsec_key)))
 		return;
 	bwfm_fwvar_var_set_int(sc, "wpa_auth", BWFM_WPA_AUTH_WPA2_PSK);
 	bwfm_fwvar_var_get_int(sc, "wsec", &wsec);
 	wsec |= wsec_enable;
 	bwfm_fwvar_var_set_int(sc, "wsec", wsec);
+}
 int
 bwfm_key_delete(struct ieee80211com *ic, const struct ieee80211_key *wk)
+{
 	struct bwfm_softc *sc = ic->ic_ifp->if_softc;
 	struct bwfm_task *t;
 	t = pcq_get(sc->sc_freetask);
 	if (t == NULL) {
 		printf("%s: no free tasks\n", DEVNAME(sc));
 		return 0;
+	}
 	t->t_cmd = BWFM_TASK_KEY_DELETE;
 	t->t_key.key = wk;
 	memset(t->t_key.mac, 0, sizeof(t->t_key.mac));
 	workqueue_enqueue(sc->sc_taskq, (struct work *)t, NULL);
 	return 1;
+}
 static void
 bwfm_key_delete_cb(struct bwfm_softc *sc, struct bwfm_cmd_key *ck)
+{
 	const struct ieee80211_key *wk = ck->key;
 	struct bwfm_wsec_key wsec_key;
 	memset(&wsec_key, 0, sizeof(wsec_key));
 	wsec_key.index = htole32(wk->wk_keyix);
 	wsec_key.flags = htole32(BWFM_WSEC_PRIMARY_KEY);
 	if (bwfm_fwvar_var_set_data(sc, "wsec_key", &wsec_key, sizeof(wsec_key)))
 		return;
+}
 int
 bwfm_newstate(struct ieee80211com *ic, enum ieee80211_state nstate, int arg)
+{
 	struct bwfm_softc *sc = ic->ic_ifp->if_softc;
 	struct bwfm_task *t;
 	t = pcq_get(sc->sc_freetask);
 	if (t == NULL) {
 		printf("%s: no free tasks\n", DEVNAME(sc));
 		return EIO;
+	}
 	t->t_cmd = BWFM_TASK_NEWSTATE;
 	t->t_newstate.state = nstate;
 	t->t_newstate.arg = arg;
 	workqueue_enqueue(sc->sc_taskq, (struct work *)t, NULL);
 	return 0;
+}
 void
 bwfm_newstate_cb(struct bwfm_softc *sc, struct bwfm_cmd_newstate *cmd)
+{
 	struct ieee80211com *ic = &sc->sc_ic;
 	enum ieee80211_state ostate = ic->ic_state;
 	enum ieee80211_state nstate = cmd->state;
 	int s;
 	DPRINTF(("%s: newstate %d -> %d\n", DEVNAME(sc), ostate, nstate));
 	s = splnet();
 	switch (nstate) {
 	case IEEE80211_S_INIT:
 		break;
 	case IEEE80211_S_SCAN:
 		if (ostate != IEEE80211_S_SCAN) {
 			/* Start of scanning */
 			bwfm_scan(sc);
+		}
 		break;
 	case IEEE80211_S_AUTH:
 		bwfm_connect(sc);
 		break;
 	case IEEE80211_S_ASSOC:
 		break;
 	case IEEE80211_S_RUN:
 		break;
+	}
 	sc->sc_newstate(ic, nstate, cmd->arg);
 	splx(s);
+}
 void
 bwfm_newassoc(struct ieee80211_node *ni, int isnew)
+{
 	/* Firmware handles rate adaptation for us */
 	ni->ni_txrate = 0;
+}
 void
 bwfm_task(struct work *wk, void *arg)
+{
 	struct bwfm_task *t = (struct bwfm_task *)wk;
 	struct bwfm_softc *sc = t->t_sc;
 	switch (t->t_cmd) {
 	case BWFM_TASK_NEWSTATE:
 		bwfm_newstate_cb(sc, &t->t_newstate);
 		break;
 	case BWFM_TASK_KEY_SET:
 		bwfm_key_set_cb(sc, &t->t_key);
 		break;
 	case BWFM_TASK_KEY_DELETE:
 		bwfm_key_delete_cb(sc, &t->t_key);
 		break;
 	case BWFM_TASK_RX_EVENT:
 		bwfm_rx_event_cb(sc, t->t_mbuf);
 		break;
 	default:
 		panic("bwfm: unknown task command %d", t->t_cmd);
+	}
 	pcq_put(sc->sc_freetask, t);
+}
 int
 bwfm_media_change(struct ifnet *ifp)
+{
 	return 0;
+}
 /* Chip initialization (SDIO, PCIe) */
 int
 bwfm_chip_attach(struct bwfm_softc *sc)
+{
 	struct bwfm_core *core;
 	int need_socram = 0;
 	int has_socram = 0;
 	int cpu_found = 0;
 	uint32_t val;
 	LIST_INIT(&sc->sc_chip.ch_list);
 	if (sc->sc_buscore_ops->bc_prepare(sc) != 0) {
 		printf("%s: failed buscore prepare\n", DEVNAME(sc));
 		return 1;
+	}
 	val = sc->sc_buscore_ops->bc_read(sc,
 	    BWFM_CHIP_BASE + BWFM_CHIP_REG_CHIPID);
 	sc->sc_chip.ch_chip = BWFM_CHIP_CHIPID_ID(val);
 	sc->sc_chip.ch_chiprev = BWFM_CHIP_CHIPID_REV(val);
 	if ((sc->sc_chip.ch_chip > 0xa000) || (sc->sc_chip.ch_chip < 0x4000))
 		snprintf(sc->sc_chip.ch_name, sizeof(sc->sc_chip.ch_name),
 		    "%d", sc->sc_chip.ch_chip);
 	else
 		snprintf(sc->sc_chip.ch_name, sizeof(sc->sc_chip.ch_name),
 		    "%x", sc->sc_chip.ch_chip);
 	switch (BWFM_CHIP_CHIPID_TYPE(val))
+	{
 	case BWFM_CHIP_CHIPID_TYPE_SOCI_SB:
 		printf("%s: SoC interconnect SB not implemented\n",
 		    DEVNAME(sc));
 		return 1;
 	case BWFM_CHIP_CHIPID_TYPE_SOCI_AI:
 		sc->sc_chip.ch_core_isup = bwfm_chip_ai_isup;
 		sc->sc_chip.ch_core_disable = bwfm_chip_ai_disable;
 		sc->sc_chip.ch_core_reset = bwfm_chip_ai_reset;
 		bwfm_chip_dmp_erom_scan(sc);
 		break;
 	default:
 		printf("%s: SoC interconnect %d unknown\n",
 		    DEVNAME(sc), BWFM_CHIP_CHIPID_TYPE(val));
 		return 1;
+	}
 	LIST_FOREACH(core, &sc->sc_chip.ch_list, co_link) {
 		DPRINTF(("%s: 0x%x:%-2d base 0x%08x wrap 0x%08x\n",
 		    DEVNAME(sc), core->co_id, core->co_rev,
 		    core->co_base, core->co_wrapbase));
 		switch (core->co_id) {
 		case BWFM_AGENT_CORE_ARM_CM3:
 			need_socram = true;
 			/* FALLTHROUGH */
 		case BWFM_AGENT_CORE_ARM_CR4:
 		case BWFM_AGENT_CORE_ARM_CA7:
 			cpu_found = true;
 			break;
 		case BWFM_AGENT_INTERNAL_MEM:
 			has_socram = true;
 			break;
 		default:
 			break;
+		}
+	}
 	if (!cpu_found) {
 		printf("%s: CPU core not detected\n", DEVNAME(sc));
 		return 1;
+	}
 	if (need_socram && !has_socram) {
 		printf("%s: RAM core not provided\n", DEVNAME(sc));
 		return 1;
+	}
 	bwfm_chip_set_passive(sc);
 	if (sc->sc_buscore_ops->bc_reset) {
 		sc->sc_buscore_ops->bc_reset(sc);
 		bwfm_chip_set_passive(sc);
+	}
 	if ((core = bwfm_chip_get_core(sc, BWFM_AGENT_CORE_ARM_CR4)) != NULL) {
 		bwfm_chip_tcm_ramsize(sc, core);
 		bwfm_chip_tcm_rambase(sc);
 	} else if ((core = bwfm_chip_get_core(sc, BWFM_AGENT_SYS_MEM)) != NULL) {
 		bwfm_chip_sysmem_ramsize(sc, core);
 		bwfm_chip_tcm_rambase(sc);
 	} else if ((core = bwfm_chip_get_core(sc, BWFM_AGENT_INTERNAL_MEM)) != NULL) {
 		bwfm_chip_socram_ramsize(sc, core);
+	}
 	core = bwfm_chip_get_core(sc, BWFM_AGENT_CORE_CHIPCOMMON);
 	sc->sc_chip.ch_cc_caps = sc->sc_buscore_ops->bc_read(sc,
 	    core->co_base + BWFM_CHIP_REG_CAPABILITIES);
 	sc->sc_chip.ch_cc_caps_ext = sc->sc_buscore_ops->bc_read(sc,
 	    core->co_base + BWFM_CHIP_REG_CAPABILITIES_EXT);
 	core = bwfm_chip_get_pmu(sc);
 	if (sc->sc_chip.ch_cc_caps & BWFM_CHIP_REG_CAPABILITIES_PMU) {
 		sc->sc_chip.ch_pmucaps = sc->sc_buscore_ops->bc_read(sc,
 		    core->co_base + BWFM_CHIP_REG_PMUCAPABILITIES);
 		sc->sc_chip.ch_pmurev = sc->sc_chip.ch_pmucaps &
 		    BWFM_CHIP_REG_PMUCAPABILITIES_REV_MASK;
+	}
 	if (sc->sc_buscore_ops->bc_setup)
 		sc->sc_buscore_ops->bc_setup(sc);
 	return 0;
+}
 struct bwfm_core *
 bwfm_chip_get_core(struct bwfm_softc *sc, int id)
+{
 	struct bwfm_core *core;
 	LIST_FOREACH(core, &sc->sc_chip.ch_list, co_link) {
 		if (core->co_id == id)
 			return core;
+	}
 	return NULL;
+}
 struct bwfm_core *
 bwfm_chip_get_pmu(struct bwfm_softc *sc)
+{
 	struct bwfm_core *cc, *pmu;
 	cc = bwfm_chip_get_core(sc, BWFM_AGENT_CORE_CHIPCOMMON);
 	if (cc->co_rev >= 35 && sc->sc_chip.ch_cc_caps_ext &
 	    BWFM_CHIP_REG_CAPABILITIES_EXT_AOB_PRESENT) {
 		pmu = bwfm_chip_get_core(sc, BWFM_AGENT_CORE_PMU);
 		if (pmu)
 			return pmu;
+	}
 	return cc;
+}
 /* Functions for the AI interconnect */
 int
 bwfm_chip_ai_isup(struct bwfm_softc *sc, struct bwfm_core *core)
+{
 	uint32_t ioctl, reset;
 	ioctl = sc->sc_buscore_ops->bc_read(sc,
 	    core->co_wrapbase + BWFM_AGENT_IOCTL);
 	reset = sc->sc_buscore_ops->bc_read(sc,
 	    core->co_wrapbase + BWFM_AGENT_RESET_CTL);
 	if (((ioctl & (BWFM_AGENT_IOCTL_FGC | BWFM_AGENT_IOCTL_CLK)) ==
 	    BWFM_AGENT_IOCTL_CLK) &&
 	    ((reset & BWFM_AGENT_RESET_CTL_RESET) == 0))
 		return 1;
 	return 0;
+}
 void
 bwfm_chip_ai_disable(struct bwfm_softc *sc, struct bwfm_core *core,
     uint32_t prereset, uint32_t reset)
+{
 	uint32_t val;
 	int i;
 	val = sc->sc_buscore_ops->bc_read(sc,
 	    core->co_wrapbase + BWFM_AGENT_RESET_CTL);
 	if ((val & BWFM_AGENT_RESET_CTL_RESET) == 0) {
 		sc->sc_buscore_ops->bc_write(sc,
 		    core->co_wrapbase + BWFM_AGENT_IOCTL,
 		    prereset | BWFM_AGENT_IOCTL_FGC | BWFM_AGENT_IOCTL_CLK);
 		sc->sc_buscore_ops->bc_read(sc,
 		    core->co_wrapbase + BWFM_AGENT_IOCTL);
 		sc->sc_buscore_ops->bc_write(sc,
 		    core->co_wrapbase + BWFM_AGENT_RESET_CTL,
 		    BWFM_AGENT_RESET_CTL_RESET);
 		delay(20);
 		for (i = 300; i > 0; i--) {
 			if (sc->sc_buscore_ops->bc_read(sc,
 			    core->co_wrapbase + BWFM_AGENT_RESET_CTL) ==
 			    BWFM_AGENT_RESET_CTL_RESET)
 				break;
+		}
 		if (i == 0)
 			printf("%s: timeout on core reset\n", DEVNAME(sc));
+	}
 	sc->sc_buscore_ops->bc_write(sc,
 	    core->co_wrapbase + BWFM_AGENT_IOCTL,
 	    reset | BWFM_AGENT_IOCTL_FGC | BWFM_AGENT_IOCTL_CLK);
 	sc->sc_buscore_ops->bc_read(sc,
 	    core->co_wrapbase + BWFM_AGENT_IOCTL);
+}
 void
 bwfm_chip_ai_reset(struct bwfm_softc *sc, struct bwfm_core *core,
     uint32_t prereset, uint32_t reset, uint32_t postreset)
+{
 	int i;
 	bwfm_chip_ai_disable(sc, core, prereset, reset);
 	for (i = 50; i > 0; i--) {
 		if ((sc->sc_buscore_ops->bc_read(sc,
 		    core->co_wrapbase + BWFM_AGENT_RESET_CTL) &
 		    BWFM_AGENT_RESET_CTL_RESET) == 0)
 			break;
 		sc->sc_buscore_ops->bc_write(sc,
 		    core->co_wrapbase + BWFM_AGENT_RESET_CTL, 0);
 		delay(60);
+	}
 	if (i == 0)
 		printf("%s: timeout on core reset\n", DEVNAME(sc));
 	sc->sc_buscore_ops->bc_write(sc,
 	    core->co_wrapbase + BWFM_AGENT_IOCTL,
 	    postreset | BWFM_AGENT_IOCTL_CLK);
 	sc->sc_buscore_ops->bc_read(sc,
 	    core->co_wrapbase + BWFM_AGENT_IOCTL);
+}
 void
 bwfm_chip_dmp_erom_scan(struct bwfm_softc *sc)
+{
 	uint32_t erom, val, base, wrap;
 	uint8_t type = 0;
 	uint16_t id;
 	uint8_t nmw, nsw, rev;
 	struct bwfm_core *core;
 	erom = sc->sc_buscore_ops->bc_read(sc,
 	    BWFM_CHIP_BASE + BWFM_CHIP_REG_EROMPTR);
 	while (type != BWFM_DMP_DESC_EOT) {
 		val = sc->sc_buscore_ops->bc_read(sc, erom);
 		type = val & BWFM_DMP_DESC_MASK;
 		erom += 4;
 		if (type != BWFM_DMP_DESC_COMPONENT)
 			continue;
 		id = (val & BWFM_DMP_COMP_PARTNUM)
 		    >> BWFM_DMP_COMP_PARTNUM_S;
 		val = sc->sc_buscore_ops->bc_read(sc, erom);
 		type = val & BWFM_DMP_DESC_MASK;
 		erom += 4;
 		if (type != BWFM_DMP_DESC_COMPONENT) {
 			printf("%s: not component descriptor\n", DEVNAME(sc));
 			return;
+		}
 		nmw = (val & BWFM_DMP_COMP_NUM_MWRAP)
 		    >> BWFM_DMP_COMP_NUM_MWRAP_S;
 		nsw = (val & BWFM_DMP_COMP_NUM_SWRAP)
 		    >> BWFM_DMP_COMP_NUM_SWRAP_S;
 		rev = (val & BWFM_DMP_COMP_REVISION)
 		    >> BWFM_DMP_COMP_REVISION_S;
 		if (nmw + nsw == 0 && id != BWFM_AGENT_CORE_PMU)
 			continue;
 		if (bwfm_chip_dmp_get_regaddr(sc, &erom, &base, &wrap))
 			continue;
 		core = kmem_alloc(sizeof(*core), KM_SLEEP);
 		core->co_id = id;
 		core->co_base = base;
 		core->co_wrapbase = wrap;
 		core->co_rev = rev;
 		LIST_INSERT_HEAD(&sc->sc_chip.ch_list, core, co_link);
+	}
+}
 int
 bwfm_chip_dmp_get_regaddr(struct bwfm_softc *sc, uint32_t *erom,
     uint32_t *base, uint32_t *wrap)
+{
 	uint8_t type = 0, mpnum __unused = 0;
 	uint8_t stype, sztype, wraptype;
 	uint32_t val;
 	*base = 0;
 	*wrap = 0;
 	val = sc->sc_buscore_ops->bc_read(sc, *erom);
 	type = val & BWFM_DMP_DESC_MASK;
 	if (type == BWFM_DMP_DESC_MASTER_PORT) {
 		mpnum = (val & BWFM_DMP_MASTER_PORT_NUM)
 		    >> BWFM_DMP_MASTER_PORT_NUM_S;
 		wraptype = BWFM_DMP_SLAVE_TYPE_MWRAP;
 		*erom += 4;
 	} else if ((type & ~BWFM_DMP_DESC_ADDRSIZE_GT32) ==
 	    BWFM_DMP_DESC_ADDRESS)
 		wraptype = BWFM_DMP_SLAVE_TYPE_SWRAP;
 	else
 		return 1;
 	do {
 		do {
 			val = sc->sc_buscore_ops->bc_read(sc, *erom);
 			type = val & BWFM_DMP_DESC_MASK;
 			if (type == BWFM_DMP_DESC_COMPONENT)
 				return 0;
 			if (type == BWFM_DMP_DESC_EOT)
 				return 1;
 			*erom += 4;
 		} while ((type & ~BWFM_DMP_DESC_ADDRSIZE_GT32) !=
 		     BWFM_DMP_DESC_ADDRESS);
 		if (type & BWFM_DMP_DESC_ADDRSIZE_GT32)
 			*erom += 4;
 		sztype = (val & BWFM_DMP_SLAVE_SIZE_TYPE)
 		    >> BWFM_DMP_SLAVE_SIZE_TYPE_S;
 		if (sztype == BWFM_DMP_SLAVE_SIZE_DESC) {
 			val = sc->sc_buscore_ops->bc_read(sc, *erom);
 			type = val & BWFM_DMP_DESC_MASK;
 			if (type & BWFM_DMP_DESC_ADDRSIZE_GT32)
 				*erom += 8;
 			else
 				*erom += 4;
+		}
 		if (sztype != BWFM_DMP_SLAVE_SIZE_4K)
 			continue;
 		stype = (val & BWFM_DMP_SLAVE_TYPE) >> BWFM_DMP_SLAVE_TYPE_S;
 		if (*base == 0 && stype == BWFM_DMP_SLAVE_TYPE_SLAVE)
 			*base = val & BWFM_DMP_SLAVE_ADDR_BASE;
 		if (*wrap == 0 && stype == wraptype)
 			*wrap = val & BWFM_DMP_SLAVE_ADDR_BASE;
 	} while (*base == 0 || *wrap == 0);
 	return 0;
+}
 /* Core configuration */
 int
 bwfm_chip_set_active(struct bwfm_softc *sc, const uint32_t rstvec)
+{
 	if (bwfm_chip_get_core(sc, BWFM_AGENT_CORE_ARM_CR4) != NULL)
 		return bwfm_chip_cr4_set_active(sc, rstvec);
 	if (bwfm_chip_get_core(sc, BWFM_AGENT_CORE_ARM_CA7) != NULL)
 		return bwfm_chip_ca7_set_active(sc, rstvec);
 	if (bwfm_chip_get_core(sc, BWFM_AGENT_CORE_ARM_CM3) != NULL)
 		return bwfm_chip_cm3_set_active(sc);
 	return 1;
+}
 void
 bwfm_chip_set_passive(struct bwfm_softc *sc)
+{
 	if (bwfm_chip_get_core(sc, BWFM_AGENT_CORE_ARM_CR4) != NULL) {
 		bwfm_chip_cr4_set_passive(sc);
 		return;
+	}
 	if (bwfm_chip_get_core(sc, BWFM_AGENT_CORE_ARM_CA7) != NULL) {
 		bwfm_chip_ca7_set_passive(sc);
 		return;
+	}
 	if (bwfm_chip_get_core(sc, BWFM_AGENT_CORE_ARM_CM3) != NULL) {
 		bwfm_chip_cm3_set_passive(sc);
 		return;
+	}
+}
 int
 bwfm_chip_cr4_set_active(struct bwfm_softc *sc, const uint32_t rstvec)
+{
 	struct bwfm_core *core;
 	sc->sc_buscore_ops->bc_activate(sc, rstvec);
 	core = bwfm_chip_get_core(sc, BWFM_AGENT_CORE_ARM_CR4);
 	sc->sc_chip.ch_core_reset(sc, core,
 	    BWFM_AGENT_IOCTL_ARMCR4_CPUHALT, 0, 0);
 	return 0;
+}
 void
 bwfm_chip_cr4_set_passive(struct bwfm_softc *sc)
+{
 	struct bwfm_core *core;
 	uint32_t val;
 	core = bwfm_chip_get_core(sc, BWFM_AGENT_CORE_ARM_CR4);
 	val = sc->sc_buscore_ops->bc_read(sc,
 	    core->co_wrapbase + BWFM_AGENT_IOCTL);
 	sc->sc_chip.ch_core_reset(sc, core,
 	    val & BWFM_AGENT_IOCTL_ARMCR4_CPUHALT,
 	    BWFM_AGENT_IOCTL_ARMCR4_CPUHALT,
 	    BWFM_AGENT_IOCTL_ARMCR4_CPUHALT);
 	core = bwfm_chip_get_core(sc, BWFM_AGENT_CORE_80211);
 	sc->sc_chip.ch_core_reset(sc, core, BWFM_AGENT_D11_IOCTL_PHYRESET |
 	    BWFM_AGENT_D11_IOCTL_PHYCLOCKEN, BWFM_AGENT_D11_IOCTL_PHYCLOCKEN,
 	    BWFM_AGENT_D11_IOCTL_PHYCLOCKEN);
+}
 int
 bwfm_chip_ca7_set_active(struct bwfm_softc *sc, const uint32_t rstvec)
+{
 	struct bwfm_core *core;
 	sc->sc_buscore_ops->bc_activate(sc, rstvec);
 	core = bwfm_chip_get_core(sc, BWFM_AGENT_CORE_ARM_CA7);
 	sc->sc_chip.ch_core_reset(sc, core,
 	    BWFM_AGENT_IOCTL_ARMCR4_CPUHALT, 0, 0);
 	return 0;
+}
 void
 bwfm_chip_ca7_set_passive(struct bwfm_softc *sc)
+{
 	struct bwfm_core *core;
 	uint32_t val;
 	core = bwfm_chip_get_core(sc, BWFM_AGENT_CORE_ARM_CA7);
 	val = sc->sc_buscore_ops->bc_read(sc,
 	    core->co_wrapbase + BWFM_AGENT_IOCTL);
 	sc->sc_chip.ch_core_reset(sc, core,
 	    val & BWFM_AGENT_IOCTL_ARMCR4_CPUHALT,
 	    BWFM_AGENT_IOCTL_ARMCR4_CPUHALT,
 	    BWFM_AGENT_IOCTL_ARMCR4_CPUHALT);
 	core = bwfm_chip_get_core(sc, BWFM_AGENT_CORE_80211);
 	sc->sc_chip.ch_core_reset(sc, core, BWFM_AGENT_D11_IOCTL_PHYRESET |
 	    BWFM_AGENT_D11_IOCTL_PHYCLOCKEN, BWFM_AGENT_D11_IOCTL_PHYCLOCKEN,
 	    BWFM_AGENT_D11_IOCTL_PHYCLOCKEN);
+}
 int
 bwfm_chip_cm3_set_active(struct bwfm_softc *sc)
+{
 	struct bwfm_core *core;
 	core = bwfm_chip_get_core(sc, BWFM_AGENT_INTERNAL_MEM);
 	if (!sc->sc_chip.ch_core_isup(sc, core))
 		return 1;
 	sc->sc_buscore_ops->bc_activate(sc, 0);
 	core = bwfm_chip_get_core(sc, BWFM_AGENT_CORE_ARM_CM3);
 	sc->sc_chip.ch_core_reset(sc, core, 0, 0, 0);
 	return 0;
+}
 void
 bwfm_chip_cm3_set_passive(struct bwfm_softc *sc)
+{
 	struct bwfm_core *core;
 	core = bwfm_chip_get_core(sc, BWFM_AGENT_CORE_ARM_CM3);
 	sc->sc_chip.ch_core_disable(sc, core, 0, 0);
 	core = bwfm_chip_get_core(sc, BWFM_AGENT_CORE_80211);
 	sc->sc_chip.ch_core_reset(sc, core, BWFM_AGENT_D11_IOCTL_PHYRESET |
 	    BWFM_AGENT_D11_IOCTL_PHYCLOCKEN, BWFM_AGENT_D11_IOCTL_PHYCLOCKEN,
 	    BWFM_AGENT_D11_IOCTL_PHYCLOCKEN);
 	core = bwfm_chip_get_core(sc, BWFM_AGENT_INTERNAL_MEM);
 	sc->sc_chip.ch_core_reset(sc, core, 0, 0, 0);
 	if (sc->sc_chip.ch_chip == BRCM_CC_43430_CHIP_ID) {
 		sc->sc_buscore_ops->bc_write(sc,
 		    core->co_base + BWFM_SOCRAM_BANKIDX, 3);
 		sc->sc_buscore_ops->bc_write(sc,
 		    core->co_base + BWFM_SOCRAM_BANKPDA, 0);
+	}
+}
 int
 bwfm_chip_sr_capable(struct bwfm_softc *sc)
+{
 	struct bwfm_core *core;
 	uint32_t reg;
 	if (sc->sc_chip.ch_pmurev < 17)
 		return 0;
 	switch (sc->sc_chip.ch_chip) {
 	case BRCM_CC_4345_CHIP_ID:
 	case BRCM_CC_4354_CHIP_ID:
 	case BRCM_CC_4356_CHIP_ID:
 		core = bwfm_chip_get_pmu(sc);
 		sc->sc_buscore_ops->bc_write(sc, core->co_base +
 		    BWFM_CHIP_REG_CHIPCONTROL_ADDR, 3);
 		reg = sc->sc_buscore_ops->bc_read(sc, core->co_base +
 		    BWFM_CHIP_REG_CHIPCONTROL_DATA);
 		return (reg & (1 << 2)) != 0;
 	case BRCM_CC_43241_CHIP_ID:
 	case BRCM_CC_4335_CHIP_ID:
 	case BRCM_CC_4339_CHIP_ID:
 		core = bwfm_chip_get_pmu(sc);
 		sc->sc_buscore_ops->bc_write(sc, core->co_base +
 		    BWFM_CHIP_REG_CHIPCONTROL_ADDR, 3);
 		reg = sc->sc_buscore_ops->bc_read(sc, core->co_base +
 		    BWFM_CHIP_REG_CHIPCONTROL_DATA);
 		return reg != 0;
 	case BRCM_CC_43430_CHIP_ID:
 		core = bwfm_chip_get_core(sc, BWFM_AGENT_CORE_CHIPCOMMON);
 		reg = sc->sc_buscore_ops->bc_read(sc, core->co_base +
 		    BWFM_CHIP_REG_SR_CONTROL1);
 		return reg != 0;
 	default:
 		core = bwfm_chip_get_pmu(sc);
 		reg = sc->sc_buscore_ops->bc_read(sc, core->co_base +
 		    BWFM_CHIP_REG_PMUCAPABILITIES_EXT);
 		if ((reg & BWFM_CHIP_REG_PMUCAPABILITIES_SR_SUPP) == 0)
 			return 0;
 		reg = sc->sc_buscore_ops->bc_read(sc, core->co_base +
 		    BWFM_CHIP_REG_RETENTION_CTL);
 		return (reg & (BWFM_CHIP_REG_RETENTION_CTL_MACPHY_DIS |
 		               BWFM_CHIP_REG_RETENTION_CTL_LOGIC_DIS)) == 0;
+	}
+}
 /* RAM size helpers */
 void
 bwfm_chip_socram_ramsize(struct bwfm_softc *sc, struct bwfm_core *core)
+{
 	uint32_t coreinfo, nb, lss, banksize, bankinfo;
 	uint32_t ramsize = 0, srsize = 0;
 	int i;
 	if (!sc->sc_chip.ch_core_isup(sc, core))
 		sc->sc_chip.ch_core_reset(sc, core, 0, 0, 0);
 	coreinfo = sc->sc_buscore_ops->bc_read(sc,
 	    core->co_base + BWFM_SOCRAM_COREINFO);
 	nb = (coreinfo & BWFM_SOCRAM_COREINFO_SRNB_MASK)
 	    >> BWFM_SOCRAM_COREINFO_SRNB_SHIFT;
 	if (core->co_rev <= 7 || core->co_rev == 12) {
 		banksize = coreinfo & BWFM_SOCRAM_COREINFO_SRBSZ_MASK;
 		lss = (coreinfo & BWFM_SOCRAM_COREINFO_LSS_MASK)
 		    >> BWFM_SOCRAM_COREINFO_LSS_SHIFT;
 		if (lss != 0)
 			nb--;
 		ramsize = nb * (1 << (banksize + BWFM_SOCRAM_COREINFO_SRBSZ_BASE));
 		if (lss != 0)
 			ramsize += (1 << ((lss - 1) + BWFM_SOCRAM_COREINFO_SRBSZ_BASE));
 	} else {
 		for (i = 0; i < nb; i++) {
 			sc->sc_buscore_ops->bc_write(sc,
 			    core->co_base + BWFM_SOCRAM_BANKIDX,
 			    (BWFM_SOCRAM_BANKIDX_MEMTYPE_RAM <<
 			    BWFM_SOCRAM_BANKIDX_MEMTYPE_SHIFT) | i);
 			bankinfo = sc->sc_buscore_ops->bc_read(sc,
 			    core->co_base + BWFM_SOCRAM_BANKINFO);
 			banksize = ((bankinfo & BWFM_SOCRAM_BANKINFO_SZMASK) + 1)
 			    * BWFM_SOCRAM_BANKINFO_SZBASE;
 			ramsize += banksize;
 			if (bankinfo & BWFM_SOCRAM_BANKINFO_RETNTRAM_MASK)
 				srsize += banksize;
+		}
+	}
 	switch (sc->sc_chip.ch_chip) {
 	case BRCM_CC_4334_CHIP_ID:
 		if (sc->sc_chip.ch_chiprev < 2)
 			srsize = 32 * 1024;
 		break;
 	case BRCM_CC_43430_CHIP_ID:
 		srsize = 64 * 1024;
 		break;
 	default:
 		break;
+	}
 	sc->sc_chip.ch_ramsize = ramsize;
 	sc->sc_chip.ch_srsize = srsize;
+}
 void
 bwfm_chip_sysmem_ramsize(struct bwfm_softc *sc, struct bwfm_core *core)
+{
 	uint32_t coreinfo, nb, banksize, bankinfo;
 	uint32_t ramsize = 0;
 	int i;
 	if (!sc->sc_chip.ch_core_isup(sc, core))
 		sc->sc_chip.ch_core_reset(sc, core, 0, 0, 0);
 	coreinfo = sc->sc_buscore_ops->bc_read(sc,
 	    core->co_base + BWFM_SOCRAM_COREINFO);
 	nb = (coreinfo & BWFM_SOCRAM_COREINFO_SRNB_MASK)
 	    >> BWFM_SOCRAM_COREINFO_SRNB_SHIFT;
 	for (i = 0; i < nb; i++) {
 		sc->sc_buscore_ops->bc_write(sc,
 		    core->co_base + BWFM_SOCRAM_BANKIDX,
 		    (BWFM_SOCRAM_BANKIDX_MEMTYPE_RAM <<
 		    BWFM_SOCRAM_BANKIDX_MEMTYPE_SHIFT) | i);
 		bankinfo = sc->sc_buscore_ops->bc_read(sc,
 		    core->co_base + BWFM_SOCRAM_BANKINFO);
 		banksize = ((bankinfo & BWFM_SOCRAM_BANKINFO_SZMASK) + 1)
 		    * BWFM_SOCRAM_BANKINFO_SZBASE;
 		ramsize += banksize;
+	}
 	sc->sc_chip.ch_ramsize = ramsize;
+}
 void
 bwfm_chip_tcm_ramsize(struct bwfm_softc *sc, struct bwfm_core *core)
+{
 	uint32_t cap, nab, nbb, totb, bxinfo, ramsize = 0;
 	int i;
 	cap = sc->sc_buscore_ops->bc_read(sc, core->co_base + BWFM_ARMCR4_CAP);
 	nab = (cap & BWFM_ARMCR4_CAP_TCBANB_MASK) >> BWFM_ARMCR4_CAP_TCBANB_SHIFT;
 	nbb = (cap & BWFM_ARMCR4_CAP_TCBBNB_MASK) >> BWFM_ARMCR4_CAP_TCBBNB_SHIFT;
 	totb = nab + nbb;
 	for (i = 0; i < totb; i++) {
 		sc->sc_buscore_ops->bc_write(sc,
 		    core->co_base + BWFM_ARMCR4_BANKIDX, i);
 		bxinfo = sc->sc_buscore_ops->bc_read(sc,
 		    core->co_base + BWFM_ARMCR4_BANKINFO);
 		ramsize += ((bxinfo & BWFM_ARMCR4_BANKINFO_BSZ_MASK) + 1) *
 		    BWFM_ARMCR4_BANKINFO_BSZ_MULT;
+	}
 	sc->sc_chip.ch_ramsize = ramsize;
+}
 void
 bwfm_chip_tcm_rambase(struct bwfm_softc *sc)
+{
 	switch (sc->sc_chip.ch_chip) {
 	case BRCM_CC_4345_CHIP_ID:
 		sc->sc_chip.ch_rambase = 0x198000;
 		break;
 	case BRCM_CC_4335_CHIP_ID:
 	case BRCM_CC_4339_CHIP_ID:
 	case BRCM_CC_4350_CHIP_ID:
 	case BRCM_CC_4354_CHIP_ID:
 	case BRCM_CC_4356_CHIP_ID:
 	case BRCM_CC_43567_CHIP_ID:
 	case BRCM_CC_43569_CHIP_ID:
 	case BRCM_CC_43570_CHIP_ID:
 	case BRCM_CC_4358_CHIP_ID:
 	case BRCM_CC_4359_CHIP_ID:
 	case BRCM_CC_43602_CHIP_ID:
 	case BRCM_CC_4371_CHIP_ID:
 		sc->sc_chip.ch_rambase = 0x180000;
 		break;
 	case BRCM_CC_43465_CHIP_ID:
 	case BRCM_CC_43525_CHIP_ID:
 	case BRCM_CC_4365_CHIP_ID:
 	case BRCM_CC_4366_CHIP_ID:
 		sc->sc_chip.ch_rambase = 0x200000;
 		break;
 	case CY_CC_4373_CHIP_ID:
 		sc->sc_chip.ch_rambase = 0x160000;
 		break;
 	default:
 		printf("%s: unknown chip: %d\n", DEVNAME(sc),
 		    sc->sc_chip.ch_chip);
 		break;
+	}
+}
 /* BCDC protocol implementation */
 int
 bwfm_proto_bcdc_query_dcmd(struct bwfm_softc *sc, int ifidx,
     int cmd, char *buf, size_t *len)
+{
 	struct bwfm_proto_bcdc_dcmd *dcmd;
 	size_t size = sizeof(dcmd->hdr) + *len;
 	int reqid;
 	int ret = 1;
 	reqid = sc->sc_bcdc_reqid++;
 	dcmd = kmem_zalloc(sizeof(*dcmd), KM_SLEEP);
 	if (*len > sizeof(dcmd->buf))
 		goto err;
 	dcmd->hdr.cmd = htole32(cmd);
 	dcmd->hdr.len = htole32(*len);
 	dcmd->hdr.flags |= BWFM_BCDC_DCMD_GET;
 	dcmd->hdr.flags |= BWFM_BCDC_DCMD_ID_SET(reqid);
 	dcmd->hdr.flags |= BWFM_BCDC_DCMD_IF_SET(ifidx);
 	dcmd->hdr.flags = htole32(dcmd->hdr.flags);
 	memcpy(&dcmd->buf, buf, *len);
 	if (sc->sc_bus_ops->bs_txctl(sc, (void *)dcmd,

 @@ -1,1050 +1,1050 @@
-/*	$NetBSD: bwi.c,v 1.36 2018/12/22 14:07:53 maxv Exp $	*/
+/*	$NetBSD: bwi.c,v 1.37 2020/01/29 14:14:55 thorpej Exp $	*/
 /*	$OpenBSD: bwi.c,v 1.74 2008/02/25 21:13:30 mglocker Exp $	*/
 /*
  * Copyright (c) 2007 The DragonFly Project.  All rights reserved.
+ *
  * This code is derived from software contributed to The DragonFly Project
  * by Sepherosa Ziehau <sepherosa@gmail.com>
+ *
  * Redistribution and use in source and binary forms, with or without
  * modification, are permitted provided that the following conditions
  * are met:
+ *
  * 1. Redistributions of source code must retain the above copyright
  *    notice, this list of conditions and the following disclaimer.
  * 2. Redistributions in binary form must reproduce the above copyright
  *    notice, this list of conditions and the following disclaimer in
  *    the documentation and/or other materials provided with the
  *    distribution.
  * 3. Neither the name of The DragonFly Project nor the names of its
  *    contributors may be used to endorse or promote products derived
  *    from this software without specific, prior written permission.
+ *
  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
  * FOR A PARTICULAR PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL THE
  * COPYRIGHT HOLDERS OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
  * INCIDENTAL, SPECIAL, EXEMPLARY OR CONSEQUENTIAL DAMAGES (INCLUDING,
  * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
  * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
  * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT
  * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
  * SUCH DAMAGE.
+ *
  * $DragonFly: src/sys/dev/netif/bwi/bwimac.c,v 1.1 2007/09/08 06:15:54 sephe Exp $
  */
 /*
  * Broadcom AirForce BCM43xx IEEE 802.11b/g wireless network driver
  * Generic back end
  */
 /* [TRC: XXX Names beginning with `bwi_ieee80211_*' are those that I
    think should be in NetBSD's generic 802.11 code, not in this
    driver.] */
 #include <sys/cdefs.h>
-__KERNEL_RCSID(0, "$NetBSD: bwi.c,v 1.36 2018/12/22 14:07:53 maxv Exp $");
+__KERNEL_RCSID(0, "$NetBSD: bwi.c,v 1.37 2020/01/29 14:14:55 thorpej Exp $");
 #include <sys/param.h>
 #include <sys/callout.h>
 #include <sys/device.h>
 #include <sys/kernel.h>
 #include <sys/malloc.h>
 #include <sys/mbuf.h>
 #include <sys/socket.h>
 #include <sys/sockio.h>
 #include <sys/sysctl.h>
 #include <sys/systm.h>
 #include <sys/bus.h>
 #include <sys/intr.h>
 #include <machine/endian.h>
 #include <dev/firmload.h>
 #include <net/if.h>
 #include <net/if_dl.h>
 #include <net/if_ether.h>
 #include <net/if_media.h>
 #include <net/bpf.h>
 #include <net80211/ieee80211_var.h>
 /* [TRC: XXX amrr] */
 #include <net80211/ieee80211_amrr.h>
 #include <net80211/ieee80211_radiotap.h>
 #include <dev/ic/bwireg.h>
 #include <dev/ic/bwivar.h>
 #ifdef BWI_DEBUG
 int bwi_debug = 0;
 #define DPRINTF(sc, dbg, fmt, ...)					\
 do {									\
 	if ((sc)->sc_debug & (dbg))					\
 		aprint_debug_dev((sc)->sc_dev, fmt, ##__VA_ARGS__);	\
 } while (0)
 #else	/* !BWI_DEBUG */
 #define DPRINTF(sc, dbg, fmt, ...)	((void)0)
 #endif	/* BWI_DEBUG */
 /* XXX temporary porting goop */
 #include <dev/pci/pcireg.h>
 #include <dev/pci/pcivar.h>
 #include <dev/pci/pcidevs.h>
 /* XXX does not belong here */
 #define IEEE80211_OFDM_PLCP_RATE_MASK	0x0000000f
 #define IEEE80211_OFDM_PLCP_LEN_MASK	0x0001ffe0
 /*
  * Contention window (slots).  [TRC: dfly/net80211/80211.h]
  */
 #define IEEE80211_CW_MAX	1023	/* aCWmax */
 #define IEEE80211_CW_MIN_0	31	/* DS/CCK aCWmin, ERP aCWmin(0) */
 #define IEEE80211_CW_MIN_1	15	/* OFDM aCWmin, ERP aCWmin(1) */
 /*
  * Slot time (microseconds).  [TRC: dfly/net80211/80211.h]
  */
 #define IEEE80211_DUR_SLOT      20      /* DS/CCK slottime, ERP long slottime */
 #define IEEE80211_DUR_SHSLOT    9       /* ERP short slottime */
 #define IEEE80211_DUR_OFDM_SLOT 9       /* OFDM slottime */
 /* XXX end porting goop */
 /* MAC */
 struct bwi_retry_lim {
 	uint16_t	shretry;
 	uint16_t	shretry_fb;
 	uint16_t	lgretry;
 	uint16_t	lgretry_fb;
 };
 struct bwi_clock_freq {
 	uint		clkfreq_min;
 	uint		clkfreq_max;
 };
 /* XXX does not belong here */
 struct ieee80211_ds_plcp_hdr {
 	uint8_t		i_signal;
 	uint8_t		i_service;
 	uint16_t	i_length;
 	uint16_t	i_crc;
 } __packed;
 static void	 bwi_sysctlattach(struct bwi_softc *);
 /* MAC */
 static void	 bwi_tmplt_write_4(struct bwi_mac *, uint32_t, uint32_t);
 static void	 bwi_hostflags_write(struct bwi_mac *, uint64_t);
 static uint64_t	 bwi_hostflags_read(struct bwi_mac *);
 static uint16_t	 bwi_memobj_read_2(struct bwi_mac *, uint16_t, uint16_t);
 static uint32_t	 bwi_memobj_read_4(struct bwi_mac *, uint16_t, uint16_t);
 static void	 bwi_memobj_write_2(struct bwi_mac *, uint16_t, uint16_t,
 		     uint16_t);
 static void	 bwi_memobj_write_4(struct bwi_mac *, uint16_t, uint16_t,
 		     uint32_t);
 static int	 bwi_mac_lateattach(struct bwi_mac *);
 static int	 bwi_mac_init(struct bwi_mac *);
 static void	 bwi_mac_reset(struct bwi_mac *, int);
 static void	 bwi_mac_set_tpctl_11bg(struct bwi_mac *,
 		     const struct bwi_tpctl *);
 static int	 bwi_mac_test(struct bwi_mac *);
 static void	 bwi_mac_setup_tpctl(struct bwi_mac *);
 static void	 bwi_mac_dummy_xmit(struct bwi_mac *);
 static void	 bwi_mac_init_tpctl_11bg(struct bwi_mac *);
 static void	 bwi_mac_detach(struct bwi_mac *);
 static int	 bwi_mac_fw_alloc(struct bwi_mac *);
 static void	 bwi_mac_fw_free(struct bwi_mac *);
 static int	 bwi_mac_fw_image_alloc(struct bwi_mac *, const char *,
     		     int idx, struct bwi_fw_image *, uint8_t);
 static void	 bwi_mac_fw_image_free(struct bwi_mac *, struct bwi_fw_image *);
 static int	 bwi_mac_fw_load(struct bwi_mac *);
 static int	 bwi_mac_gpio_init(struct bwi_mac *);
 static int	 bwi_mac_gpio_fini(struct bwi_mac *);
 static int	 bwi_mac_fw_load_iv(struct bwi_mac *,
 		     const struct bwi_fw_image *);
 static int	 bwi_mac_fw_init(struct bwi_mac *);
 static void	 bwi_mac_opmode_init(struct bwi_mac *);
 static void	 bwi_mac_hostflags_init(struct bwi_mac *);
 static void	 bwi_mac_bss_param_init(struct bwi_mac *);
 static void	 bwi_mac_set_retry_lim(struct bwi_mac *,
 		     const struct bwi_retry_lim *);
 static void	 bwi_mac_set_ackrates(struct bwi_mac *,
 		     const struct ieee80211_rateset *);
 static int	 bwi_mac_start(struct bwi_mac *);
 static int	 bwi_mac_stop(struct bwi_mac *);
 static int	 bwi_mac_config_ps(struct bwi_mac *);
 static void	 bwi_mac_reset_hwkeys(struct bwi_mac *);
 static void	 bwi_mac_shutdown(struct bwi_mac *);
 static int	 bwi_mac_get_property(struct bwi_mac *);
 static void	 bwi_mac_updateslot(struct bwi_mac *, int);
 static int	 bwi_mac_attach(struct bwi_softc *, int, uint8_t);
 static void	 bwi_mac_balance_atten(int *, int *);
 static void	 bwi_mac_adjust_tpctl(struct bwi_mac *, int, int);
 static void	 bwi_mac_calibrate_txpower(struct bwi_mac *,
 		     enum bwi_txpwrcb_type);
 static void	 bwi_mac_lock(struct bwi_mac *);
 static void	 bwi_mac_unlock(struct bwi_mac *);
 static void	 bwi_mac_set_promisc(struct bwi_mac *, int);
 /* PHY */
 static void	 bwi_phy_write(struct bwi_mac *, uint16_t, uint16_t);
 static uint16_t	 bwi_phy_read(struct bwi_mac *, uint16_t);
 static int	 bwi_phy_attach(struct bwi_mac *);
 static void	 bwi_phy_set_bbp_atten(struct bwi_mac *, uint16_t);
 static int	 bwi_phy_calibrate(struct bwi_mac *);
 static void	 bwi_tbl_write_2(struct bwi_mac *mac, uint16_t, uint16_t);
 static void	 bwi_tbl_write_4(struct bwi_mac *mac, uint16_t, uint32_t);
 static void	 bwi_nrssi_write(struct bwi_mac *, uint16_t, int16_t);
 static int16_t	 bwi_nrssi_read(struct bwi_mac *, uint16_t);
 static void	 bwi_phy_init_11a(struct bwi_mac *);
 static void	 bwi_phy_init_11g(struct bwi_mac *);
 static void	 bwi_phy_init_11b_rev2(struct bwi_mac *);
 static void	 bwi_phy_init_11b_rev4(struct bwi_mac *);
 static void	 bwi_phy_init_11b_rev5(struct bwi_mac *);
 static void	 bwi_phy_init_11b_rev6(struct bwi_mac *);
 static void	 bwi_phy_config_11g(struct bwi_mac *);
 static void	 bwi_phy_config_agc(struct bwi_mac *);
 static void	 bwi_set_gains(struct bwi_mac *, const struct bwi_gains *);
 static void	 bwi_phy_clear_state(struct bwi_phy *);
 /* RF */
 static int16_t	 bwi_nrssi_11g(struct bwi_mac *);
 static struct bwi_rf_lo
 		*bwi_get_rf_lo(struct bwi_mac *, uint16_t, uint16_t);
 static int	 bwi_rf_lo_isused(struct bwi_mac *, const struct bwi_rf_lo *);
 static void	 bwi_rf_write(struct bwi_mac *, uint16_t, uint16_t);
 static uint16_t	 bwi_rf_read(struct bwi_mac *, uint16_t);
 static int	 bwi_rf_attach(struct bwi_mac *);
 static void	 bwi_rf_set_chan(struct bwi_mac *, uint, int);
 static void	 bwi_rf_get_gains(struct bwi_mac *);
 static void	 bwi_rf_init(struct bwi_mac *);
 static void	 bwi_rf_off_11a(struct bwi_mac *);
 static void	 bwi_rf_off_11bg(struct bwi_mac *);
 static void	 bwi_rf_off_11g_rev5(struct bwi_mac *);
 static void	 bwi_rf_workaround(struct bwi_mac *, uint);
 static struct bwi_rf_lo
 		*bwi_rf_lo_find(struct bwi_mac *, const struct bwi_tpctl *);
 static void	 bwi_rf_lo_adjust(struct bwi_mac *, const struct bwi_tpctl *);
 static void	 bwi_rf_lo_write(struct bwi_mac *, const struct bwi_rf_lo *);
 static int	 bwi_rf_gain_max_reached(struct bwi_mac *, int);
 static uint16_t	 bwi_bitswap4(uint16_t);
 static uint16_t	 bwi_phy812_value(struct bwi_mac *, uint16_t);
 static void	 bwi_rf_init_bcm2050(struct bwi_mac *);
 static uint16_t	 bwi_rf_calibval(struct bwi_mac *);
 static int32_t	 _bwi_adjust_devide(int32_t, int32_t);
 static int	 bwi_rf_calc_txpower(int8_t *, uint8_t, const int16_t[]);
 static int	 bwi_rf_map_txpower(struct bwi_mac *);
 static void	 bwi_rf_lo_update_11g(struct bwi_mac *);
 static uint32_t	 bwi_rf_lo_devi_measure(struct bwi_mac *, uint16_t);
 static uint16_t	 bwi_rf_get_tp_ctrl2(struct bwi_mac *);
 static uint8_t	 _bwi_rf_lo_update_11g(struct bwi_mac *, uint16_t);
 static void	 bwi_rf_lo_measure_11g(struct bwi_mac *,
 		     const struct bwi_rf_lo *, struct bwi_rf_lo *, uint8_t);
 static void	 bwi_rf_calc_nrssi_slope_11b(struct bwi_mac *);
 static void	 bwi_rf_set_nrssi_ofs_11g(struct bwi_mac *);
 static void	 bwi_rf_calc_nrssi_slope_11g(struct bwi_mac *);
 static void	 bwi_rf_init_sw_nrssi_table(struct bwi_mac *);
 static void	 bwi_rf_init_hw_nrssi_table(struct bwi_mac *, uint16_t);
 static void	 bwi_rf_set_nrssi_thr_11b(struct bwi_mac *);
 static int32_t	 _nrssi_threshold(const struct bwi_rf *, int32_t);
 static void	 bwi_rf_set_nrssi_thr_11g(struct bwi_mac *);
 static void	 bwi_rf_clear_tssi(struct bwi_mac *);
 static void	 bwi_rf_clear_state(struct bwi_rf *);
 static void	 bwi_rf_on_11a(struct bwi_mac *);
 static void	 bwi_rf_on_11bg(struct bwi_mac *);
 static void	 bwi_rf_set_ant_mode(struct bwi_mac *, int);
 static int	 bwi_rf_get_latest_tssi(struct bwi_mac *, int8_t[], uint16_t);
 static int	 bwi_rf_tssi2dbm(struct bwi_mac *, int8_t, int8_t *);
 static int	 bwi_rf_calc_rssi_bcm2050(struct bwi_mac *,
 		     const struct bwi_rxbuf_hdr *);
 static int	 bwi_rf_calc_rssi_bcm2053(struct bwi_mac *,
 		     const struct bwi_rxbuf_hdr *);
 static int	 bwi_rf_calc_rssi_bcm2060(struct bwi_mac *,
 		     const struct bwi_rxbuf_hdr *);
 static uint16_t	 bwi_rf_lo_measure_11b(struct bwi_mac *);
 static void	 bwi_rf_lo_update_11b(struct bwi_mac *);
 /* INTERFACE */
 static uint16_t	 bwi_read_sprom(struct bwi_softc *, uint16_t);
 static void	 bwi_setup_desc32(struct bwi_softc *, struct bwi_desc32 *, int,
 		     int, bus_addr_t, int, int);
 static void	 bwi_power_on(struct bwi_softc *, int);
 static int	 bwi_power_off(struct bwi_softc *, int);
 static int	 bwi_regwin_switch(struct bwi_softc *, struct bwi_regwin *,
 		     struct bwi_regwin **);
 static int	 bwi_regwin_select(struct bwi_softc *, int);
 static void	 bwi_regwin_info(struct bwi_softc *, uint16_t *, uint8_t *);
 static void	 bwi_led_attach(struct bwi_softc *);
 static void	 bwi_led_newstate(struct bwi_softc *, enum ieee80211_state);
 static uint16_t	 bwi_led_onoff(const struct bwi_led *, uint16_t, int);
 static void	 bwi_led_event(struct bwi_softc *, int);
 static void	 bwi_led_blink_start(struct bwi_softc *, int, int);
 static void	 bwi_led_blink_next(void *);
 static void	 bwi_led_blink_end(void *);
 static int	 bwi_bbp_attach(struct bwi_softc *);
 static int	 bwi_bus_init(struct bwi_softc *, struct bwi_mac *);
 static void	 bwi_get_card_flags(struct bwi_softc *);
 static void	 bwi_get_eaddr(struct bwi_softc *, uint16_t, uint8_t *);
 static void	 bwi_get_clock_freq(struct bwi_softc *,
 		     struct bwi_clock_freq *);
 static int	 bwi_set_clock_mode(struct bwi_softc *, enum bwi_clock_mode);
 static int	 bwi_set_clock_delay(struct bwi_softc *);
 static int	 bwi_init(struct ifnet *);
 static void	 bwi_init_statechg(struct bwi_softc *, int);
 static int	 bwi_ioctl(struct ifnet *, u_long, void *);
 static void	 bwi_start(struct ifnet *);
 static void	 bwi_watchdog(struct ifnet *);
 static void	 bwi_stop(struct ifnet *, int);
 static void	 bwi_newstate_begin(struct bwi_softc *, enum ieee80211_state);
 static int	 bwi_newstate(struct ieee80211com *, enum ieee80211_state, int);
 static int	 bwi_media_change(struct ifnet *);
 /* [TRC: XXX amrr] */
 static void	 bwi_iter_func(void *, struct ieee80211_node *);
 static void	 bwi_amrr_timeout(void *);
 static void	 bwi_newassoc(struct ieee80211_node *, int);
 static struct ieee80211_node *
 		 bwi_node_alloc(struct ieee80211_node_table *);
 static int	 bwi_dma_alloc(struct bwi_softc *);
 static void	 bwi_dma_free(struct bwi_softc *);
 static void	 bwi_ring_data_free(struct bwi_ring_data *, struct bwi_softc *);
 static int	 bwi_dma_ring_alloc(struct bwi_softc *,
 		     struct bwi_ring_data *, bus_size_t, uint32_t);
 static int	 bwi_dma_txstats_alloc(struct bwi_softc *, uint32_t,
 		     bus_size_t);
 static void	 bwi_dma_txstats_free(struct bwi_softc *);
 static int	 bwi_dma_mbuf_create(struct bwi_softc *);
 static void	 bwi_dma_mbuf_destroy(struct bwi_softc *, int, int);
 static void	 bwi_enable_intrs(struct bwi_softc *, uint32_t);
 static void	 bwi_disable_intrs(struct bwi_softc *, uint32_t);
 static int	 bwi_init_tx_ring32(struct bwi_softc *, int);
 static void	 bwi_init_rxdesc_ring32(struct bwi_softc *, uint32_t,
 		     bus_addr_t, int, int);
 static int	 bwi_init_rx_ring32(struct bwi_softc *);
 static int	 bwi_init_txstats32(struct bwi_softc *);
 static void	 bwi_setup_rx_desc32(struct bwi_softc *, int, bus_addr_t, int);
 static void	 bwi_setup_tx_desc32(struct bwi_softc *, struct bwi_ring_data *,
 		     int, bus_addr_t, int);
 static int	 bwi_init_tx_ring64(struct bwi_softc *, int);
 static int	 bwi_init_rx_ring64(struct bwi_softc *);
 static int	 bwi_init_txstats64(struct bwi_softc *);
 static void	 bwi_setup_rx_desc64(struct bwi_softc *, int, bus_addr_t, int);
 static void	 bwi_setup_tx_desc64(struct bwi_softc *, struct bwi_ring_data *,
 		     int, bus_addr_t, int);
 static int	 bwi_newbuf(struct bwi_softc *, int, int);
 static void	 bwi_set_addr_filter(struct bwi_softc *, uint16_t,
 		     const uint8_t *);
 static int	 bwi_set_chan(struct bwi_softc *, struct ieee80211_channel *);
 static void	 bwi_next_scan(void *);
 static int	 bwi_rxeof(struct bwi_softc *, int);
 static int	 bwi_rxeof32(struct bwi_softc *);
 static int	 bwi_rxeof64(struct bwi_softc *);
 static void	 bwi_reset_rx_ring32(struct bwi_softc *, uint32_t);
 static void	 bwi_free_txstats32(struct bwi_softc *);
 static void	 bwi_free_rx_ring32(struct bwi_softc *);
 static void	 bwi_free_tx_ring32(struct bwi_softc *, int);
 static void	 bwi_free_txstats64(struct bwi_softc *);
 static void	 bwi_free_rx_ring64(struct bwi_softc *);
 static void	 bwi_free_tx_ring64(struct bwi_softc *, int);
 static uint8_t	 bwi_ieee80211_rate2plcp(uint8_t rate, enum ieee80211_phymode);
 static uint8_t	 bwi_ieee80211_plcp2rate(uint8_t rate, enum ieee80211_phymode);
 static enum bwi_ieee80211_modtype
 		 bwi_ieee80211_rate2modtype(uint8_t rate);
 static uint8_t	 bwi_ofdm_plcp2rate(const void *);
 static uint8_t	 bwi_ds_plcp2rate(const struct ieee80211_ds_plcp_hdr *);
 static void	 bwi_ofdm_plcp_header(uint32_t *, int, uint8_t);
 static void	 bwi_ds_plcp_header(struct ieee80211_ds_plcp_hdr *, int,
 		     uint8_t);
 static void	 bwi_plcp_header(void *, int, uint8_t);
 static int	 bwi_encap(struct bwi_softc *, int, struct mbuf *,
 		     struct ieee80211_node **, int);
 static void	 bwi_start_tx32(struct bwi_softc *, uint32_t, int);
 static void	 bwi_start_tx64(struct bwi_softc *, uint32_t, int);
 static void	 bwi_txeof_status32(struct bwi_softc *);
 static void	 bwi_txeof_status64(struct bwi_softc *);
 static void	 _bwi_txeof(struct bwi_softc *, uint16_t);
 static void	 bwi_txeof_status(struct bwi_softc *, int);
 static void	 bwi_txeof(struct bwi_softc *);
 static int	 bwi_bbp_power_on(struct bwi_softc *, enum bwi_clock_mode);
 static void	 bwi_bbp_power_off(struct bwi_softc *);
 static int	 bwi_get_pwron_delay(struct bwi_softc *sc);
 static int	 bwi_bus_attach(struct bwi_softc *);
 static const char
 		*bwi_regwin_name(const struct bwi_regwin *);
 static int	 bwi_regwin_is_enabled(struct bwi_softc *, struct bwi_regwin *);
 static uint32_t	 bwi_regwin_disable_bits(struct bwi_softc *);
 static void	 bwi_regwin_enable(struct bwi_softc *, struct bwi_regwin *,
 		     uint32_t);
 static void	 bwi_regwin_disable(struct bwi_softc *, struct bwi_regwin *,
 		     uint32_t);
 static void	 bwi_set_bssid(struct bwi_softc *, const uint8_t *);
 static void	 bwi_updateslot(struct ifnet *);
 static void	 bwi_calibrate(void *);
 static int	 bwi_calc_rssi(struct bwi_softc *,
 		     const struct bwi_rxbuf_hdr *);
 static uint8_t	 bwi_ieee80211_ack_rate(struct ieee80211_node *, uint8_t);
 static uint16_t	 bwi_ieee80211_txtime(struct ieee80211com *,
 		     struct ieee80211_node *, uint, uint8_t, uint32_t);
 /* MAC */
 static const uint8_t bwi_sup_macrev[] = { 2, 4, 5, 6, 7, 9, 10, 12 };
 /* PHY */
 #define SUP_BPHY(num)	{ .rev = num, .init = bwi_phy_init_11b_rev##num }
 static const struct {
 	uint8_t	rev;
 	void	(*init)(struct bwi_mac *);
 } bwi_sup_bphy[] = {
 	SUP_BPHY(2),
 	SUP_BPHY(4),
 	SUP_BPHY(5),
 	SUP_BPHY(6)
 };
 #undef SUP_BPHY
 #define BWI_PHYTBL_WRSSI	0x1000
 #define BWI_PHYTBL_NOISE_SCALE	0x1400
 #define BWI_PHYTBL_NOISE	0x1800
 #define BWI_PHYTBL_ROTOR	0x2000
 #define BWI_PHYTBL_DELAY	0x2400
 #define BWI_PHYTBL_RSSI		0x4000
 #define BWI_PHYTBL_SIGMA_SQ	0x5000
 #define BWI_PHYTBL_WRSSI_REV1	0x5400
 #define BWI_PHYTBL_FREQ		0x5800
 static const uint16_t	bwi_phy_freq_11g_rev1[] =
 	{ BWI_PHY_FREQ_11G_REV1 };
 static const uint16_t	bwi_phy_noise_11g_rev1[] =
 	{ BWI_PHY_NOISE_11G_REV1 };
 static const uint16_t	bwi_phy_noise_11g[] =
 	{ BWI_PHY_NOISE_11G };
 static const uint32_t	bwi_phy_rotor_11g_rev1[] =
 	{ BWI_PHY_ROTOR_11G_REV1 };
 static const uint16_t	bwi_phy_noise_scale_11g_rev2[] =
 	{ BWI_PHY_NOISE_SCALE_11G_REV2 };
 static const uint16_t	bwi_phy_noise_scale_11g_rev7[] =
 	{ BWI_PHY_NOISE_SCALE_11G_REV7 };
 static const uint16_t	bwi_phy_noise_scale_11g[] =
 	{ BWI_PHY_NOISE_SCALE_11G };
 static const uint16_t	bwi_phy_sigma_sq_11g_rev2[] =
 	{ BWI_PHY_SIGMA_SQ_11G_REV2 };
 static const uint16_t	bwi_phy_sigma_sq_11g_rev7[] =
 	{ BWI_PHY_SIGMA_SQ_11G_REV7 };
 static const uint32_t	bwi_phy_delay_11g_rev1[] =
 	{ BWI_PHY_DELAY_11G_REV1 };
 /* RF */
 #define RF_LO_WRITE(mac, lo)	bwi_rf_lo_write((mac), (lo))
 #define BWI_RF_2GHZ_CHAN(chan) \
 	(ieee80211_ieee2mhz((chan), IEEE80211_CHAN_2GHZ) - 2400)
 #define BWI_DEFAULT_IDLE_TSSI	52
 struct rf_saveregs {
 	uint16_t	phy_01;
 	uint16_t	phy_03;
 	uint16_t	phy_0a;
 	uint16_t	phy_15;
 	uint16_t	phy_2a;
 	uint16_t	phy_30;
 	uint16_t	phy_35;
 	uint16_t	phy_60;
 	uint16_t	phy_429;
 	uint16_t	phy_802;
 	uint16_t	phy_811;
 	uint16_t	phy_812;
 	uint16_t	phy_814;
 	uint16_t	phy_815;
 	uint16_t	rf_43;
 	uint16_t	rf_52;
 	uint16_t	rf_7a;
 };
 #define SAVE_RF_REG(mac, regs, n)	(regs)->rf_##n = RF_READ((mac), 0x##n)
 #define RESTORE_RF_REG(mac, regs, n)	RF_WRITE((mac), 0x##n, (regs)->rf_##n)
 #define SAVE_PHY_REG(mac, regs, n)	(regs)->phy_##n = PHY_READ((mac), 0x##n)
 #define RESTORE_PHY_REG(mac, regs, n)	PHY_WRITE((mac), 0x##n, (regs)->phy_##n)
 static const int8_t	bwi_txpower_map_11b[BWI_TSSI_MAX] =
 	{ BWI_TXPOWER_MAP_11B };
 static const int8_t	bwi_txpower_map_11g[BWI_TSSI_MAX] =
 	{ BWI_TXPOWER_MAP_11G };
 /* INTERFACE */
 struct bwi_myaddr_bssid {
 	uint8_t		myaddr[IEEE80211_ADDR_LEN];
 	uint8_t		bssid[IEEE80211_ADDR_LEN];
 } __packed;
 /* [TRC: XXX What are these about?] */
 #define IEEE80211_DS_PLCP_SERVICE_LOCKED	0x04
 #define IEEE80211_DS_PLCL_SERVICE_PBCC		0x08
 #define IEEE80211_DS_PLCP_SERVICE_LENEXT5	0x20
 #define IEEE80211_DS_PLCP_SERVICE_LENEXT6	0x40
 #define IEEE80211_DS_PLCP_SERVICE_LENEXT7	0x80
 static const struct {
 	uint16_t	did_min;
 	uint16_t	did_max;
 	uint16_t	bbp_id;
 } bwi_bbpid_map[] = {
 	{ 0x4301, 0x4301, 0x4301 },
 	{ 0x4305, 0x4307, 0x4307 },
 	{ 0x4403, 0x4403, 0x4402 },
 	{ 0x4610, 0x4615, 0x4610 },
 	{ 0x4710, 0x4715, 0x4710 },
 	{ 0x4720, 0x4725, 0x4309 }
 };
 static const struct {
 	uint16_t	bbp_id;
 	int		nregwin;
 } bwi_regwin_count[] = {
 	{ 0x4301, 5 },
 	{ 0x4306, 6 },
 	{ 0x4307, 5 },
 	{ 0x4310, 8 },
 	{ 0x4401, 3 },
 	{ 0x4402, 3 },
 	{ 0x4610, 9 },
 	{ 0x4704, 9 },
 	{ 0x4710, 9 },
 	{ 0x5365, 7 }
 };
 #define CLKSRC(src) 				\
 [BWI_CLKSRC_ ## src] = {			\
 	.freq_min = BWI_CLKSRC_ ##src## _FMIN,	\
 	.freq_max = BWI_CLKSRC_ ##src## _FMAX	\
+}
 static const struct {
 	uint	freq_min;
 	uint	freq_max;
 } bwi_clkfreq[BWI_CLKSRC_MAX] = {
 	CLKSRC(LP_OSC),
 	CLKSRC(CS_OSC),
 	CLKSRC(PCI)
 };
 #undef CLKSRC
 #define VENDOR_LED_ACT(vendor)				\
 {							\
 	.vid = PCI_VENDOR_##vendor,			\
 	.led_act = { BWI_VENDOR_LED_ACT_##vendor }	\
+}
 static const struct {
 	uint16_t	vid;
 	uint8_t		led_act[BWI_LED_MAX];
 } bwi_vendor_led_act[] = {
 	VENDOR_LED_ACT(COMPAQ),
 	VENDOR_LED_ACT(LINKSYS)
 };
 static const uint8_t bwi_default_led_act[BWI_LED_MAX] =
 	{ BWI_VENDOR_LED_ACT_DEFAULT };
 #undef VENDOR_LED_ACT
 static const struct {
 	int	on_dur;
 	int	off_dur;
 } bwi_led_duration[109] = {
 	[0]	= { 400, 100 },
 	[2]	= { 150, 75 },
 	[4]	= { 90, 45 },
 	[11]	= { 66, 34 },
 	[12]	= { 53, 26 },
 	[18]	= { 42, 21 },
 	[22]	= { 35, 17 },
 	[24]	= { 32, 16 },
 	[36]	= { 21, 10 },
 	[48]	= { 16, 8 },
 	[72]	= { 11, 5 },
 	[96]	= { 9, 4 },
 	[108]	= { 7, 3 }
 };
 /* [TRC: XXX Should this be zeroed?] */
 static const uint8_t bwi_zero_addr[IEEE80211_ADDR_LEN];
 /* [TRC: Derived from DragonFly's src/sys/netproto/802_11/_ieee80211.h */
 enum bwi_ieee80211_modtype {
 	IEEE80211_MODTYPE_DS	= 0,	/* DS/CCK modulation */
 	IEEE80211_MODTYPE_PBCC	= 1,	/* PBCC modulation */
 	IEEE80211_MODTYPE_OFDM	= 2	/* OFDM modulation */
 };
 #define IEEE80211_MODTYPE_CCK   IEEE80211_MODTYPE_DS
 /*
  * Setup sysctl(3) MIB, hw.bwi.* and hw.bwiN.*
  */
 #ifdef BWI_DEBUG
 SYSCTL_SETUP(sysctl_bwi, "sysctl bwi(4) subtree setup")
+{
 	int rc;
 	const struct sysctlnode *rnode;
 	const struct sysctlnode *cnode;
 	if ((rc = sysctl_createv(clog, 0, NULL, &rnode,
 	    CTLFLAG_PERMANENT, CTLTYPE_NODE, "bwi",
 	    SYSCTL_DESCR("bwi global controls"),
 	    NULL, 0, NULL, 0, CTL_HW, CTL_CREATE, CTL_EOL)) != 0)
 		goto err;
 	if ((rc = sysctl_createv(clog, 0, &rnode, &cnode,
 	    CTLFLAG_PERMANENT|CTLFLAG_READWRITE, CTLTYPE_INT,
 	    "debug", SYSCTL_DESCR("default debug flags"),
 	    NULL, 0, &bwi_debug, 0, CTL_CREATE, CTL_EOL)) != 0)
 		goto err;
 	return;
 err:
 	aprint_error("%s: sysctl_createv failed (rc = %d)\n", __func__, rc);
+}
 #endif	/* BWI_DEBUG */
 static void
 bwi_sysctlattach(struct bwi_softc *sc)
+{
 	int rc;
 	const struct sysctlnode *rnode;
 	const struct sysctlnode *cnode;
 	struct sysctllog **clog = &sc->sc_sysctllog;
 	if ((rc = sysctl_createv(clog, 0, NULL, &rnode,
 	    CTLFLAG_PERMANENT, CTLTYPE_NODE, device_xname(sc->sc_dev),
 	    SYSCTL_DESCR("bwi controls and statistics"),
 	    NULL, 0, NULL, 0, CTL_HW, CTL_CREATE, CTL_EOL)) != 0)
 		goto err;
 	if ((rc = sysctl_createv(clog, 0, &rnode, &cnode,
 	    CTLFLAG_PERMANENT|CTLFLAG_READWRITE, CTLTYPE_INT,
 	    "fw_version", SYSCTL_DESCR("firmware version"),
 	    NULL, 0, &sc->sc_fw_version, 0, CTL_CREATE, CTL_EOL)) != 0)
 		goto err;
 	if ((rc = sysctl_createv(clog, 0, &rnode, &cnode,
 	    CTLFLAG_PERMANENT|CTLFLAG_READWRITE, CTLTYPE_INT,
 	    "dwell_time", SYSCTL_DESCR("channel dwell time during scan (msec)"),
 	    NULL, 0, &sc->sc_dwell_time, 0, CTL_CREATE, CTL_EOL)) != 0)
 		goto err;
 	if ((rc = sysctl_createv(clog, 0, &rnode, &cnode,
 	    CTLFLAG_PERMANENT|CTLFLAG_READWRITE, CTLTYPE_INT,
 	    "led_idle", SYSCTL_DESCR("# ticks before LED enters idle state"),
 	    NULL, 0, &sc->sc_led_idle, 0, CTL_CREATE, CTL_EOL)) != 0)
 		goto err;
 	if ((rc = sysctl_createv(clog, 0, &rnode, &cnode,
 	    CTLFLAG_PERMANENT|CTLFLAG_READWRITE, CTLTYPE_INT,
 	    "led_blink", SYSCTL_DESCR("allow LED to blink"),
 	    NULL, 0, &sc->sc_led_blink, 0, CTL_CREATE, CTL_EOL)) != 0)
 		goto err;
 	if ((rc = sysctl_createv(clog, 0, &rnode, &cnode,
 	    CTLFLAG_PERMANENT|CTLFLAG_READWRITE, CTLTYPE_INT,
 	    "txpwr_calib", SYSCTL_DESCR("enable software TX power calibration"),
 	    NULL, 0, &sc->sc_txpwr_calib, 0, CTL_CREATE, CTL_EOL)) != 0)
 		goto err;
 #ifdef BWI_DEBUG
 	if ((rc = sysctl_createv(clog, 0, &rnode, &cnode,
 	    CTLFLAG_PERMANENT|CTLFLAG_READWRITE, CTLTYPE_INT,
 	    "debug", SYSCTL_DESCR("debug flags"),
 	    NULL, 0, &sc->sc_debug, 0, CTL_CREATE, CTL_EOL)) != 0)
 		goto err;
 #endif
 	return;
 err:
 	aprint_error("%s: sysctl_createv failed (rc = %d)\n", __func__, rc);
+}
 /* CODE */
 int
 bwi_intr(void *arg)
+{
 	struct bwi_softc *sc = arg;
 	struct ifnet *ifp = &sc->sc_if;
 	if (!device_is_active(sc->sc_dev) ||
 	    (ifp->if_flags & IFF_RUNNING) == 0)
 		return (0);
 	/* Disable all interrupts */
 	bwi_disable_intrs(sc, BWI_ALL_INTRS);
 	softint_schedule(sc->sc_soft_ih);
 	return (1);
+}
 static void
 bwi_softintr(void *arg)
+{
 	struct bwi_softc *sc = arg;
 	struct bwi_mac *mac;
 	struct ifnet *ifp = &sc->sc_if;
 	uint32_t intr_status;
 	uint32_t txrx_intr_status[BWI_TXRX_NRING];
 	int i, s, txrx_error, tx = 0, rx_data = -1;
 	if (!device_is_active(sc->sc_dev) ||
 	    (ifp->if_flags & IFF_RUNNING) == 0)
 		return;
 	for (;;) {
 		/*
 		 * Get interrupt status
 		 */
 		intr_status = CSR_READ_4(sc, BWI_MAC_INTR_STATUS);
 		if (intr_status == 0xffffffff)	/* Not for us */
 			goto out;
 		intr_status &= CSR_READ_4(sc, BWI_MAC_INTR_MASK);
 		if (intr_status == 0)		/* Nothing is interesting */
 			goto out;
 		DPRINTF(sc, BWI_DBG_INTR, "intr status 0x%08x\n", intr_status);
 		KASSERT(sc->sc_cur_regwin->rw_type == BWI_REGWIN_T_MAC);
 		mac = (struct bwi_mac *)sc->sc_cur_regwin;
 		txrx_error = 0;
 		for (i = 0; i < BWI_TXRX_NRING; ++i) {
 			uint32_t mask;
 			if (BWI_TXRX_IS_RX(i))
 				mask = BWI_TXRX_RX_INTRS;
 			else
 				mask = BWI_TXRX_TX_INTRS;
 			txrx_intr_status[i] =
 			    CSR_READ_4(sc, BWI_TXRX_INTR_STATUS(i)) & mask;
 			if (txrx_intr_status[i] & BWI_TXRX_INTR_ERROR) {
 				aprint_error_dev(sc->sc_dev,
 				    "intr fatal TX/RX (%d) error 0x%08x\n",
 				    i, txrx_intr_status[i]);
 				txrx_error = 1;
+			}
+		}
 		/*
 		 * Acknowledge interrupt
 		 */
 		CSR_WRITE_4(sc, BWI_MAC_INTR_STATUS, intr_status);
 		for (i = 0; i < BWI_TXRX_NRING; ++i)
 			CSR_WRITE_4(sc, BWI_TXRX_INTR_STATUS(i),
 			    txrx_intr_status[i]);
 		if (intr_status & BWI_INTR_PHY_TXERR) {
 			if (mac->mac_flags & BWI_MAC_F_PHYE_RESET) {
 				aprint_error_dev(sc->sc_dev,
 				    "intr PHY TX error\n");
 				/* XXX to netisr0? */
 				s = splnet();
 				bwi_init_statechg(sc, 0);
 				splx(s);
 				goto out;
+			}
+		}
 		if (txrx_error) {
 			/* TODO: reset device */
+		}
 		if (intr_status & BWI_INTR_TBTT)
 			bwi_mac_config_ps(mac);
 		if (intr_status & BWI_INTR_EO_ATIM)
 			aprint_normal_dev(sc->sc_dev, "EO_ATIM\n");
 		if (intr_status & BWI_INTR_PMQ) {
 			for (;;) {
 				if ((CSR_READ_4(sc, BWI_MAC_PS_STATUS) & 0x8)
 				    == 0)
 					break;
+			}
 			CSR_WRITE_2(sc, BWI_MAC_PS_STATUS, 0x2);
+		}
 		if (intr_status & BWI_INTR_NOISE)
 			aprint_normal_dev(sc->sc_dev, "intr noise\n");
 		if (txrx_intr_status[0] & BWI_TXRX_INTR_RX)
 			rx_data = (sc->sc_rxeof)(sc);
 		if (txrx_intr_status[3] & BWI_TXRX_INTR_RX) {
 			(sc->sc_txeof_status)(sc);
 			tx = 1;
+		}
 		if (intr_status & BWI_INTR_TX_DONE) {
 			bwi_txeof(sc);
 			tx = 1;
+		}
 		if (sc->sc_blink_led != NULL && sc->sc_led_blink) {
 			int evt = BWI_LED_EVENT_NONE;
 			if (tx && rx_data > 0) {
 				if (sc->sc_rx_rate > sc->sc_tx_rate)
 					evt = BWI_LED_EVENT_RX;
 				else
 					evt = BWI_LED_EVENT_TX;
 			} else if (tx) {
 				evt = BWI_LED_EVENT_TX;
 			} else if (rx_data > 0) {
 				evt = BWI_LED_EVENT_RX;
 			} else if (rx_data == 0) {
 				evt = BWI_LED_EVENT_POLL;
+			}
 			if (evt != BWI_LED_EVENT_NONE)
 				bwi_led_event(sc, evt);
+		}
+	}
 out:
 	/* Re-enable interrupts */
 	bwi_enable_intrs(sc, BWI_INIT_INTRS);
+}
 int
 bwi_attach(struct bwi_softc *sc)
+{
 	struct ieee80211com *ic = &sc->sc_ic;
 	struct ifnet *ifp = &sc->sc_if;
 	struct bwi_mac *mac;
 	struct bwi_phy *phy;
 	int s, i, error;
 	/* [TRC: XXX Is this necessary?] */
 	s = splnet();
 	sc->sc_soft_ih = softint_establish(SOFTINT_NET, bwi_softintr, sc);
 	if (sc->sc_soft_ih == NULL) {
 		error = ENXIO;
 		goto fail;
+	}
 	/*
 	 * Initialize sysctl variables
 	 */
 	sc->sc_fw_version = BWI_FW_VERSION3;
 	sc->sc_dwell_time = 200;
 	sc->sc_led_idle = (2350 * hz) / 1000;
 	sc->sc_led_blink = 1;
 	sc->sc_txpwr_calib = 1;
 #ifdef BWI_DEBUG
 	sc->sc_debug = bwi_debug;
 #endif
 	DPRINTF(sc, BWI_DBG_ATTACH, "%s\n", __func__);
 	/* [TRC: XXX amrr] */
 	/* AMRR rate control */
 	sc->sc_amrr.amrr_min_success_threshold = 1;
 	sc->sc_amrr.amrr_max_success_threshold = 15;
 	callout_init(&sc->sc_amrr_ch, 0);
 	callout_setfunc(&sc->sc_amrr_ch, bwi_amrr_timeout, sc);
 	callout_init(&sc->sc_scan_ch, 0);
 	callout_setfunc(&sc->sc_scan_ch, bwi_next_scan, sc);
 	callout_init(&sc->sc_calib_ch, 0);
 	callout_setfunc(&sc->sc_calib_ch, bwi_calibrate, sc);
 	bwi_sysctlattach(sc);
 	bwi_power_on(sc, 1);
 	error = bwi_bbp_attach(sc);
 	if (error)
 		goto fail;
 	error = bwi_bbp_power_on(sc, BWI_CLOCK_MODE_FAST);
 	if (error)
 		goto fail;
 	if (BWI_REGWIN_EXIST(&sc->sc_com_regwin)) {
 		error = bwi_set_clock_delay(sc);
 		if (error)
 			goto fail;
 		error = bwi_set_clock_mode(sc, BWI_CLOCK_MODE_FAST);
 		if (error)
 			goto fail;
 		error = bwi_get_pwron_delay(sc);
 		if (error)
 			goto fail;
+	}
 	error = bwi_bus_attach(sc);
 	if (error)
 		goto fail;
 	bwi_get_card_flags(sc);
 	bwi_led_attach(sc);
 	for (i = 0; i < sc->sc_nmac; ++i) {
 		struct bwi_regwin *old;
 		mac = &sc->sc_mac[i];
 		error = bwi_regwin_switch(sc, &mac->mac_regwin, &old);
 		if (error)
 			goto fail;
 		error = bwi_mac_lateattach(mac);
 		if (error)
 			goto fail;
 		error = bwi_regwin_switch(sc, old, NULL);
 		if (error)
 			goto fail;
+	}
 	/*
 	 * XXX First MAC is known to exist
 	 * TODO2
 	 */
 	mac = &sc->sc_mac[0];
 	phy = &mac->mac_phy;
 	bwi_bbp_power_off(sc);
 	error = bwi_dma_alloc(sc);
 	if (error)
 		goto fail;
 	/* setup interface */
 	ifp->if_softc = sc;
 	ifp->if_init = bwi_init;
 	ifp->if_ioctl = bwi_ioctl;
 	ifp->if_start = bwi_start;
 	ifp->if_watchdog = bwi_watchdog;
 	ifp->if_stop = bwi_stop;
 	ifp->if_flags = IFF_SIMPLEX | IFF_BROADCAST | IFF_MULTICAST;
 	memcpy(ifp->if_xname, device_xname(sc->sc_dev), IFNAMSIZ);
 	IFQ_SET_READY(&ifp->if_snd);
 	/* Get locale */
 	sc->sc_locale = __SHIFTOUT(bwi_read_sprom(sc, BWI_SPROM_CARD_INFO),
 	    BWI_SPROM_CARD_INFO_LOCALE);
 	DPRINTF(sc, BWI_DBG_ATTACH, "locale: %d\n", sc->sc_locale);
 	/*
 	 * Setup ratesets, phytype, channels and get MAC address
 	 */
 	if (phy->phy_mode == IEEE80211_MODE_11B ||
 	    phy->phy_mode == IEEE80211_MODE_11G) {
 		uint16_t chan_flags;
 		ic->ic_sup_rates[IEEE80211_MODE_11B] =
 		    ieee80211_std_rateset_11b;
 		if (phy->phy_mode == IEEE80211_MODE_11B) {
 			chan_flags = IEEE80211_CHAN_B;
 			ic->ic_phytype = IEEE80211_T_DS;
 		} else {
 			chan_flags = IEEE80211_CHAN_CCK |
 			    IEEE80211_CHAN_OFDM |
 			    IEEE80211_CHAN_DYN |
 			    IEEE80211_CHAN_2GHZ;
 			ic->ic_phytype = IEEE80211_T_OFDM;
 			ic->ic_sup_rates[IEEE80211_MODE_11G] =
 			    ieee80211_std_rateset_11g;
+		}
 		/* XXX depend on locale */
 		for (i = 1; i <= 14; ++i) {
 			ic->ic_channels[i].ic_freq =
 			    ieee80211_ieee2mhz(i, IEEE80211_CHAN_2GHZ);
 			ic->ic_channels[i].ic_flags = chan_flags;
+		}
 		bwi_get_eaddr(sc, BWI_SPROM_11BG_EADDR, ic->ic_myaddr);
 		if (IEEE80211_IS_MULTICAST(ic->ic_myaddr)) {
 			bwi_get_eaddr(sc, BWI_SPROM_11A_EADDR, ic->ic_myaddr);
 			if (IEEE80211_IS_MULTICAST(ic->ic_myaddr))
 				aprint_error_dev(sc->sc_dev,
 				    "invalid MAC address: %s\n",
 				    ether_sprintf(ic->ic_myaddr));
+		}
 	} else if (phy->phy_mode == IEEE80211_MODE_11A) {
 		/* TODO: 11A */
 		error = ENXIO;
 		goto fail;
 	} else
 		panic("unknown phymode %d\n", phy->phy_mode);
 	ic->ic_ifp = ifp;
 	ic->ic_caps = IEEE80211_C_SHSLOT |
 	    IEEE80211_C_SHPREAMBLE |
 	    IEEE80211_C_IBSS |
 	    IEEE80211_C_HOSTAP |
 	    IEEE80211_C_MONITOR;
 	ic->ic_state = IEEE80211_S_INIT;
 	ic->ic_opmode = IEEE80211_M_STA;
 	ic->ic_updateslot = bwi_updateslot;
 	error = if_initialize(ifp);
 	if (error != 0) {
 		aprint_error_dev(sc->sc_dev, "if_initialize failed(%d)\n",
 		    error);
 		goto fail;
+	}
 	ieee80211_ifattach(ic);
 	ifp->if_percpuq = if_percpuq_create(ifp);
 	if_register(ifp);
 	/* [TRC: XXX Not supported on NetBSD?] */
 	/* ic->ic_flags_ext |= IEEE80211_FEXT_SWBMISS; */
 	sc->sc_newstate = ic->ic_newstate;
 	ic->ic_newstate = bwi_newstate;
 	/* [TRC: XXX amrr] */
 	ic->ic_newassoc = bwi_newassoc;
 	ic->ic_node_alloc = bwi_node_alloc;
 	ieee80211_media_init(ic, bwi_media_change, ieee80211_media_status);
 	bpf_attach2(ifp, DLT_IEEE802_11_RADIO,
 	    sizeof(struct ieee80211_frame) + IEEE80211_RADIOTAP_HDRLEN,
 	    &sc->sc_drvbpf);
 	/* [TRC: XXX DragonFlyBSD rounds this up to a multiple of
 	   sizeof(uint32_t).  Should we?] */
 @@ -6424,3337 +6424,3337 @@ bwi_power_on(struct bwi_softc *sc, int w
 	DPRINTF(sc, BWI_DBG_MISC, "%s\n", __func__);
 	gpio_in = (sc->sc_conf_read)(sc, BWI_PCIR_GPIO_IN);
 	if (gpio_in & BWI_PCIM_GPIO_PWR_ON)
 		goto back;
 	gpio_out = (sc->sc_conf_read)(sc, BWI_PCIR_GPIO_OUT);
 	gpio_en = (sc->sc_conf_read)(sc, BWI_PCIR_GPIO_ENABLE);
 	gpio_out |= BWI_PCIM_GPIO_PWR_ON;
 	gpio_en |= BWI_PCIM_GPIO_PWR_ON;
 	if (with_pll) {
 		/* Turn off PLL first */
 		gpio_out |= BWI_PCIM_GPIO_PLL_PWR_OFF;
 		gpio_en |= BWI_PCIM_GPIO_PLL_PWR_OFF;
+	}
 	(sc->sc_conf_write)(sc, BWI_PCIR_GPIO_OUT, gpio_out);
 	(sc->sc_conf_write)(sc, BWI_PCIR_GPIO_ENABLE, gpio_en);
 	DELAY(1000);
 	if (with_pll) {
 		/* Turn on PLL */
 		gpio_out &= ~BWI_PCIM_GPIO_PLL_PWR_OFF;
 		(sc->sc_conf_write)(sc, BWI_PCIR_GPIO_OUT, gpio_out);
 		DELAY(5000);
+	}
 back:
 	/* [TRC: XXX This looks totally wrong -- what's PCI doing in here?] */
 	/* Clear "Signaled Target Abort" */
 	status = (sc->sc_conf_read)(sc, PCI_COMMAND_STATUS_REG);
 	status &= ~PCI_STATUS_TARGET_TARGET_ABORT;
 	(sc->sc_conf_write)(sc, PCI_COMMAND_STATUS_REG, status);
+}
 static int
 bwi_power_off(struct bwi_softc *sc, int with_pll)
+{
 	uint32_t gpio_out, gpio_en;
 	DPRINTF(sc, BWI_DBG_MISC, "%s\n", __func__);
 	(sc->sc_conf_read)(sc, BWI_PCIR_GPIO_IN); /* dummy read */
 	gpio_out = (sc->sc_conf_read)(sc, BWI_PCIR_GPIO_OUT);
 	gpio_en = (sc->sc_conf_read)(sc, BWI_PCIR_GPIO_ENABLE);
 	gpio_out &= ~BWI_PCIM_GPIO_PWR_ON;
 	gpio_en |= BWI_PCIM_GPIO_PWR_ON;
 	if (with_pll) {
 		gpio_out |= BWI_PCIM_GPIO_PLL_PWR_OFF;
 		gpio_en |= BWI_PCIM_GPIO_PLL_PWR_OFF;
+	}
 	(sc->sc_conf_write)(sc, BWI_PCIR_GPIO_OUT, gpio_out);
 	(sc->sc_conf_write)(sc, BWI_PCIR_GPIO_ENABLE, gpio_en);
 	return (0);
+}
 static int
 bwi_regwin_switch(struct bwi_softc *sc, struct bwi_regwin *rw,
     struct bwi_regwin **old_rw)
+{
 	int error;
 	if (old_rw != NULL)
 		*old_rw = NULL;
 	if (!BWI_REGWIN_EXIST(rw))
 		return (EINVAL);
 	if (sc->sc_cur_regwin != rw) {
 		error = bwi_regwin_select(sc, rw->rw_id);
 		if (error) {
 			aprint_error_dev(sc->sc_dev,
 			    "can't select regwin %d\n", rw->rw_id);
 			return (error);
+		}
+	}
 	if (old_rw != NULL)
 		*old_rw = sc->sc_cur_regwin;
 	sc->sc_cur_regwin = rw;
 	return (0);
+}
 static int
 bwi_regwin_select(struct bwi_softc *sc, int id)
+{
 	uint32_t win = BWI_PCIM_REGWIN(id);
 	int i;
 #define RETRY_MAX	50
 	for (i = 0; i < RETRY_MAX; ++i) {
 		(sc->sc_conf_write)(sc, BWI_PCIR_SEL_REGWIN, win);
 		if ((sc->sc_conf_read)(sc, BWI_PCIR_SEL_REGWIN) == win)
 			return (0);
 		DELAY(10);
+	}
 #undef RETRY_MAX
 	return (ENXIO);
+}
 static void
 bwi_regwin_info(struct bwi_softc *sc, uint16_t *type, uint8_t *rev)
+{
 	uint32_t val;
 	val = CSR_READ_4(sc, BWI_ID_HI);
 	*type = BWI_ID_HI_REGWIN_TYPE(val);
 	*rev = BWI_ID_HI_REGWIN_REV(val);
 	DPRINTF(sc, BWI_DBG_ATTACH, "regwin: type 0x%03x, rev %d,"
 	    " vendor 0x%04x\n", *type, *rev,
 	    __SHIFTOUT(val, BWI_ID_HI_REGWIN_VENDOR_MASK));
+}
 static void
 bwi_led_attach(struct bwi_softc *sc)
+{
 	const uint8_t *led_act = NULL;
 	uint16_t gpio, val[BWI_LED_MAX];
 	int i;
 	for (i = 0; i < __arraycount(bwi_vendor_led_act); ++i) {
 		if (sc->sc_pci_subvid == bwi_vendor_led_act[i].vid) {
 			led_act = bwi_vendor_led_act[i].led_act;
 			break;
+		}
+	}
 	if (led_act == NULL)
 		led_act = bwi_default_led_act;
 	gpio = bwi_read_sprom(sc, BWI_SPROM_GPIO01);
 	val[0] = __SHIFTOUT(gpio, BWI_SPROM_GPIO_0);
 	val[1] = __SHIFTOUT(gpio, BWI_SPROM_GPIO_1);
 	gpio = bwi_read_sprom(sc, BWI_SPROM_GPIO23);
 	val[2] = __SHIFTOUT(gpio, BWI_SPROM_GPIO_2);
 	val[3] = __SHIFTOUT(gpio, BWI_SPROM_GPIO_3);
 	for (i = 0; i < BWI_LED_MAX; ++i) {
 		struct bwi_led *led = &sc->sc_leds[i];
 		if (val[i] == 0xff) {
 			led->l_act = led_act[i];
 		} else {
 			if (val[i] & BWI_LED_ACT_LOW)
 				led->l_flags |= BWI_LED_F_ACTLOW;
 			led->l_act = __SHIFTOUT(val[i], BWI_LED_ACT_MASK);
+		}
 		led->l_mask = (1 << i);
 		if (led->l_act == BWI_LED_ACT_BLINK_SLOW ||
 		    led->l_act == BWI_LED_ACT_BLINK_POLL ||
 		    led->l_act == BWI_LED_ACT_BLINK) {
 			led->l_flags |= BWI_LED_F_BLINK;
 			if (led->l_act == BWI_LED_ACT_BLINK_POLL)
 				led->l_flags |= BWI_LED_F_POLLABLE;
 			else if (led->l_act == BWI_LED_ACT_BLINK_SLOW)
 				led->l_flags |= BWI_LED_F_SLOW;
 			if (sc->sc_blink_led == NULL) {
 				sc->sc_blink_led = led;
 				if (led->l_flags & BWI_LED_F_SLOW)
 					BWI_LED_SLOWDOWN(sc->sc_led_idle);
+			}
+		}
 		DPRINTF(sc, BWI_DBG_LED | BWI_DBG_ATTACH,
 		    "%dth led, act %d, lowact %d\n", i, led->l_act,
 		    led->l_flags & BWI_LED_F_ACTLOW);
+	}
 	callout_init(&sc->sc_led_blink_ch, 0);
+}
 static uint16_t
 bwi_led_onoff(const struct bwi_led *led, uint16_t val, int on)
+{
 	if (led->l_flags & BWI_LED_F_ACTLOW)
 		on = !on;
 	if (on)
 		val |= led->l_mask;
 	else
 		val &= ~led->l_mask;
 	return (val);
+}
 static void
 bwi_led_newstate(struct bwi_softc *sc, enum ieee80211_state nstate)
+{
 	struct ieee80211com *ic = &sc->sc_ic;
 	struct ifnet *ifp = &sc->sc_if;
 	uint16_t val;
 	int i;
 	if (nstate == IEEE80211_S_INIT) {
 		callout_stop(&sc->sc_led_blink_ch);
 		sc->sc_led_blinking = 0;
+	}
 	if ((ifp->if_flags & IFF_RUNNING) == 0)
 		return;
 	val = CSR_READ_2(sc, BWI_MAC_GPIO_CTRL);
 	for (i = 0; i < BWI_LED_MAX; ++i) {
 		struct bwi_led *led = &sc->sc_leds[i];
 		int on;
 		if (led->l_act == BWI_LED_ACT_UNKN ||
 		    led->l_act == BWI_LED_ACT_NULL)
 			continue;
 		if ((led->l_flags & BWI_LED_F_BLINK) &&
 		    nstate != IEEE80211_S_INIT)
 			continue;
 		switch (led->l_act) {
 		case BWI_LED_ACT_ON:	/* Always on */
 			on = 1;
 			break;
 		case BWI_LED_ACT_OFF:	/* Always off */
 		case BWI_LED_ACT_5GHZ:	/* TODO: 11A */
 			on = 0;
 			break;
 		default:
 			on = 1;
 			switch (nstate) {
 			case IEEE80211_S_INIT:
 				on = 0;
 				break;
 			case IEEE80211_S_RUN:
 				if (led->l_act == BWI_LED_ACT_11G &&
 				    ic->ic_curmode != IEEE80211_MODE_11G)
 					on = 0;
 				break;
 			default:
 				if (led->l_act == BWI_LED_ACT_ASSOC)
 					on = 0;
 				break;
+			}
 			break;
+		}
 		val = bwi_led_onoff(led, val, on);
+	}
 	CSR_WRITE_2(sc, BWI_MAC_GPIO_CTRL, val);
+}
 static void
 bwi_led_event(struct bwi_softc *sc, int event)
+{
 	struct bwi_led *led = sc->sc_blink_led;
 	int rate;
 	if (event == BWI_LED_EVENT_POLL) {
 		if ((led->l_flags & BWI_LED_F_POLLABLE) == 0)
 			return;
 		if (ticks - sc->sc_led_ticks < sc->sc_led_idle)
 			return;
+	}
 	sc->sc_led_ticks = ticks;
 	if (sc->sc_led_blinking)
 		return;
 	switch (event) {
 	case BWI_LED_EVENT_RX:
 		rate = sc->sc_rx_rate;
 		break;
 	case BWI_LED_EVENT_TX:
 		rate = sc->sc_tx_rate;
 		break;
 	case BWI_LED_EVENT_POLL:
 		rate = 0;
 		break;
 	default:
 		panic("unknown LED event %d\n", event);
 		break;
+	}
 	bwi_led_blink_start(sc, bwi_led_duration[rate].on_dur,
 	    bwi_led_duration[rate].off_dur);
+}
 static void
 bwi_led_blink_start(struct bwi_softc *sc, int on_dur, int off_dur)
+{
 	struct bwi_led *led = sc->sc_blink_led;
 	uint16_t val;
 	val = CSR_READ_2(sc, BWI_MAC_GPIO_CTRL);
 	val = bwi_led_onoff(led, val, 1);
 	CSR_WRITE_2(sc, BWI_MAC_GPIO_CTRL, val);
 	if (led->l_flags & BWI_LED_F_SLOW) {
 		BWI_LED_SLOWDOWN(on_dur);
 		BWI_LED_SLOWDOWN(off_dur);
+	}
 	sc->sc_led_blinking = 1;
 	sc->sc_led_blink_offdur = off_dur;
 	callout_reset(&sc->sc_led_blink_ch, on_dur, bwi_led_blink_next, sc);
+}
 static void
 bwi_led_blink_next(void *xsc)
+{
 	struct bwi_softc *sc = xsc;
 	uint16_t val;
 	val = CSR_READ_2(sc, BWI_MAC_GPIO_CTRL);
 	val = bwi_led_onoff(sc->sc_blink_led, val, 0);
 	CSR_WRITE_2(sc, BWI_MAC_GPIO_CTRL, val);
 	callout_reset(&sc->sc_led_blink_ch, sc->sc_led_blink_offdur,
 	    bwi_led_blink_end, sc);
+}
 static void
 bwi_led_blink_end(void *xsc)
+{
 	struct bwi_softc *sc = xsc;
 	sc->sc_led_blinking = 0;
+}
 static int
 bwi_bbp_attach(struct bwi_softc *sc)
+{
 	uint16_t bbp_id, rw_type;
 	uint8_t rw_rev;
 	uint32_t info;
 	int error, nregwin, i;
 	/*
 	 * Get 0th regwin information
 	 * NOTE: 0th regwin should exist
 	 */
 	error = bwi_regwin_select(sc, 0);
 	if (error) {
 		aprint_error_dev(sc->sc_dev, "can't select regwin 0\n");
 		return (error);
+	}
 	bwi_regwin_info(sc, &rw_type, &rw_rev);
 	/*
 	 * Find out BBP id
 	 */
 	bbp_id = 0;
 	info = 0;
 	if (rw_type == BWI_REGWIN_T_COM) {
 		info = CSR_READ_4(sc, BWI_INFO);
 		bbp_id = __SHIFTOUT(info, BWI_INFO_BBPID_MASK);
 		BWI_CREATE_REGWIN(&sc->sc_com_regwin, 0, rw_type, rw_rev);
 		sc->sc_cap = CSR_READ_4(sc, BWI_CAPABILITY);
 	} else {
 		uint16_t did = sc->sc_pci_did;
 		uint8_t revid = sc->sc_pci_revid;
 		for (i = 0; i < __arraycount(bwi_bbpid_map); ++i) {
 			if (did >= bwi_bbpid_map[i].did_min &&
 			    did <= bwi_bbpid_map[i].did_max) {
 				bbp_id = bwi_bbpid_map[i].bbp_id;
 				break;
+			}
+		}
 		if (bbp_id == 0) {
 			aprint_error_dev(sc->sc_dev, "no BBP id for device id"
 			    " 0x%04x\n", did);
 			return (ENXIO);
+		}
 		info = __SHIFTIN(revid, BWI_INFO_BBPREV_MASK) |
 		    __SHIFTIN(0, BWI_INFO_BBPPKG_MASK);
+	}
 	/*
 	 * Find out number of regwins
 	 */
 	nregwin = 0;
 	if (rw_type == BWI_REGWIN_T_COM && rw_rev >= 4) {
 		nregwin = __SHIFTOUT(info, BWI_INFO_NREGWIN_MASK);
 	} else {
 		for (i = 0; i < __arraycount(bwi_regwin_count); ++i) {
 			if (bwi_regwin_count[i].bbp_id == bbp_id) {
 				nregwin = bwi_regwin_count[i].nregwin;
 				break;
+			}
+		}
 		if (nregwin == 0) {
 			aprint_error_dev(sc->sc_dev, "no number of win for"
 			    " BBP id 0x%04x\n", bbp_id);
 			return (ENXIO);
+		}
+	}
 	/* Record BBP id/rev for later using */
 	sc->sc_bbp_id = bbp_id;
 	sc->sc_bbp_rev = __SHIFTOUT(info, BWI_INFO_BBPREV_MASK);
 	sc->sc_bbp_pkg = __SHIFTOUT(info, BWI_INFO_BBPPKG_MASK);
 	aprint_normal_dev(sc->sc_dev,
 	    "BBP id 0x%04x, BBP rev 0x%x, BBP pkg %d\n",
 	    sc->sc_bbp_id, sc->sc_bbp_rev, sc->sc_bbp_pkg);
 	DPRINTF(sc, BWI_DBG_ATTACH, "nregwin %d, cap 0x%08x\n",
 	    nregwin, sc->sc_cap);
 	/*
 	 * Create rest of the regwins
 	 */
 	/* Don't re-create common regwin, if it is already created */
 	i = BWI_REGWIN_EXIST(&sc->sc_com_regwin) ? 1 : 0;
 	for (; i < nregwin; ++i) {
 		/*
 		 * Get regwin information
 		 */
 		error = bwi_regwin_select(sc, i);
 		if (error) {
 			aprint_error_dev(sc->sc_dev, "can't select regwin"
 			    " %d\n", i);
 			return (error);
+		}
 		bwi_regwin_info(sc, &rw_type, &rw_rev);
 		/*
 		 * Try attach:
 		 * 1) Bus (PCI/PCIE) regwin
 		 * 2) MAC regwin
 		 * Ignore rest types of regwin
 		 */
 		if (rw_type == BWI_REGWIN_T_BUSPCI ||
 		    rw_type == BWI_REGWIN_T_BUSPCIE) {
 			if (BWI_REGWIN_EXIST(&sc->sc_bus_regwin)) {
 				aprint_error_dev(sc->sc_dev,
 				    "bus regwin already exists\n");
 			} else {
 				BWI_CREATE_REGWIN(&sc->sc_bus_regwin, i,
 				    rw_type, rw_rev);
+			}
 		} else if (rw_type == BWI_REGWIN_T_MAC) {
 			/* XXX ignore return value */
 			bwi_mac_attach(sc, i, rw_rev);
+		}
+	}
 	/* At least one MAC shold exist */
 	if (!BWI_REGWIN_EXIST(&sc->sc_mac[0].mac_regwin)) {
 		aprint_error_dev(sc->sc_dev, "no MAC was found\n");
 		return (ENXIO);
+	}
 	KASSERT(sc->sc_nmac > 0);
 	/* Bus regwin must exist */
 	if (!BWI_REGWIN_EXIST(&sc->sc_bus_regwin)) {
 		aprint_error_dev(sc->sc_dev, "no bus regwin was found\n");
 		return (ENXIO);
+	}
 	/* Start with first MAC */
 	error = bwi_regwin_switch(sc, &sc->sc_mac[0].mac_regwin, NULL);
 	if (error)
 		return (error);
 	return (0);
+}
 static int
 bwi_bus_init(struct bwi_softc *sc, struct bwi_mac *mac)
+{
 	struct bwi_regwin *old, *bus;
 	uint32_t val;
 	int error;
 	bus = &sc->sc_bus_regwin;
 	KASSERT(sc->sc_cur_regwin == &mac->mac_regwin);
 	/*
 	 * Tell bus to generate requested interrupts
 	 */
 	if (bus->rw_rev < 6 && bus->rw_type == BWI_REGWIN_T_BUSPCI) {
 		/*
 		 * NOTE: Read BWI_FLAGS from MAC regwin
 		 */
 		val = CSR_READ_4(sc, BWI_FLAGS);
 		error = bwi_regwin_switch(sc, bus, &old);
 		if (error)
 			return (error);
 		CSR_SETBITS_4(sc, BWI_INTRVEC, (val & BWI_FLAGS_INTR_MASK));
 	} else {
 		uint32_t mac_mask;
 		mac_mask = 1 << mac->mac_id;
 		error = bwi_regwin_switch(sc, bus, &old);
 		if (error)
 			return (error);
 		val = (sc->sc_conf_read)(sc, BWI_PCIR_INTCTL);
 		val |= mac_mask << 8;
 		(sc->sc_conf_write)(sc, BWI_PCIR_INTCTL, val);
+	}
 	if (sc->sc_flags & BWI_F_BUS_INITED)
 		goto back;
 	if (bus->rw_type == BWI_REGWIN_T_BUSPCI) {
 		/*
 		 * Enable prefetch and burst
 		 */
 		CSR_SETBITS_4(sc, BWI_BUS_CONFIG,
 		    BWI_BUS_CONFIG_PREFETCH | BWI_BUS_CONFIG_BURST);
 		if (bus->rw_rev < 5) {
 			struct bwi_regwin *com = &sc->sc_com_regwin;
 			/*
 			 * Configure timeouts for bus operation
 			 */
 			/*
 			 * Set service timeout and request timeout
 			 */
 			CSR_SETBITS_4(sc, BWI_CONF_LO,
 			    __SHIFTIN(BWI_CONF_LO_SERVTO,
 				BWI_CONF_LO_SERVTO_MASK) |
 			    __SHIFTIN(BWI_CONF_LO_REQTO,
 				BWI_CONF_LO_REQTO_MASK));
 			/*
 			 * If there is common regwin, we switch to that regwin
 			 * and switch back to bus regwin once we have done.
 			 */
 			if (BWI_REGWIN_EXIST(com)) {
 				error = bwi_regwin_switch(sc, com, NULL);
 				if (error)
 					return (error);
+			}
 			/* Let bus know what we have changed */
 			CSR_WRITE_4(sc, BWI_BUS_ADDR, BWI_BUS_ADDR_MAGIC);
 			CSR_READ_4(sc, BWI_BUS_ADDR); /* Flush */
 			CSR_WRITE_4(sc, BWI_BUS_DATA, 0);
 			CSR_READ_4(sc, BWI_BUS_DATA); /* Flush */
 			if (BWI_REGWIN_EXIST(com)) {
 				error = bwi_regwin_switch(sc, bus, NULL);
 				if (error)
 					return (error);
+			}
 		} else if (bus->rw_rev >= 11) {
 			/*
 			 * Enable memory read multiple
 			 */
 			CSR_SETBITS_4(sc, BWI_BUS_CONFIG, BWI_BUS_CONFIG_MRM);
+		}
 	} else {
 		/* TODO: PCIE */
+	}
 	sc->sc_flags |= BWI_F_BUS_INITED;
 back:
 	return (bwi_regwin_switch(sc, old, NULL));
+}
 static void
 bwi_get_card_flags(struct bwi_softc *sc)
+{
 	sc->sc_card_flags = bwi_read_sprom(sc, BWI_SPROM_CARD_FLAGS);
 	if (sc->sc_card_flags == 0xffff)
 		sc->sc_card_flags = 0;
 	if (sc->sc_pci_subvid == PCI_VENDOR_APPLE &&
 	    sc->sc_pci_subdid == 0x4e && /* XXX */
 	    sc->sc_pci_revid > 0x40)
 		sc->sc_card_flags |= BWI_CARD_F_PA_GPIO9;
 	DPRINTF(sc, BWI_DBG_ATTACH, "card flags 0x%04x\n", sc->sc_card_flags);
+}
 static void
 bwi_get_eaddr(struct bwi_softc *sc, uint16_t eaddr_ofs, uint8_t *eaddr)
+{
 	int i;
 	for (i = 0; i < 3; ++i) {
 		*((uint16_t *)eaddr + i) =
 		    htobe16(bwi_read_sprom(sc, eaddr_ofs + 2 * i));
+	}
+}
 static void
 bwi_get_clock_freq(struct bwi_softc *sc, struct bwi_clock_freq *freq)
+{
 	struct bwi_regwin *com;
 	uint32_t val;
 	uint div;
 	int src;
 	memset(freq, 0, sizeof(*freq));
 	com = &sc->sc_com_regwin;
 	KASSERT(BWI_REGWIN_EXIST(com));
 	KASSERT(sc->sc_cur_regwin == com);
 	KASSERT(sc->sc_cap & BWI_CAP_CLKMODE);
 	/*
 	 * Calculate clock frequency
 	 */
 	src = -1;
 	div = 0;
 	if (com->rw_rev < 6) {
 		val = (sc->sc_conf_read)(sc, BWI_PCIR_GPIO_OUT);
 		if (val & BWI_PCIM_GPIO_OUT_CLKSRC) {
 			src = BWI_CLKSRC_PCI;
 			div = 64;
 		} else {
 			src = BWI_CLKSRC_CS_OSC;
 			div = 32;
+		}
 	} else if (com->rw_rev < 10) {
 		val = CSR_READ_4(sc, BWI_CLOCK_CTRL);
 		src = __SHIFTOUT(val, BWI_CLOCK_CTRL_CLKSRC);
 		if (src == BWI_CLKSRC_LP_OSC)
 			div = 1;
 		else {
 			div = (__SHIFTOUT(val, BWI_CLOCK_CTRL_FDIV) + 1) << 2;
 			/* Unknown source */
 			if (src >= BWI_CLKSRC_MAX)
 				src = BWI_CLKSRC_CS_OSC;
+		}
 	} else {
 		val = CSR_READ_4(sc, BWI_CLOCK_INFO);
 		src = BWI_CLKSRC_CS_OSC;
 		div = (__SHIFTOUT(val, BWI_CLOCK_INFO_FDIV) + 1) << 2;
+	}
 	KASSERT(src >= 0 && src < BWI_CLKSRC_MAX);
 	KASSERT(div != 0);
 	DPRINTF(sc, BWI_DBG_ATTACH, "clksrc %s\n",
 	    src == BWI_CLKSRC_PCI ? "PCI" :
 	    (src == BWI_CLKSRC_LP_OSC ? "LP_OSC" : "CS_OSC"));
 	freq->clkfreq_min = bwi_clkfreq[src].freq_min / div;
 	freq->clkfreq_max = bwi_clkfreq[src].freq_max / div;
 	DPRINTF(sc, BWI_DBG_ATTACH, "clkfreq min %u, max %u\n",
 	    freq->clkfreq_min, freq->clkfreq_max);
+}
 static int
 bwi_set_clock_mode(struct bwi_softc *sc, enum bwi_clock_mode clk_mode)
+{
 	struct bwi_regwin *old, *com;
 	uint32_t clk_ctrl, clk_src;
 	int error, pwr_off = 0;
 	com = &sc->sc_com_regwin;
 	if (!BWI_REGWIN_EXIST(com))
 		return (0);
 	if (com->rw_rev >= 10 || com->rw_rev < 6)
 		return (0);
 	/*
 	 * For common regwin whose rev is [6, 10), the chip
 	 * must be capable to change clock mode.
 	 */
 	if ((sc->sc_cap & BWI_CAP_CLKMODE) == 0)
 		return (0);
 	error = bwi_regwin_switch(sc, com, &old);
 	if (error)
 		return (error);
 	if (clk_mode == BWI_CLOCK_MODE_FAST)
 		bwi_power_on(sc, 0);	/* Don't turn on PLL */
 	clk_ctrl = CSR_READ_4(sc, BWI_CLOCK_CTRL);
 	clk_src = __SHIFTOUT(clk_ctrl, BWI_CLOCK_CTRL_CLKSRC);
 	switch (clk_mode) {
 	case BWI_CLOCK_MODE_FAST:
 		clk_ctrl &= ~BWI_CLOCK_CTRL_SLOW;
 		clk_ctrl |= BWI_CLOCK_CTRL_IGNPLL;
 		break;
 	case BWI_CLOCK_MODE_SLOW:
 		clk_ctrl |= BWI_CLOCK_CTRL_SLOW;
 		break;
 	case BWI_CLOCK_MODE_DYN:
 		clk_ctrl &= ~(BWI_CLOCK_CTRL_SLOW |
 		    BWI_CLOCK_CTRL_IGNPLL |
 		    BWI_CLOCK_CTRL_NODYN);
 		if (clk_src != BWI_CLKSRC_CS_OSC) {
 			clk_ctrl |= BWI_CLOCK_CTRL_NODYN;
 			pwr_off = 1;
+		}
 		break;
+	}
 	CSR_WRITE_4(sc, BWI_CLOCK_CTRL, clk_ctrl);
 	if (pwr_off)
 		bwi_power_off(sc, 0);	/* Leave PLL as it is */
 	return (bwi_regwin_switch(sc, old, NULL));
+}
 static int
 bwi_set_clock_delay(struct bwi_softc *sc)
+{
 	struct bwi_regwin *old, *com;
 	int error;
 	com = &sc->sc_com_regwin;
 	if (!BWI_REGWIN_EXIST(com))
 		return (0);
 	error = bwi_regwin_switch(sc, com, &old);
 	if (error)
 		return (error);
 	if (sc->sc_bbp_id == BWI_BBPID_BCM4321) {
 		if (sc->sc_bbp_rev == 0)
 			CSR_WRITE_4(sc, BWI_CONTROL, BWI_CONTROL_MAGIC0);
 		else if (sc->sc_bbp_rev == 1)
 			CSR_WRITE_4(sc, BWI_CONTROL, BWI_CONTROL_MAGIC1);
+	}
 	if (sc->sc_cap & BWI_CAP_CLKMODE) {
 		if (com->rw_rev >= 10)
 			CSR_FILT_SETBITS_4(sc, BWI_CLOCK_INFO, 0xffff, 0x40000);
 		else {
 			struct bwi_clock_freq freq;
 			bwi_get_clock_freq(sc, &freq);
 			CSR_WRITE_4(sc, BWI_PLL_ON_DELAY,
 			    howmany(freq.clkfreq_max * 150, 1000000));
 			CSR_WRITE_4(sc, BWI_FREQ_SEL_DELAY,
 			    howmany(freq.clkfreq_max * 15, 1000000));
+		}
+	}
 	return (bwi_regwin_switch(sc, old, NULL));
+}
 static int
 bwi_init(struct ifnet *ifp)
+{
 	struct bwi_softc *sc = ifp->if_softc;
 	bwi_init_statechg(sc, 1);
 	return (0);
+}
 static void
 bwi_init_statechg(struct bwi_softc *sc, int statechg)
+{
 	struct ieee80211com *ic = &sc->sc_ic;
 	struct ifnet *ifp = &sc->sc_if;
 	struct bwi_mac *mac;
 	int error;
 	DPRINTF(sc, BWI_DBG_MISC, "%s\n", __func__);
 	bwi_stop(ifp, statechg);
 	/* power on cardbus socket */
 	if (sc->sc_enable != NULL)
 		(sc->sc_enable)(sc, 0);
 	bwi_bbp_power_on(sc, BWI_CLOCK_MODE_FAST);
 	/* TODO: 2 MAC */
 	mac = &sc->sc_mac[0];
 	error = bwi_regwin_switch(sc, &mac->mac_regwin, NULL);
 	if (error)
 		goto back;
 	error = bwi_mac_init(mac);
 	if (error)
 		goto back;
 	bwi_bbp_power_on(sc, BWI_CLOCK_MODE_DYN);
 	IEEE80211_ADDR_COPY(ic->ic_myaddr, CLLADDR(ifp->if_sadl));
 	bwi_set_bssid(sc, bwi_zero_addr);	/* Clear BSSID */
 	bwi_set_addr_filter(sc, BWI_ADDR_FILTER_MYADDR, ic->ic_myaddr);
 	bwi_mac_reset_hwkeys(mac);
 	if ((mac->mac_flags & BWI_MAC_F_HAS_TXSTATS) == 0) {
 		int i;
 #define NRETRY	1000
 		/*
 		 * Drain any possible pending TX status
 		 */
 		for (i = 0; i < NRETRY; ++i) {
 			if ((CSR_READ_4(sc, BWI_TXSTATUS_0) &
 			     BWI_TXSTATUS_0_MORE) == 0)
 				break;
 			CSR_READ_4(sc, BWI_TXSTATUS_1);
+		}
 		if (i == NRETRY)
 			aprint_error_dev(sc->sc_dev,
 			    "can't drain TX status\n");
 #undef NRETRY
+	}
 	if (mac->mac_phy.phy_mode == IEEE80211_MODE_11G)
 		bwi_mac_updateslot(mac, 1);
 	/* Start MAC */
 	error = bwi_mac_start(mac);
 	if (error)
 		goto back;
 	/* Enable intrs */
 	bwi_enable_intrs(sc, BWI_INIT_INTRS);
 	ifp->if_flags |= IFF_RUNNING;
 	ifp->if_flags &= ~IFF_OACTIVE;
 	if (statechg) {
 		if (ic->ic_opmode != IEEE80211_M_MONITOR) {
 			/* [TRC: XXX OpenBSD omits this conditional.] */
 			if (ic->ic_roaming != IEEE80211_ROAMING_MANUAL)
 				ieee80211_new_state(ic, IEEE80211_S_SCAN, -1);
 		} else {
 			ieee80211_new_state(ic, IEEE80211_S_RUN, -1);
+		}
 	} else {
 		ieee80211_new_state(ic, ic->ic_state, -1);
+	}
 back:
 	if (error)
 		bwi_stop(ifp, 1);
 	else
 		/* [TRC: XXX DragonFlyBD uses ifp->if_start(ifp).] */
 		bwi_start(ifp);
+}
 static int
 bwi_ioctl(struct ifnet *ifp, u_long cmd, void *data)
+{
 	struct bwi_softc *sc = ifp->if_softc;
 	struct ieee80211com *ic = &sc->sc_ic;
 	int s, error = 0;
 	/* [TRC: XXX Superstitiously cargo-culted from wi(4).] */
 	if (!device_is_active(sc->sc_dev))
 		return (ENXIO);
 	s = splnet();
 	switch (cmd) {
 	case SIOCSIFFLAGS:
 		if ((error = ifioctl_common(ifp, cmd, data)) != 0)
 			break;
 		if ((ifp->if_flags & (IFF_UP | IFF_RUNNING)) ==
 		    (IFF_UP | IFF_RUNNING)) {
 			struct bwi_mac *mac;
 			int promisc = -1;
 			KASSERT(sc->sc_cur_regwin->rw_type ==
 			    BWI_REGWIN_T_MAC);
 			mac = (struct bwi_mac *)sc->sc_cur_regwin;
 			if ((ifp->if_flags & IFF_PROMISC) &&
 			    (sc->sc_flags & BWI_F_PROMISC) == 0) {
 				promisc = 1;
 				sc->sc_flags |= BWI_F_PROMISC;
 			} else if ((ifp->if_flags & IFF_PROMISC) == 0 &&
 				   (sc->sc_flags & BWI_F_PROMISC)) {
 				promisc = 0;
 				sc->sc_flags &= ~BWI_F_PROMISC;
+			}
 			if (promisc >= 0)
 				bwi_mac_set_promisc(mac, promisc);
+		}
 		if (ifp->if_flags & IFF_UP) {
 			if (!(ifp->if_flags & IFF_RUNNING))
 				bwi_init(ifp);
 		} else {
 			if (ifp->if_flags & IFF_RUNNING)
 				bwi_stop(ifp, 1);
+		}
 		break;
 	case SIOCADDMULTI:
 	case SIOCDELMULTI:
 		/* [TRC: Several other drivers appear to have this
 		   copied & pasted, so I'm following suit.] */
 		/* XXX no h/w multicast filter? --dyoung */
 		if ((error = ether_ioctl(ifp, cmd, data)) == ENETRESET) {
 			/* setup multicast filter, etc */
 			error = 0;
+		}
 		break;
 	case SIOCS80211CHANNEL:
 		/* [TRC: Pilfered from OpenBSD.  No clue whether it works.] */
 		/* allow fast channel switching in monitor mode */
 		error = ieee80211_ioctl(ic, cmd, data);
 		if (error == ENETRESET &&
 		    ic->ic_opmode == IEEE80211_M_MONITOR) {
 			if ((ifp->if_flags & (IFF_UP | IFF_RUNNING)) ==
 			    (IFF_UP | IFF_RUNNING)) {
 				/* [TRC: XXX ????] */
 				ic->ic_bss->ni_chan = ic->ic_ibss_chan;
 				ic->ic_curchan = ic->ic_ibss_chan;
 				bwi_set_chan(sc, ic->ic_bss->ni_chan);
+			}
 			error = 0;
+		}
 		break;
 	default:
 		error = ieee80211_ioctl(ic, cmd, data);
 		break;
+	}
 	if (error == ENETRESET) {
 		if ((ifp->if_flags & (IFF_UP | IFF_RUNNING)) ==
 		    (IFF_UP | IFF_RUNNING) &&
 		    /* [TRC: XXX Superstitiously cargo-culted from iwi(4). */
 		    (ic->ic_roaming != IEEE80211_ROAMING_MANUAL))
 			bwi_init(ifp);
 		error = 0;
+	}
 	splx(s);
 	return (error);
+}
 static void
 bwi_start(struct ifnet *ifp)
+{
 	struct bwi_softc *sc = ifp->if_softc;
 	struct ieee80211com *ic = &sc->sc_ic;
 	struct bwi_txbuf_data *tbd = &sc->sc_tx_bdata[BWI_TX_DATA_RING];
 	int trans, idx;
 	/* [TRC: XXX I'm not sure under which conditions we're actually
 	   supposed to refuse to start, so I'm copying what OpenBSD and
 	   DragonFlyBSD do, even if no one else on NetBSD does it. */
 	if ((ifp->if_flags & IFF_OACTIVE) ||
 	    (ifp->if_flags & IFF_RUNNING) == 0)
 		return;
 	trans = 0;
 	idx = tbd->tbd_idx;
 	while (tbd->tbd_buf[idx].tb_mbuf == NULL) {
 		struct ieee80211_frame *wh;
 		struct ieee80211_node *ni;
 		struct mbuf *m;
 		int mgt_pkt = 0;
 		IF_DEQUEUE(&ic->ic_mgtq, m);
 		if (m != NULL) {
 			ni = M_GETCTX(m, struct ieee80211_node *);
 			M_CLEARCTX(m);
 			mgt_pkt = 1;
 		} else {
 			struct ether_header *eh;
 			if (ic->ic_state != IEEE80211_S_RUN)
 				break;
 			IFQ_DEQUEUE(&ifp->if_snd, m);
 			if (m == NULL)
 				break;
 			if (m->m_len < sizeof(*eh)) {
 				m = m_pullup(m, sizeof(*eh));
 				if (m == NULL) {
-					ifp->if_oerrors++;
+					if_statinc(ifp, if_oerrors);
 					continue;
+				}
+			}
 			eh = mtod(m, struct ether_header *);
 			ni = ieee80211_find_txnode(ic, eh->ether_dhost);
 			if (ni == NULL) {
-				ifp->if_oerrors++;
+				if_statinc(ifp, if_oerrors);
 				m_freem(m);
 				continue;
+			}
 			/* [TRC: XXX Superstitiously cargo-culted from
 			   ath(4) and wi(4).] */
 			if ((ni->ni_flags & IEEE80211_NODE_PWR_MGT) &&
 			    (m->m_flags & M_PWR_SAV) == 0) {
 				ieee80211_pwrsave(ic, ni, m);
 				ieee80211_free_node(ni);
 				continue;
+			}
 			/* [TRC: XXX I *think* we're supposed to do
 			   this, but honestly I have no clue.  We don't
 			   use M_WME_GETAC, so...] */
 			if (ieee80211_classify(ic, m, ni)) {
 				/* [TRC: XXX What debug flag?] */
 				DPRINTF(sc, BWI_DBG_MISC,
 				    "%s: discard, classification failure\n",
 				    __func__);
-				ifp->if_oerrors++;
+				if_statinc(ifp, if_oerrors);
 				m_freem(m);
 				ieee80211_free_node(ni);
 				continue;
+			}
 			/* [TRC: XXX wi(4) and awi(4) do this; iwi(4)
 			   doesn't.] */
-			ifp->if_opackets++;
+			if_statinc(ifp, if_opackets);
 			/* [TRC: XXX When should the packet be
 			   filtered?  Different drivers appear to do it
 			   at different times.] */
 			/* TODO: PS */
 			bpf_mtap(ifp, m, BPF_D_OUT);
 			m = ieee80211_encap(ic, m, ni);
 			if (m == NULL) {
-				ifp->if_oerrors++;
+				if_statinc(ifp, if_oerrors);
 				ieee80211_free_node(ni);
 				continue;
+			}
+		}
 		bpf_mtap3(ic->ic_rawbpf, m, BPF_D_OUT);
 		wh = mtod(m, struct ieee80211_frame *);
 		/* [TRC: XXX What about ic->ic_flags & IEEE80211_F_PRIVACY?] */
 		if (wh->i_fc[1] & IEEE80211_FC1_WEP) {
 			if (ieee80211_crypto_encap(ic, ni, m) == NULL) {
-				ifp->if_oerrors++;
+				if_statinc(ifp, if_oerrors);
 				m_freem(m);
 				ieee80211_free_node(ni);
 				continue;
+			}
+		}
 		wh = NULL;	/* [TRC: XXX Huh?] */
 		if (bwi_encap(sc, idx, m, &ni, mgt_pkt) != 0) {
 			/* 'm' is freed in bwi_encap() if we reach here */
-			ifp->if_oerrors++;
+			if_statinc(ifp, if_oerrors);
 			if (ni != NULL)
 				ieee80211_free_node(ni);
 			continue;
+		}
 		trans = 1;
 		tbd->tbd_used++;
 		idx = (idx + 1) % BWI_TX_NDESC;
 		if (tbd->tbd_used + BWI_TX_NSPRDESC >= BWI_TX_NDESC) {
 			ifp->if_flags |= IFF_OACTIVE;
 			break;
+		}
+	}
 	tbd->tbd_idx = idx;
 	if (trans)
 		sc->sc_tx_timer = 5;
 	ifp->if_timer = 1;
+}
 static void
 bwi_watchdog(struct ifnet *ifp)
+{
 	struct bwi_softc *sc = ifp->if_softc;
 	ifp->if_timer = 0;
 	if ((ifp->if_flags & IFF_RUNNING) == 0 ||
 	    !device_is_active(sc->sc_dev))
 		return;
 	if (sc->sc_tx_timer) {
 		if (--sc->sc_tx_timer == 0) {
 			aprint_error_dev(sc->sc_dev, "device timeout\n");
-			ifp->if_oerrors++;
+			if_statinc(ifp, if_oerrors);
 			/* TODO */
 			/* [TRC: XXX TODO what?  Stop the device?
 			   Bring it down?  iwi(4) does this.] */
 		} else
 			ifp->if_timer = 1;
+	}
 	ieee80211_watchdog(&sc->sc_ic);
+}
 static void
 bwi_stop(struct ifnet *ifp, int state_chg)
+{
 	struct bwi_softc *sc = ifp->if_softc;
 	struct ieee80211com *ic = &sc->sc_ic;
 	struct bwi_mac *mac;
 	int i, error, pwr_off = 0;
 	DPRINTF(sc, BWI_DBG_MISC, "%s\n", __func__);
 	if (state_chg)
 		ieee80211_new_state(ic, IEEE80211_S_INIT, -1);
 	else
 		bwi_newstate_begin(sc, IEEE80211_S_INIT);
 	if (ifp->if_flags & IFF_RUNNING) {
 		KASSERT(sc->sc_cur_regwin->rw_type == BWI_REGWIN_T_MAC);
 		mac = (struct bwi_mac *)sc->sc_cur_regwin;
 		bwi_disable_intrs(sc, BWI_ALL_INTRS);
 		CSR_READ_4(sc, BWI_MAC_INTR_MASK);
 		bwi_mac_stop(mac);
+	}
 	for (i = 0; i < sc->sc_nmac; ++i) {
 		struct bwi_regwin *old_rw;
 		mac = &sc->sc_mac[i];
 		if ((mac->mac_flags & BWI_MAC_F_INITED) == 0)
 			continue;
 		error = bwi_regwin_switch(sc, &mac->mac_regwin, &old_rw);
 		if (error)
 			continue;
 		bwi_mac_shutdown(mac);
 		pwr_off = 1;
 		bwi_regwin_switch(sc, old_rw, NULL);
+	}
 	if (pwr_off)
 		bwi_bbp_power_off(sc);
 	sc->sc_tx_timer = 0;
 	ifp->if_timer = 0;
 	ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE);
 	/* power off cardbus socket */
 	if (sc->sc_disable != NULL)
 		(sc->sc_disable)(sc, 0);
 	return;
+}
 static void
 bwi_newstate_begin(struct bwi_softc *sc, enum ieee80211_state nstate)
+{
 	callout_stop(&sc->sc_scan_ch);
 	callout_stop(&sc->sc_calib_ch);
 	bwi_led_newstate(sc, nstate);
 	if (nstate == IEEE80211_S_INIT)
 		sc->sc_txpwrcb_type = BWI_TXPWR_INIT;
+}
 static int
 bwi_newstate(struct ieee80211com *ic, enum ieee80211_state nstate, int arg)
+{
 	struct bwi_softc *sc = ic->ic_ifp->if_softc;
 	struct ieee80211_node *ni;
 	int error;
 	/* [TRC: XXX amrr] */
 	callout_stop(&sc->sc_amrr_ch);
 	bwi_newstate_begin(sc, nstate);
 	if (nstate == IEEE80211_S_INIT)
 		goto back;
 	/* [TRC: XXX What channel do we set this to? */
 	error = bwi_set_chan(sc, ic->ic_curchan);
 	if (error) {
 		aprint_error_dev(sc->sc_dev, "can't set channel to %u\n",
 		    ieee80211_chan2ieee(ic, ic->ic_curchan));
 		return (error);
+	}
 	if (ic->ic_opmode == IEEE80211_M_MONITOR) {
 		/* Nothing to do */
 	} else if (nstate == IEEE80211_S_RUN) {
 		struct bwi_mac *mac;
 		ni = ic->ic_bss;
 		bwi_set_bssid(sc, ic->ic_bss->ni_bssid);
 		KASSERT(sc->sc_cur_regwin->rw_type == BWI_REGWIN_T_MAC);
 		mac = (struct bwi_mac *)sc->sc_cur_regwin;
 		/* Initial TX power calibration */
 		bwi_mac_calibrate_txpower(mac, BWI_TXPWR_INIT);
 #ifdef notyet
 		sc->sc_txpwrcb_type = BWI_TXPWR_FORCE;
 #else
 		sc->sc_txpwrcb_type = BWI_TXPWR_CALIB;
 #endif
 		/* [TRC: XXX amrr] */
 		if (ic->ic_opmode == IEEE80211_M_STA) {
 			/* fake a join to init the tx rate */
 			bwi_newassoc(ni, 1);
+		}
 		if (ic->ic_opmode != IEEE80211_M_MONITOR) {
 			/* start automatic rate control timer */
 			if (ic->ic_fixed_rate == -1)
 				callout_schedule(&sc->sc_amrr_ch, hz / 2);
+		}
 	} else
 		bwi_set_bssid(sc, bwi_zero_addr);
 back:
 	error = (sc->sc_newstate)(ic, nstate, arg);
 	if (nstate == IEEE80211_S_SCAN) {
 		callout_schedule(&sc->sc_scan_ch,
 		    (sc->sc_dwell_time * hz) / 1000);
 	} else if (nstate == IEEE80211_S_RUN) {
 		/* XXX 15 seconds */
 		callout_schedule(&sc->sc_calib_ch, hz);
+	}
 	return (error);
+}
 static int
 bwi_media_change(struct ifnet *ifp)
+{
 	int error;
 	error = ieee80211_media_change(ifp);
 	if (error != ENETRESET)
 		return (error);
 	if ((ifp->if_flags & (IFF_UP | IFF_RUNNING)) == (IFF_UP | IFF_RUNNING))
 		bwi_init(ifp);
 	return (0);
+}
 /* [TRC: XXX amrr] */
 static void
 bwi_iter_func(void *arg, struct ieee80211_node *ni)
+{
 	struct bwi_softc *sc = arg;
 	struct bwi_node *bn = (struct bwi_node *)ni;
 	ieee80211_amrr_choose(&sc->sc_amrr, ni, &bn->amn);
+}
 static void
 bwi_amrr_timeout(void *arg)
+{
 	struct bwi_softc *sc = arg;
 	struct ieee80211com *ic = &sc->sc_ic;
 	int s;
 	s = splnet();
 	if (ic->ic_opmode == IEEE80211_M_STA)
 		bwi_iter_func(sc, ic->ic_bss);
 	else
 		/* [TRC: XXX I'm making a wild guess about what to
 		   supply for the node table.] */
 		ieee80211_iterate_nodes(&ic->ic_sta, bwi_iter_func, sc);
 	callout_schedule(&sc->sc_amrr_ch, hz / 2);
 	splx(s);
+}
 static void
 bwi_newassoc(struct ieee80211_node *ni, int isnew)
+{
 	struct ieee80211com *ic = ni->ni_ic;
 	struct bwi_softc *sc = ic->ic_ifp->if_softc;
 	int i;
 	DPRINTF(sc, BWI_DBG_STATION, "%s\n", __func__);
 	ieee80211_amrr_node_init(&sc->sc_amrr, &((struct bwi_node *)ni)->amn);
 	/* set rate to some reasonable initial value */
 	for (i = ni->ni_rates.rs_nrates - 1;
 	    i > 0 && (ni->ni_rates.rs_rates[i] & IEEE80211_RATE_VAL) > 72;
 	    i--);
 	ni->ni_txrate = i;
+}
 static struct ieee80211_node *
 bwi_node_alloc(struct ieee80211_node_table *nt)
+{
 	struct bwi_node *bn;
 	bn = malloc(sizeof(struct bwi_node), M_80211_NODE, M_NOWAIT | M_ZERO);
 	return ((struct ieee80211_node *)bn);
+}
 /* [TRC: XXX amrr end] */
 static int
 bwi_dma_alloc(struct bwi_softc *sc)
+{
 	int error, i, has_txstats;
 	/* [TRC: XXX DragonFlyBSD adjusts the low address for different
 	   bus spaces.  Should we?] */
 	bus_size_t tx_ring_sz, rx_ring_sz, desc_sz = 0;
 	uint32_t txrx_ctrl_step = 0;
 	has_txstats = 0;
 	for (i = 0; i < sc->sc_nmac; ++i) {
 		if (sc->sc_mac[i].mac_flags & BWI_MAC_F_HAS_TXSTATS) {
 			has_txstats = 1;
 			break;
+		}
+	}
 	switch (sc->sc_bus_space) {
 	case BWI_BUS_SPACE_30BIT:
 	case BWI_BUS_SPACE_32BIT:
 		desc_sz = sizeof(struct bwi_desc32);
 		txrx_ctrl_step = 0x20;
 		sc->sc_init_tx_ring = bwi_init_tx_ring32;
 		sc->sc_free_tx_ring = bwi_free_tx_ring32;
 		sc->sc_init_rx_ring = bwi_init_rx_ring32;
 		sc->sc_free_rx_ring = bwi_free_rx_ring32;
 		sc->sc_setup_rxdesc = bwi_setup_rx_desc32;
 		sc->sc_setup_txdesc = bwi_setup_tx_desc32;
 		sc->sc_rxeof = bwi_rxeof32;
 		sc->sc_start_tx = bwi_start_tx32;
 		if (has_txstats) {
 			sc->sc_init_txstats = bwi_init_txstats32;
 			sc->sc_free_txstats = bwi_free_txstats32;
 			sc->sc_txeof_status = bwi_txeof_status32;
+		}
 		break;
 	case BWI_BUS_SPACE_64BIT:
 		desc_sz = sizeof(struct bwi_desc64);
 		txrx_ctrl_step = 0x40;
 		sc->sc_init_tx_ring = bwi_init_tx_ring64;
 		sc->sc_free_tx_ring = bwi_free_tx_ring64;
 		sc->sc_init_rx_ring = bwi_init_rx_ring64;
 		sc->sc_free_rx_ring = bwi_free_rx_ring64;
 		sc->sc_setup_rxdesc = bwi_setup_rx_desc64;
 		sc->sc_setup_txdesc = bwi_setup_tx_desc64;
 		sc->sc_rxeof = bwi_rxeof64;
 		sc->sc_start_tx = bwi_start_tx64;
 		if (has_txstats) {
 			sc->sc_init_txstats = bwi_init_txstats64;
 			sc->sc_free_txstats = bwi_free_txstats64;
 			sc->sc_txeof_status = bwi_txeof_status64;
+		}
 		break;
+	}
 	KASSERT(desc_sz != 0);
 	KASSERT(txrx_ctrl_step != 0);
 	tx_ring_sz = roundup(desc_sz * BWI_TX_NDESC, BWI_RING_ALIGN);
 	rx_ring_sz = roundup(desc_sz * BWI_RX_NDESC, BWI_RING_ALIGN);
 	/* [TRC: XXX Using OpenBSD's code, which is rather different
 	   from DragonFlyBSD's.] */
 #define TXRX_CTRL(idx)	(BWI_TXRX_CTRL_BASE + (idx) * txrx_ctrl_step)
 	/*
 	 * Create TX ring DMA stuffs
 	 */
 	for (i = 0; i < BWI_TX_NRING; ++i) {
 		error = bus_dmamap_create(sc->sc_dmat, tx_ring_sz, 1,
 		    tx_ring_sz, 0, BUS_DMA_NOWAIT,
 		    &sc->sc_tx_rdata[i].rdata_dmap);
 		if (error) {
 			aprint_error_dev(sc->sc_dev,
 			    "%dth TX ring DMA create failed\n", i);
 			return (error);
+		}
 		error = bwi_dma_ring_alloc(sc,
 		    &sc->sc_tx_rdata[i], tx_ring_sz, TXRX_CTRL(i));
 		if (error) {
 			aprint_error_dev(sc->sc_dev,
 			    "%dth TX ring DMA alloc failed\n", i);
 			return (error);
+		}
+	}
 	/*
 	 * Create RX ring DMA stuffs
 	 */
 	error = bus_dmamap_create(sc->sc_dmat, rx_ring_sz, 1,
 	    rx_ring_sz, 0, BUS_DMA_NOWAIT,
 	    &sc->sc_rx_rdata.rdata_dmap);
 	if (error) {
 		aprint_error_dev(sc->sc_dev, "RX ring DMA create failed\n");
 		return (error);
+	}
 	error = bwi_dma_ring_alloc(sc, &sc->sc_rx_rdata,
 	    rx_ring_sz, TXRX_CTRL(0));
 	if (error) {
 		aprint_error_dev(sc->sc_dev, "RX ring DMA alloc failed\n");
 		return (error);
+	}
 	if (has_txstats) {
 		error = bwi_dma_txstats_alloc(sc, TXRX_CTRL(3), desc_sz);
 		if (error) {
 			aprint_error_dev(sc->sc_dev,
 			    "TX stats DMA alloc failed\n");
 			return (error);
+		}
+	}
 #undef TXRX_CTRL
 	return (bwi_dma_mbuf_create(sc));
+}
 static void
 bwi_dma_free(struct bwi_softc *sc)
+{
 	int i;
 	for (i = 0; i < BWI_TX_NRING; ++i)
 		bwi_ring_data_free(&sc->sc_tx_rdata[i], sc);
 	bwi_ring_data_free(&sc->sc_rx_rdata, sc);
 	bwi_dma_txstats_free(sc);
 	bwi_dma_mbuf_destroy(sc, BWI_TX_NRING, 1);
+}
 static void
 bwi_ring_data_free(struct bwi_ring_data *rd, struct bwi_softc *sc)
+{
 	if (rd->rdata_desc != NULL) {
 		bus_dmamap_unload(sc->sc_dmat, rd->rdata_dmap);
 		bus_dmamem_free(sc->sc_dmat, &rd->rdata_seg, 1);
+	}
+}
 static int
 bwi_dma_ring_alloc(struct bwi_softc *sc,
     struct bwi_ring_data *rd, bus_size_t size, uint32_t txrx_ctrl)
+{
 	int error, nsegs;
 	error = bus_dmamem_alloc(sc->sc_dmat, size, BWI_ALIGN, 0,
 	    &rd->rdata_seg, 1, &nsegs, BUS_DMA_NOWAIT);
 	if (error) {
 		aprint_error_dev(sc->sc_dev, "can't allocate DMA mem\n");
 		return (error);
+	}
 	error = bus_dmamem_map(sc->sc_dmat, &rd->rdata_seg, nsegs,
 	    size, (void **)&rd->rdata_desc, BUS_DMA_NOWAIT);
 	if (error) {
 		aprint_error_dev(sc->sc_dev, "can't map DMA mem\n");
 		return (error);
+	}
 	error = bus_dmamap_load(sc->sc_dmat, rd->rdata_dmap, rd->rdata_desc,
 	    size, NULL, BUS_DMA_WAITOK);
 	if (error) {
 		aprint_error_dev(sc->sc_dev, "can't load DMA mem\n");
 		bus_dmamem_free(sc->sc_dmat, &rd->rdata_seg, nsegs);
 		rd->rdata_desc = NULL;
 		return (error);
+	}
 	rd->rdata_paddr = rd->rdata_dmap->dm_segs[0].ds_addr;
 	rd->rdata_txrx_ctrl = txrx_ctrl;
 	return (0);
+}
 static int
 bwi_dma_txstats_alloc(struct bwi_softc *sc, uint32_t ctrl_base,
     bus_size_t desc_sz)
+{
 	struct bwi_txstats_data *st;
 	bus_size_t dma_size;
 	int error, nsegs;
 	st = malloc(sizeof(*st), M_DEVBUF, M_WAITOK | M_ZERO);
 	sc->sc_txstats = st;
 	/*
 	 * Create TX stats descriptor DMA stuffs
 	 */
 	dma_size = roundup(desc_sz * BWI_TXSTATS_NDESC, BWI_RING_ALIGN);
 	error = bus_dmamap_create(sc->sc_dmat, dma_size, 1, dma_size, 0,
 	    BUS_DMA_NOWAIT, &st->stats_ring_dmap);
 	if (error) {
 		aprint_error_dev(sc->sc_dev,
 		    "can't create txstats ring DMA mem\n");
 		return (error);
+	}
 	error = bus_dmamem_alloc(sc->sc_dmat, dma_size, BWI_RING_ALIGN, 0,
 	     &st->stats_ring_seg, 1, &nsegs, BUS_DMA_NOWAIT);
 	if (error) {
 		aprint_error_dev(sc->sc_dev,
 		    "can't allocate txstats ring DMA mem\n");
 		return (error);
+	}
 	error = bus_dmamem_map(sc->sc_dmat, &st->stats_ring_seg, nsegs,
 	    dma_size, (void **)&st->stats_ring, BUS_DMA_NOWAIT);
 	if (error) {
 		aprint_error_dev(sc->sc_dev,
 		    "can't map txstats ring DMA mem\n");
 		return (error);
+	}
 	error = bus_dmamap_load(sc->sc_dmat, st->stats_ring_dmap,
 	    st->stats_ring, dma_size, NULL, BUS_DMA_WAITOK);
 	if (error) {
 		aprint_error_dev(sc->sc_dev,
 		    "can't load txstats ring DMA mem\n");
 		bus_dmamem_free(sc->sc_dmat, &st->stats_ring_seg, nsegs);
 		return (error);
+	}
 	memset(st->stats_ring, 0, dma_size);
 	st->stats_ring_paddr = st->stats_ring_dmap->dm_segs[0].ds_addr;
 	/*
 	 * Create TX stats DMA stuffs
 	 */
 	dma_size = roundup(sizeof(struct bwi_txstats) * BWI_TXSTATS_NDESC,
 	    BWI_ALIGN);
 	error = bus_dmamap_create(sc->sc_dmat, dma_size, 1, dma_size, 0,
 	    BUS_DMA_NOWAIT, &st->stats_dmap);
 	if (error) {
 		aprint_error_dev(sc->sc_dev,
 		    "can't create txstats ring DMA mem\n");
 		return (error);
+	}
 	error = bus_dmamem_alloc(sc->sc_dmat, dma_size, BWI_ALIGN, 0,
 	    &st->stats_seg, 1, &nsegs, BUS_DMA_NOWAIT);
 	if (error) {
 		aprint_error_dev(sc->sc_dev,
 		    "can't allocate txstats DMA mem\n");
 		return (error);
+	}
 	error = bus_dmamem_map(sc->sc_dmat, &st->stats_seg, nsegs,
 	    dma_size, (void **)&st->stats, BUS_DMA_NOWAIT);
 	if (error) {
 		aprint_error_dev(sc->sc_dev, "can't map txstats DMA mem\n");
 		return (error);
+	}
 	error = bus_dmamap_load(sc->sc_dmat, st->stats_dmap, st->stats,
 	    dma_size, NULL, BUS_DMA_WAITOK);
 	if (error) {
 		aprint_error_dev(sc->sc_dev, "can't load txstats DMA mem\n");
 		bus_dmamem_free(sc->sc_dmat, &st->stats_seg, nsegs);
 		return (error);
+	}
 	memset(st->stats, 0, dma_size);
 	st->stats_paddr = st->stats_dmap->dm_segs[0].ds_addr;
 	st->stats_ctrl_base = ctrl_base;
 	return (0);
+}
 static void
 bwi_dma_txstats_free(struct bwi_softc *sc)
+{
 	struct bwi_txstats_data *st;
 	if (sc->sc_txstats == NULL)
 		return;
 	st = sc->sc_txstats;
 	bus_dmamap_unload(sc->sc_dmat, st->stats_ring_dmap);
 	bus_dmamem_free(sc->sc_dmat, &st->stats_ring_seg, 1);
 	bus_dmamap_unload(sc->sc_dmat, st->stats_dmap);
 	bus_dmamem_free(sc->sc_dmat, &st->stats_seg, 1);
 	free(st, M_DEVBUF);
+}
 static int
 bwi_dma_mbuf_create(struct bwi_softc *sc)
+{
 	struct bwi_rxbuf_data *rbd = &sc->sc_rx_bdata;
 	int i, j, k, ntx, error;
 	ntx = 0;
 	/*
 	 * Create TX mbuf DMA map
 	 */
 	for (i = 0; i < BWI_TX_NRING; ++i) {
 		struct bwi_txbuf_data *tbd = &sc->sc_tx_bdata[i];
 		for (j = 0; j < BWI_TX_NDESC; ++j) {
 			error = bus_dmamap_create(sc->sc_dmat, MCLBYTES, 1, MCLBYTES,
 , BUS_DMA_NOWAIT, &tbd->tbd_buf[j].tb_dmap);
 			if (error) {
 				aprint_error_dev(sc->sc_dev,
 				    "can't create %dth tbd, %dth DMA map\n",
 				    i, j);
 				ntx = i;
 				for (k = 0; k < j; ++k) {
 					bus_dmamap_destroy(sc->sc_dmat,
 					    tbd->tbd_buf[k].tb_dmap);
+				}
 				goto fail;
+			}
+		}
+	}
 	ntx = BWI_TX_NRING;
 	/*
 	 * Create RX mbuf DMA map and a spare DMA map
 	 */
 	error = bus_dmamap_create(sc->sc_dmat, MCLBYTES, 1, MCLBYTES, 0,
 	    BUS_DMA_NOWAIT, &rbd->rbd_tmp_dmap);
 	if (error) {
 		aprint_error_dev(sc->sc_dev,
 		    "can't create spare RX buf DMA map\n");
 		goto fail;
+	}
 	for (j = 0; j < BWI_RX_NDESC; ++j) {
 		error = bus_dmamap_create(sc->sc_dmat, MCLBYTES, 1, MCLBYTES, 0,
 		    BUS_DMA_NOWAIT, &rbd->rbd_buf[j].rb_dmap);
 		if (error) {
 			aprint_error_dev(sc->sc_dev,
 			    "can't create %dth RX buf DMA map\n", j);
 			for (k = 0; k < j; ++k) {
 				bus_dmamap_destroy(sc->sc_dmat,
 				    rbd->rbd_buf[j].rb_dmap);
+			}
 			bus_dmamap_destroy(sc->sc_dmat,
 			    rbd->rbd_tmp_dmap);
 			goto fail;
+		}
+	}
 	return (0);
 fail:
 	bwi_dma_mbuf_destroy(sc, ntx, 0);
 	return (error);
+}
 static void
 bwi_dma_mbuf_destroy(struct bwi_softc *sc, int ntx, int nrx)
+{
 	int i, j;
 	for (i = 0; i < ntx; ++i) {
 		struct bwi_txbuf_data *tbd = &sc->sc_tx_bdata[i];
 		for (j = 0; j < BWI_TX_NDESC; ++j) {
 			struct bwi_txbuf *tb = &tbd->tbd_buf[j];
 			if (tb->tb_mbuf != NULL) {
 				bus_dmamap_unload(sc->sc_dmat,
 				    tb->tb_dmap);
 				m_freem(tb->tb_mbuf);
+			}
 			if (tb->tb_ni != NULL)
 				ieee80211_free_node(tb->tb_ni);
 			bus_dmamap_destroy(sc->sc_dmat, tb->tb_dmap);
+		}
+	}
 	if (nrx) {
 		struct bwi_rxbuf_data *rbd = &sc->sc_rx_bdata;
 		bus_dmamap_destroy(sc->sc_dmat, rbd->rbd_tmp_dmap);
 		for (j = 0; j < BWI_RX_NDESC; ++j) {
 			struct bwi_rxbuf *rb = &rbd->rbd_buf[j];
 			if (rb->rb_mbuf != NULL) {
 				bus_dmamap_unload(sc->sc_dmat,
 						  rb->rb_dmap);
 				m_freem(rb->rb_mbuf);
+			}
 			bus_dmamap_destroy(sc->sc_dmat, rb->rb_dmap);
+		}
+	}
+}
 static void
 bwi_enable_intrs(struct bwi_softc *sc, uint32_t enable_intrs)
+{
 	CSR_SETBITS_4(sc, BWI_MAC_INTR_MASK, enable_intrs);
+}
 static void
 bwi_disable_intrs(struct bwi_softc *sc, uint32_t disable_intrs)
+{
 	CSR_CLRBITS_4(sc, BWI_MAC_INTR_MASK, disable_intrs);
+}
 static int
 bwi_init_tx_ring32(struct bwi_softc *sc, int ring_idx)
+{
 	struct bwi_ring_data *rd;
 	struct bwi_txbuf_data *tbd;
 	uint32_t val, addr_hi, addr_lo;
 	KASSERT(ring_idx < BWI_TX_NRING);
 	rd = &sc->sc_tx_rdata[ring_idx];
 	tbd = &sc->sc_tx_bdata[ring_idx];
 	tbd->tbd_idx = 0;
 	tbd->tbd_used = 0;
 	memset(rd->rdata_desc, 0, sizeof(struct bwi_desc32) * BWI_TX_NDESC);
 	bus_dmamap_sync(sc->sc_dmat, rd->rdata_dmap, 0,
 	    rd->rdata_dmap->dm_mapsize, BUS_DMASYNC_PREWRITE);
 	addr_lo = __SHIFTOUT(rd->rdata_paddr, BWI_TXRX32_RINGINFO_ADDR_MASK);
 	addr_hi = __SHIFTOUT(rd->rdata_paddr, BWI_TXRX32_RINGINFO_FUNC_MASK);
 	val = __SHIFTIN(addr_lo, BWI_TXRX32_RINGINFO_ADDR_MASK) |
 	    __SHIFTIN(BWI_TXRX32_RINGINFO_FUNC_TXRX,
 	    BWI_TXRX32_RINGINFO_FUNC_MASK);
 	CSR_WRITE_4(sc, rd->rdata_txrx_ctrl + BWI_TX32_RINGINFO, val);
 	val = __SHIFTIN(addr_hi, BWI_TXRX32_CTRL_ADDRHI_MASK) |
 	      BWI_TXRX32_CTRL_ENABLE;
 	CSR_WRITE_4(sc, rd->rdata_txrx_ctrl + BWI_TX32_CTRL, val);
 	return (0);
+}
 static void
 bwi_init_rxdesc_ring32(struct bwi_softc *sc, uint32_t ctrl_base,
     bus_addr_t paddr, int hdr_size, int ndesc)
+{
 	uint32_t val, addr_hi, addr_lo;
 	addr_lo = __SHIFTOUT(paddr, BWI_TXRX32_RINGINFO_ADDR_MASK);
 	addr_hi = __SHIFTOUT(paddr, BWI_TXRX32_RINGINFO_FUNC_MASK);
 	val = __SHIFTIN(addr_lo, BWI_TXRX32_RINGINFO_ADDR_MASK) |
 	    __SHIFTIN(BWI_TXRX32_RINGINFO_FUNC_TXRX,
 	      		BWI_TXRX32_RINGINFO_FUNC_MASK);
 	CSR_WRITE_4(sc, ctrl_base + BWI_RX32_RINGINFO, val);
 	val = __SHIFTIN(hdr_size, BWI_RX32_CTRL_HDRSZ_MASK) |
 	    __SHIFTIN(addr_hi, BWI_TXRX32_CTRL_ADDRHI_MASK) |
 	    BWI_TXRX32_CTRL_ENABLE;
 	CSR_WRITE_4(sc, ctrl_base + BWI_RX32_CTRL, val);
 	CSR_WRITE_4(sc, ctrl_base + BWI_RX32_INDEX,
 	    (ndesc - 1) * sizeof(struct bwi_desc32));
+}
 static int
 bwi_init_rx_ring32(struct bwi_softc *sc)
+{
 	struct bwi_ring_data *rd = &sc->sc_rx_rdata;
 	int i, error;
 	sc->sc_rx_bdata.rbd_idx = 0;
 	for (i = 0; i < BWI_RX_NDESC; ++i) {
 		error = bwi_newbuf(sc, i, 1);
 		if (error) {
 			aprint_error_dev(sc->sc_dev,
 			    "can't allocate %dth RX buffer\n", i);
 			return (error);
+		}
+	}
 	bus_dmamap_sync(sc->sc_dmat, rd->rdata_dmap, 0,
 	    rd->rdata_dmap->dm_mapsize, BUS_DMASYNC_PREWRITE);
 	bwi_init_rxdesc_ring32(sc, rd->rdata_txrx_ctrl, rd->rdata_paddr,
 	    sizeof(struct bwi_rxbuf_hdr), BWI_RX_NDESC);
 	return (0);
+}
 static int
 bwi_init_txstats32(struct bwi_softc *sc)
+{
 	struct bwi_txstats_data *st = sc->sc_txstats;
 	bus_addr_t stats_paddr;
 	int i;
 	memset(st->stats, 0, BWI_TXSTATS_NDESC * sizeof(struct bwi_txstats));
 	bus_dmamap_sync(sc->sc_dmat, st->stats_dmap, 0,
 	    st->stats_dmap->dm_mapsize, BUS_DMASYNC_PREWRITE);
 	st->stats_idx = 0;
 	stats_paddr = st->stats_paddr;
 	for (i = 0; i < BWI_TXSTATS_NDESC; ++i) {
 		bwi_setup_desc32(sc, st->stats_ring, BWI_TXSTATS_NDESC, i,
 				 stats_paddr, sizeof(struct bwi_txstats), 0);
 		stats_paddr += sizeof(struct bwi_txstats);
+	}
 	bus_dmamap_sync(sc->sc_dmat, st->stats_ring_dmap, 0,
 	    st->stats_ring_dmap->dm_mapsize, BUS_DMASYNC_PREWRITE);
 	bwi_init_rxdesc_ring32(sc, st->stats_ctrl_base,
 	    st->stats_ring_paddr, 0, BWI_TXSTATS_NDESC);
 	return (0);
+}
 static void
 bwi_setup_rx_desc32(struct bwi_softc *sc, int buf_idx, bus_addr_t paddr,
     int buf_len)
+{
 	struct bwi_ring_data *rd = &sc->sc_rx_rdata;
 	KASSERT(buf_idx < BWI_RX_NDESC);
 	bwi_setup_desc32(sc, rd->rdata_desc, BWI_RX_NDESC, buf_idx,
 	    paddr, buf_len, 0);
+}
 static void
 bwi_setup_tx_desc32(struct bwi_softc *sc, struct bwi_ring_data *rd,
     int buf_idx, bus_addr_t paddr, int buf_len)
+{
 	KASSERT(buf_idx < BWI_TX_NDESC);
 	bwi_setup_desc32(sc, rd->rdata_desc, BWI_TX_NDESC, buf_idx,
 	    paddr, buf_len, 1);
+}
 static int
 bwi_init_tx_ring64(struct bwi_softc *sc, int ring_idx)
+{
 	/* TODO: 64 */
 	return (EOPNOTSUPP);
+}
 static int
 bwi_init_rx_ring64(struct bwi_softc *sc)
+{
 	/* TODO: 64 */
 	return (EOPNOTSUPP);
+}
 static int
 bwi_init_txstats64(struct bwi_softc *sc)
+{
 	/* TODO: 64 */
 	return (EOPNOTSUPP);
+}
 static void
 bwi_setup_rx_desc64(struct bwi_softc *sc, int buf_idx, bus_addr_t paddr,
     int buf_len)
+{
 	/* TODO: 64 */
+}
 static void
 bwi_setup_tx_desc64(struct bwi_softc *sc, struct bwi_ring_data *rd,
     int buf_idx, bus_addr_t paddr, int buf_len)
+{
 	/* TODO: 64 */
+}
 static int
 bwi_newbuf(struct bwi_softc *sc, int buf_idx, int init)
+{
 	struct bwi_rxbuf_data *rbd = &sc->sc_rx_bdata;
 	struct bwi_rxbuf *rxbuf = &rbd->rbd_buf[buf_idx];
 	struct bwi_rxbuf_hdr *hdr;
 	bus_dmamap_t map;
 	bus_addr_t paddr;
 	struct mbuf *m;
 	int error;
 	KASSERT(buf_idx < BWI_RX_NDESC);
 	MGETHDR(m, init ? M_WAITOK : M_DONTWAIT, MT_DATA);
 	if (m == NULL)
 		return (ENOBUFS);
 	MCLGET(m, init ? M_WAITOK : M_DONTWAIT);
 	if ((m->m_flags & M_EXT) == 0) {
 		error = ENOBUFS;
 		/*
 		 * If the NIC is up and running, we need to:
 		 * - Clear RX buffer's header.
 		 * - Restore RX descriptor settings.
 		 */
 		if (init)
 			return error;
 		else
 			goto back;
+	}
 	m->m_len = m->m_pkthdr.len = MCLBYTES;
 	/*
 	 * Try to load RX buf into temporary DMA map
 	 */
 	error = bus_dmamap_load_mbuf(sc->sc_dmat, rbd->rbd_tmp_dmap, m,
 	    init ? BUS_DMA_WAITOK : BUS_DMA_NOWAIT);
 	if (error) {
 		m_freem(m);
 		/*
 		 * See the comment above
 		 */
 		if (init)
 			return error;
 		else
 			goto back;
+	}
 	if (!init)
 		bus_dmamap_unload(sc->sc_dmat, rxbuf->rb_dmap);
 	rxbuf->rb_mbuf = m;
 	/*
 	 * Swap RX buf's DMA map with the loaded temporary one
 	 */
 	map = rxbuf->rb_dmap;
 	rxbuf->rb_dmap = rbd->rbd_tmp_dmap;
 	rbd->rbd_tmp_dmap = map;
 	paddr = rxbuf->rb_dmap->dm_segs[0].ds_addr;
 	rxbuf->rb_paddr = paddr;
 back:
 	/*
 	 * Clear RX buf header
 	 */
 	hdr = mtod(rxbuf->rb_mbuf, struct bwi_rxbuf_hdr *);
 	memset(hdr, 0, sizeof(*hdr));
 	bus_dmamap_sync(sc->sc_dmat, rxbuf->rb_dmap, 0,
 	    rxbuf->rb_dmap->dm_mapsize, BUS_DMASYNC_PREWRITE);
 	/*
 	 * Setup RX buf descriptor
 	 */
 	(sc->sc_setup_rxdesc)(sc, buf_idx, rxbuf->rb_paddr,
 	    rxbuf->rb_mbuf->m_len - sizeof(*hdr));
 	return error;
+}
 static void
 bwi_set_addr_filter(struct bwi_softc *sc, uint16_t addr_ofs,
     const uint8_t *addr)
+{
 	int i;
 	CSR_WRITE_2(sc, BWI_ADDR_FILTER_CTRL,
 	    BWI_ADDR_FILTER_CTRL_SET | addr_ofs);
 	for (i = 0; i < (IEEE80211_ADDR_LEN / 2); ++i) {
 		uint16_t addr_val;
 		addr_val = (uint16_t)addr[i * 2] |
 		    (((uint16_t)addr[(i * 2) + 1]) << 8);
 		CSR_WRITE_2(sc, BWI_ADDR_FILTER_DATA, addr_val);
+	}
+}
 static int
 bwi_set_chan(struct bwi_softc *sc, struct ieee80211_channel *c)
+{
 	struct ieee80211com *ic = &sc->sc_ic;
 	struct bwi_mac *mac;
 	/* uint16_t flags; */ /* [TRC: XXX See below.] */
 	uint chan;
 	KASSERT(sc->sc_cur_regwin->rw_type == BWI_REGWIN_T_MAC);
 	mac = (struct bwi_mac *)sc->sc_cur_regwin;
 	chan = ieee80211_chan2ieee(ic, c);
 	bwi_rf_set_chan(mac, chan, 0);
 	/* [TRC: XXX DragonFlyBSD sets up radio tap channel frequency
 	   and flags here.  OpenBSD does not, and appears to do so
 	   later (in bwi_rxeof and bwi_encap).] */
 	return (0);
+}
 static void
 bwi_next_scan(void *xsc)
+{
 	struct bwi_softc *sc = xsc;
 	struct ieee80211com *ic = &sc->sc_ic;
 	int s;
 	s = splnet();
 	if (ic->ic_state == IEEE80211_S_SCAN)
 		ieee80211_next_scan(ic);
 	splx(s);
+}
 static int
 bwi_rxeof(struct bwi_softc *sc, int end_idx)
+{
 	struct bwi_ring_data *rd = &sc->sc_rx_rdata;
 	struct bwi_rxbuf_data *rbd = &sc->sc_rx_bdata;
 	struct ieee80211com *ic = &sc->sc_ic;
 	struct ifnet *ifp = &sc->sc_if;
 	int s, idx, rx_data = 0;
 	idx = rbd->rbd_idx;
 	while (idx != end_idx) {
 		struct bwi_rxbuf *rb = &rbd->rbd_buf[idx];
 		struct bwi_rxbuf_hdr *hdr;
 		struct ieee80211_frame_min *wh;
 		struct ieee80211_node *ni;
 		struct mbuf *m;
 		const void *plcp;
 		uint16_t flags2;
 		int buflen, wh_ofs, hdr_extra, rssi, type, rate;
 		m = rb->rb_mbuf;
 		bus_dmamap_sync(sc->sc_dmat, rb->rb_dmap, 0,
 		    rb->rb_dmap->dm_mapsize, BUS_DMASYNC_POSTREAD);
 		if (bwi_newbuf(sc, idx, 0)) {
-			ifp->if_ierrors++;
+			if_statinc(ifp, if_ierrors);
 			goto next;
+		}
 		hdr = mtod(m, struct bwi_rxbuf_hdr *);
 		flags2 = le16toh(hdr->rxh_flags2);
 		hdr_extra = 0;
 		if (flags2 & BWI_RXH_F2_TYPE2FRAME)
 			hdr_extra = 2;
 		wh_ofs = hdr_extra + 6; /* XXX magic number */
 		buflen = le16toh(hdr->rxh_buflen);
 		if (buflen < BWI_FRAME_MIN_LEN(wh_ofs)) {
 			aprint_error_dev(sc->sc_dev, "short frame %d,"
 			    " hdr_extra %d\n", buflen, hdr_extra);
-			ifp->if_ierrors++;
+			if_statinc(ifp, if_ierrors);
 			m_freem(m);
 			goto next;
+		}
 		plcp = ((const uint8_t *)(hdr + 1) + hdr_extra);
 		rssi = bwi_calc_rssi(sc, hdr);
 		m_set_rcvif(m, ifp);
 		m->m_len = m->m_pkthdr.len = buflen + sizeof(*hdr);
 		m_adj(m, sizeof(*hdr) + wh_ofs);
 		if (htole16(hdr->rxh_flags1) & BWI_RXH_F1_OFDM)
 			rate = bwi_ofdm_plcp2rate(plcp);
 		else
 			rate = bwi_ds_plcp2rate(plcp);
 		s = splnet();
 		/* RX radio tap */
 		if (sc->sc_drvbpf != NULL) {
 			struct mbuf mb;
 			struct bwi_rx_radiotap_hdr *tap = &sc->sc_rxtap;
 			tap->wr_tsf = hdr->rxh_tsf;
 			tap->wr_flags = 0;
 			tap->wr_rate = rate;
 			tap->wr_chan_freq =
 			    htole16(ic->ic_bss->ni_chan->ic_freq);
 			tap->wr_chan_flags =
 			    htole16(ic->ic_bss->ni_chan->ic_flags);
 			tap->wr_antsignal = rssi;
 			tap->wr_antnoise = BWI_NOISE_FLOOR;
 			mb.m_data = (void *)tap;
 			mb.m_len = sc->sc_rxtap_len;
 			mb.m_next = m;
 			mb.m_nextpkt = NULL;
 			mb.m_owner = NULL;
 			mb.m_type = 0;
 			mb.m_flags = 0;
 			bpf_mtap3(sc->sc_drvbpf, &mb, BPF_D_IN);
+		}
 		m_adj(m, -IEEE80211_CRC_LEN);
 		wh = mtod(m, struct ieee80211_frame_min *);
 		ni = ieee80211_find_rxnode(ic, wh);
 		type = wh->i_fc[0] & IEEE80211_FC0_TYPE_MASK;
 		ieee80211_input(ic, m, ni, hdr->rxh_rssi,
 		    le16toh(hdr->rxh_tsf));
 		ieee80211_free_node(ni);
 		if (type == IEEE80211_FC0_TYPE_DATA) {
 			rx_data = 1;
 			sc->sc_rx_rate = rate;
+		}
 		splx(s);
 next:
 		idx = (idx + 1) % BWI_RX_NDESC;
+	}
 	rbd->rbd_idx = idx;
 	bus_dmamap_sync(sc->sc_dmat, rd->rdata_dmap, 0,
 	    rd->rdata_dmap->dm_mapsize, BUS_DMASYNC_PREWRITE);
 	return (rx_data);
+}
 static int
 bwi_rxeof32(struct bwi_softc *sc)
+{
 	uint32_t val, rx_ctrl;
 	int end_idx, rx_data;
 	rx_ctrl = sc->sc_rx_rdata.rdata_txrx_ctrl;
 	val = CSR_READ_4(sc, rx_ctrl + BWI_RX32_STATUS);
 	end_idx = __SHIFTOUT(val, BWI_RX32_STATUS_INDEX_MASK) /
 	    sizeof(struct bwi_desc32);
 	rx_data = bwi_rxeof(sc, end_idx);
 	CSR_WRITE_4(sc, rx_ctrl + BWI_RX32_INDEX,
 	    end_idx * sizeof(struct bwi_desc32));
 	return (rx_data);
+}
 static int
 bwi_rxeof64(struct bwi_softc *sc)
+{
 	/* TODO: 64 */
 	return (0);
+}
 static void
 bwi_reset_rx_ring32(struct bwi_softc *sc, uint32_t rx_ctrl)
+{
 	int i;
 	CSR_WRITE_4(sc, rx_ctrl + BWI_RX32_CTRL, 0);
 #define NRETRY 10
 	for (i = 0; i < NRETRY; ++i) {
 		uint32_t status;
 		status = CSR_READ_4(sc, rx_ctrl + BWI_RX32_STATUS);
 		if (__SHIFTOUT(status, BWI_RX32_STATUS_STATE_MASK) ==
 		    BWI_RX32_STATUS_STATE_DISABLED)
 			break;
 		DELAY(1000);
+	}
 	if (i == NRETRY)
 		aprint_error_dev(sc->sc_dev, "reset rx ring timedout\n");
 #undef NRETRY
 	CSR_WRITE_4(sc, rx_ctrl + BWI_RX32_RINGINFO, 0);
+}
 static void
 bwi_free_txstats32(struct bwi_softc *sc)
+{
 	bwi_reset_rx_ring32(sc, sc->sc_txstats->stats_ctrl_base);
+}
 static void
 bwi_free_rx_ring32(struct bwi_softc *sc)
+{
 	struct bwi_ring_data *rd = &sc->sc_rx_rdata;
 	struct bwi_rxbuf_data *rbd = &sc->sc_rx_bdata;
 	int i;
 	bwi_reset_rx_ring32(sc, rd->rdata_txrx_ctrl);
 	for (i = 0; i < BWI_RX_NDESC; ++i) {
 		struct bwi_rxbuf *rb = &rbd->rbd_buf[i];
 		if (rb->rb_mbuf != NULL) {
 			bus_dmamap_unload(sc->sc_dmat, rb->rb_dmap);
 			m_freem(rb->rb_mbuf);
 			rb->rb_mbuf = NULL;
+		}
+	}
+}
 static void
 bwi_free_tx_ring32(struct bwi_softc *sc, int ring_idx)
+{
 	struct bwi_ring_data *rd;
 	struct bwi_txbuf_data *tbd;
 	uint32_t state, val;
 	int i;
 	KASSERT(ring_idx < BWI_TX_NRING);
 	rd = &sc->sc_tx_rdata[ring_idx];
 	tbd = &sc->sc_tx_bdata[ring_idx];
 #define NRETRY 10
 	for (i = 0; i < NRETRY; ++i) {
 		val = CSR_READ_4(sc, rd->rdata_txrx_ctrl + BWI_TX32_STATUS);
 		state = __SHIFTOUT(val, BWI_TX32_STATUS_STATE_MASK);
 		if (state == BWI_TX32_STATUS_STATE_DISABLED ||
 		    state == BWI_TX32_STATUS_STATE_IDLE ||
 		    state == BWI_TX32_STATUS_STATE_STOPPED)
 			break;
 		DELAY(1000);
+	}
 	if (i == NRETRY)
 		aprint_error_dev(sc->sc_dev,
 		    "wait for TX ring(%d) stable timed out\n", ring_idx);
 	CSR_WRITE_4(sc, rd->rdata_txrx_ctrl + BWI_TX32_CTRL, 0);
 	for (i = 0; i < NRETRY; ++i) {
 		val = CSR_READ_4(sc, rd->rdata_txrx_ctrl + BWI_TX32_STATUS);
 		state = __SHIFTOUT(val, BWI_TX32_STATUS_STATE_MASK);
 		if (state == BWI_TX32_STATUS_STATE_DISABLED)
 			break;
 		DELAY(1000);
+	}
 	if (i == NRETRY)
 		aprint_error_dev(sc->sc_dev, "reset TX ring (%d) timed out\n",
 		    ring_idx);
 #undef NRETRY
 	DELAY(1000);
 	CSR_WRITE_4(sc, rd->rdata_txrx_ctrl + BWI_TX32_RINGINFO, 0);
 	for (i = 0; i < BWI_TX_NDESC; ++i) {
 		struct bwi_txbuf *tb = &tbd->tbd_buf[i];
 		if (tb->tb_mbuf != NULL) {
 			bus_dmamap_unload(sc->sc_dmat, tb->tb_dmap);
 			m_freem(tb->tb_mbuf);
 			tb->tb_mbuf = NULL;
+		}
 		if (tb->tb_ni != NULL) {
 			ieee80211_free_node(tb->tb_ni);
 			tb->tb_ni = NULL;
+		}
+	}
+}
 static void
 bwi_free_txstats64(struct bwi_softc *sc)
+{
 	/* TODO: 64 */
+}
 static void
 bwi_free_rx_ring64(struct bwi_softc *sc)
+{
 	/* TODO: 64 */
+}
 static void
 bwi_free_tx_ring64(struct bwi_softc *sc, int ring_idx)
+{
 	/* TODO: 64 */
+}
 /* XXX does not belong here */
 /* [TRC: Begin pilferage from OpenBSD.] */
 /*
  * Convert bit rate (in 0.5Mbps units) to PLCP signal (R4-R1) and vice versa.
  */
 uint8_t
 bwi_ieee80211_rate2plcp(u_int8_t rate, enum ieee80211_phymode mode)
+{
 	rate &= IEEE80211_RATE_VAL;
 	if (mode == IEEE80211_MODE_11B) {
 		/* IEEE Std 802.11b-1999 page 15, subclause 18.2.3.3 */
 		switch (rate) {
 		case 2:		return 10;
 		case 4:		return 20;
 		case 11:	return 55;
 		case 22:	return 110;
 		/* IEEE Std 802.11g-2003 page 19, subclause 19.3.2.1 */
 		case 44:	return 220;
+		}
 	} else if (mode == IEEE80211_MODE_11G || mode == IEEE80211_MODE_11A) {
 		/* IEEE Std 802.11a-1999 page 14, subclause 17.3.4.1 */
 		switch (rate) {
 		case 12:	return 0x0b;
 		case 18:	return 0x0f;
 		case 24:	return 0x0a;
 		case 36:	return 0x0e;
 		case 48:	return 0x09;
 		case 72:	return 0x0d;
 		case 96:	return 0x08;
 		case 108:	return 0x0c;
+		}
         } else
 		panic("Unexpected mode %u", mode);
 	return 0;
+}
 static uint8_t
 bwi_ieee80211_plcp2rate(uint8_t plcp, enum ieee80211_phymode mode)
+{
 	if (mode == IEEE80211_MODE_11B) {
 		/* IEEE Std 802.11g-2003 page 19, subclause 19.3.2.1 */
 		switch (plcp) {
 		case 10:	return 2;
 		case 20:	return 4;
 		case 55:	return 11;
 		case 110:	return 22;
 		/* IEEE Std 802.11g-2003 page 19, subclause 19.3.2.1 */
 		case 220:	return 44;
+		}
 	} else if (mode == IEEE80211_MODE_11G || mode == IEEE80211_MODE_11A) {
 		/* IEEE Std 802.11a-1999 page 14, subclause 17.3.4.1 */
 		switch (plcp) {
 		case 0x0b:	return 12;
 		case 0x0f:	return 18;
 		case 0x0a:	return 24;
 		case 0x0e:	return 36;
 		case 0x09:	return 48;
 		case 0x0d:	return 72;
 		case 0x08:	return 96;
 		case 0x0c:	return 108;
+		}
 	} else
 		panic("Unexpected mode %u", mode);
 	return 0;
+}
 /* [TRC: End pilferage from OpenBSD.] */
 static enum bwi_ieee80211_modtype
 bwi_ieee80211_rate2modtype(uint8_t rate)
+{
 	rate &= IEEE80211_RATE_VAL;
 	if (rate == 44)
 		return (IEEE80211_MODTYPE_PBCC);
 	else if (rate == 22 || rate < 12)
 		return (IEEE80211_MODTYPE_DS);
 	else
 		return (IEEE80211_MODTYPE_OFDM);
+}
 static uint8_t
 bwi_ofdm_plcp2rate(const void *plcp0)
+{
 	uint32_t plcp;
 	uint8_t plcp_rate;
 	/* plcp0 may not be 32-bit aligned. */
 	plcp = le32dec(plcp0);
 	plcp_rate = __SHIFTOUT(plcp, IEEE80211_OFDM_PLCP_RATE_MASK);
 	return (bwi_ieee80211_plcp2rate(plcp_rate, IEEE80211_MODE_11G));
+}
 static uint8_t
 bwi_ds_plcp2rate(const struct ieee80211_ds_plcp_hdr *hdr)
+{
 	return (bwi_ieee80211_plcp2rate(hdr->i_signal, IEEE80211_MODE_11B));
+}
 static void
 bwi_ofdm_plcp_header(uint32_t *plcp0, int pkt_len, uint8_t rate)
+{
 	uint32_t plcp;
 	plcp = __SHIFTIN(bwi_ieee80211_rate2plcp(rate, IEEE80211_MODE_11G),
 	    IEEE80211_OFDM_PLCP_RATE_MASK) |
 	    __SHIFTIN(pkt_len, IEEE80211_OFDM_PLCP_LEN_MASK);
 	*plcp0 = htole32(plcp);
+}
 static void
 bwi_ds_plcp_header(struct ieee80211_ds_plcp_hdr *plcp, int pkt_len,
     uint8_t rate)
+{
 	int len, service, pkt_bitlen;
 	pkt_bitlen = pkt_len * NBBY;
 	len = howmany(pkt_bitlen * 2, rate);
 	service = IEEE80211_DS_PLCP_SERVICE_LOCKED;
 	if (rate == (11 * 2)) {
 		int pkt_bitlen1;
 		/*
 		 * PLCP service field needs to be adjusted,
 		 * if TX rate is 11Mbytes/s
 		 */
 		pkt_bitlen1 = len * 11;
 		if (pkt_bitlen1 - pkt_bitlen >= NBBY)
 			service |= IEEE80211_DS_PLCP_SERVICE_LENEXT7;
+	}
 	plcp->i_signal = bwi_ieee80211_rate2plcp(rate, IEEE80211_MODE_11B);
 	plcp->i_service = service;
 	plcp->i_length = htole16(len);
 	/* NOTE: do NOT touch i_crc */
+}
 static void
 bwi_plcp_header(void *plcp, int pkt_len, uint8_t rate)
+{
 	enum bwi_ieee80211_modtype modtype;
 	/*
 	 * Assume caller has zeroed 'plcp'
 	 */
 	modtype = bwi_ieee80211_rate2modtype(rate);
 	if (modtype == IEEE80211_MODTYPE_OFDM)
 		bwi_ofdm_plcp_header(plcp, pkt_len, rate);
 	else if (modtype == IEEE80211_MODTYPE_DS)
 		bwi_ds_plcp_header(plcp, pkt_len, rate);
 	else
 		panic("unsupport modulation type %u\n", modtype);
+}
 static uint8_t
 bwi_ieee80211_ack_rate(struct ieee80211_node *ni, uint8_t rate)
+{
 	const struct ieee80211_rateset *rs = &ni->ni_rates;
 	uint8_t ack_rate = 0;
 	enum bwi_ieee80211_modtype modtype;
 	int i;
 	rate &= IEEE80211_RATE_VAL;
 	modtype = bwi_ieee80211_rate2modtype(rate);
 	for (i = 0; i < rs->rs_nrates; ++i) {
 		uint8_t rate1 = rs->rs_rates[i] & IEEE80211_RATE_VAL;
 		if (rate1 > rate) {
 			if (ack_rate != 0)
 				return (ack_rate);
 			else
 				break;
+		}
 		if ((rs->rs_rates[i] & IEEE80211_RATE_BASIC) &&
 		    bwi_ieee80211_rate2modtype(rate1) == modtype)
 			ack_rate = rate1;
+	}
 	switch (rate) {
 	/* CCK */
 	case 2:
 	case 4:
 	case 11:
 	case 22:
 		ack_rate = rate;
 		break;
 	/* PBCC */
 	case 44:
 		ack_rate = 22;
 		break;
 	/* OFDM */
 	case 12:
 	case 18:
 		ack_rate = 12;
 		break;
 	case 24:
 	case 36:
 		ack_rate = 24;
 		break;
 	case 48:
 	case 72:
 	case 96:
 	case 108:
 		ack_rate = 48;
 		break;
 	default:
 		panic("unsupported rate %d\n", rate);
+	}
 	return (ack_rate);
+}
 /* [TRC: XXX does not belong here] */
 #define IEEE80211_OFDM_TXTIME(kbps, frmlen)	\
 	(IEEE80211_OFDM_PREAMBLE_TIME +		\
 	 IEEE80211_OFDM_SIGNAL_TIME +		\
 	(IEEE80211_OFDM_NSYMS((kbps), (frmlen)) * IEEE80211_OFDM_SYM_TIME))
 #define IEEE80211_OFDM_SYM_TIME			4
 #define IEEE80211_OFDM_PREAMBLE_TIME		16
 #define IEEE80211_OFDM_SIGNAL_EXT_TIME		6
 #define IEEE80211_OFDM_SIGNAL_TIME		4
 #define IEEE80211_OFDM_PLCP_SERVICE_NBITS	16
 #define IEEE80211_OFDM_TAIL_NBITS		6
 #define IEEE80211_OFDM_NBITS(frmlen)		\
 	(IEEE80211_OFDM_PLCP_SERVICE_NBITS +	\
 	 ((frmlen) * NBBY) +			\
 	 IEEE80211_OFDM_TAIL_NBITS)
 #define IEEE80211_OFDM_NBITS_PER_SYM(kbps)	\
 	(((kbps) * IEEE80211_OFDM_SYM_TIME) / 1000)
 #define IEEE80211_OFDM_NSYMS(kbps, frmlen)	\
 	howmany(IEEE80211_OFDM_NBITS((frmlen)),	\
 	IEEE80211_OFDM_NBITS_PER_SYM((kbps)))
 #define IEEE80211_CCK_TXTIME(kbps, frmlen)	\
 	(((IEEE80211_CCK_NBITS((frmlen)) * 1000) + (kbps) - 1) / (kbps))
 #define IEEE80211_CCK_PREAMBLE_LEN		144
 #define IEEE80211_CCK_PLCP_HDR_TIME		48
 #define IEEE80211_CCK_SHPREAMBLE_LEN		72
 #define IEEE80211_CCK_SHPLCP_HDR_TIME		24
 #define IEEE80211_CCK_NBITS(frmlen)		((frmlen) * NBBY)
 static uint16_t
 bwi_ieee80211_txtime(struct ieee80211com *ic, struct ieee80211_node *ni,
     uint len, uint8_t rs_rate, uint32_t flags)
+{
 	enum bwi_ieee80211_modtype modtype;
 	uint16_t txtime;
 	int rate;
 	rs_rate &= IEEE80211_RATE_VAL;
 	rate = rs_rate * 500;	/* ieee80211 rate -> kbps */
 	modtype = bwi_ieee80211_rate2modtype(rs_rate);
 	if (modtype == IEEE80211_MODTYPE_OFDM) {
 		/*
 		 * IEEE Std 802.11a-1999, page 37, equation (29)
 		 * IEEE Std 802.11g-2003, page 44, equation (42)
 		 */
 		txtime = IEEE80211_OFDM_TXTIME(rate, len);
 		if (ic->ic_curmode == IEEE80211_MODE_11G)
 			txtime += IEEE80211_OFDM_SIGNAL_EXT_TIME;
 	} else {
 		/*
 		 * IEEE Std 802.11b-1999, page 28, subclause 18.3.4
 		 * IEEE Std 802.11g-2003, page 45, equation (43)
 		 */
 		if (modtype == IEEE80211_MODTYPE_PBCC)
 			++len;
 		txtime = IEEE80211_CCK_TXTIME(rate, len);
 		/*
 		 * Short preamble is not applicable for DS 1Mbits/s
 		 */
 		if (rs_rate != 2 && (flags & IEEE80211_F_SHPREAMBLE)) {
 			txtime += IEEE80211_CCK_SHPREAMBLE_LEN +
 				  IEEE80211_CCK_SHPLCP_HDR_TIME;
 		} else {
 			txtime += IEEE80211_CCK_PREAMBLE_LEN +
 				  IEEE80211_CCK_PLCP_HDR_TIME;
+		}
+	}
 	return (txtime);
+}
 static int
 bwi_encap(struct bwi_softc *sc, int idx, struct mbuf *m,
     struct ieee80211_node **nip, int mgt_pkt)
+{
 	struct ieee80211com *ic = &sc->sc_ic;
 	struct ieee80211_node *ni = *nip;
 	struct bwi_ring_data *rd = &sc->sc_tx_rdata[BWI_TX_DATA_RING];
 	struct bwi_txbuf_data *tbd = &sc->sc_tx_bdata[BWI_TX_DATA_RING];
 	struct bwi_txbuf *tb = &tbd->tbd_buf[idx];
 	struct bwi_mac *mac;
 	struct bwi_txbuf_hdr *hdr;
 	struct ieee80211_frame *wh;
 	uint8_t rate;		/* [TRC: XXX Use a fallback rate?] */
 	uint32_t mac_ctrl;
 	uint16_t phy_ctrl;
 	bus_addr_t paddr;
 	int pkt_len, error, mcast_pkt = 0;
 #if 0
 	const uint8_t *p;
 	int i;
 #endif
 	KASSERT(ni != NULL);
 	KASSERT(sc->sc_cur_regwin->rw_type == BWI_REGWIN_T_MAC);
 	mac = (struct bwi_mac *)sc->sc_cur_regwin;
 	wh = mtod(m, struct ieee80211_frame *);
 	/* Get 802.11 frame len before prepending TX header */
 	pkt_len = m->m_pkthdr.len + IEEE80211_CRC_LEN;
 	/*
 	 * Find TX rate
 	 */
 	memset(tb->tb_rate_idx, 0, sizeof(tb->tb_rate_idx));
 	if (!mgt_pkt) {
 		if (ic->ic_fixed_rate != -1) {
 			rate = ic->ic_sup_rates[ic->ic_curmode].
 			    rs_rates[ic->ic_fixed_rate];
 			/* [TRC: XXX Set fallback rate.] */
 		} else {
 			/* AMRR rate control */
 			/* [TRC: XXX amrr] */
 			/* rate = ni->ni_rates.rs_rates[ni->ni_txrate]; */
 			rate = (1 * 2);
 			/* [TRC: XXX Set fallback rate.] */
+		}
 	} else {
 		/* Fixed at 1Mbits/s for mgt frames */
 		/* [TRC: XXX Set fallback rate.] */
 		rate = (1 * 2);
+	}
 	rate &= IEEE80211_RATE_VAL;
 	if (IEEE80211_IS_MULTICAST(wh->i_addr1)) {
 		/* [TRC: XXX Set fallback rate.] */
 		rate = ic->ic_mcast_rate;
 		mcast_pkt = 1;
+	}
 	/* [TRC: XXX Check fallback rate.] */
 	if (rate == 0) {
 		aprint_error_dev(sc->sc_dev, "invalid rate %u", rate);
 		/* [TRC: In the margin of the following line,
 		   DragonFlyBSD writes `Force 1Mbits/s', whereas
 		   OpenBSD writes `Force 1Mbytes/s'.] */
 		rate = (1 * 2);
 		/* [TRC: XXX Set fallback rate.] */
+	}
 	sc->sc_tx_rate = rate;
 	/* TX radio tap */
 	if (sc->sc_drvbpf != NULL) {
 		struct mbuf mb;
 		struct bwi_tx_radiotap_hdr *tap = &sc->sc_txtap;
 		tap->wt_flags = 0;
 		tap->wt_rate = rate;
 		tap->wt_chan_freq =
 		    htole16(ic->ic_bss->ni_chan->ic_freq);
 		tap->wt_chan_flags =
 		    htole16(ic->ic_bss->ni_chan->ic_flags);
 		mb.m_data = (void *)tap;
 		mb.m_len = sc->sc_txtap_len;
 		mb.m_next = m;
 		mb.m_nextpkt = NULL;
 		mb.m_type = 0;
 		mb.m_flags = 0;
 		bpf_mtap3(sc->sc_drvbpf, &mb, BPF_D_OUT);
+	}
 	/*
 	 * Setup the embedded TX header
 	 */
 	M_PREPEND(m, sizeof(*hdr), M_DONTWAIT);
 	if (m == NULL) {
 		aprint_error_dev(sc->sc_dev, "prepend TX header failed\n");
 		return (ENOBUFS);
+	}
 	hdr = mtod(m, struct bwi_txbuf_hdr *);
 	memset(hdr, 0, sizeof(*hdr));
 	memcpy(hdr->txh_fc, wh->i_fc, sizeof(hdr->txh_fc));
 	memcpy(hdr->txh_addr1, wh->i_addr1, sizeof(hdr->txh_addr1));
 	if (!mcast_pkt) {
 		uint16_t dur;
 		uint8_t ack_rate;
 		/* [TRC: XXX Set fallback rate.] */
 		ack_rate = bwi_ieee80211_ack_rate(ni, rate);
 		dur = bwi_ieee80211_txtime(ic, ni,
 		    sizeof(struct ieee80211_frame_ack) + IEEE80211_CRC_LEN,
 		    ack_rate, ic->ic_flags & IEEE80211_F_SHPREAMBLE);
 		hdr->txh_fb_duration = htole16(dur);
+	}
 	hdr->txh_id = htole16(
 	    __SHIFTIN(BWI_TX_DATA_RING, BWI_TXH_ID_RING_MASK) |
 	    __SHIFTIN(idx, BWI_TXH_ID_IDX_MASK));
 	bwi_plcp_header(hdr->txh_plcp, pkt_len, rate);
 	/* [TRC: XXX Use fallback rate.] */
 	bwi_plcp_header(hdr->txh_fb_plcp, pkt_len, rate);
 	phy_ctrl = __SHIFTIN(mac->mac_rf.rf_ant_mode,
 	    BWI_TXH_PHY_C_ANTMODE_MASK);
 	if (bwi_ieee80211_rate2modtype(rate) == IEEE80211_MODTYPE_OFDM)
 		phy_ctrl |= BWI_TXH_PHY_C_OFDM;
 	else if ((ic->ic_flags & IEEE80211_F_SHPREAMBLE) && rate != (2 * 1))
 		phy_ctrl |= BWI_TXH_PHY_C_SHPREAMBLE;
 	mac_ctrl = BWI_TXH_MAC_C_HWSEQ | BWI_TXH_MAC_C_FIRST_FRAG;
 	if (!IEEE80211_IS_MULTICAST(wh->i_addr1))
 		mac_ctrl |= BWI_TXH_MAC_C_ACK;
 	if (bwi_ieee80211_rate2modtype(rate) == IEEE80211_MODTYPE_OFDM)
 		mac_ctrl |= BWI_TXH_MAC_C_FB_OFDM;
 	hdr->txh_mac_ctrl = htole32(mac_ctrl);
 	hdr->txh_phy_ctrl = htole16(phy_ctrl);
 	/* Catch any further usage */
 	hdr = NULL;
 	wh = NULL;
 	/* DMA load */
 	error = bus_dmamap_load_mbuf(sc->sc_dmat, tb->tb_dmap, m,
 	    BUS_DMA_NOWAIT);
 	if (error && error != EFBIG) {
 		aprint_error_dev(sc->sc_dev, "can't load TX buffer (1) %d\n",
 		    error);
 		goto back;
+	}
 	if (error) {	/* error == EFBIG */
 		struct mbuf *m_new;
 		error = 0;
 		MGETHDR(m_new, M_DONTWAIT, MT_DATA);
 		if (m_new == NULL) {
 			error = ENOBUFS;
 			aprint_error_dev(sc->sc_dev,
 			    "can't defrag TX buffer (1)\n");
 			goto back;
+		}
 		m_copy_pkthdr(m_new, m);
 		if (m->m_pkthdr.len > MHLEN) {
 			MCLGET(m_new, M_DONTWAIT);
 			if (!(m_new->m_flags & M_EXT)) {
 				m_freem(m_new);
 				error = ENOBUFS;
+			}
+		}
 		if (error) {
 			aprint_error_dev(sc->sc_dev,
 			    "can't defrag TX buffer (2)\n");
 			goto back;
+		}
 		m_copydata(m, 0, m->m_pkthdr.len, mtod(m_new, void *));
 		m_freem(m);
 		m_new->m_len = m_new->m_pkthdr.len;
 		m = m_new;
 		error = bus_dmamap_load_mbuf(sc->sc_dmat, tb->tb_dmap, m,
 		    BUS_DMA_NOWAIT);
 		if (error) {
 			aprint_error_dev(sc->sc_dev,
 			    "can't load TX buffer (2) %d\n", error);
 			goto back;
+		}
+	}
 	error = 0;
 	bus_dmamap_sync(sc->sc_dmat, tb->tb_dmap, 0,
 	    tb->tb_dmap->dm_mapsize, BUS_DMASYNC_PREWRITE);
 	if (mgt_pkt || mcast_pkt) {
 		/* Don't involve mcast/mgt packets into TX rate control */
 		ieee80211_free_node(ni);
 		*nip = ni = NULL;
+	}
 	tb->tb_mbuf = m;
 	tb->tb_ni = ni;
 #if 0
 	p = mtod(m, const uint8_t *);
 	for (i = 0; i < m->m_pkthdr.len; ++i) {
 		if (i % 8 == 0) {
 			if (i != 0)
 				aprint_debug("\n");
 			aprint_debug_dev(sc->sc_dev, "");
+		}
 		aprint_debug(" %02x", p[i]);
+	}
 	aprint_debug("\n");
 #endif
 	DPRINTF(sc, BWI_DBG_TX, "idx %d, pkt_len %d, buflen %d\n",
 	    idx, pkt_len, m->m_pkthdr.len);
 	/* Setup TX descriptor */
 	paddr = tb->tb_dmap->dm_segs[0].ds_addr;
 	(sc->sc_setup_txdesc)(sc, rd, idx, paddr, m->m_pkthdr.len);
 	bus_dmamap_sync(sc->sc_dmat, rd->rdata_dmap, 0,
 	    rd->rdata_dmap->dm_mapsize, BUS_DMASYNC_PREWRITE);
 	/* Kick start */
 	(sc->sc_start_tx)(sc, rd->rdata_txrx_ctrl, idx);
 back:
 	if (error)
 		m_freem(m);
 	return (error);
+}
 static void
 bwi_start_tx32(struct bwi_softc *sc, uint32_t tx_ctrl, int idx)
+{
 	idx = (idx + 1) % BWI_TX_NDESC;
 	CSR_WRITE_4(sc, tx_ctrl + BWI_TX32_INDEX,
 	    idx * sizeof(struct bwi_desc32));
+}
 static void
 bwi_start_tx64(struct bwi_softc *sc, uint32_t tx_ctrl, int idx)
+{
 	/* TODO: 64 */
+}
 static void
 bwi_txeof_status32(struct bwi_softc *sc)
+{
 	struct ifnet *ifp = &sc->sc_if;
 	uint32_t val, ctrl_base;
 	int end_idx, s;
 	s = splnet();
 	ctrl_base = sc->sc_txstats->stats_ctrl_base;
 	val = CSR_READ_4(sc, ctrl_base + BWI_RX32_STATUS);
 	end_idx = __SHIFTOUT(val, BWI_RX32_STATUS_INDEX_MASK) /
 	    sizeof(struct bwi_desc32);
 	bwi_txeof_status(sc, end_idx);
 	CSR_WRITE_4(sc, ctrl_base + BWI_RX32_INDEX,
 	    end_idx * sizeof(struct bwi_desc32));
 	if ((ifp->if_flags & IFF_OACTIVE) == 0)
 		ifp->if_start(ifp); /* [TRC: XXX Why not bwi_start?] */
 	splx(s);
+}
 static void
 bwi_txeof_status64(struct bwi_softc *sc)
+{
 	/* TODO: 64 */
+}
 static void
 _bwi_txeof(struct bwi_softc *sc, uint16_t tx_id)
+{
 	struct ifnet *ifp = &sc->sc_if;
 	struct bwi_txbuf_data *tbd;
 	struct bwi_txbuf *tb;
 	int ring_idx, buf_idx;
 	if (tx_id == 0) {
 		/* [TRC: XXX What is the severity of this message?] */
 		aprint_normal_dev(sc->sc_dev, "zero tx id\n");
 		return;
+	}
 	ring_idx = __SHIFTOUT(tx_id, BWI_TXH_ID_RING_MASK);
 	buf_idx = __SHIFTOUT(tx_id, BWI_TXH_ID_IDX_MASK);
 	KASSERT(ring_idx == BWI_TX_DATA_RING);
 	KASSERT(buf_idx < BWI_TX_NDESC);
 	tbd = &sc->sc_tx_bdata[ring_idx];
 	KASSERT(tbd->tbd_used > 0);
 	tbd->tbd_used--;
 	tb = &tbd->tbd_buf[buf_idx];
 	bus_dmamap_unload(sc->sc_dmat, tb->tb_dmap);
 	m_freem(tb->tb_mbuf);
 	tb->tb_mbuf = NULL;
 	if (tb->tb_ni != NULL) {
 		ieee80211_free_node(tb->tb_ni);
 		tb->tb_ni = NULL;
+	}
 	if (tbd->tbd_used == 0)
 		sc->sc_tx_timer = 0;
 	ifp->if_flags &= ~IFF_OACTIVE;
+}
 static void
 bwi_txeof_status(struct bwi_softc *sc, int end_idx)
+{
 	struct bwi_txstats_data *st = sc->sc_txstats;
 	int idx;
 	bus_dmamap_sync(sc->sc_dmat, st->stats_dmap, 0,
 	    st->stats_dmap->dm_mapsize, BUS_DMASYNC_POSTREAD);
 	idx = st->stats_idx;
 	while (idx != end_idx) {
 		/* [TRC: XXX Filter this out if it is not pending; see
 		   DragonFlyBSD's revision 1.5. */
 		_bwi_txeof(sc, le16toh(st->stats[idx].txs_id));
 		idx = (idx + 1) % BWI_TXSTATS_NDESC;
+	}
 	st->stats_idx = idx;
+}
 static void
 bwi_txeof(struct bwi_softc *sc)
+{
 	struct ifnet *ifp = &sc->sc_if;
 	int s;
 	s = splnet();
 	for (;;) {
 		uint32_t tx_status0;
 		uint16_t tx_id, tx_info;
 		tx_status0 = CSR_READ_4(sc, BWI_TXSTATUS_0);
 		if ((tx_status0 & BWI_TXSTATUS_0_MORE) == 0)
 			break;
 		(void)CSR_READ_4(sc, BWI_TXSTATUS_1);
 		tx_id = __SHIFTOUT(tx_status0, BWI_TXSTATUS_0_TXID_MASK);
 		tx_info = BWI_TXSTATUS_0_INFO(tx_status0);
 		if (tx_info & 0x30) /* XXX */
 			continue;
 		_bwi_txeof(sc, tx_id);
-		ifp->if_opackets++;
+		if_statinc(ifp, if_opackets);
+	}
 	if ((ifp->if_flags & IFF_OACTIVE) == 0)
 		ifp->if_start(ifp);
 	splx(s);
+}
 static int
 bwi_bbp_power_on(struct bwi_softc *sc, enum bwi_clock_mode clk_mode)
+{
 	bwi_power_on(sc, 1);
 	return (bwi_set_clock_mode(sc, clk_mode));
+}
 static void
 bwi_bbp_power_off(struct bwi_softc *sc)
+{
 	bwi_set_clock_mode(sc, BWI_CLOCK_MODE_SLOW);
 	bwi_power_off(sc, 1);
+}
 static int
 bwi_get_pwron_delay(struct bwi_softc *sc)
+{
 	struct bwi_regwin *com, *old;
 	struct bwi_clock_freq freq;
 	uint32_t val;
 	int error;
 	com = &sc->sc_com_regwin;
 	KASSERT(BWI_REGWIN_EXIST(com));
 	if ((sc->sc_cap & BWI_CAP_CLKMODE) == 0)
 		return (0);
 	error = bwi_regwin_switch(sc, com, &old);
 	if (error)
 		return (error);
 	bwi_get_clock_freq(sc, &freq);
 	val = CSR_READ_4(sc, BWI_PLL_ON_DELAY);
 	sc->sc_pwron_delay = howmany((val + 2) * 1000000, freq.clkfreq_min);
 	DPRINTF(sc, BWI_DBG_ATTACH, "power on delay %u\n", sc->sc_pwron_delay);
 	return (bwi_regwin_switch(sc, old, NULL));
+}
 static int
 bwi_bus_attach(struct bwi_softc *sc)
+{
 	struct bwi_regwin *bus, *old;
 	int error;
 	bus = &sc->sc_bus_regwin;
 	error = bwi_regwin_switch(sc, bus, &old);
 	if (error)
 		return (error);
 	if (!bwi_regwin_is_enabled(sc, bus))
 		bwi_regwin_enable(sc, bus, 0);
 	/* Disable interripts */
 	CSR_WRITE_4(sc, BWI_INTRVEC, 0);
 	return (bwi_regwin_switch(sc, old, NULL));
+}
 static const char *
 bwi_regwin_name(const struct bwi_regwin *rw)
+{
 	switch (rw->rw_type) {
 	case BWI_REGWIN_T_COM:
 		return ("COM");
 	case BWI_REGWIN_T_BUSPCI:
 		return ("PCI");
 	case BWI_REGWIN_T_MAC:
 		return ("MAC");
 	case BWI_REGWIN_T_BUSPCIE:
 		return ("PCIE");
+	}
 	panic("unknown regwin type 0x%04x\n", rw->rw_type);
 	return (NULL);
+}
 static uint32_t
 bwi_regwin_disable_bits(struct bwi_softc *sc)
+{
 	uint32_t busrev;
 	/* XXX cache this */
 	busrev = __SHIFTOUT(CSR_READ_4(sc, BWI_ID_LO), BWI_ID_LO_BUSREV_MASK);
 	DPRINTF(sc, BWI_DBG_ATTACH | BWI_DBG_INIT | BWI_DBG_MISC,
 	    "bus rev %u\n", busrev);
 	if (busrev == BWI_BUSREV_0)
 		return (BWI_STATE_LO_DISABLE1);
 	else if (busrev == BWI_BUSREV_1)
 		return (BWI_STATE_LO_DISABLE2);
 	else
 		return (BWI_STATE_LO_DISABLE1 | BWI_STATE_LO_DISABLE2);
+}
 static int
 bwi_regwin_is_enabled(struct bwi_softc *sc, struct bwi_regwin *rw)
+{
 	uint32_t val, disable_bits;
 	disable_bits = bwi_regwin_disable_bits(sc);
 	val = CSR_READ_4(sc, BWI_STATE_LO);
 	if ((val & (BWI_STATE_LO_CLOCK |
 		    BWI_STATE_LO_RESET |
 		    disable_bits)) == BWI_STATE_LO_CLOCK) {
 		DPRINTF(sc, BWI_DBG_ATTACH | BWI_DBG_INIT, "%s is enabled\n",
 		    bwi_regwin_name(rw));
 		return (1);
 	} else {
 		DPRINTF(sc, BWI_DBG_ATTACH | BWI_DBG_INIT, "%s is disabled\n",
 		    bwi_regwin_name(rw));
 		return (0);
+	}
+}
 static void
 bwi_regwin_disable(struct bwi_softc *sc, struct bwi_regwin *rw, uint32_t flags)
+{
 	uint32_t state_lo, disable_bits;
 	int i;
 	state_lo = CSR_READ_4(sc, BWI_STATE_LO);
 	/*
 	 * If current regwin is in 'reset' state, it was already disabled.
 	 */
 	if (state_lo & BWI_STATE_LO_RESET) {
 		DPRINTF(sc, BWI_DBG_ATTACH | BWI_DBG_INIT,
 		    "%s was already disabled\n", bwi_regwin_name(rw));
 		return;
+	}
 	disable_bits = bwi_regwin_disable_bits(sc);
 	/*
 	 * Disable normal clock
 	 */
 	state_lo = BWI_STATE_LO_CLOCK | disable_bits;
 	CSR_WRITE_4(sc, BWI_STATE_LO, state_lo);
 	/*
 	 * Wait until normal clock is disabled
 	 */
 #define NRETRY	1000
 	for (i = 0; i < NRETRY; ++i) {
 		state_lo = CSR_READ_4(sc, BWI_STATE_LO);
 		if (state_lo & disable_bits)
 			break;
 		DELAY(10);
+	}
 	if (i == NRETRY) {
 		aprint_error_dev(sc->sc_dev, "%s disable clock timeout\n",
 		    bwi_regwin_name(rw));
+	}
 	for (i = 0; i < NRETRY; ++i) {
 		uint32_t state_hi;
 		state_hi = CSR_READ_4(sc, BWI_STATE_HI);
 		if ((state_hi & BWI_STATE_HI_BUSY) == 0)
 			break;
 		DELAY(10);
+	}
 	if (i == NRETRY) {
 		aprint_error_dev(sc->sc_dev, "%s wait BUSY unset timeout\n",
 		    bwi_regwin_name(rw));
+	}
 #undef NRETRY
 	/*
 	 * Reset and disable regwin with gated clock
 	 */
 	state_lo = BWI_STATE_LO_RESET | disable_bits |
 	    BWI_STATE_LO_CLOCK | BWI_STATE_LO_GATED_CLOCK |
 	    __SHIFTIN(flags, BWI_STATE_LO_FLAGS_MASK);
 	CSR_WRITE_4(sc, BWI_STATE_LO, state_lo);
 	/* Flush pending bus write */
 	CSR_READ_4(sc, BWI_STATE_LO);
 	DELAY(1);
 	/* Reset and disable regwin */
 	state_lo = BWI_STATE_LO_RESET | disable_bits |
 		   __SHIFTIN(flags, BWI_STATE_LO_FLAGS_MASK);
 	CSR_WRITE_4(sc, BWI_STATE_LO, state_lo);
 	/* Flush pending bus write */
 	CSR_READ_4(sc, BWI_STATE_LO);
 	DELAY(1);
+}
 static void
 bwi_regwin_enable(struct bwi_softc *sc, struct bwi_regwin *rw, uint32_t flags)
+{
 	uint32_t state_lo, state_hi, imstate;
 	bwi_regwin_disable(sc, rw, flags);
 	/* Reset regwin with gated clock */
 	state_lo = BWI_STATE_LO_RESET |
 	    BWI_STATE_LO_CLOCK |
 	    BWI_STATE_LO_GATED_CLOCK |
 	    __SHIFTIN(flags, BWI_STATE_LO_FLAGS_MASK);
 	CSR_WRITE_4(sc, BWI_STATE_LO, state_lo);
 	/* Flush pending bus write */
 	CSR_READ_4(sc, BWI_STATE_LO);
 	DELAY(1);
 	state_hi = CSR_READ_4(sc, BWI_STATE_HI);
 	if (state_hi & BWI_STATE_HI_SERROR)
 		CSR_WRITE_4(sc, BWI_STATE_HI, 0);
 	imstate = CSR_READ_4(sc, BWI_IMSTATE);
 	if (imstate & (BWI_IMSTATE_INBAND_ERR | BWI_IMSTATE_TIMEOUT)) {
 		imstate &= ~(BWI_IMSTATE_INBAND_ERR | BWI_IMSTATE_TIMEOUT);
 		CSR_WRITE_4(sc, BWI_IMSTATE, imstate);
+	}
 	/* Enable regwin with gated clock */
 	state_lo = BWI_STATE_LO_CLOCK |
 	    BWI_STATE_LO_GATED_CLOCK |
 	    __SHIFTIN(flags, BWI_STATE_LO_FLAGS_MASK);
 	CSR_WRITE_4(sc, BWI_STATE_LO, state_lo);
 	/* Flush pending bus write */
 	CSR_READ_4(sc, BWI_STATE_LO);
 	DELAY(1);
 	/* Enable regwin with normal clock */
 	state_lo = BWI_STATE_LO_CLOCK |
 	    __SHIFTIN(flags, BWI_STATE_LO_FLAGS_MASK);
 	CSR_WRITE_4(sc, BWI_STATE_LO, state_lo);
 	/* Flush pending bus write */
 	CSR_READ_4(sc, BWI_STATE_LO);
 	DELAY(1);
+}
 static void
 bwi_set_bssid(struct bwi_softc *sc, const uint8_t *bssid)
+{
 	struct ieee80211com *ic = &sc->sc_ic;
 	struct bwi_mac *mac;
 	struct bwi_myaddr_bssid buf;
 	const uint8_t *p;
 	uint32_t val;
 	int n, i;
 	KASSERT(sc->sc_cur_regwin->rw_type == BWI_REGWIN_T_MAC);
 	mac = (struct bwi_mac *)sc->sc_cur_regwin;
 	bwi_set_addr_filter(sc, BWI_ADDR_FILTER_BSSID, bssid);
 	memcpy(buf.myaddr, ic->ic_myaddr, sizeof(buf.myaddr));
 	memcpy(buf.bssid, bssid, sizeof(buf.bssid));
 	n = sizeof(buf) / sizeof(val);
 	p = (const uint8_t *)&buf;
 	for (i = 0; i < n; ++i) {
 		int j;
 		val = 0;
 		for (j = 0; j < sizeof(val); ++j)
 			val |= ((uint32_t)(*p++)) << (j * 8);
 		TMPLT_WRITE_4(mac, 0x20 + (i * sizeof(val)), val);
+	}
+}
 static void
 bwi_updateslot(struct ifnet *ifp)
+{
 	struct bwi_softc *sc = ifp->if_softc;
 	struct ieee80211com *ic = &sc->sc_ic;
 	struct bwi_mac *mac;
 	if ((ifp->if_flags & IFF_RUNNING) == 0)
 		return;
 	DPRINTF(sc, BWI_DBG_80211, "%s\n", __func__);
 	KASSERT(sc->sc_cur_regwin->rw_type == BWI_REGWIN_T_MAC);
 	mac = (struct bwi_mac *)sc->sc_cur_regwin;
 	bwi_mac_updateslot(mac, (ic->ic_flags & IEEE80211_F_SHSLOT));
+}
 static void
 bwi_calibrate(void *xsc)
+{
 	struct bwi_softc *sc = xsc;
 	struct ieee80211com *ic = &sc->sc_ic;
 	int s;
 	s = splnet();
 	if (ic->ic_state == IEEE80211_S_RUN) {
 		struct bwi_mac *mac;
 		KASSERT(sc->sc_cur_regwin->rw_type == BWI_REGWIN_T_MAC);
 		mac = (struct bwi_mac *)sc->sc_cur_regwin;
 		if (ic->ic_opmode != IEEE80211_M_MONITOR) {
 			bwi_mac_calibrate_txpower(mac, sc->sc_txpwrcb_type);
 			sc->sc_txpwrcb_type = BWI_TXPWR_CALIB;
+		}
 		/* XXX 15 seconds */
 		callout_schedule(&sc->sc_calib_ch, hz * 15);
+	}
 	splx(s);
+}
 static int
 bwi_calc_rssi(struct bwi_softc *sc, const struct bwi_rxbuf_hdr *hdr)
+{
 	struct bwi_mac *mac;
 	KASSERT(sc->sc_cur_regwin->rw_type == BWI_REGWIN_T_MAC);
 	mac = (struct bwi_mac *)sc->sc_cur_regwin;
 	return (bwi_rf_calc_rssi(mac, hdr));
+}
 bool
 bwi_suspend(device_t dv, const pmf_qual_t *qual)
+{
 	struct bwi_softc *sc = device_private(dv);
 	bwi_power_off(sc, 0);
 	if (sc->sc_disable != NULL)
 		(sc->sc_disable)(sc, 1);
 	return true;
+}
 bool
 bwi_resume(device_t dv, const pmf_qual_t *qual)
+{
 	struct bwi_softc *sc = device_private(dv);
 	if (sc->sc_enable != NULL)
 		(sc->sc_enable)(sc, 1);
 	bwi_power_on(sc, 1);
 	return true;
+}

 @@ -1,2145 +1,2148 @@
-/*	$NetBSD: cs89x0.c,v 1.47 2019/05/29 10:07:29 msaitoh Exp $	*/
+/*	$NetBSD: cs89x0.c,v 1.48 2020/01/29 14:14:55 thorpej Exp $	*/
 /*
  * Copyright (c) 2004 Christopher Gilbert
  * All rights reserved.
+ *
  * 1. Redistributions of source code must retain the above copyright
  *    notice, this list of conditions and the following disclaimer.
  * 2. Redistributions in binary form must reproduce the above copyright
  *    notice, this list of conditions and the following disclaimer in the
  *    documentation and/or other materials provided with the distribution.
  * 3. The name of the company nor the name of the author may be used to
  *    endorse or promote products derived from this software without specific
  *    prior written permission.
+ *
  * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED
  * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
  * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
  * IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
  * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
  * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
  * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
  * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
  * SUCH DAMAGE.
  */
 /*
  * Copyright 1997
  * Digital Equipment Corporation. All rights reserved.
+ *
  * This software is furnished under license and may be used and
  * copied only in accordance with the following terms and conditions.
  * Subject to these conditions, you may download, copy, install,
  * use, modify and distribute this software in source and/or binary
  * form. No title or ownership is transferred hereby.
+ *
  * 1) Any source code used, modified or distributed must reproduce
  *    and retain this copyright notice and list of conditions as
  *    they appear in the source file.
+ *
  * 2) No right is granted to use any trade name, trademark, or logo of
  *    Digital Equipment Corporation. Neither the "Digital Equipment
  *    Corporation" name nor any trademark or logo of Digital Equipment
  *    Corporation may be used to endorse or promote products derived
  *    from this software without the prior written permission of
  *    Digital Equipment Corporation.
+ *
  * 3) This software is provided "AS-IS" and any express or implied
  *    warranties, including but not limited to, any implied warranties
  *    of merchantability, fitness for a particular purpose, or
  *    non-infringement are disclaimed. In no event shall DIGITAL be
  *    liable for any damages whatsoever, and in particular, DIGITAL
  *    shall not be liable for special, indirect, consequential, or
  *    incidental damages or damages for lost profits, loss of
  *    revenue or loss of use, whether such damages arise in contract,
  *    negligence, tort, under statute, in equity, at law or otherwise,
  *    even if advised of the possibility of such damage.
  */
 /*
 **++
 **  FACILITY
 **
 **     Device Driver for the Crystal CS8900 ISA Ethernet Controller.
 **
 **  ABSTRACT
 **
 **     This module provides standard ethernet access for INET protocols
 **     only.
 **
 **  AUTHORS
 **
 **     Peter Dettori     SEA - Software Engineering.
 **
 **  CREATION DATE:
 **
 **     13-Feb-1997.
 **
 **  MODIFICATION HISTORY (Digital):
 **
 **     Revision 1.27  1998/01/20  17:59:40  cgd
 **     update for moved headers
 **
 **     Revision 1.26  1998/01/12  19:29:36  cgd
 **     use arm32/isa versions of isadma code.
 **
 **     Revision 1.25  1997/12/12  01:35:27  cgd
 **     convert to use new arp code (from Brini)
 **
 **     Revision 1.24  1997/12/10  22:31:56  cgd
 **     trim some fat (get rid of ability to explicitly supply enet addr, since
 **     it was never used and added a bunch of code which really doesn't belong in
 **     an enet driver), and clean up slightly.
 **
 **     Revision 1.23  1997/10/06  16:42:12  cgd
 **     copyright notices
 **
 **     Revision 1.22  1997/06/20  19:38:01  chaiken
 **     fixes some smartcard problems
 **
 **     Revision 1.21  1997/06/10 02:56:20  grohn
 **     Added call to ledNetActive
 **
 **     Revision 1.20  1997/06/05 00:47:06  dettori
 **     Changed cs_process_rx_dma to reset and re-initialise the
 **     ethernet chip when DMA gets out of sync, or mbufs
 **     can't be allocated.
 **
 **     Revision 1.19  1997/06/03 03:09:58  dettori
 **     Turn off sc_txbusy flag when a transmit underrun
 **     occurs.
 **
 **     Revision 1.18  1997/06/02 00:04:35  dettori
 **     redefined the transmit table to get around the nfs_timer bug while we are
 **     looking into it further.
 **
 **     Also changed interrupts from EDGE to LEVEL.
 **
 **     Revision 1.17  1997/05/27 23:31:01  dettori
 **     Pulled out changes to DMAMODE defines.
 **
 **     Revision 1.16  1997/05/23 04:25:16  cgd
 **     reformat log so it fits in 80cols
 **
 **     Revision 1.15  1997/05/23  04:22:18  cgd
 **     remove the existing copyright notice (which Peter Dettori indicated
 **     was incorrect, copied from an existing NetBSD file only so that the
 **     file would have a copyright notice on it, and which he'd intended to
 **     replace).  Replace it with a Digital copyright notice, cloned from
 **     ess.c.  It's not really correct either (it indicates that the source
 **     is Digital confidential!), but is better than nothing and more
 **     correct than what was there before.
 **
 **     Revision 1.14  1997/05/23  04:12:50  cgd
 **     use an adaptive transmit start algorithm: start by telling the chip
 **     to start transmitting after 381 bytes have been fed to it.  if that
 **     gets transmit underruns, ramp down to 1021 bytes then "whole
 **     packet."  If successful at a given level for a while, try the next
 **     more agressive level.  This code doesn't ever try to start
 **     transmitting after 5 bytes have been sent to the NIC, because
 **     that underruns rather regularly.  The back-off and ramp-up mechanism
 **     could probably be tuned a little bit, but this works well enough to
 **     support > 1MB/s transmit rates on a clear ethernet (which is about
 **     20-25% better than the driver had previously been getting).
 **
 **     Revision 1.13  1997/05/22  21:06:54  cgd
 **     redo cs_copy_tx_frame() from scratch.  It had a fatal flaw: it was blindly
 **     casting from uint8_t * to uint16_t * without worrying about alignment
 **     issues.  This would cause bogus data to be spit out for mbufs with
 **     misaligned data.  For instance, it caused the following bits to appear
 **     on the wire:
 **     	... etBND 1S2C .SHA(K) R ...
 **     	    11112222333344445555
 **     which should have appeared as:
 **     	... NetBSD 1.2C (SHARK) ...
 **     	    11112222333344445555
 **     Note the apparent 'rotate' of the bytes in the word, which was due to
 **     incorrect unaligned accesses.  This data corruption was the cause of
 **     incoming telnet/rlogin hangs.
 **
 **     Revision 1.12  1997/05/22  01:55:32  cgd
 **     reformat log so it fits in 80cols
 **
 **     Revision 1.11  1997/05/22  01:50:27  cgd
 **     * enable input packet address checking in the BPF+IFF_PROMISCUOUS case,
 **       so packets aimed at other hosts don't get sent to ether_input().
 **     * Add a static const char *rcsid initialized with an RCS Id tag, so that
 **       you can easily tell (`strings`) what version of the driver is in your
 **       kernel binary.
 **     * get rid of ether_cmp().  It was inconsistently used, not necessarily
 **       safe, and not really a performance win anyway.  (It was only used when
 **       setting up the multicast logical address filter, which is an
 **       infrequent event.  It could have been used in the IFF_PROMISCUOUS
 **       address check above, but the benefit of it vs. memcmp would be
 **       inconsequential, there.)  Use memcmp() instead.
 **     * restructure csStartOuput to avoid the following bugs in the case where
 **       txWait was being set:
 **         * it would accidentally drop the outgoing packet if told to wait
 **           but the outgoing packet queue was empty.
 **         * it would bpf_mtap() the outgoing packet multiple times (once for
 **           each time it was told to wait), and would also recalculate
 **           the length of the outgoing packet each time it was told to
 **           wait.
 **       While there, rename txWait to txLoop, since with the new structure of
 **       the code, the latter name makes more sense.
 **
 **     Revision 1.10  1997/05/19  02:03:20  cgd
 **     Set RX_CTL in cs_set_ladr_filt(), rather than cs_initChip().  cs_initChip()
 **     is the only caller of cs_set_ladr_filt(), and always calls it, so this
 **     ends up being logically the same.  In cs_set_ladr_filt(), if IFF_PROMISC
 **     is set, enable promiscuous mode (and set IFF_ALLMULTI), otherwise behave
 **     as before.
 **
 **     Revision 1.9  1997/05/19  01:45:37  cgd
 **     create a new function, cs_ether_input(), which does received-packet
 **     BPF and ether_input processing.  This code used to be in three places,
 **     and centralizing it will make adding IFF_PROMISC support much easier.
 **     Also, in cs_copy_tx_frame(), put it some (currently disabled) code to
 **     do copies with bus_space_write_region_2().  It's more correct, and
 **     potentially more efficient.  That function needs to be gutted (to
 **     deal properly with alignment issues, which it currently does wrong),
 **     however, and the change doesn't gain much, so there's no point in
 **     enabling it now.
 **
 **     Revision 1.8  1997/05/19  01:17:10  cgd
 **     fix a comment re: the setting of the TxConfig register.  Clean up
 **     interface counter maintenance (make it use standard idiom).
 **
 **--
 */
 #include <sys/cdefs.h>
-__KERNEL_RCSID(0, "$NetBSD: cs89x0.c,v 1.47 2019/05/29 10:07:29 msaitoh Exp $");
+__KERNEL_RCSID(0, "$NetBSD: cs89x0.c,v 1.48 2020/01/29 14:14:55 thorpej Exp $");
 #include "opt_inet.h"
 #include <sys/param.h>
 #include <sys/systm.h>
 #include <sys/mbuf.h>
 #include <sys/syslog.h>
 #include <sys/socket.h>
 #include <sys/device.h>
 #include <sys/malloc.h>
 #include <sys/ioctl.h>
 #include <sys/errno.h>
 #include <sys/bus.h>
 #include <sys/intr.h>
 #include <sys/rndsource.h>
 #include <net/if.h>
 #include <net/if_ether.h>
 #include <net/if_media.h>
 #include <net/bpf.h>
 #ifdef INET
 #include <netinet/in.h>
 #include <netinet/if_inarp.h>
 #endif
 #include <dev/ic/cs89x0reg.h>
 #include <dev/ic/cs89x0var.h>
 #ifdef SHARK
 #include <shark/shark/sequoia.h>
 #endif
 /*
  * MACRO DEFINITIONS
  */
 #define CS_OUTPUT_LOOP_MAX 100	/* max times round notorious tx loop */
 /*
  * FUNCTION PROTOTYPES
  */
 static void	cs_get_default_media(struct cs_softc *);
 static int	cs_get_params(struct cs_softc *);
 static int	cs_get_enaddr(struct cs_softc *);
 static int	cs_reset_chip(struct cs_softc *);
 static void	cs_reset(struct cs_softc *);
 static int	cs_ioctl(struct ifnet *, u_long, void *);
 static void	cs_initChip(struct cs_softc *);
 static void	cs_buffer_event(struct cs_softc *, uint16_t);
 static void	cs_transmit_event(struct cs_softc *, uint16_t);
 static void	cs_receive_event(struct cs_softc *, uint16_t);
 static void	cs_process_receive(struct cs_softc *);
 static void	cs_process_rx_early(struct cs_softc *);
 static void	cs_start_output(struct ifnet *);
 static void	cs_copy_tx_frame(struct cs_softc *, struct mbuf *);
 static void	cs_set_ladr_filt(struct cs_softc *, struct ethercom *);
 static uint16_t cs_hash_index(char *);
 static void	cs_counter_event(struct cs_softc *, uint16_t);
 static int	cs_mediachange(struct ifnet *);
 static void	cs_mediastatus(struct ifnet *, struct ifmediareq *);
 static bool cs_shutdown(device_t, int);
 static int cs_enable(struct cs_softc *);
 static void cs_disable(struct cs_softc *);
 static void cs_stop(struct ifnet *, int);
 static int cs_scan_eeprom(struct cs_softc *);
 static int cs_read_pktpg_from_eeprom(struct cs_softc *, int, uint16_t *);
 /*
  * GLOBAL DECLARATIONS
  */
 /*
  * Xmit-early table.
+ *
  * To get better performance, we tell the chip to start packet
  * transmission before the whole packet is copied to the chip.
  * However, this can fail under load.  When it fails, we back off
  * to a safer setting for a little while.
+ *
  * txcmd is the value of txcmd used to indicate when to start transmission.
  * better is the next 'better' state in the table.
  * better_count is the number of output packets before transition to the
  *   better state.
  * worse is the next 'worse' state in the table.
+ *
  * Transition to the next worse state happens automatically when a
  * transmittion underrun occurs.
  */
 struct cs_xmit_early {
 	uint16_t	txcmd;
 	int		better;
 	int		better_count;
 	int		worse;
 } cs_xmit_early_table[3] = {
 	{ TX_CMD_START_381,	0,	INT_MAX,	1, },
 	{ TX_CMD_START_1021,	0,	50000,		2, },
 	{ TX_CMD_START_ALL,	1,	5000,		2, },
 };
 int cs_default_media[] = {
 	IFM_ETHER | IFM_10_2,
 	IFM_ETHER | IFM_10_5,
 	IFM_ETHER | IFM_10_T,
 	IFM_ETHER | IFM_10_T | IFM_FDX,
 };
 int cs_default_nmedia = __arraycount(cs_default_media);
 int
 cs_attach(struct cs_softc *sc, uint8_t *enaddr, int *media,
 	  int nmedia, int defmedia)
+{
 	struct ifnet *ifp = &sc->sc_ethercom.ec_if;
 	const char *chipname, *medname;
 	uint16_t reg;
 	int i;
 	/* Start out in IO mode */
 	sc->sc_memorymode = FALSE;
 	/* Make sure we're right */
 	for (i = 0; i < 10000; i++) {
 		reg = CS_READ_PACKET_PAGE(sc, PKTPG_EISA_NUM);
 		if (reg == EISA_NUM_CRYSTAL)
 			break;
+	}
 	if (i == 10000) {
 		aprint_error_dev(sc->sc_dev, "wrong id(0x%x)\n", reg);
 		return 1; /* XXX should panic? */
+	}
 	reg = CS_READ_PACKET_PAGE(sc, PKTPG_PRODUCT_ID);
 	sc->sc_prodid = reg & PROD_ID_MASK;
 	sc->sc_prodrev = (reg & PROD_REV_MASK) >> 8;
 	switch (sc->sc_prodid) {
 	case PROD_ID_CS8900:
 		chipname = "CS8900";
 		break;
 	case PROD_ID_CS8920:
 		chipname = "CS8920";
 		break;
 	case PROD_ID_CS8920M:
 		chipname = "CS8920M";
 		break;
 	default:
 		panic("cs_attach: impossible");
+	}
 	/*
 	 * The first thing to do is check that the mbuf cluster size is
 	 * greater than the MTU for an ethernet frame. The code depends on
 	 * this and to port this to a OS where this was not the case would
 	 * not be straightforward.
+	 *
 	 * We need 1 byte spare because our packet read loop can overrun.
 	 * and we may need pad bytes to align ip header.
 	 */
 	if (MCLBYTES < ETHER_MAX_LEN + 1 + ALIGN(sizeof(struct ether_header))
 	    - sizeof(struct ether_header)) {
 		printf("%s: MCLBYTES too small for Ethernet frame\n",
 		    device_xname(sc->sc_dev));
 		return 1;
+	}
 	/* Start out not transmitting */
 	sc->sc_txbusy = FALSE;
 	/* Set up early transmit threshhold */
 	sc->sc_xe_ent = 0;
 	sc->sc_xe_togo = cs_xmit_early_table[sc->sc_xe_ent].better_count;
 	/* Initialize ifnet structure. */
 	strlcpy(ifp->if_xname, device_xname(sc->sc_dev), IFNAMSIZ);
 	ifp->if_softc = sc;
 	ifp->if_start = cs_start_output;
 	ifp->if_init = cs_init;
 	ifp->if_ioctl = cs_ioctl;
 	ifp->if_stop = cs_stop;
 	ifp->if_watchdog = NULL;	/* No watchdog at this stage */
 	ifp->if_flags = IFF_SIMPLEX | IFF_BROADCAST | IFF_MULTICAST;
 	IFQ_SET_READY(&ifp->if_snd);
 	/* Initialize ifmedia structures. */
 	sc->sc_ethercom.ec_ifmedia = &sc->sc_media;
 	ifmedia_init(&sc->sc_media, 0, cs_mediachange, cs_mediastatus);
 	if (media != NULL) {
 		for (i = 0; i < nmedia; i++)
 			ifmedia_add(&sc->sc_media, media[i], 0, NULL);
 		ifmedia_set(&sc->sc_media, defmedia);
 	} else {
 		for (i = 0; i < cs_default_nmedia; i++)
 			ifmedia_add(&sc->sc_media, cs_default_media[i],
 , NULL);
 		cs_get_default_media(sc);
+	}
 	if (sc->sc_cfgflags & CFGFLG_PARSE_EEPROM) {
 		if (cs_scan_eeprom(sc) == CS_ERROR) {
 			/*
 			 * Failed to scan the eeprom, pretend there isn't an
 			 * eeprom
 			 */
 			aprint_error_dev(sc->sc_dev,
 			    "unable to scan EEPROM\n");
 			sc->sc_cfgflags |= CFGFLG_NOT_EEPROM;
+		}
+	}
 	if ((sc->sc_cfgflags & CFGFLG_NOT_EEPROM) == 0) {
 		/* Get parameters from the EEPROM */
 		if (cs_get_params(sc) == CS_ERROR) {
 			aprint_error_dev(sc->sc_dev,
 			    "unable to get settings from EEPROM\n");
 			return 1;
+		}
+	}
 	if (enaddr != NULL)
 		memcpy(sc->sc_enaddr, enaddr, sizeof(sc->sc_enaddr));
 	else if ((sc->sc_cfgflags & CFGFLG_NOT_EEPROM) == 0) {
 		/* Get and store the Ethernet address */
 		if (cs_get_enaddr(sc) == CS_ERROR) {
 			aprint_error_dev(sc->sc_dev,
 			    "unable to read Ethernet address\n");
 			return 1;
+		}
 	} else {
 #if 1
 		int j;
 		uint v;
 		for (j = 0; j < 6; j += 2) {
 			v = CS_READ_PACKET_PAGE(sc, PKTPG_IND_ADDR + j);
 			sc->sc_enaddr[j + 0] = v;
 			sc->sc_enaddr[j + 1] = v >> 8;
+		}
 #else
 		printf("%s: no Ethernet address!\n", device_xname(sc->sc_dev));
 		return 1;
 #endif
+	}
 	switch (IFM_SUBTYPE(sc->sc_media.ifm_cur->ifm_media)) {
 	case IFM_10_2:
 		medname = "BNC";
 		break;
 	case IFM_10_5:
 		medname = "AUI";
 		break;
 	case IFM_10_T:
 		if (sc->sc_media.ifm_cur->ifm_media & IFM_FDX)
 			medname = "UTP <full-duplex>";
 		else
 			medname = "UTP";
 		break;
 	default:
 		panic("cs_attach: impossible");
+	}
 	printf("%s: %s rev. %c, address %s, media %s\n",
 	    device_xname(sc->sc_dev),
 	    chipname, sc->sc_prodrev + 'A', ether_sprintf(sc->sc_enaddr),
 	    medname);
 	if (sc->sc_dma_attach)
 		(*sc->sc_dma_attach)(sc);
 	/* Attach the interface. */
 	if_attach(ifp);
 	if_deferred_start_init(ifp, NULL);
 	ether_ifattach(ifp, sc->sc_enaddr);
 	rnd_attach_source(&sc->rnd_source, device_xname(sc->sc_dev),
 			  RND_TYPE_NET, RND_FLAG_DEFAULT);
 	sc->sc_cfgflags |= CFGFLG_ATTACHED;
 	if (pmf_device_register1(sc->sc_dev, NULL, NULL, cs_shutdown))
 		pmf_class_network_register(sc->sc_dev, ifp);
 	else
 		aprint_error_dev(sc->sc_dev,
 		    "couldn't establish power handler\n");
 	/* Reset the chip */
 	if (cs_reset_chip(sc) == CS_ERROR) {
 		aprint_error_dev(sc->sc_dev, "reset failed\n");
 		cs_detach(sc);
 		return 1;
+	}
 	return 0;
+}
 int
 cs_detach(struct cs_softc *sc)
+{
 	struct ifnet *ifp = &sc->sc_ethercom.ec_if;
 	if (sc->sc_cfgflags & CFGFLG_ATTACHED) {
 		rnd_detach_source(&sc->rnd_source);
 		ether_ifdetach(ifp);
 		if_detach(ifp);
 		sc->sc_cfgflags &= ~CFGFLG_ATTACHED;
+	}
 #if 0
 	/* XXX not necessary */
 	if (sc->sc_cfgflags & CFGFLG_DMA_MODE) {
 		isa_dmamem_unmap(sc->sc_ic, sc->sc_drq, sc->sc_dmabase,
 		    sc->sc_dmasize);
 		isa_dmamem_free(sc->sc_ic, sc->sc_drq, sc->sc_dmaaddr,
 		    sc->sc_dmasize);
 		isa_dmamap_destroy(sc->sc_ic, sc->sc_drq);
 		sc->sc_cfgflags &= ~CFGFLG_DMA_MODE;
+	}
 #endif
 	pmf_device_deregister(sc->sc_dev);
 	return 0;
+}
 bool
 cs_shutdown(device_t self, int howto)
+{
 	struct cs_softc *sc;
 	sc = device_private(self);
 	cs_reset(sc);
 	return true;
+}
 void
 cs_get_default_media(struct cs_softc *sc)
+{
 	uint16_t adp_cfg, xmit_ctl;
 	if (cs_verify_eeprom(sc) == CS_ERROR) {
 		aprint_error_dev(sc->sc_dev,
 		    "cs_get_default_media: EEPROM missing or bad\n");
 		goto fakeit;
+	}
 	if (cs_read_eeprom(sc, EEPROM_ADPTR_CFG, &adp_cfg) == CS_ERROR) {
 		aprint_error_dev(sc->sc_dev,
 		    "unable to read adapter config from EEPROM\n");
 		goto fakeit;
+	}
 	if (cs_read_eeprom(sc, EEPROM_XMIT_CTL, &xmit_ctl) == CS_ERROR) {
 		aprint_error_dev(sc->sc_dev,
 		    "unable to read transmit control from EEPROM\n");
 		goto fakeit;
+	}
 	switch (adp_cfg & ADPTR_CFG_MEDIA) {
 	case ADPTR_CFG_AUI:
 		ifmedia_set(&sc->sc_media, IFM_ETHER | IFM_10_5);
 		break;
 	case ADPTR_CFG_10BASE2:
 		ifmedia_set(&sc->sc_media, IFM_ETHER | IFM_10_2);
 		break;
 	case ADPTR_CFG_10BASET:
 	default:
 		if (xmit_ctl & XMIT_CTL_FDX)
 			ifmedia_set(&sc->sc_media, IFM_ETHER | IFM_10_T
 			    | IFM_FDX);
 		else
 			ifmedia_set(&sc->sc_media, IFM_ETHER | IFM_10_T);
 		break;
+	}
 	return;
  fakeit:
 	aprint_error_dev(sc->sc_dev,
 	    "WARNING: default media setting may be inaccurate\n");
 	/* XXX Arbitrary... */
 	ifmedia_set(&sc->sc_media, IFM_ETHER | IFM_10_T);
+}
 /*
  * cs_scan_eeprom
+ *
  * Attempt to take a complete copy of the eeprom into main memory.
  * this will allow faster parsing of the eeprom data.
+ *
  * Only tested against a 8920M's eeprom, but the data sheet for the
  * 8920A indicates that is uses the same layout.
  */
 int
 cs_scan_eeprom(struct cs_softc *sc)
+{
 	uint16_t result;
 	int	i;
 	int	eeprom_size;
 	uint8_t checksum = 0;
 	if (cs_verify_eeprom(sc) == CS_ERROR) {
 		aprint_error_dev(sc->sc_dev,
 		    "cs_scan_params: EEPROM missing or bad\n");
 		return CS_ERROR;
+	}
 	/*
 	 * Read the 0th word from the eeprom, it will tell us the length
 	 * and if the eeprom is valid
 	 */
 	cs_read_eeprom(sc, 0, &result);
 	/* Check the eeprom signature */
 	if ((result & 0xE000) != 0xA000) {
 		/* Empty eeprom */
 		return CS_ERROR;
+	}
 	/*
 	 * Take the eeprom size (note the read value doesn't include the header
 	 * word)
 	 */
 	eeprom_size = (result & 0xff) + 2;
 	sc->eeprom_data = malloc(eeprom_size, M_DEVBUF, M_WAITOK);
 	if (sc->eeprom_data == NULL) {
 		/* No memory, treat this as if there's no eeprom */
 		return CS_ERROR;
+	}
 	sc->eeprom_size = eeprom_size;
 	/* Read the eeprom into the buffer, also calculate the checksum	 */
 	for (i = 0; i < (eeprom_size >> 1); i++) {
 		cs_read_eeprom(sc, i, &(sc->eeprom_data[i]));
 		checksum += (sc->eeprom_data[i] & 0xff00) >> 8;
 		checksum += (sc->eeprom_data[i] & 0x00ff);
+	}
 	/*
 	 * Validate checksum calculation, the sum of all the bytes should be 0,
 	 * as the high byte of the last word is the 2's complement of the
 	 * sum to that point.
 	 */
 	if (checksum != 0) {
 		aprint_error_dev(sc->sc_dev, "eeprom checksum failure\n");
 		return CS_ERROR;
+	}
 	return CS_OK;
+}
 static int
 cs_read_pktpg_from_eeprom(struct cs_softc *sc, int pktpg, uint16_t *pValue)
+{
 	int x, maxword;
 	/* Check that we have eeprom data */
 	if ((sc->eeprom_data == NULL) || (sc->eeprom_size < 2))
 		return CS_ERROR;
 	/*
 	 * We only want to read the data words, the last word contains the
 	 * checksum
 	 */
 	maxword = (sc->eeprom_size - 2) >> 1;
 	/* Start 1 word in, as the first word is the length and signature */
 	x = 1;
 	while ( x < (maxword)) {
 		uint16_t header;
 		int group_size;
 		int offset;
 		int offset_max;
 		/* Read in the group header word */
 		header = sc->eeprom_data[x];
 		x++;	/* Skip group header */
 		/*
 		 * Size of group in words is in the top 4 bits, note that it
 		 * is one less than the number of words
 		 */
 		group_size = header & 0xF000;
 		/*
 		 * CS8900 Data sheet says this should be 0x01ff,
 		 * but my cs8920 eeprom has higher offsets,
 		 * perhaps the 8920 allows higher offsets, otherwise
 		 * it's writing to places that it shouldn't
 		 */
 		/* Work out the offsets this group covers */
 		offset = header & 0x0FFF;
 		offset_max = offset + (group_size << 1);
 		/* Check if the pkgpg we're after is in this group */
 		if ((offset <= pktpg) && (pktpg <= offset_max)) {
 			/* The pkgpg value we want is in here */
 			int eeprom_location;
 			eeprom_location = ((pktpg - offset) >> 1) ;
 			*pValue = sc->eeprom_data[x + eeprom_location];
 			return CS_OK;
 		} else {
 			/* Skip this group (+ 1 for first entry) */
 			x += group_size + 1;
+		}
+	}
 	/*
 	 * If we've fallen out here then we don't have a value in the EEPROM
 	 * for this pktpg so return an error
 	 */
 	return CS_ERROR;
+}
 int
 cs_get_params(struct cs_softc *sc)
+{
 	uint16_t isaConfig;
 	uint16_t adapterConfig;
 	if (cs_verify_eeprom(sc) == CS_ERROR) {
 		aprint_error_dev(sc->sc_dev,
 		    "cs_get_params: EEPROM missing or bad\n");
 		return CS_ERROR;
+	}
 	if (sc->sc_cfgflags & CFGFLG_PARSE_EEPROM) {
 		/* Get ISA configuration from the EEPROM */
 		if (cs_read_pktpg_from_eeprom(sc, PKTPG_BUS_CTL, &isaConfig)
 		    == CS_ERROR) {
 			/*
 			 * Eeprom doesn't have this value, use data sheet
 			 * default
 			 */
 			isaConfig = 0x0017;
+		}
 		/* Get adapter configuration from the EEPROM */
 		if (cs_read_pktpg_from_eeprom(sc, PKTPG_SELF_CTL,
 		    &adapterConfig) == CS_ERROR) {
 			/*
 			 * Eeprom doesn't have this value, use data sheet
 			 * default
 			 */
 			adapterConfig = 0x0015;
+		}
 		/* Copy the USE_SA flag */
 		if (isaConfig & BUS_CTL_USE_SA)
 			sc->sc_cfgflags |= CFGFLG_USE_SA;
 		/* Copy the IO Channel Ready flag */
 		if (isaConfig & BUS_CTL_IOCHRDY)
 			sc->sc_cfgflags |= CFGFLG_IOCHRDY;
 		/* Copy the DC/DC Polarity flag */
 		if (adapterConfig & SELF_CTL_HCB1)
 			sc->sc_cfgflags |= CFGFLG_DCDC_POL;
 	} else {
 		/* Get ISA configuration from the EEPROM */
 		if (cs_read_eeprom(sc, EEPROM_ISA_CFG, &isaConfig) == CS_ERROR)
 			goto eeprom_bad;
 		/* Get adapter configuration from the EEPROM */
 		if (cs_read_eeprom(sc, EEPROM_ADPTR_CFG, &adapterConfig)
 		    == CS_ERROR)
 			goto eeprom_bad;
 		/* Copy the USE_SA flag */
 		if (isaConfig & ISA_CFG_USE_SA)
 			sc->sc_cfgflags |= CFGFLG_USE_SA;
 		/* Copy the IO Channel Ready flag */
 		if (isaConfig & ISA_CFG_IOCHRDY)
 			sc->sc_cfgflags |= CFGFLG_IOCHRDY;
 		/* Copy the DC/DC Polarity flag */
 		if (adapterConfig & ADPTR_CFG_DCDC_POL)
 			sc->sc_cfgflags |= CFGFLG_DCDC_POL;
+	}
 	return CS_OK;
 eeprom_bad:
 	aprint_error_dev(sc->sc_dev,
 	    "cs_get_params: unable to read from EEPROM\n");
 	return CS_ERROR;
+}
 int
 cs_get_enaddr(struct cs_softc *sc)
+{
 	uint16_t myea[ETHER_ADDR_LEN / sizeof(uint16_t)];
 	int i;
 	if (cs_verify_eeprom(sc) == CS_ERROR) {
 		aprint_error_dev(sc->sc_dev,
 		    "cs_get_enaddr: EEPROM missing or bad\n");
 		return CS_ERROR;
+	}
 	/* Get Ethernet address from the EEPROM */
 	if (sc->sc_cfgflags & CFGFLG_PARSE_EEPROM) {
 		if (cs_read_pktpg_from_eeprom(sc, PKTPG_IND_ADDR, &myea[0])
 				== CS_ERROR)
 			goto eeprom_bad;
 		if (cs_read_pktpg_from_eeprom(sc, PKTPG_IND_ADDR + 2, &myea[1])
 				== CS_ERROR)
 			goto eeprom_bad;
 		if (cs_read_pktpg_from_eeprom(sc, PKTPG_IND_ADDR + 4, &myea[2])
 				== CS_ERROR)
 			goto eeprom_bad;
 	} else {
 		if (cs_read_eeprom(sc, EEPROM_IND_ADDR_H, &myea[0]) == CS_ERROR)
 			goto eeprom_bad;
 		if (cs_read_eeprom(sc, EEPROM_IND_ADDR_M, &myea[1]) == CS_ERROR)
 			goto eeprom_bad;
 		if (cs_read_eeprom(sc, EEPROM_IND_ADDR_L, &myea[2]) == CS_ERROR)
 			goto eeprom_bad;
+	}
 	for (i = 0; i < __arraycount(myea); i++) {
 		sc->sc_enaddr[i * 2 + 0] = myea[i];
 		sc->sc_enaddr[i * 2 + 1] = myea[i] >> 8;
+	}
 	return CS_OK;
  eeprom_bad:
 	aprint_error_dev(sc->sc_dev,
 	    "cs_get_enaddr: unable to read from EEPROM\n");
 	return CS_ERROR;
+}
 int
 cs_reset_chip(struct cs_softc *sc)
+{
 	int intState;
 	int x;
 	/* Disable interrupts at the CPU so reset command is atomic */
 	intState = splnet();
 	/*
 	 * We are now resetting the chip
+	 *
 	 * A spurious interrupt is generated by the chip when it is reset. This
 	 * variable informs the interrupt handler to ignore this interrupt.
 	 */
 	sc->sc_resetting = TRUE;
 	/* Issue a reset command to the chip */
 	CS_WRITE_PACKET_PAGE(sc, PKTPG_SELF_CTL, SELF_CTL_RESET);
 	/* Re-enable interrupts at the CPU */
 	splx(intState);
 	/* The chip is always in IO mode after a reset */
 	sc->sc_memorymode = FALSE;
 	/* If transmission was in progress, it is not now */
 	sc->sc_txbusy = FALSE;
 	/*
 	 * There was a delay(125); here, but it seems uneccesary 125 usec is
 	 * 1/8000 of a second, not 1/8 of a second. the data sheet advises
 	 * 1/10 of a second here, but the SI_BUSY and INIT_DONE loops below
 	 * should be sufficient.
 	 */
 	/* Transition SBHE to switch chip from 8-bit to 16-bit */
 	IO_READ_1(sc, PORT_PKTPG_PTR + 0);
 	IO_READ_1(sc, PORT_PKTPG_PTR + 1);
 	IO_READ_1(sc, PORT_PKTPG_PTR + 0);
 	IO_READ_1(sc, PORT_PKTPG_PTR + 1);
 	/* Wait until the EEPROM is not busy */
 	for (x = 0; x < MAXLOOP; x++) {
 		if (!(CS_READ_PACKET_PAGE(sc, PKTPG_SELF_ST) & SELF_ST_SI_BUSY))
 			break;
+	}
 	if (x == MAXLOOP)
 		return CS_ERROR;
 	/* Wait until initialization is done */
 	for (x = 0; x < MAXLOOP; x++) {
 		if (CS_READ_PACKET_PAGE(sc, PKTPG_SELF_ST) & SELF_ST_INIT_DONE)
 			break;
+	}
 	if (x == MAXLOOP)
 		return CS_ERROR;
 	/* Reset is no longer in progress */
 	sc->sc_resetting = FALSE;
 	return CS_OK;
+}
 int
 cs_verify_eeprom(struct cs_softc *sc)
+{
 	uint16_t self_status;
 	/* Verify that the EEPROM is present and OK */
 	self_status = CS_READ_PACKET_PAGE_IO(sc, PKTPG_SELF_ST);
 	if (((self_status & SELF_ST_EEP_PRES) &&
 	     (self_status & SELF_ST_EEP_OK)) == 0)
 		return CS_ERROR;
 	return CS_OK;
+}
 int
 cs_read_eeprom(struct cs_softc *sc, int offset, uint16_t *pValue)
+{
 	int x;
 	/* Ensure that the EEPROM is not busy */
 	for (x = 0; x < MAXLOOP; x++) {
 		if (!(CS_READ_PACKET_PAGE_IO(sc, PKTPG_SELF_ST) &
 		      SELF_ST_SI_BUSY))
 			break;
+	}
 	if (x == MAXLOOP)
 		return CS_ERROR;
 	/* Issue the command to read the offset within the EEPROM */
 	CS_WRITE_PACKET_PAGE_IO(sc, PKTPG_EEPROM_CMD,
 	    offset | EEPROM_CMD_READ);
 	/* Wait until the command is completed */
 	for (x = 0; x < MAXLOOP; x++) {
 		if (!(CS_READ_PACKET_PAGE_IO(sc, PKTPG_SELF_ST) &
 		      SELF_ST_SI_BUSY))
 			break;
+	}
 	if (x == MAXLOOP)
 		return CS_ERROR;
 	/* Get the EEPROM data from the EEPROM Data register */
 	*pValue = CS_READ_PACKET_PAGE_IO(sc, PKTPG_EEPROM_DATA);
 	return CS_OK;
+}
 void
 cs_initChip(struct cs_softc *sc)
+{
 	uint16_t busCtl;
 	uint16_t selfCtl;
 	uint16_t v;
 	uint16_t isaId;
 	int i;
 	int media = IFM_SUBTYPE(sc->sc_media.ifm_cur->ifm_media);
 	/* Disable reception and transmission of frames */
 	CS_WRITE_PACKET_PAGE(sc, PKTPG_LINE_CTL,
 	    CS_READ_PACKET_PAGE(sc, PKTPG_LINE_CTL) &
 	    ~LINE_CTL_RX_ON & ~LINE_CTL_TX_ON);
 	/* Disable interrupt at the chip */
 	CS_WRITE_PACKET_PAGE(sc, PKTPG_BUS_CTL,
 	    CS_READ_PACKET_PAGE(sc, PKTPG_BUS_CTL) & ~BUS_CTL_INT_ENBL);
 	/* If IOCHRDY is enabled then clear the bit in the busCtl register */
 	busCtl = CS_READ_PACKET_PAGE(sc, PKTPG_BUS_CTL);
 	if (sc->sc_cfgflags & CFGFLG_IOCHRDY) {
 		CS_WRITE_PACKET_PAGE(sc, PKTPG_BUS_CTL,
 		    busCtl & ~BUS_CTL_IOCHRDY);
 	} else {
 		CS_WRITE_PACKET_PAGE(sc, PKTPG_BUS_CTL,
 		    busCtl | BUS_CTL_IOCHRDY);
+	}
 	/* Set the Line Control register to match the media type */
 	if (media == IFM_10_T)
 		CS_WRITE_PACKET_PAGE(sc, PKTPG_LINE_CTL, LINE_CTL_10BASET);
 	else
 		CS_WRITE_PACKET_PAGE(sc, PKTPG_LINE_CTL, LINE_CTL_AUI_ONLY);
 	/*
 	 * Set the BSTATUS/HC1 pin to be used as HC1.  HC1 is used to
 	 * enable the DC/DC converter
 	 */
 	selfCtl = SELF_CTL_HC1E;
 	/* If the media type is 10Base2 */
 	if (media == IFM_10_2) {
 		/* Enable the DC/DC converter if it has a low enable. */
 		if ((sc->sc_cfgflags & CFGFLG_DCDC_POL) == 0)
 			/*
 			 * Set the HCB1 bit, which causes the HC1 pin to go
 			 * low.
 			 */
 			selfCtl |= SELF_CTL_HCB1;
 	} else { /* Media type is 10BaseT or AUI */
 		/* Disable the DC/DC converter if it has a high enable. */
 		if ((sc->sc_cfgflags & CFGFLG_DCDC_POL) != 0) {
 			/*
 			 * Set the HCB1 bit, which causes the HC1 pin to go
 			 * low.
 			 */
 			selfCtl |= SELF_CTL_HCB1;
+		}
+	}
 	CS_WRITE_PACKET_PAGE(sc, PKTPG_SELF_CTL, selfCtl);
 	/* Enable normal link pulse */
 	if (sc->sc_prodid == PROD_ID_CS8920 || sc->sc_prodid == PROD_ID_CS8920M)
 		CS_WRITE_PACKET_PAGE(sc, PKTPG_AUTONEG_CTL, AUTOCTL_NLP_ENABLE);
 	/* Enable full-duplex, if appropriate */
 	if (sc->sc_media.ifm_cur->ifm_media & IFM_FDX)
 		CS_WRITE_PACKET_PAGE(sc, PKTPG_TEST_CTL, TEST_CTL_FDX);
 	/* RX_CTL set in cs_set_ladr_filt(), below */
 	/* Enable all transmission interrupts */
 	CS_WRITE_PACKET_PAGE(sc, PKTPG_TX_CFG, TX_CFG_ALL_IE);
 	/* Accept all receive interrupts */
 	CS_WRITE_PACKET_PAGE(sc, PKTPG_RX_CFG, RX_CFG_ALL_IE);
 	/*
 	 * Configure Operational Modes
+	 *
 	 * I have turned off the BUF_CFG_RX_MISS_IE, to speed things up, this
 	 * is a better way to do it because the card has a counter which can be
 	 * read to update the RX_MISS counter. This saves many interrupts.
+	 *
 	 * I have turned on the tx and rx overflow interrupts to counter using
 	 * the receive miss interrupt. This is a better estimate of errors
 	 * and requires lower system overhead.
 	 */
 	CS_WRITE_PACKET_PAGE(sc, PKTPG_BUF_CFG, BUF_CFG_TX_UNDR_IE |
 			  BUF_CFG_RX_DMA_IE);
 	if (sc->sc_dma_chipinit)
 		(*sc->sc_dma_chipinit)(sc);
 	/* If memory mode is enabled */
 	if (sc->sc_cfgflags & CFGFLG_MEM_MODE) {
 		/* If external logic is present for address decoding */
 		if (CS_READ_PACKET_PAGE(sc, PKTPG_SELF_ST) & SELF_ST_EL_PRES) {
 			/*
 			 * Program the external logic to decode address bits
 			 * SA20-SA23
 			 */
 			CS_WRITE_PACKET_PAGE(sc, PKTPG_EEPROM_CMD,
 			    ((sc->sc_pktpgaddr & 0xffffff) >> 20) |
 			    EEPROM_CMD_ELSEL);
+		}
 		/*
 		 * Write the packet page base physical address to the memory
 		 * base register.
 		 */
 		CS_WRITE_PACKET_PAGE(sc, PKTPG_MEM_BASE + 0,
 		    sc->sc_pktpgaddr & 0xFFFF);
 		CS_WRITE_PACKET_PAGE(sc, PKTPG_MEM_BASE + 2,
 		    sc->sc_pktpgaddr >> 16);
 		busCtl = BUS_CTL_MEM_MODE;
 		/* Tell the chip to read the addresses off the SA pins */
 		if (sc->sc_cfgflags & CFGFLG_USE_SA) {
 			busCtl |= BUS_CTL_USE_SA;
+		}
 		CS_WRITE_PACKET_PAGE(sc, PKTPG_BUS_CTL,
 		    CS_READ_PACKET_PAGE(sc, PKTPG_BUS_CTL) | busCtl);
 		/* We are in memory mode now! */
 		sc->sc_memorymode = TRUE;
 		/*
 		 * Wait here (10ms) for the chip to swap over. this is the
 		 * maximum time that this could take.
 		 */
 		delay(10000);
 		/* Verify that we can read from the chip */
 		isaId = CS_READ_PACKET_PAGE(sc, PKTPG_EISA_NUM);
 		/*
 		 * As a last minute sanity check before actually using mapped
 		 * memory we verify that we can read the isa number from the
 		 * chip in memory mode.
 		 */
 		if (isaId != EISA_NUM_CRYSTAL) {
 			aprint_error_dev(sc->sc_dev,
 			    "failed to enable memory mode\n");
 			sc->sc_memorymode = FALSE;
 		} else {
 			/*
 			 * We are in memory mode so if we aren't using DMA,
 			 * then program the chip to interrupt early.
 			 */
 			if ((sc->sc_cfgflags & CFGFLG_DMA_MODE) == 0) {
 				CS_WRITE_PACKET_PAGE(sc, PKTPG_BUF_CFG,
 				    BUF_CFG_RX_DEST_IE |
 				    BUF_CFG_RX_MISS_OVER_IE |
 				    BUF_CFG_TX_COL_OVER_IE);
+			}
+		}
+	}
 	/* Put Ethernet address into the Individual Address register */
 	for (i = 0; i < 6; i += 2) {
 		v = sc->sc_enaddr[i + 0] | (sc->sc_enaddr[i + 1]) << 8;
 		CS_WRITE_PACKET_PAGE(sc, PKTPG_IND_ADDR + i, v);
+	}
 	if (sc->sc_irq != -1) {
 		/* Set the interrupt level in the chip */
 		if (sc->sc_prodid == PROD_ID_CS8900) {
 			if (sc->sc_irq == 5)
 				CS_WRITE_PACKET_PAGE(sc, PKTPG_INT_NUM, 3);
 			else
 				CS_WRITE_PACKET_PAGE(sc, PKTPG_INT_NUM,
 				    (sc->sc_irq) - 10);
 		} else { /* CS8920 */
 			CS_WRITE_PACKET_PAGE(sc, PKTPG_8920_INT_NUM,
 			    sc->sc_irq);
+		}
+	}
 	/* Write the multicast mask to the address filter register */
 	cs_set_ladr_filt(sc, &sc->sc_ethercom);
 	/* Enable reception and transmission of frames */
 	CS_WRITE_PACKET_PAGE(sc, PKTPG_LINE_CTL,
 	    CS_READ_PACKET_PAGE(sc, PKTPG_LINE_CTL) |
 	    LINE_CTL_RX_ON | LINE_CTL_TX_ON);
 	/* Enable interrupt at the chip */
 	CS_WRITE_PACKET_PAGE(sc, PKTPG_BUS_CTL,
 	    CS_READ_PACKET_PAGE(sc, PKTPG_BUS_CTL) | BUS_CTL_INT_ENBL);
+}
 int
 cs_init(struct ifnet *ifp)
+{
 	int intState;
 	int error = CS_OK;
 	struct cs_softc *sc = ifp->if_softc;
 	if (cs_enable(sc))
 		goto out;
 	cs_stop(ifp, 0);
 	intState = splnet();
 #if 0
 	/* Mark the interface as down */
 	sc->sc_ethercom.ec_if.if_flags &= ~(IFF_UP | IFF_RUNNING);
 #endif
 #ifdef CS_DEBUG
 	/* Enable debugging */
 	sc->sc_ethercom.ec_if.if_flags |= IFF_DEBUG;
 #endif
 	/* Reset the chip */
 	if ((error = cs_reset_chip(sc)) == CS_OK) {
 		/* Initialize the chip */
 		cs_initChip(sc);
 		/* Mark the interface as running */
 		sc->sc_ethercom.ec_if.if_flags |= IFF_RUNNING;
 		sc->sc_ethercom.ec_if.if_flags &= ~IFF_OACTIVE;
 		sc->sc_ethercom.ec_if.if_timer = 0;
 		/* Assume we have carrier until we are told otherwise. */
 		sc->sc_carrier = 1;
 	} else
 		aprint_error_dev(sc->sc_dev, "unable to reset chip\n");
 	splx(intState);
 out:
 	if (error == CS_OK)
 		return 0;
 	return EIO;
+}
 void
 cs_set_ladr_filt(struct cs_softc *sc, struct ethercom *ec)
+{
 	struct ifnet *ifp = &ec->ec_if;
 	struct ether_multi *enm;
 	struct ether_multistep step;
 	uint16_t af[4];
 	uint16_t port, mask, index;
 	/*
 	 * Set up multicast address filter by passing all multicast addresses
 	 * through a crc generator, and then using the high order 6 bits as an
 	 * index into the 64 bit logical address filter.  The high order bit
 	 * selects the word, while the rest of the bits select the bit within
 	 * the word.
 	 */
 	if (ifp->if_flags & IFF_PROMISC) {
 		/* Accept all valid frames. */
 		CS_WRITE_PACKET_PAGE(sc, PKTPG_RX_CTL,
 		    RX_CTL_PROMISC_A | RX_CTL_RX_OK_A |
 		    RX_CTL_IND_A | RX_CTL_BCAST_A | RX_CTL_MCAST_A);
 		ifp->if_flags |= IFF_ALLMULTI;
 		return;
+	}
 	/*
 	 * Accept frames if a. crc valid, b. individual address match c.
 	 * broadcast address,and d. multicast addresses matched in the hash
 	 * filter
 	 */
 	CS_WRITE_PACKET_PAGE(sc, PKTPG_RX_CTL,
 	    RX_CTL_RX_OK_A | RX_CTL_IND_A | RX_CTL_BCAST_A | RX_CTL_MCAST_A);
 	/*
 	 * Start off with all multicast flag clear, set it if we need to
 	 * later, otherwise we will leave it.
 	 */
 	ifp->if_flags &= ~IFF_ALLMULTI;
 	af[0] = af[1] = af[2] = af[3] = 0x0000;
 	/*
 	 * Loop through all the multicast addresses unless we get a range of
 	 * addresses, in which case we will just accept all packets.
 	 * Justification for this is given in the next comment.
 	 */
 	ETHER_LOCK(ec);
 	ETHER_FIRST_MULTI(step, ec, enm);
 	while (enm != NULL) {
 		if (memcmp(enm->enm_addrlo, enm->enm_addrhi,
 		    sizeof enm->enm_addrlo)) {
 			/*
 			 * We must listen to a range of multicast addresses.
 			 * For now, just accept all multicasts, rather than
 			 * trying to set only those filter bits needed to match
 			 * the range.  (At this time, the only use of address
 			 * ranges is for IP multicast routing, for which the
 			 * range is big enough to require all bits set.)
 			 */
 			ifp->if_flags |= IFF_ALLMULTI;
 			af[0] = af[1] = af[2] = af[3] = 0xffff;
 			break;
 		} else {
 			/*
 			 * We have got an individual address so just set that
 			 * bit.
 			 */
 			index = cs_hash_index(enm->enm_addrlo);
 			/* Set the bit the Logical address filter. */
 			port = (uint16_t) (index >> 4);
 			mask = (uint16_t) (1 << (index & 0xf));
 			af[port] |= mask;
 			ETHER_NEXT_MULTI(step, enm);
+		}
+	}
 	ETHER_UNLOCK(ec);
 	/* Now program the chip with the addresses */
 	CS_WRITE_PACKET_PAGE(sc, PKTPG_LOG_ADDR + 0, af[0]);
 	CS_WRITE_PACKET_PAGE(sc, PKTPG_LOG_ADDR + 2, af[1]);
 	CS_WRITE_PACKET_PAGE(sc, PKTPG_LOG_ADDR + 4, af[2]);
 	CS_WRITE_PACKET_PAGE(sc, PKTPG_LOG_ADDR + 6, af[3]);
 	return;
+}
 uint16_t
 cs_hash_index(char *addr)
+{
 	uint32_t crc;
 	uint16_t hash_code;
 	crc = ether_crc32_le(addr, ETHER_ADDR_LEN);
 	hash_code = crc >> 26;
 	return hash_code;
+}
 void
 cs_reset(struct cs_softc *sc)
+{
 	/* Mark the interface as down */
 	sc->sc_ethercom.ec_if.if_flags &= ~IFF_RUNNING;
 	/* Reset the chip */
 	cs_reset_chip(sc);
+}
 int
 cs_ioctl(struct ifnet *ifp, u_long cmd, void *data)
+{
 	struct cs_softc *sc = ifp->if_softc;
 	int state;
 	int result;
 	state = splnet();
 	result = 0;		/* Only set if something goes wrong */
 	switch (cmd) {
 	default:
 		result = ether_ioctl(ifp, cmd, data);
 		if (result == ENETRESET) {
 			if (ifp->if_flags & IFF_RUNNING) {
 				/*
 				 * Multicast list has changed.  Set the
 				 * hardware filter accordingly.
 				 */
 				cs_set_ladr_filt(sc, &sc->sc_ethercom);
+			}
 			result = 0;
+		}
 		break;
+	}
 	splx(state);
 	return result;
+}
 int
 cs_mediachange(struct ifnet *ifp)
+{
 	/*
 	 * Current media is already set up.  Just reset the interface
 	 * to let the new value take hold.
 	 */
 	cs_init(ifp);
 	return 0;
+}
 void
 cs_mediastatus(struct ifnet *ifp, struct ifmediareq *ifmr)
+{
 	struct cs_softc *sc = ifp->if_softc;
 	/* The currently selected media is always the active media. */
 	ifmr->ifm_active = sc->sc_media.ifm_cur->ifm_media;
 	if (ifp->if_flags & IFF_UP) {
 		/* Interface up, status is valid. */
 		ifmr->ifm_status = IFM_AVALID |
 		    (sc->sc_carrier ? IFM_ACTIVE : 0);
+	}
 		else ifmr->ifm_status = 0;
+}
 int
 cs_intr(void *arg)
+{
 	struct cs_softc *sc = arg;
 	uint16_t Event;
 	uint16_t rndEvent;
 /*printf("cs_intr %p\n", sc);*/
 	/* Ignore any interrupts that happen while the chip is being reset */
 	if (sc->sc_resetting) {
 		printf("%s: cs_intr: reset in progress\n",
 		    device_xname(sc->sc_dev));
 		return 1;
+	}
 	/* Read an event from the Interrupt Status Queue */
 	if (sc->sc_memorymode)
 		Event = CS_READ_PACKET_PAGE(sc, PKTPG_ISQ);
 	else
 		Event = CS_READ_PORT(sc, PORT_ISQ);
 	if ((Event & REG_NUM_MASK) == 0 || Event == 0xffff)
 		return 0;	/* Not ours */
 	rndEvent = Event;
 	/* Process all the events in the Interrupt Status Queue */
 	while ((Event & REG_NUM_MASK) != 0 && Event != 0xffff) {
 		/* Dispatch to an event handler based on the register number */
 		switch (Event & REG_NUM_MASK) {
 		case REG_NUM_RX_EVENT:
 			cs_receive_event(sc, Event);
 			break;
 		case REG_NUM_TX_EVENT:
 			cs_transmit_event(sc, Event);
 			break;
 		case REG_NUM_BUF_EVENT:
 			cs_buffer_event(sc, Event);
 			break;
 		case REG_NUM_TX_COL:
 		case REG_NUM_RX_MISS:
 			cs_counter_event(sc, Event);
 			break;
 		default:
 			printf("%s: unknown interrupt event 0x%x\n",
 			    device_xname(sc->sc_dev), Event);
 			break;
+		}
 		/* Read another event from the Interrupt Status Queue */
 		if (sc->sc_memorymode)
 			Event = CS_READ_PACKET_PAGE(sc, PKTPG_ISQ);
 		else
 			Event = CS_READ_PORT(sc, PORT_ISQ);
+	}
 	/* have handled the interrupt */
 	rnd_add_uint32(&sc->rnd_source, rndEvent);
 	return 1;
+}
 void
 cs_counter_event(struct cs_softc *sc, uint16_t cntEvent)
+{
 	struct ifnet *ifp;
 	uint16_t errorCount;
 	ifp = &sc->sc_ethercom.ec_if;
 	switch (cntEvent & REG_NUM_MASK) {
 	case REG_NUM_TX_COL:
 		/* The count should be read before an overflow occurs. */
 		errorCount = CS_READ_PACKET_PAGE(sc, PKTPG_TX_COL);
 		/*
 		 * The tramsit event routine always checks the number of
 		 * collisions for any packet so we don't increment any
 		 * counters here, as they should already have been
 		 * considered.
 		 */
 		break;
 	case REG_NUM_RX_MISS:
 		/* The count should be read before an overflow occurs. */
 		errorCount = CS_READ_PACKET_PAGE(sc, PKTPG_RX_MISS);
 		/*
 		 * Increment the input error count, the first 6bits are the
 		 * register id.
 		 */
-		ifp->if_ierrors += ((errorCount & 0xffC0) >> 6);
+		if_statadd(ifp, if_ierrors, (errorCount & 0xffC0) >> 6);
 		break;
 	default:
 		/* Do nothing */
 		break;
+	}
+}
 void
 cs_buffer_event(struct cs_softc *sc, uint16_t bufEvent)
+{
 	/*
 	 * Multiple events can be in the buffer event register at one time so
 	 * a standard switch statement will not suffice, here every event
 	 * must be checked.
 	 */
 	/*
 	 * If 128 bits have been rxed by the time we get here, the dest event
 	 * will be cleared and 128 event will be set.
 	 */
 	if ((bufEvent & (BUF_EVENT_RX_DEST | BUF_EVENT_RX_128)) != 0)
 		cs_process_rx_early(sc);
 	if (bufEvent & BUF_EVENT_RX_DMA) {
 		/* Process the receive data */
 		if (sc->sc_dma_process_rx)
 			(*sc->sc_dma_process_rx)(sc);
 		else
 			/* Should panic? */
 			aprint_error_dev(sc->sc_dev, "unexpected DMA event\n");
+	}
 	if (bufEvent & BUF_EVENT_TX_UNDR) {
 #if 0
 		/*
 		 * This can happen occasionally, and it's not worth worrying
 		 * about.
 		 */
 		printf("%s: transmit underrun (%d -> %d)\n",
 		    device_xname(sc->sc_dev), sc->sc_xe_ent,
 		    cs_xmit_early_table[sc->sc_xe_ent].worse);
 #endif
 		sc->sc_xe_ent = cs_xmit_early_table[sc->sc_xe_ent].worse;
 		sc->sc_xe_togo =
 		    cs_xmit_early_table[sc->sc_xe_ent].better_count;
 		/* had an underrun, transmit is finished */
 		sc->sc_txbusy = FALSE;
+	}
 	if (bufEvent & BUF_EVENT_SW_INT)
 		printf("%s: software initiated interrupt\n",
 		    device_xname(sc->sc_dev));
+}
 void
 cs_transmit_event(struct cs_softc *sc, uint16_t txEvent)
+{
 	struct ifnet *ifp = &sc->sc_ethercom.ec_if;
 	/* If there were any errors transmitting this frame */
 	if (txEvent & (TX_EVENT_LOSS_CRS | TX_EVENT_SQE_ERR |
 	    TX_EVENT_OUT_WIN | TX_EVENT_JABBER | TX_EVENT_16_COLL)) {
 		/* Increment the output error count */
-		ifp->if_oerrors++;
+		if_statinc(ifp, if_oerrors);
 		/* Note carrier loss. */
 		if (txEvent & TX_EVENT_LOSS_CRS)
 			sc->sc_carrier = 0;
 		/* If debugging is enabled then log error messages */
 		if (ifp->if_flags & IFF_DEBUG) {
 			if (txEvent & TX_EVENT_LOSS_CRS)
 				aprint_error_dev(sc->sc_dev, "lost carrier\n");
 			if (txEvent & TX_EVENT_SQE_ERR)
 				aprint_error_dev(sc->sc_dev, "SQE error\n");
 			if (txEvent & TX_EVENT_OUT_WIN)
 				aprint_error_dev(sc->sc_dev,
 				    "out-of-window collision\n");
 			if (txEvent & TX_EVENT_JABBER)
 				aprint_error_dev(sc->sc_dev, "jabber\n");
 			if (txEvent & TX_EVENT_16_COLL)
 				aprint_error_dev(sc->sc_dev,
 				    "16 collisions\n");
+		}
 	} else {
 		/* Transmission successful, carrier is up. */
 		sc->sc_carrier = 1;
 #ifdef SHARK
 		ledNetActive();
 #endif
+	}
 	/* Add the number of collisions for this frame */
 	net_stat_ref_t nsr = IF_STAT_GETREF(ifp);
 	if (txEvent & TX_EVENT_16_COLL)
-		ifp->if_collisions += 16;
+		if_statadd_ref(nsr, if_collisions, 16);
 	else
-		ifp->if_collisions += ((txEvent & TX_EVENT_COLL_MASK) >> 11);
+		if_statadd_ref(nsr, if_collisions,
 		    ((txEvent & TX_EVENT_COLL_MASK) >> 11));
-	ifp->if_opackets++;
+	if_statinc_ref(nsr, if_opackets);
 	IF_STAT_PUTREF(ifp);
 	/* Transmission is no longer in progress */
 	sc->sc_txbusy = FALSE;
 	/* If there is more to transmit, start the next transmission */
 	if_schedule_deferred_start(ifp);
+}
 void
 cs_print_rx_errors(struct cs_softc *sc, uint16_t rxEvent)
+{
 	if (rxEvent & RX_EVENT_RUNT)
 		aprint_error_dev(sc->sc_dev, "runt\n");
 	if (rxEvent & RX_EVENT_X_DATA)
 		aprint_error_dev(sc->sc_dev, "extra data\n");
 	if (rxEvent & RX_EVENT_CRC_ERR) {
 		if (rxEvent & RX_EVENT_DRIBBLE)
 			aprint_error_dev(sc->sc_dev, "alignment error\n");
 		else
 			aprint_error_dev(sc->sc_dev, "CRC error\n");
 	} else {
 		if (rxEvent & RX_EVENT_DRIBBLE)
 			aprint_error_dev(sc->sc_dev, "dribble bits\n");
+	}
+}
 void
 cs_receive_event(struct cs_softc *sc, uint16_t rxEvent)
+{
 	struct ifnet *ifp = &sc->sc_ethercom.ec_if;
 	/* If the frame was not received OK */
 	if (!(rxEvent & RX_EVENT_RX_OK)) {
 		/* Increment the input error count */
-		ifp->if_ierrors++;
+		if_statinc(ifp, if_ierrors);
 		/* If debugging is enabled then log error messages. */
 		if (ifp->if_flags & IFF_DEBUG) {
 			if (rxEvent != REG_NUM_RX_EVENT) {
 				cs_print_rx_errors(sc, rxEvent);
 				/*
 				 * Must read the length of all received
 				 * frames
 				 */
 				CS_READ_PACKET_PAGE(sc, PKTPG_RX_LENGTH);
 				/* Skip the received frame */
 				CS_WRITE_PACKET_PAGE(sc, PKTPG_RX_CFG,
 					CS_READ_PACKET_PAGE(sc, PKTPG_RX_CFG) |
 						  RX_CFG_SKIP);
 			} else
 				aprint_error_dev(sc->sc_dev, "implied skip\n");
+		}
 	} else {
 		/*
 		 * Process the received frame and pass it up to the upper
 		 * layers.
 		 */
 		cs_process_receive(sc);
+	}
+}
 void
 cs_ether_input(struct cs_softc *sc, struct mbuf *m)
+{
 	struct ifnet *ifp = &sc->sc_ethercom.ec_if;
 	/* Pass the packet up. */
 	if_percpuq_enqueue(ifp->if_percpuq, m);
+}
 void
 cs_process_receive(struct cs_softc *sc)
+{
 	struct ifnet *ifp;
 	struct mbuf *m;
 	int totlen;
 	uint16_t *pBuff, *pBuffLimit;
 	int pad;
 	unsigned int frameOffset = 0;	/* XXX: gcc */
 #ifdef SHARK
 	ledNetActive();
 #endif
 	ifp = &sc->sc_ethercom.ec_if;
 	/* Received a packet; carrier is up. */
 	sc->sc_carrier = 1;
 	if (sc->sc_memorymode) {
 		/* Initialize the frame offset */
 		frameOffset = PKTPG_RX_LENGTH;
 		/* Get the length of the received frame */
 		totlen = CS_READ_PACKET_PAGE(sc, frameOffset);
 		frameOffset += 2;
 	} else {
 		/* Drop status */
 		CS_READ_PORT(sc, PORT_RXTX_DATA);
 		/* Get the length of the received frame */
 		totlen = CS_READ_PORT(sc, PORT_RXTX_DATA);
+	}
 	if (totlen > ETHER_MAX_LEN) {
 		aprint_error_dev(sc->sc_dev, "invalid packet length %d\n",
 		    totlen);
 		/* Skip the received frame */
 		CS_WRITE_PACKET_PAGE(sc, PKTPG_RX_CFG,
 			CS_READ_PACKET_PAGE(sc, PKTPG_RX_CFG) | RX_CFG_SKIP);
 		return;
+	}
 	MGETHDR(m, M_DONTWAIT, MT_DATA);
 	if (m == 0) {
 		aprint_error_dev(sc->sc_dev,
 		    "cs_process_receive: unable to allocate mbuf\n");
-		ifp->if_ierrors++;
+		if_statinc(ifp, if_ierrors);
 		/*
 		 * Couldn't allocate an mbuf so things are not good, may as
 		 * well drop the packet I think.
+		 *
 		 * have already read the length so we should be right to skip
 		 * the packet.
 		 */
 		CS_WRITE_PACKET_PAGE(sc, PKTPG_RX_CFG,
 		    CS_READ_PACKET_PAGE(sc, PKTPG_RX_CFG) | RX_CFG_SKIP);
 		return;
+	}
 	m_set_rcvif(m, ifp);
 	m->m_pkthdr.len = totlen;
 	/* Number of bytes to align ip header on word boundary for ipintr */
 	pad = ALIGN(sizeof(struct ether_header)) - sizeof(struct ether_header);
 	/*
 	 * Alloc mbuf cluster if we need.
 	 * We need 1 byte spare because following packet read loop can overrun.
 	 */
 	if (totlen + pad + 1 > MHLEN) {
 		MCLGET(m, M_DONTWAIT);
 		if ((m->m_flags & M_EXT) == 0) {
 			/* Couldn't allocate an mbuf cluster */
 			aprint_error_dev(sc->sc_dev,
 			    "cs_process_receive: "
 			    "unable to allocate a cluster\n");
 			m_freem(m);
 			/* Skip the received frame */
 			CS_WRITE_PACKET_PAGE(sc, PKTPG_RX_CFG,
 			    CS_READ_PACKET_PAGE(sc, PKTPG_RX_CFG)
 			    | RX_CFG_SKIP);
 			return;
+		}
+	}
 	/* Align ip header on word boundary for ipintr */
 	m->m_data += pad;
 	m->m_len = totlen;
 	pBuff = mtod(m, uint16_t *);
 	/* Now read the data from the chip */
 	if (sc->sc_memorymode) {
 		/* Don't want to go over */
 		pBuffLimit = pBuff + (totlen + 1) / 2;
 		while (pBuff < pBuffLimit) {
 			*pBuff++ = CS_READ_PACKET_PAGE(sc, frameOffset);
 			frameOffset += 2;
+		}
 	} else
 		IO_READ_MULTI_2(sc, PORT_RXTX_DATA, pBuff, (totlen + 1)>>1);
 	cs_ether_input(sc, m);
+}
 void
 cs_process_rx_early(struct cs_softc *sc)
+{
 	struct ifnet *ifp;
 	struct mbuf *m;
 	uint16_t frameCount, oldFrameCount;
 	uint16_t rxEvent;
 	uint16_t *pBuff;
 	int pad;
 	unsigned int frameOffset;
 	ifp = &sc->sc_ethercom.ec_if;
 	/* Initialize the frame offset */
 	frameOffset = PKTPG_RX_FRAME;
 	frameCount = 0;
 	MGETHDR(m, M_DONTWAIT, MT_DATA);
 	if (m == 0) {
 		aprint_error_dev(sc->sc_dev,
 		    "cs_process_rx_early: unable to allocate mbuf\n");
-		ifp->if_ierrors++;
+		if_statinc(ifp, if_ierrors);
 		/*
 		 * Couldn't allocate an mbuf so things are not good, may as
 		 * well drop the packet I think.
+		 *
 		 * have already read the length so we should be right to skip
 		 * the packet.
 		 */
 		CS_WRITE_PACKET_PAGE(sc, PKTPG_RX_CFG,
 		    CS_READ_PACKET_PAGE(sc, PKTPG_RX_CFG) | RX_CFG_SKIP);
 		return;
+	}
 	m_set_rcvif(m, ifp);
 	/*
 	 * Save processing by always using a mbuf cluster, guaranteed to fit
 	 * packet
 	 */
 	MCLGET(m, M_DONTWAIT);
 	if ((m->m_flags & M_EXT) == 0) {
 		/* Couldn't allocate an mbuf cluster */
 		aprint_error_dev(sc->sc_dev,
 		    "cs_process_rx_early: unable to allocate a cluster\n");
 		m_freem(m);
 		/* Skip the frame */
 		CS_WRITE_PACKET_PAGE(sc, PKTPG_RX_CFG,
 		    CS_READ_PACKET_PAGE(sc, PKTPG_RX_CFG) | RX_CFG_SKIP);
 		return;
+	}
 	/* Align ip header on word boundary for ipintr */
 	pad = ALIGN(sizeof(struct ether_header)) - sizeof(struct ether_header);
 	m->m_data += pad;
 	/* Set up the buffer pointer to point to the data area */
 	pBuff = mtod(m, uint16_t *);
 	/*
 	 * Now read the frame byte counter until we have finished reading the
 	 * frame
 	 */
 	oldFrameCount = 0;
 	frameCount = CS_READ_PACKET_PAGE(sc, PKTPG_FRAME_BYTE_COUNT);
 	while ((frameCount != 0) && (frameCount < MCLBYTES)) {
 		for (; oldFrameCount < frameCount; oldFrameCount += 2) {
 			*pBuff++ = CS_READ_PACKET_PAGE(sc, frameOffset);
 			frameOffset += 2;
+		}
 		/* Read the new count from the chip */
 		frameCount = CS_READ_PACKET_PAGE(sc, PKTPG_FRAME_BYTE_COUNT);
+	}
 	/* Update the mbuf counts */
 	m->m_len = oldFrameCount;
 	m->m_pkthdr.len = oldFrameCount;
 	/* Now check the Rx Event register */
 	rxEvent = CS_READ_PACKET_PAGE(sc, PKTPG_RX_EVENT);
 	if ((rxEvent & RX_EVENT_RX_OK) != 0) {
 		/*
 		 * Do an implied skip, it seems to be more reliable than a
 		 * forced skip.
 		 */
 		rxEvent = CS_READ_PACKET_PAGE(sc, PKTPG_RX_STATUS);
 		rxEvent = CS_READ_PACKET_PAGE(sc, PKTPG_RX_LENGTH);
 		/*
 		 * Now read the RX_EVENT register to perform an implied skip.
 		 */
 		rxEvent = CS_READ_PACKET_PAGE(sc, PKTPG_RX_EVENT);
 		cs_ether_input(sc, m);
 	} else {
 		m_freem(m);
-		ifp->if_ierrors++;
+		if_statinc(ifp, if_ierrors);
+	}
+}
 void
 cs_start_output(struct ifnet *ifp)
+{
 	struct cs_softc *sc;
 	struct mbuf *pMbuf;
 	struct mbuf *pMbufChain;
 	uint16_t BusStatus;
 	uint16_t Length;
 	int txLoop = 0;
 	int dropout = 0;
 	sc = ifp->if_softc;
 	/* Check that the interface is up and running */
 	if ((ifp->if_flags & (IFF_RUNNING | IFF_OACTIVE)) != IFF_RUNNING)
 		return;
 	/* Don't interrupt a transmission in progress */
 	if (sc->sc_txbusy)
 		return;
 	/* This loop will only run through once if transmission is successful */
 	/*
 	 * While there are packets to transmit and a transmit is not in
 	 * progress
 	 */
 	while (sc->sc_txbusy == 0 && dropout == 0) {
 		IFQ_DEQUEUE(&ifp->if_snd, pMbufChain);
 		if (pMbufChain == NULL)
 			break;
 		/*
 		 * If BPF is listening on this interface, let it see the packet
 		 * before we commit it to the wire.
 		 */
 		bpf_mtap(ifp, pMbufChain, BPF_D_OUT);
 		/* Find the total length of the data to transmit */
 		Length = 0;
 		for (pMbuf = pMbufChain; pMbuf != NULL; pMbuf = pMbuf->m_next)
 			Length += pMbuf->m_len;
 		do {
 			/*
 			 * Request that the transmit be started after all
 			 * data has been copied
+			 *
 			 * In IO mode must write to the IO port not the packet
 			 * page address
+			 *
 			 * If this is changed to start transmission after a
 			 * small amount of data has been copied you tend to
 			 * get packet missed errors i think because the ISA
 			 * bus is too slow. Or possibly the copy routine is
 			 * not streamlined enough.
 			 */
 			if (sc->sc_memorymode) {
 				CS_WRITE_PACKET_PAGE(sc, PKTPG_TX_CMD,
 				    cs_xmit_early_table[sc->sc_xe_ent].txcmd);
 				CS_WRITE_PACKET_PAGE(sc, PKTPG_TX_LENGTH, Length);
 			} else {
 				CS_WRITE_PORT(sc, PORT_TX_CMD,
 				    cs_xmit_early_table[sc->sc_xe_ent].txcmd);
 				CS_WRITE_PORT(sc, PORT_TX_LENGTH, Length);
+			}
 			/* Adjust early-transmit machinery. */
 			if (--sc->sc_xe_togo == 0) {
 				sc->sc_xe_ent =
 				    cs_xmit_early_table[sc->sc_xe_ent].better;
 				sc->sc_xe_togo =
 			    cs_xmit_early_table[sc->sc_xe_ent].better_count;
+			}
 			/*
 			 * Read the BusStatus register which indicates
 			 * success of the request
 			 */
 			BusStatus = CS_READ_PACKET_PAGE(sc, PKTPG_BUS_ST);
 			/*
 			 * If there was an error in the transmit bid free the
 			 * mbuf and go on. This is presuming that mbuf is
 			 * corrupt.
 			 */
 			if (BusStatus & BUS_ST_TX_BID_ERR) {
 				aprint_error_dev(sc->sc_dev,
 				    "transmit bid error (too big)");
 				/* Discard the bad mbuf chain */
 				m_freem(pMbufChain);
-				sc->sc_ethercom.ec_if.if_oerrors++;
+				if_statinc(&sc->sc_ethercom.ec_if, if_oerrors);
 				/* Loop up to transmit the next chain */
 				txLoop = 0;
 			} else {
 				if (BusStatus & BUS_ST_RDY4TXNOW) {
 					/*
 					 * The chip is ready for transmission
 					 * now
 					 */
 					/*
 					 * Copy the frame to the chip to
 					 * start transmission
 					 */
 					cs_copy_tx_frame(sc, pMbufChain);
 					/* Free the mbuf chain */
 					m_freem(pMbufChain);
 					/* Transmission is now in progress */
 					sc->sc_txbusy = TRUE;
 					txLoop = 0;
 				} else {
 					/*
 					 * If we get here we want to try
 					 * again with the same mbuf, until
 					 * the chip lets us transmit.
 					 */
 					txLoop++;
 					if (txLoop > CS_OUTPUT_LOOP_MAX) {
 						/* Free the mbuf chain */
 						m_freem(pMbufChain);
 						/*
 						 * Transmission is not in
 						 * progress
 						 */
 						sc->sc_txbusy = FALSE;
 						/*
 						 * Increment the output error
 						 * count
 						 */
-						ifp->if_oerrors++;
+						if_statinc(ifp, if_oerrors);
 						/*
 						 * exit the routine and drop
 						 * the packet.
 						 */
 						txLoop = 0;
 						dropout = 1;
+					}
+				}
+			}
 		} while (txLoop);
+	}
+}
 void
 cs_copy_tx_frame(struct cs_softc *sc, struct mbuf *m0)
+{
 	struct mbuf *m;
 	int len, leftover, frameoff;
 	uint16_t dbuf;
 	uint8_t *p;
 #ifdef DIAGNOSTIC
 	uint8_t *lim;
 #endif
 	/* Initialize frame pointer and data port address */
 	frameoff = PKTPG_TX_FRAME;
 	/* Start out with no leftover data */
 	leftover = 0;
 	dbuf = 0;
 	/* Process the chain of mbufs */
 	for (m = m0; m != NULL; m = m->m_next) {
 		/* Process all of the data in a single mbuf. */
 		p = mtod(m, uint8_t *);
 		len = m->m_len;
 #ifdef DIAGNOSTIC
 		lim = p + len;
 #endif
 		while (len > 0) {
 			if (leftover) {
 				/*
 				 * Data left over (from mbuf or realignment).
 				 * Buffer the next byte, and write it and
 				 * the leftover data out.
 				 */
 				dbuf |= *p++ << 8;
 				len--;
 				if (sc->sc_memorymode) {
 					CS_WRITE_PACKET_PAGE(sc, frameoff, dbuf);
 					frameoff += 2;
+				}
 				else {
 					CS_WRITE_PORT(sc, PORT_RXTX_DATA, dbuf);
+				}
 				leftover = 0;
 			} else if ((long) p & 1) {
 				/* Misaligned data.  Buffer the next byte. */
 				dbuf = *p++;
 				len--;
 				leftover = 1;
 			} else {
 				/*
 				 * Aligned data.  This is the case we like.
+				 *
 				 * Write-region out as much as we can, then
 				 * buffer the remaining byte (if any).
 				 */
 				leftover = len & 1;
 				len &= ~1;
 				if (sc->sc_memorymode) {
 					MEM_WRITE_REGION_2(sc, frameoff,
 					    (uint16_t *) p, len >> 1);
 					frameoff += len;
 				} else
 					IO_WRITE_MULTI_2(sc, PORT_RXTX_DATA,
 					    (uint16_t *)p, len >> 1);
 				p += len;
 				if (leftover)
 					dbuf = *p++;
 				len = 0;
+			}
+		}
 		if (len < 0)
 			panic("cs_copy_tx_frame: negative len");
 #ifdef DIAGNOSTIC
 		if (p != lim)
 			panic("cs_copy_tx_frame: p != lim");
 #endif
+	}
 	if (leftover) {
 		if (sc->sc_memorymode)
 			CS_WRITE_PACKET_PAGE(sc, frameoff, dbuf);
 		else
 			CS_WRITE_PORT(sc, PORT_RXTX_DATA, dbuf);
+	}
+}
 static int
 cs_enable(struct cs_softc *sc)
+{
 	if (CS_IS_ENABLED(sc) == 0) {
 		if (sc->sc_enable != NULL) {
 			int error;
 			error = (*sc->sc_enable)(sc);
 			if (error)
 				return error;
+		}
 		sc->sc_cfgflags |= CFGFLG_ENABLED;
+	}
 	return 0;
+}
 static void
 cs_disable(struct cs_softc *sc)
+{
 	if (CS_IS_ENABLED(sc)) {
 		if (sc->sc_disable != NULL)
 			(*sc->sc_disable)(sc);
 		sc->sc_cfgflags &= ~CFGFLG_ENABLED;
+	}
+}
 static void
 cs_stop(struct ifnet *ifp, int disable)
+{
 	struct cs_softc *sc = ifp->if_softc;
 	CS_WRITE_PACKET_PAGE(sc, PKTPG_RX_CFG, 0);
 	CS_WRITE_PACKET_PAGE(sc, PKTPG_TX_CFG, 0);
 	CS_WRITE_PACKET_PAGE(sc, PKTPG_BUF_CFG, 0);
 	CS_WRITE_PACKET_PAGE(sc, PKTPG_BUS_CTL, 0);
 	if (disable)
 		cs_disable(sc);
 	ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE);
+}
 int
 cs_activate(device_t self, enum devact act)
+{
 	struct cs_softc *sc = device_private(self);
 	switch (act) {
 	case DVACT_DEACTIVATE:
 		if_deactivate(&sc->sc_ethercom.ec_if);
 		return 0;
 	default:
 		return EOPNOTSUPP;
+	}
+}

 @@ -1,1229 +1,1229 @@
-/*	$NetBSD: dm9000.c,v 1.21 2019/05/29 10:07:29 msaitoh Exp $	*/
+/*	$NetBSD: dm9000.c,v 1.22 2020/01/29 14:14:55 thorpej Exp $	*/
 /*
  * Copyright (c) 2009 Paul Fleischer
  * All rights reserved.
+ *
  * 1. Redistributions of source code must retain the above copyright
  *    notice, this list of conditions and the following disclaimer.
  * 2. Redistributions in binary form must reproduce the above copyright
  *    notice, this list of conditions and the following disclaimer in the
  *    documentation and/or other materials provided with the distribution.
  * 3. The name of the company nor the name of the author may be used to
  *    endorse or promote products derived from this software without specific
  *    prior written permission.
+ *
  * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED
  * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
  * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
  * IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
  * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
  * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
  * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
  * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
  * SUCH DAMAGE.
  */
 /* based on sys/dev/ic/cs89x0.c */
 /*
  * Copyright (c) 2004 Christopher Gilbert
  * All rights reserved.
+ *
  * 1. Redistributions of source code must retain the above copyright
  *    notice, this list of conditions and the following disclaimer.
  * 2. Redistributions in binary form must reproduce the above copyright
  *    notice, this list of conditions and the following disclaimer in the
  *    documentation and/or other materials provided with the distribution.
  * 3. The name of the company nor the name of the author may be used to
  *    endorse or promote products derived from this software without specific
  *    prior written permission.
+ *
  * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED
  * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
  * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
  * IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
  * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
  * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
  * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
  * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
  * SUCH DAMAGE.
  */
 /*
  * Copyright 1997
  * Digital Equipment Corporation. All rights reserved.
+ *
  * This software is furnished under license and may be used and
  * copied only in accordance with the following terms and conditions.
  * Subject to these conditions, you may download, copy, install,
  * use, modify and distribute this software in source and/or binary
  * form. No title or ownership is transferred hereby.
+ *
  * 1) Any source code used, modified or distributed must reproduce
  *    and retain this copyright notice and list of conditions as
  *    they appear in the source file.
+ *
  * 2) No right is granted to use any trade name, trademark, or logo of
  *    Digital Equipment Corporation. Neither the "Digital Equipment
  *    Corporation" name nor any trademark or logo of Digital Equipment
  *    Corporation may be used to endorse or promote products derived
  *    from this software without the prior written permission of
  *    Digital Equipment Corporation.
+ *
  * 3) This software is provided "AS-IS" and any express or implied
  *    warranties, including but not limited to, any implied warranties
  *    of merchantability, fitness for a particular purpose, or
  *    non-infringement are disclaimed. In no event shall DIGITAL be
  *    liable for any damages whatsoever, and in particular, DIGITAL
  *    shall not be liable for special, indirect, consequential, or
  *    incidental damages or damages for lost profits, loss of
  *    revenue or loss of use, whether such damages arise in contract,
  *    negligence, tort, under statute, in equity, at law or otherwise,
  *    even if advised of the possibility of such damage.
  */
 #include <sys/cdefs.h>
 #include <sys/param.h>
 #include <sys/kernel.h>
 #include <sys/systm.h>
 #include <sys/mbuf.h>
 #include <sys/syslog.h>
 #include <sys/socket.h>
 #include <sys/device.h>
 #include <sys/malloc.h>
 #include <sys/ioctl.h>
 #include <sys/errno.h>
 #include <net/if.h>
 #include <net/if_ether.h>
 #include <net/if_media.h>
 #include <net/bpf.h>
 #ifdef INET
 #include <netinet/in.h>
 #include <netinet/if_inarp.h>
 #endif
 #include <sys/bus.h>
 #include <sys/intr.h>
 #include <dev/ic/dm9000var.h>
 #include <dev/ic/dm9000reg.h>
 #if 1
 #undef DM9000_DEBUG
 #undef DM9000_TX_DEBUG
 #undef DM9000_TX_DATA_DEBUG
 #undef DM9000_RX_DEBUG
 #undef  DM9000_RX_DATA_DEBUG
 #else
 #define DM9000_DEBUG
 #define  DM9000_TX_DEBUG
 #define DM9000_TX_DATA_DEBUG
 #define DM9000_RX_DEBUG
 #define  DM9000_RX_DATA_DEBUG
 #endif
 #ifdef DM9000_DEBUG
 #define DPRINTF(s) do {printf s; } while (/*CONSTCOND*/0)
 #else
 #define DPRINTF(s) do {} while (/*CONSTCOND*/0)
 #endif
 #ifdef DM9000_TX_DEBUG
 #define TX_DPRINTF(s) do {printf s; } while (/*CONSTCOND*/0)
 #else
 #define TX_DPRINTF(s) do {} while (/*CONSTCOND*/0)
 #endif
 #ifdef DM9000_RX_DEBUG
 #define RX_DPRINTF(s) do {printf s; } while (/*CONSTCOND*/0)
 #else
 #define RX_DPRINTF(s) do {} while (/*CONSTCOND*/0)
 #endif
 #ifdef DM9000_RX_DATA_DEBUG
 #define RX_DATA_DPRINTF(s) do {printf s; } while (/*CONSTCOND*/0)
 #else
 #define RX_DATA_DPRINTF(s) do {} while (/*CONSTCOND*/0)
 #endif
 #ifdef DM9000_TX_DATA_DEBUG
 #define TX_DATA_DPRINTF(s) do {printf s; } while (/*CONSTCOND*/0)
 #else
 #define TX_DATA_DPRINTF(s) do {} while (/*CONSTCOND*/0)
 #endif
 /*** Internal PHY functions ***/
 uint16_t dme_phy_read(struct dme_softc *, int );
 void	dme_phy_write(struct dme_softc *, int, uint16_t);
 void	dme_phy_init(struct dme_softc *);
 void	dme_phy_reset(struct dme_softc *);
 void	dme_phy_update_media(struct dme_softc *);
 void	dme_phy_check_link(void *);
 /*** Methods registered in struct ifnet ***/
 void	dme_start_output(struct ifnet *);
 int	dme_init(struct ifnet *);
 int	dme_ioctl(struct ifnet *, u_long, void *);
 void	dme_stop(struct ifnet *, int);
 int	dme_mediachange(struct ifnet *);
 void	dme_mediastatus(struct ifnet *, struct ifmediareq *);
 /*** Internal methods ***/
 /* Prepare data to be transmitted (i.e. dequeue and load it into the DM9000) */
 void	dme_prepare(struct dme_softc *, struct ifnet *);
 /* Transmit prepared data */
 void	dme_transmit(struct dme_softc *);
 /* Receive data */
 void	dme_receive(struct dme_softc *, struct ifnet *);
 /* Software Initialize/Reset of the DM9000 */
 void	dme_reset(struct dme_softc *);
 /* Configure multicast filter */
 void	dme_set_addr_filter(struct dme_softc *);
 /* Set media */
 int	dme_set_media(struct dme_softc *, int );
 /* Read/write packet data from/to DM9000 IC in various transfer sizes */
 int	dme_pkt_read_2(struct dme_softc *, struct ifnet *, struct mbuf **);
 int	dme_pkt_write_2(struct dme_softc *, struct mbuf *);
 int	dme_pkt_read_1(struct dme_softc *, struct ifnet *, struct mbuf **);
 int	dme_pkt_write_1(struct dme_softc *, struct mbuf *);
 /* TODO: Implement 32 bit read/write functions */
 uint16_t
 dme_phy_read(struct dme_softc *sc, int reg)
+{
 	uint16_t val;
 	/* Select Register to read*/
 	dme_write(sc, DM9000_EPAR, DM9000_EPAR_INT_PHY +
 	    (reg & DM9000_EPAR_EROA_MASK));
 	/* Select read operation (DM9000_EPCR_ERPRR) from the PHY */
 	dme_write(sc, DM9000_EPCR, DM9000_EPCR_ERPRR + DM9000_EPCR_EPOS_PHY);
 	/* Wait until access to PHY has completed */
 	while (dme_read(sc, DM9000_EPCR) & DM9000_EPCR_ERRE)
+		;
 	/* Reset ERPRR-bit */
 	dme_write(sc, DM9000_EPCR, DM9000_EPCR_EPOS_PHY);
 	val = dme_read(sc, DM9000_EPDRL);
 	val += dme_read(sc, DM9000_EPDRH) << 8;
 	return val;
+}
 void
 dme_phy_write(struct dme_softc *sc, int reg, uint16_t value)
+{
 	/* Select Register to write*/
 	dme_write(sc, DM9000_EPAR, DM9000_EPAR_INT_PHY +
 	    (reg & DM9000_EPAR_EROA_MASK));
 	/* Write data to the two data registers */
 	dme_write(sc, DM9000_EPDRL, value & 0xFF);
 	dme_write(sc, DM9000_EPDRH, (value >> 8) & 0xFF);
 	/* Select write operation (DM9000_EPCR_ERPRW) from the PHY */
 	dme_write(sc, DM9000_EPCR, DM9000_EPCR_ERPRW + DM9000_EPCR_EPOS_PHY);
 	/* Wait until access to PHY has completed */
 	while (dme_read(sc, DM9000_EPCR) & DM9000_EPCR_ERRE)
+		;
 	/* Reset ERPRR-bit */
 	dme_write(sc, DM9000_EPCR, DM9000_EPCR_EPOS_PHY);
+}
 void
 dme_phy_init(struct dme_softc *sc)
+{
 	u_int ifm_media = sc->sc_media.ifm_media;
 	uint32_t bmcr, anar;
 	bmcr = dme_phy_read(sc, DM9000_PHY_BMCR);
 	anar = dme_phy_read(sc, DM9000_PHY_ANAR);
 	anar = anar & ~DM9000_PHY_ANAR_10_HDX
 		& ~DM9000_PHY_ANAR_10_FDX
 		& ~DM9000_PHY_ANAR_TX_HDX
 		& ~DM9000_PHY_ANAR_TX_FDX;
 	switch (IFM_SUBTYPE(ifm_media)) {
 	case IFM_AUTO:
 		bmcr |= DM9000_PHY_BMCR_AUTO_NEG_EN;
 		anar |= DM9000_PHY_ANAR_10_HDX |
 			DM9000_PHY_ANAR_10_FDX |
 			DM9000_PHY_ANAR_TX_HDX |
 			DM9000_PHY_ANAR_TX_FDX;
 		break;
 	case IFM_10_T:
 		//bmcr &= ~DM9000_PHY_BMCR_AUTO_NEG_EN;
 		bmcr &= ~DM9000_PHY_BMCR_SPEED_SELECT;
 		if (ifm_media & IFM_FDX)
 			anar |= DM9000_PHY_ANAR_10_FDX;
 		else
 			anar |= DM9000_PHY_ANAR_10_HDX;
 		break;
 	case IFM_100_TX:
 		//bmcr &= ~DM9000_PHY_BMCR_AUTO_NEG_EN;
 		bmcr |= DM9000_PHY_BMCR_SPEED_SELECT;
 		if (ifm_media & IFM_FDX)
 			anar |= DM9000_PHY_ANAR_TX_FDX;
 		else
 			anar |= DM9000_PHY_ANAR_TX_HDX;
 		break;
+	}
 	if (ifm_media & IFM_FDX)
 		bmcr |= DM9000_PHY_BMCR_DUPLEX_MODE;
 	else
 		bmcr &= ~DM9000_PHY_BMCR_DUPLEX_MODE;
 	dme_phy_write(sc, DM9000_PHY_BMCR, bmcr);
 	dme_phy_write(sc, DM9000_PHY_ANAR, anar);
+}
 void
 dme_phy_reset(struct dme_softc *sc)
+{
 	uint32_t reg;
 	/* PHY Reset */
 	dme_phy_write(sc, DM9000_PHY_BMCR, DM9000_PHY_BMCR_RESET);
 	reg = dme_read(sc, DM9000_GPCR);
 	dme_write(sc, DM9000_GPCR, reg & ~DM9000_GPCR_GPIO0_OUT);
 	reg = dme_read(sc, DM9000_GPR);
 	dme_write(sc, DM9000_GPR, reg | DM9000_GPR_PHY_PWROFF);
 	dme_phy_init(sc);
 	reg = dme_read(sc, DM9000_GPR);
 	dme_write(sc, DM9000_GPR, reg & ~DM9000_GPR_PHY_PWROFF);
 	reg = dme_read(sc, DM9000_GPCR);
 	dme_write(sc, DM9000_GPCR, reg | DM9000_GPCR_GPIO0_OUT);
 	dme_phy_update_media(sc);
+}
 void
 dme_phy_update_media(struct dme_softc *sc)
+{
 	u_int ifm_media = sc->sc_media.ifm_media;
 	uint32_t reg;
 	if (IFM_SUBTYPE(ifm_media) == IFM_AUTO) {
 		/* If auto-negotiation is used, ensures that it is completed
 		 before trying to extract any media information. */
 		reg = dme_phy_read(sc, DM9000_PHY_BMSR);
 		if ((reg & DM9000_PHY_BMSR_AUTO_NEG_AB) == 0) {
 			/* Auto-negotation not possible, therefore there is no
 			   reason to try obtain any media information. */
 			return;
+		}
 		/* Then loop until the negotiation is completed. */
 		while ((reg & DM9000_PHY_BMSR_AUTO_NEG_COM) == 0) {
 			/* TODO: Bail out after a finite number of attempts
 			 in case something goes wrong. */
 			preempt();
 			reg = dme_phy_read(sc, DM9000_PHY_BMSR);
+		}
+	}
 	sc->sc_media_active = IFM_ETHER;
 	reg = dme_phy_read(sc, DM9000_PHY_BMCR);
 	if (reg & DM9000_PHY_BMCR_SPEED_SELECT)
 		sc->sc_media_active |= IFM_100_TX;
 	else
 		sc->sc_media_active |= IFM_10_T;
 	if (reg & DM9000_PHY_BMCR_DUPLEX_MODE)
 		sc->sc_media_active |= IFM_FDX;
+}
 void
 dme_phy_check_link(void *arg)
+{
 	struct dme_softc *sc = arg;
 	uint32_t reg;
 	int s;
 	s = splnet();
 	reg = dme_read(sc, DM9000_NSR) & DM9000_NSR_LINKST;
 	if (reg)
 		reg = IFM_ETHER | IFM_AVALID | IFM_ACTIVE;
 	else {
 		reg = IFM_ETHER | IFM_AVALID;
 		sc->sc_media_active = IFM_NONE;
+	}
 	if ((sc->sc_media_status != reg) && (reg & IFM_ACTIVE))
 		dme_phy_reset(sc);
 	sc->sc_media_status = reg;
 	callout_schedule(&sc->sc_link_callout, mstohz(2000));
 	splx(s);
+}
 int
 dme_set_media(struct dme_softc *sc, int media)
+{
 	int s;
 	s = splnet();
 	sc->sc_media.ifm_media = media;
 	dme_phy_reset(sc);
 	splx(s);
 	return 0;
+}
 int
 dme_attach(struct dme_softc *sc, const uint8_t *enaddr)
+{
 	struct ifnet	*ifp = &sc->sc_ethercom.ec_if;
 	uint8_t		b[2];
 	uint16_t	io_mode;
 	dme_read_c(sc, DM9000_VID0, b, 2);
 #if BYTE_ORDER == BIG_ENDIAN
 	sc->sc_vendor_id = (b[0] << 8) | b[1];
 #else
 	sc->sc_vendor_id = b[0] | (b[1] << 8);
 #endif
 	dme_read_c(sc, DM9000_PID0, b, 2);
 #if BYTE_ORDER == BIG_ENDIAN
 	sc->sc_product_id = (b[0] << 8) | b[1];
 #else
 	sc->sc_product_id = b[0] | (b[1] << 8);
 #endif
 	/* TODO: Check the vendor ID as well */
 	if (sc->sc_product_id != 0x9000) {
 		panic("dme_attach: product id mismatch (0x%hx != 0x9000)",
 		    sc->sc_product_id);
+	}
 	/* Initialize ifnet structure. */
 	strlcpy(ifp->if_xname, device_xname(sc->sc_dev), IFNAMSIZ);
 	ifp->if_softc = sc;
 	ifp->if_start = dme_start_output;
 	ifp->if_init = dme_init;
 	ifp->if_ioctl = dme_ioctl;
 	ifp->if_stop = dme_stop;
 	ifp->if_watchdog = NULL;	/* no watchdog at this stage */
 	ifp->if_flags = IFF_SIMPLEX | IFF_BROADCAST | IFF_MULTICAST;
 	IFQ_SET_READY(&ifp->if_snd);
 	/* Initialize ifmedia structures. */
 	sc->sc_ethercom.ec_ifmedia = &sc->sc_media;
 	ifmedia_init(&sc->sc_media, 0, dme_mediachange, dme_mediastatus);
 	ifmedia_add(&sc->sc_media, IFM_ETHER | IFM_AUTO, 0, NULL);
 	ifmedia_add(&sc->sc_media, IFM_ETHER | IFM_10_T | IFM_FDX, 0, NULL);
 	ifmedia_add(&sc->sc_media, IFM_ETHER | IFM_10_T, 0, NULL);
 	ifmedia_add(&sc->sc_media, IFM_ETHER | IFM_100_TX | IFM_FDX, 0, NULL);
 	ifmedia_add(&sc->sc_media, IFM_ETHER | IFM_100_TX, 0, NULL);
 	ifmedia_set(&sc->sc_media, IFM_ETHER | IFM_AUTO);
 	if (enaddr != NULL)
 		memcpy(sc->sc_enaddr, enaddr, sizeof(sc->sc_enaddr));
 	/* TODO: Support an EEPROM attached to the DM9000 chip */
 	callout_init(&sc->sc_link_callout, 0);
 	callout_setfunc(&sc->sc_link_callout, dme_phy_check_link, sc);
 	sc->sc_media_status = 0;
 	/* Configure DM9000 with the MAC address */
 	dme_write_c(sc, DM9000_PAB0, sc->sc_enaddr, 6);
 #ifdef DM9000_DEBUG
+	{
 		uint8_t macAddr[6];
 		dme_read_c(sc, DM9000_PAB0, macAddr, 6);
 		printf("DM9000 configured with MAC address: ");
 		for (int i = 0; i < 6; i++)
 			printf("%02X:", macAddr[i]);
 		printf("\n");
+	}
 #endif
 	if_attach(ifp);
 	ether_ifattach(ifp, sc->sc_enaddr);
 #ifdef DM9000_DEBUG
+	{
 		uint8_t network_state;
 		network_state = dme_read(sc, DM9000_NSR);
 		printf("DM9000 Link status: ");
 		if (network_state & DM9000_NSR_LINKST) {
 			if (network_state & DM9000_NSR_SPEED)
 				printf("10Mbps");
 			else
 				printf("100Mbps");
 		} else
 			printf("Down");
 		printf("\n");
+	}
 #endif
 	io_mode = (dme_read(sc, DM9000_ISR) &
 	    DM9000_IOMODE_MASK) >> DM9000_IOMODE_SHIFT;
 	DPRINTF(("DM9000 Operation Mode: "));
 	switch (io_mode) {
 	case DM9000_MODE_16BIT:
 		DPRINTF(("16-bit mode"));
 		sc->sc_data_width = 2;
 		sc->sc_pkt_write = dme_pkt_write_2;
 		sc->sc_pkt_read = dme_pkt_read_2;
 		break;
 	case DM9000_MODE_32BIT:
 		DPRINTF(("32-bit mode"));
 		sc->sc_data_width = 4;
 		panic("32bit mode is unsupported\n");
 		break;
 	case DM9000_MODE_8BIT:
 		DPRINTF(("8-bit mode"));
 		sc->sc_data_width = 1;
 		sc->sc_pkt_write = dme_pkt_write_1;
 		sc->sc_pkt_read = dme_pkt_read_1;
 		break;
 	default:
 		DPRINTF(("Invalid mode"));
 		break;
+	}
 	DPRINTF(("\n"));
 	callout_schedule(&sc->sc_link_callout, mstohz(2000));
 	return 0;
+}
 int dme_intr(void *arg)
+{
 	struct dme_softc *sc = arg;
 	struct ifnet *ifp = &sc->sc_ethercom.ec_if;
 	uint8_t status;
 	DPRINTF(("dme_intr: Begin\n"));
 	/* Disable interrupts */
 	dme_write(sc, DM9000_IMR, DM9000_IMR_PAR );
 	status = dme_read(sc, DM9000_ISR);
 	dme_write(sc, DM9000_ISR, status);
 	if (status & DM9000_ISR_PRS) {
 		if (ifp->if_flags & IFF_RUNNING )
 			dme_receive(sc, ifp);
+	}
 	if (status & DM9000_ISR_PTS) {
 		uint8_t nsr;
 		uint8_t tx_status = 0x01; /* Initialize to an error value */
 		/* A packet has been transmitted */
 		sc->txbusy = 0;
 		nsr = dme_read(sc, DM9000_NSR);
 		if (nsr & DM9000_NSR_TX1END) {
 			tx_status = dme_read(sc, DM9000_TSR1);
 			TX_DPRINTF(("dme_intr: Sent using channel 0\n"));
 		} else if (nsr & DM9000_NSR_TX2END) {
 			tx_status = dme_read(sc, DM9000_TSR2);
 			TX_DPRINTF(("dme_intr: Sent using channel 1\n"));
+		}
 		if (tx_status == 0x0) {
 			/* Frame successfully sent */
-			ifp->if_opackets++;
+			if_statinc(ifp, if_opackets);
 		} else {
-			ifp->if_oerrors++;
+			if_statinc(ifp, if_oerrors);
+		}
 		/* If we have nothing ready to transmit, prepare something */
 		if (!sc->txready)
 			dme_prepare(sc, ifp);
 		if (sc->txready)
 			dme_transmit(sc);
 		/* Prepare the next frame */
 		dme_prepare(sc, ifp);
+	}
 #ifdef notyet
 	if (status & DM9000_ISR_LNKCHNG) {
+	}
 #endif
 	/* Enable interrupts again */
 	dme_write(sc, DM9000_IMR,
 	    DM9000_IMR_PAR | DM9000_IMR_PRM | DM9000_IMR_PTM);
 	DPRINTF(("dme_intr: End\n"));
 	return 1;
+}
 void
 dme_start_output(struct ifnet *ifp)
+{
 	struct dme_softc *sc;
 	sc = ifp->if_softc;
 	DPRINTF(("dme_start_output: Begin\n"));
 	if ((ifp->if_flags & (IFF_RUNNING | IFF_OACTIVE)) != IFF_RUNNING) {
 		printf("No output\n");
 		return;
+	}
 	if (sc->txbusy && sc->txready)
 		panic("DM9000: Internal error, trying to send without"
 		    " any empty queue\n");
 	dme_prepare(sc, ifp);
 	if (sc->txbusy == 0) {
 		/* We are ready to transmit right away */
 		dme_transmit(sc);
 		dme_prepare(sc, ifp); /* Prepare next one */
 	} else {
 		/* We need to wait until the current packet has
 		 * been transmitted.
 		 */
 		ifp->if_flags |= IFF_OACTIVE;
+	}
 	DPRINTF(("dme_start_output: End\n"));
+}
 void
 dme_prepare(struct dme_softc *sc, struct ifnet *ifp)
+{
 	struct mbuf *bufChain;
 	uint16_t length;
 	TX_DPRINTF(("dme_prepare: Entering\n"));
 	if (sc->txready)
 		panic("dme_prepare: Someone called us with txready set\n");
 	IFQ_DEQUEUE(&ifp->if_snd, bufChain);
 	if (bufChain == NULL) {
 		TX_DPRINTF(("dme_prepare: Nothing to transmit\n"));
 		ifp->if_flags &= ~IFF_OACTIVE; /* Clear OACTIVE bit */
 		return; /* Nothing to transmit */
+	}
 	/* Element has now been removed from the queue, so we better send it */
 	bpf_mtap(ifp, bufChain, BPF_D_OUT);
 	/* Setup the DM9000 to accept the writes, and then write each buf in
 	   the chain. */
 	TX_DATA_DPRINTF(("dme_prepare: Writing data: "));
 	bus_space_write_1(sc->sc_iot, sc->sc_ioh, sc->dme_io, DM9000_MWCMD);
 	length = sc->sc_pkt_write(sc, bufChain);
 	TX_DATA_DPRINTF(("\n"));
 	if (length % sc->sc_data_width != 0)
 		panic("dme_prepare: length is not compatible with IO_MODE");
 	sc->txready_length = length;
 	sc->txready = 1;
 	TX_DPRINTF(("dme_prepare: txbusy: %d\ndme_prepare: "
 		"txready: %d, txready_length: %d\n",
 		sc->txbusy, sc->txready, sc->txready_length));
 	m_freem(bufChain);
 	TX_DPRINTF(("dme_prepare: Leaving\n"));
+}
 int
 dme_init(struct ifnet *ifp)
+{
 	int s;
 	struct dme_softc *sc = ifp->if_softc;
 	dme_stop(ifp, 0);
 	s = splnet();
 	dme_reset(sc);
 	sc->sc_ethercom.ec_if.if_flags |= IFF_RUNNING;
 	sc->sc_ethercom.ec_if.if_flags &= ~IFF_OACTIVE;
 	sc->sc_ethercom.ec_if.if_timer = 0;
 	splx(s);
 	return 0;
+}
 int
 dme_ioctl(struct ifnet *ifp, u_long cmd, void *data)
+{
 	struct dme_softc *sc = ifp->if_softc;
 	int s, error = 0;
 	s = splnet();
 	switch (cmd) {
 	default:
 		error = ether_ioctl(ifp, cmd, data);
 		if (error == ENETRESET) {
 			if (ifp->if_flags && IFF_RUNNING) {
 				/* Address list has changed, reconfigure
 				   filter */
 				dme_set_addr_filter(sc);
+			}
 			error = 0;
+		}
 		break;
+	}
 	splx(s);
 	return error;
+}
 void
 dme_stop(struct ifnet *ifp, int disable)
+{
 	struct dme_softc *sc = ifp->if_softc;
 	/* Not quite sure what to do when called with disable == 0 */
 	if (disable) {
 		/* Disable RX */
 		dme_write(sc, DM9000_RCR, 0x0);
+	}
 	ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE);
 	ifp->if_timer = 0;
+}
 int
 dme_mediachange(struct ifnet *ifp)
+{
 	struct dme_softc *sc = ifp->if_softc;
 	return dme_set_media(sc, sc->sc_media.ifm_cur->ifm_media);
+}
 void
 dme_mediastatus(struct ifnet *ifp, struct ifmediareq *ifmr)
+{
 	struct dme_softc *sc = ifp->if_softc;
 	ifmr->ifm_active = sc->sc_media_active;
 	ifmr->ifm_status = sc->sc_media_status;
+}
 void
 dme_transmit(struct dme_softc *sc)
+{
 	TX_DPRINTF(("dme_transmit: PRE: txready: %d, txbusy: %d\n",
 		sc->txready, sc->txbusy));
 	dme_write(sc, DM9000_TXPLL, sc->txready_length & 0xff);
 	dme_write(sc, DM9000_TXPLH, (sc->txready_length >> 8) & 0xff );
 	/* Request to send the packet */
 	dme_read(sc, DM9000_ISR);
 	dme_write(sc, DM9000_TCR, DM9000_TCR_TXREQ);
 	sc->txready = 0;
 	sc->txbusy = 1;
 	sc->txready_length = 0;
+}
 void
 dme_receive(struct dme_softc *sc, struct ifnet *ifp)
+{
 	uint8_t ready = 0x01;
 	DPRINTF(("inside dme_receive\n"));
 	while (ready == 0x01) {
 		/* Packet received, retrieve it */
 		/* Read without address increment to get the ready byte without
 		   moving past it. */
 		bus_space_write_1(sc->sc_iot, sc->sc_ioh,
 		    sc->dme_io, DM9000_MRCMDX);
 		/* Dummy ready */
 		ready = bus_space_read_1(sc->sc_iot, sc->sc_ioh, sc->dme_data);
 		ready = bus_space_read_1(sc->sc_iot, sc->sc_ioh, sc->dme_data);
 		ready &= 0x03;	/* we only want bits 1:0 */
 		if (ready == 0x01) {
 			uint8_t		rx_status;
 			struct mbuf	*m;
 			/* Read with address increment. */
 			bus_space_write_1(sc->sc_iot, sc->sc_ioh,
 					  sc->dme_io, DM9000_MRCMD);
 			rx_status = sc->sc_pkt_read(sc, ifp, &m);
 			if (m == NULL) {
 				/* failed to allocate a receive buffer */
-				ifp->if_ierrors++;
+				if_statinc(ifp, if_ierrors);
 				RX_DPRINTF(("dme_receive: "
 					"Error allocating buffer\n"));
 			} else if (rx_status & (DM9000_RSR_CE | DM9000_RSR_PLE)) {
 				/* Error while receiving the packet,
 				 * discard it and keep track of counters
 				 */
-				ifp->if_ierrors++;
+				if_statinc(ifp, if_ierrors);
 				RX_DPRINTF(("dme_receive: "
 					"Error reciving packet\n"));
 			} else if (rx_status & DM9000_RSR_LCS) {
-				ifp->if_collisions++;
+				if_statinc(ifp, if_collisions);
 			} else {
 				if_percpuq_enqueue(ifp->if_percpuq, m);
+			}
 		} else if (ready != 0x00) {
 			/* Should this be logged somehow? */
 			printf("%s: Resetting chip\n",
 			       device_xname(sc->sc_dev));
 			dme_reset(sc);
+		}
+	}
+}
 void
 dme_reset(struct dme_softc *sc)
+{
 	uint8_t var;
 	/* We only re-initialized the PHY in this function the first time it is
 	   called. */
 	if (!sc->sc_phy_initialized) {
 		/* PHY Reset */
 		dme_phy_write(sc, DM9000_PHY_BMCR, DM9000_PHY_BMCR_RESET);
 		/* PHY Power Down */
 		var = dme_read(sc, DM9000_GPR);
 		dme_write(sc, DM9000_GPR, var | DM9000_GPR_PHY_PWROFF);
+	}
 	/* Reset the DM9000 twice, as described in section 2 of the Programming
 	   Guide.
 	   The PHY is initialized and enabled between those two resets.
 	 */
 	/* Software Reset*/
 	dme_write(sc, DM9000_NCR,
 	    DM9000_NCR_RST | DM9000_NCR_LBK_MAC_INTERNAL);
 	delay(20);
 	dme_write(sc, DM9000_NCR, 0x0);
 	if (!sc->sc_phy_initialized) {
 		/* PHY Initialization */
 		dme_phy_init(sc);
 		/* PHY Enable */
 		var = dme_read(sc, DM9000_GPR);
 		dme_write(sc, DM9000_GPR, var & ~DM9000_GPR_PHY_PWROFF);
 		var = dme_read(sc, DM9000_GPCR);
 		dme_write(sc, DM9000_GPCR, var | DM9000_GPCR_GPIO0_OUT);
 		dme_write(sc, DM9000_NCR,
 		    DM9000_NCR_RST | DM9000_NCR_LBK_MAC_INTERNAL);
 		delay(20);
 		dme_write(sc, DM9000_NCR, 0x0);
+	}
 	/* Select internal PHY, no wakeup event, no collosion mode,
 	 * normal loopback mode.
 	 */
 	dme_write(sc, DM9000_NCR, DM9000_NCR_LBK_NORMAL );
 	/* Will clear TX1END, TX2END, and WAKEST fields by reading DM9000_NSR*/
 	dme_read(sc, DM9000_NSR);
 	/* Enable wraparound of read/write pointer, packet received latch,
 	 * and packet transmitted latch.
 	 */
 	dme_write(sc, DM9000_IMR,
 	    DM9000_IMR_PAR | DM9000_IMR_PRM | DM9000_IMR_PTM);
 	/* Setup multicast address filter, and enable RX. */
 	dme_set_addr_filter(sc);
 	/* Obtain media information from PHY */
 	dme_phy_update_media(sc);
 	sc->txbusy = 0;
 	sc->txready = 0;
 	sc->sc_phy_initialized = 1;
+}
 void
 dme_set_addr_filter(struct dme_softc *sc)
+{
 	struct ether_multi	*enm;
 	struct ether_multistep	step;
 	struct ethercom		*ec;
 	struct ifnet		*ifp;
 	uint16_t		af[4];
 	int			i;
 	ec = &sc->sc_ethercom;
 	ifp = &ec->ec_if;
 	if (ifp->if_flags & IFF_PROMISC) {
 		dme_write(sc, DM9000_RCR, DM9000_RCR_RXEN  |
 					  DM9000_RCR_WTDIS |
 					  DM9000_RCR_PRMSC);
 		ifp->if_flags |= IFF_ALLMULTI;
 		return;
+	}
 	af[0] = af[1] = af[2] = af[3] = 0x0000;
 	ifp->if_flags &= ~IFF_ALLMULTI;
 	ETHER_LOCK(ec);
 	ETHER_FIRST_MULTI(step, ec, enm);
 	while (enm != NULL) {
 		uint16_t hash;
 		if (memcpy(enm->enm_addrlo, enm->enm_addrhi,
 		    sizeof(enm->enm_addrlo))) {
 			/*
 			 * We must listen to a range of multicast addresses.
 			 * For now, just accept all multicasts, rather than
 			 * trying to set only those filter bits needed to match
 			 * the range.  (At this time, the only use of address
 			 * ranges is for IP multicast routing, for which the
 			 * range is big enough to require all bits set.)
 			 */
 			ifp->if_flags |= IFF_ALLMULTI;
 			af[0] = af[1] = af[2] = af[3] = 0xffff;
 			break;
 		} else {
 			hash = ether_crc32_le(enm->enm_addrlo, ETHER_ADDR_LEN) & 0x3F;
 			af[(uint16_t)(hash>>4)] |= (uint16_t)(1 << (hash % 16));
 			ETHER_NEXT_MULTI(step, enm);
+		}
+	}
 	ETHER_UNLOCK(ec);
 	/* Write the multicast address filter */
 	for (i = 0; i < 4; i++) {
 		dme_write(sc, DM9000_MAB0+i*2, af[i] & 0xFF);
 		dme_write(sc, DM9000_MAB0+i*2+1, (af[i] >> 8) & 0xFF);
+	}
 	/* Setup RX controls */
 	dme_write(sc, DM9000_RCR, DM9000_RCR_RXEN | DM9000_RCR_WTDIS);
+}
 int
 dme_pkt_write_2(struct dme_softc *sc, struct mbuf *bufChain)
+{
 	int left_over_count = 0; /* Number of bytes from previous mbuf, which
 				    need to be written with the next.*/
 	uint16_t left_over_buf = 0;
 	int length = 0;
 	struct mbuf *buf;
 	uint8_t *write_ptr;
 	/* We expect that the DM9000 has been setup to accept writes before
 	   this function is called. */
 	for (buf = bufChain; buf != NULL; buf = buf->m_next) {
 		int to_write = buf->m_len;
 		length += to_write;
 		write_ptr = buf->m_data;
 		while (to_write > 0 ||
 		    (buf->m_next == NULL && left_over_count > 0)) {
 			if (left_over_count > 0) {
 				uint8_t b = 0;
 				DPRINTF(("dme_pkt_write_16: "
 					 "Writing left over byte\n"));
 				if (to_write > 0) {
 					b = *write_ptr;
 					to_write--;
 					write_ptr++;
 					DPRINTF(("Took single byte\n"));
 				} else {
 					DPRINTF(("Leftover in last run\n"));
 					length++;
+				}
 				/* Does shift direction depend on endianess? */
 				left_over_buf = left_over_buf | (b << 8);
 				bus_space_write_2(sc->sc_iot, sc->sc_ioh,
 						  sc->dme_data, left_over_buf);
 				TX_DATA_DPRINTF(("%02X ", left_over_buf));
 				left_over_count = 0;
 			} else if ((long)write_ptr % 2 != 0) {
 				/* Misaligned data */
 				DPRINTF(("dme_pkt_write_16: "
 					 "Detected misaligned data\n"));
 				left_over_buf = *write_ptr;
 				left_over_count = 1;
 				write_ptr++;
 				to_write--;
 			} else {
 				int i;
 				uint16_t *dptr = (uint16_t *)write_ptr;
 				/* A block of aligned data. */
 				for (i = 0; i < to_write / 2; i++) {
 					/* buf will be half-word aligned
 					 * all the time
 					 */
 					bus_space_write_2(sc->sc_iot,
 					    sc->sc_ioh, sc->dme_data, *dptr);
 					TX_DATA_DPRINTF(("%02X %02X ",
 					    *dptr & 0xFF, (*dptr >> 8) & 0xFF));
 					dptr++;
+				}
 				write_ptr += i * 2;
 				if (to_write % 2 != 0) {
 					DPRINTF(("dme_pkt_write_16: "
 						 "to_write %% 2: %d\n",
 						 to_write % 2));
 					left_over_count = 1;
 					/* XXX: Does this depend on
 					 * the endianess?
 					 */
 					left_over_buf = *write_ptr;
 					write_ptr++;
 					to_write--;
 					DPRINTF(("dme_pkt_write_16: "
 						 "to_write (after): %d\n",
 						 to_write));
 					DPRINTF(("dme_pkt_write_16: i * 2: %d\n",
 						 i*2));
+				}
 				to_write -= i * 2;
+			}
 		} /* while (...) */
 	} /* for (...) */
 	return length;
+}
 int
 dme_pkt_read_2(struct dme_softc *sc, struct ifnet *ifp, struct mbuf **outBuf)
+{
 	uint8_t rx_status;
 	struct mbuf *m;
 	uint16_t data;
 	uint16_t frame_length;
 	uint16_t i;
 	uint16_t *buf;
 	data = bus_space_read_2(sc->sc_iot, sc->sc_ioh, sc->dme_data);
 	rx_status = data & 0xFF;
 	frame_length = bus_space_read_2(sc->sc_iot,
 					sc->sc_ioh, sc->dme_data);
 	if (frame_length > ETHER_MAX_LEN) {
 		printf("Got frame of length: %d\n", frame_length);
 		printf("ETHER_MAX_LEN is: %d\n", ETHER_MAX_LEN);
 		panic("Something is rotten");
+	}
 	RX_DPRINTF(("dme_receive: rx_statux: 0x%x, frame_length: %d\n",
 		rx_status, frame_length));
 	m = dme_alloc_receive_buffer(ifp, frame_length);
 	if (m == NULL) {
 		/*
 		 * didn't get a receive buffer, so we read the rest of the
 		 * packet, throw it away and return an error
 		 */
 		for (i = 0; i < frame_length; i += 2 ) {
 			data = bus_space_read_2(sc->sc_iot,
 					sc->sc_ioh, sc->dme_data);
+		}
 		*outBuf = NULL;
 		return 0;
+	}
 	buf = mtod(m, uint16_t*);
 	RX_DPRINTF(("dme_receive: "));
 	for (i = 0; i < frame_length; i += 2 ) {
 		data = bus_space_read_2(sc->sc_iot,
 					sc->sc_ioh, sc->dme_data);
 		if ( (frame_length % 2 != 0) &&
 		     (i == frame_length - 1) ) {
 			data = data & 0xff;
 			RX_DPRINTF((" L "));
+		}
 		*buf = data;
 		buf++;
 		RX_DATA_DPRINTF(("%02X %02X ", data & 0xff,
 				 (data >> 8) & 0xff));
+	}
 	RX_DATA_DPRINTF(("\n"));
 	RX_DPRINTF(("Read %d bytes\n", i));
 	*outBuf = m;
 	return rx_status;
+}
 int
 dme_pkt_write_1(struct dme_softc *sc, struct mbuf *bufChain)
+{
 	int length = 0, i;
 	struct mbuf *buf;
 	uint8_t *write_ptr;
 	/*
 	 * We expect that the DM9000 has been setup to accept writes before
 	 * this function is called.
 	 */
 	for (buf = bufChain; buf != NULL; buf = buf->m_next) {
 		int to_write = buf->m_len;
 		length += to_write;
 		write_ptr = buf->m_data;
 		for (i = 0; i < to_write; i++) {
 			bus_space_write_1(sc->sc_iot, sc->sc_ioh,
 			    sc->dme_data, *write_ptr);
 			write_ptr++;
+		}
 	} /* for (...) */
 	return length;
+}
 int
 dme_pkt_read_1(struct dme_softc *sc, struct ifnet *ifp, struct mbuf **outBuf)
+{
 	uint8_t rx_status;
 	struct mbuf *m;
 	uint8_t *buf;
 	uint16_t frame_length;
 	uint16_t i, reg;
 	uint8_t data;
 	reg = bus_space_read_1(sc->sc_iot, sc->sc_ioh, sc->dme_data);
 	reg |= bus_space_read_1(sc->sc_iot, sc->sc_ioh, sc->dme_data) << 8;
 	rx_status = reg & 0xFF;
 	reg = bus_space_read_1(sc->sc_iot, sc->sc_ioh, sc->dme_data);
 	reg |= bus_space_read_1(sc->sc_iot, sc->sc_ioh, sc->dme_data) << 8;
 	frame_length = reg;
 	if (frame_length > ETHER_MAX_LEN) {
 		printf("Got frame of length: %d\n", frame_length);
 		printf("ETHER_MAX_LEN is: %d\n", ETHER_MAX_LEN);
 		panic("Something is rotten");
+	}
 	RX_DPRINTF(("dme_receive: "
 		    "rx_statux: 0x%x, frame_length: %d\n",
 		    rx_status, frame_length));
 	m = dme_alloc_receive_buffer(ifp, frame_length);
 	if (m == NULL) {
 		/*
 		 * didn't get a receive buffer, so we read the rest of the
 		 * packet, throw it away and return an error
 		 */
 		for (i = 0; i < frame_length; i++ ) {
 			data = bus_space_read_2(sc->sc_iot,
 					sc->sc_ioh, sc->dme_data);
+		}
 		*outBuf = NULL;
 		return 0;
+	}
 	buf = mtod(m, uint8_t *);
 	RX_DPRINTF(("dme_receive: "));
 	for (i = 0; i< frame_length; i += 1 ) {
 		data = bus_space_read_1(sc->sc_iot, sc->sc_ioh, sc->dme_data);
 		*buf = data;
 		buf++;
 		RX_DATA_DPRINTF(("%02X ", data));
+	}
 	RX_DATA_DPRINTF(("\n"));
 	RX_DPRINTF(("Read %d bytes\n", i));
 	*outBuf = m;
 	return rx_status;
+}
 struct mbuf*
 dme_alloc_receive_buffer(struct ifnet *ifp, unsigned int frame_length)
+{
 	struct dme_softc *sc = ifp->if_softc;
 	struct mbuf *m;
 	int pad;
 	MGETHDR(m, M_DONTWAIT, MT_DATA);
 	if (m == NULL) return NULL;
 	m_set_rcvif(m, ifp);
 	/* Ensure that we always allocate an even number of
 	 * bytes in order to avoid writing beyond the buffer
 	 */
 	m->m_pkthdr.len = frame_length + (frame_length % sc->sc_data_width);
 	pad = ALIGN(sizeof(struct ether_header)) -
 		sizeof(struct ether_header);
 	/* All our frames have the CRC attached */
 	m->m_flags |= M_HASFCS;
 	if (m->m_pkthdr.len + pad > MHLEN) {
 		MCLGET(m, M_DONTWAIT);
 		if ((m->m_flags & M_EXT) == 0) {
 			m_freem(m);
 			return NULL;
+		}
+	}
 	m->m_data += pad;
 	m->m_len = frame_length + (frame_length % sc->sc_data_width);
 	return m;
+}

 @@ -1,1227 +1,1231 @@
-/*	$NetBSD: dp8390.c,v 1.95 2019/05/29 10:07:29 msaitoh Exp $	*/
+/*	$NetBSD: dp8390.c,v 1.96 2020/01/29 14:14:55 thorpej Exp $	*/
 /*
  * Device driver for National Semiconductor DS8390/WD83C690 based ethernet
  * adapters.
+ *
  * Copyright (c) 1994, 1995 Charles M. Hannum.  All rights reserved.
+ *
  * Copyright (C) 1993, David Greenman.  This software may be used, modified,
  * copied, distributed, and sold, in both source and binary form provided that
  * the above copyright and these terms are retained.  Under no circumstances is
  * the author responsible for the proper functioning of this software, nor does
  * the author assume any responsibility for damages incurred with its use.
  */
 #include <sys/cdefs.h>
-__KERNEL_RCSID(0, "$NetBSD: dp8390.c,v 1.95 2019/05/29 10:07:29 msaitoh Exp $");
+__KERNEL_RCSID(0, "$NetBSD: dp8390.c,v 1.96 2020/01/29 14:14:55 thorpej Exp $");
 #include "opt_inet.h"
 #include <sys/param.h>
 #include <sys/systm.h>
 #include <sys/device.h>
 #include <sys/errno.h>
 #include <sys/ioctl.h>
 #include <sys/mbuf.h>
 #include <sys/socket.h>
 #include <sys/syslog.h>
 #include <sys/rndsource.h>
 #include <sys/bus.h>
 #include <net/if.h>
 #include <net/if_dl.h>
 #include <net/if_types.h>
 #include <net/if_media.h>
 #include <net/if_ether.h>
 #include <net/bpf.h>
 #ifdef INET
 #include <netinet/in.h>
 #include <netinet/in_systm.h>
 #include <netinet/in_var.h>
 #include <netinet/ip.h>
 #include <netinet/if_inarp.h>
 #endif
 #include <dev/ic/dp8390reg.h>
 #include <dev/ic/dp8390var.h>
 #ifdef DEBUG
 int	dp8390_debug = 0;
 #endif
 static void dp8390_xmit(struct dp8390_softc *);
 static void dp8390_read_hdr(struct dp8390_softc *, int, struct dp8390_ring *);
 static int  dp8390_ring_copy(struct dp8390_softc *, int, void *, u_short);
 static int  dp8390_write_mbuf(struct dp8390_softc *, struct mbuf *, int);
 static int  dp8390_test_mem(struct dp8390_softc *);
 /*
  * Standard media init routine for the dp8390.
  */
 void
 dp8390_media_init(struct dp8390_softc *sc)
+{
 	sc->sc_ec.ec_ifmedia = &sc->sc_media;
 	ifmedia_init(&sc->sc_media, 0, dp8390_mediachange, dp8390_mediastatus);
 	ifmedia_add(&sc->sc_media, IFM_ETHER | IFM_MANUAL, 0, NULL);
 	ifmedia_set(&sc->sc_media, IFM_ETHER | IFM_MANUAL);
+}
 /*
  * Do bus-independent setup.
  */
 int
 dp8390_config(struct dp8390_softc *sc)
+{
 	struct ifnet *ifp = &sc->sc_ec.ec_if;
 	int rv;
 	rv = 1;
 	if (sc->test_mem == NULL)
 		sc->test_mem = dp8390_test_mem;
 	if (sc->read_hdr == NULL)
 		sc->read_hdr = dp8390_read_hdr;
 	if (sc->recv_int == NULL)
 		sc->recv_int = dp8390_rint;
 	if (sc->ring_copy == NULL)
 		sc->ring_copy = dp8390_ring_copy;
 	if (sc->write_mbuf == NULL)
 		sc->write_mbuf = dp8390_write_mbuf;
 	/* Allocate one xmit buffer if < 16k, two buffers otherwise. */
 	if ((sc->mem_size < 16384) ||
 	    (sc->sc_flags & DP8390_NO_MULTI_BUFFERING))
 		sc->txb_cnt = 1;
 	else if (sc->mem_size < 8192 * 3)
 		sc->txb_cnt = 2;
 	else
 		sc->txb_cnt = 3;
 	sc->tx_page_start = sc->mem_start >> ED_PAGE_SHIFT;
 	sc->rec_page_start = sc->tx_page_start + sc->txb_cnt * ED_TXBUF_SIZE;
 	sc->rec_page_stop = sc->tx_page_start + (sc->mem_size >> ED_PAGE_SHIFT);
 	sc->mem_ring = sc->mem_start +
 	    ((sc->txb_cnt * ED_TXBUF_SIZE) << ED_PAGE_SHIFT);
 	sc->mem_end = sc->mem_start + sc->mem_size;
 	/* Now zero memory and verify that it is clear. */
 	if ((*sc->test_mem)(sc))
 		goto out;
 	/* Set interface to stopped condition (reset). */
 	dp8390_stop(sc);
 	/* Initialize ifnet structure. */
 	strcpy(ifp->if_xname, device_xname(sc->sc_dev));
 	ifp->if_softc = sc;
 	ifp->if_start = dp8390_start;
 	ifp->if_ioctl = dp8390_ioctl;
 	if (ifp->if_watchdog == NULL)
 		ifp->if_watchdog = dp8390_watchdog;
 	ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST;
 	IFQ_SET_READY(&ifp->if_snd);
 	/* Print additional info when attached. */
 	aprint_normal_dev(sc->sc_dev, "Ethernet address %s\n",
 	    ether_sprintf(sc->sc_enaddr));
 	/* Initialize media goo. */
 	(*sc->sc_media_init)(sc);
 	/* We can support 802.1Q VLAN-sized frames. */
 	sc->sc_ec.ec_capabilities |= ETHERCAP_VLAN_MTU;
 	/* Attach the interface. */
 	if_attach(ifp);
 	if_deferred_start_init(ifp, NULL);
 	ether_ifattach(ifp, sc->sc_enaddr);
 	rnd_attach_source(&sc->rnd_source, device_xname(sc->sc_dev),
 	    RND_TYPE_NET, RND_FLAG_DEFAULT);
 	/* The attach is successful. */
 	sc->sc_flags |= DP8390_ATTACHED;
 	rv = 0;
  out:
 	return rv;
+}
 /*
  * Media change callback.
  */
 int
 dp8390_mediachange(struct ifnet *ifp)
+{
 	struct dp8390_softc *sc = ifp->if_softc;
 	if (sc->sc_mediachange)
 		return (*sc->sc_mediachange)(sc);
 	return 0;
+}
 /*
  * Media status callback.
  */
 void
 dp8390_mediastatus(struct ifnet *ifp, struct ifmediareq *ifmr)
+{
 	struct dp8390_softc *sc = ifp->if_softc;
 	if (sc->sc_enabled == 0) {
 		ifmr->ifm_active = IFM_ETHER | IFM_NONE;
 		ifmr->ifm_status = 0;
 		return;
+	}
 	if (sc->sc_mediastatus)
 		(*sc->sc_mediastatus)(sc, ifmr);
+}
 /*
  * Reset interface.
  */
 void
 dp8390_reset(struct dp8390_softc *sc)
+{
 	int s;
 	s = splnet();
 	dp8390_stop(sc);
 	dp8390_init(sc);
 	splx(s);
+}
 /*
  * Take interface offline.
  */
 void
 dp8390_stop(struct dp8390_softc *sc)
+{
 	bus_space_tag_t regt = sc->sc_regt;
 	bus_space_handle_t regh = sc->sc_regh;
 	int n = 5000;
 	/* Stop everything on the interface, and select page 0 registers. */
 	NIC_BARRIER(regt, regh);
 	NIC_PUT(regt, regh, ED_P0_CR,
 	    sc->cr_proto | ED_CR_PAGE_0 | ED_CR_STP);
 	NIC_BARRIER(regt, regh);
 	/*
 	 * Wait for interface to enter stopped state, but limit # of checks to
 	 * 'n' (about 5ms).  It shouldn't even take 5us on modern DS8390's, but
 	 * just in case it's an old one.
 	 */
 	while (((NIC_GET(regt, regh, ED_P0_ISR) & ED_ISR_RST) == 0) && --n)
 		DELAY(1);
 	if (sc->stop_card != NULL)
 		(*sc->stop_card)(sc);
+}
 /*
  * Device timeout/watchdog routine.  Entered if the device neglects to generate
  * an interrupt after a transmit has been started on it.
  */
 void
 dp8390_watchdog(struct ifnet *ifp)
+{
 	struct dp8390_softc *sc = ifp->if_softc;
 	log(LOG_ERR, "%s: device timeout\n", device_xname(sc->sc_dev));
-	++sc->sc_ec.ec_if.if_oerrors;
+	if_statinc(ifp, if_oerrors);
 	dp8390_reset(sc);
+}
 /*
  * Initialize device.
  */
 void
 dp8390_init(struct dp8390_softc *sc)
+{
 	bus_space_tag_t regt = sc->sc_regt;
 	bus_space_handle_t regh = sc->sc_regh;
 	struct ifnet *ifp = &sc->sc_ec.ec_if;
 	uint8_t mcaf[8];
 	int i;
 	/*
 	 * Initialize the NIC in the exact order outlined in the NS manual.
 	 * This init procedure is "mandatory"...don't change what or when
 	 * things happen.
 	 */
 	/* Reset transmitter flags. */
 	ifp->if_timer = 0;
 	sc->txb_inuse = 0;
 	sc->txb_new = 0;
 	sc->txb_next_tx = 0;
 	/* Set interface for page 0, remote DMA complete, stopped. */
 	NIC_BARRIER(regt, regh);
 	NIC_PUT(regt, regh, ED_P0_CR,
 	    sc->cr_proto | ED_CR_PAGE_0 | ED_CR_STP);
 	NIC_BARRIER(regt, regh);
 	if (sc->dcr_reg & ED_DCR_LS) {
 		NIC_PUT(regt, regh, ED_P0_DCR, sc->dcr_reg);
 	} else {
 		/*
 		 * Set FIFO threshold to 8, No auto-init Remote DMA, byte
 		 * order=80x86, byte-wide DMA xfers,
 		 */
 		NIC_PUT(regt, regh, ED_P0_DCR, ED_DCR_FT1 | ED_DCR_LS);
+	}
 	/* Clear remote byte count registers. */
 	NIC_PUT(regt, regh, ED_P0_RBCR0, 0);
 	NIC_PUT(regt, regh, ED_P0_RBCR1, 0);
 	/* Tell RCR to do nothing for now. */
 	NIC_PUT(regt, regh, ED_P0_RCR, ED_RCR_MON | sc->rcr_proto);
 	/* Place NIC in internal loopback mode. */
 	NIC_PUT(regt, regh, ED_P0_TCR, ED_TCR_LB0);
 	/* Set lower bits of byte addressable framing to 0. */
 	if (sc->is790)
 		NIC_PUT(regt, regh, 0x09, 0);
 	/* Initialize receive buffer ring. */
 	NIC_PUT(regt, regh, ED_P0_BNRY, sc->rec_page_start);
 	NIC_PUT(regt, regh, ED_P0_PSTART, sc->rec_page_start);
 	NIC_PUT(regt, regh, ED_P0_PSTOP, sc->rec_page_stop);
 	/*
 	 * Enable the following interrupts: receive/transmit complete,
 	 * receive/transmit error, and Receiver OverWrite.
+	 *
 	 * Counter overflow and Remote DMA complete are *not* enabled.
 	 */
 	NIC_PUT(regt, regh, ED_P0_IMR,
 	    ED_IMR_PRXE | ED_IMR_PTXE | ED_IMR_RXEE | ED_IMR_TXEE |
 	    ED_IMR_OVWE);
 	/*
 	 * Clear all interrupts.  A '1' in each bit position clears the
 	 * corresponding flag.
 	 */
 	NIC_PUT(regt, regh, ED_P0_ISR, 0xff);
 	/* Program command register for page 1. */
 	NIC_BARRIER(regt, regh);
 	NIC_PUT(regt, regh, ED_P0_CR,
 	    sc->cr_proto | ED_CR_PAGE_1 | ED_CR_STP);
 	NIC_BARRIER(regt, regh);
 	/* Copy out our station address. */
 	for (i = 0; i < ETHER_ADDR_LEN; i++)
 		NIC_PUT(regt, regh, ED_P1_PAR0 + i, CLLADDR(ifp->if_sadl)[i]);
 	/* Set multicast filter on chip. */
 	dp8390_getmcaf(&sc->sc_ec, mcaf);
 	for (i = 0; i < 8; i++)
 		NIC_PUT(regt, regh, ED_P1_MAR0 + i, mcaf[i]);
 	/*
 	 * Set current page pointer to one page after the boundary pointer, as
 	 * recommended in the National manual.
 	 */
 	sc->next_packet = sc->rec_page_start + 1;
 	NIC_PUT(regt, regh, ED_P1_CURR, sc->next_packet);
 	/* Program command register for page 0. */
 	NIC_BARRIER(regt, regh);
 	NIC_PUT(regt, regh, ED_P1_CR,
 	    sc->cr_proto | ED_CR_PAGE_0 | ED_CR_STP);
 	NIC_BARRIER(regt, regh);
 	/* Accept broadcast and multicast packets by default. */
 	i = ED_RCR_AB | ED_RCR_AM | sc->rcr_proto;
 	if (ifp->if_flags & IFF_PROMISC) {
 		/*
 		 * Set promiscuous mode.  Multicast filter was set earlier so
 		 * that we should receive all multicast packets.
 		 */
 		i |= ED_RCR_PRO | ED_RCR_AR | ED_RCR_SEP;
+	}
 	NIC_PUT(regt, regh, ED_P0_RCR, i);
 	/* Take interface out of loopback. */
 	NIC_PUT(regt, regh, ED_P0_TCR, 0);
 	/* Do any card-specific initialization, if applicable. */
 	if (sc->init_card != NULL)
 		(*sc->init_card)(sc);
 	/* Fire up the interface. */
 	NIC_BARRIER(regt, regh);
 	NIC_PUT(regt, regh, ED_P0_CR,
 	    sc->cr_proto | ED_CR_PAGE_0 | ED_CR_STA);
 	/* Set 'running' flag, and clear output active flag. */
 	ifp->if_flags |= IFF_RUNNING;
 	ifp->if_flags &= ~IFF_OACTIVE;
 	/* ...and attempt to start output. */
 	dp8390_start(ifp);
+}
 /*
  * This routine actually starts the transmission on the interface.
  */
 static void
 dp8390_xmit(struct dp8390_softc *sc)
+{
 	bus_space_tag_t regt = sc->sc_regt;
 	bus_space_handle_t regh = sc->sc_regh;
 	struct ifnet *ifp = &sc->sc_ec.ec_if;
 	u_short len;
 #ifdef DIAGNOSTIC
 	if ((sc->txb_next_tx + sc->txb_inuse) % sc->txb_cnt != sc->txb_new)
 		panic("dp8390_xmit: desync, next_tx=%d inuse=%d cnt=%d new=%d",
 		    sc->txb_next_tx, sc->txb_inuse, sc->txb_cnt, sc->txb_new);
 	if (sc->txb_inuse == 0)
 		panic("dp8390_xmit: no packets to xmit");
 #endif
 	len = sc->txb_len[sc->txb_next_tx];
 	/* Set NIC for page 0 register access. */
 	NIC_BARRIER(regt, regh);
 	NIC_PUT(regt, regh, ED_P0_CR,
 	    sc->cr_proto | ED_CR_PAGE_0 | ED_CR_STA);
 	NIC_BARRIER(regt, regh);
 	/* Set TX buffer start page. */
 	NIC_PUT(regt, regh, ED_P0_TPSR,
 	    sc->tx_page_start + sc->txb_next_tx * ED_TXBUF_SIZE);
 	/* Set TX length. */
 	NIC_PUT(regt, regh, ED_P0_TBCR0, len);
 	NIC_PUT(regt, regh, ED_P0_TBCR1, len >> 8);
 	/* Set page 0, remote DMA complete, transmit packet, and *start*. */
 	NIC_BARRIER(regt, regh);
 	NIC_PUT(regt, regh, ED_P0_CR,
 	    sc->cr_proto | ED_CR_PAGE_0 | ED_CR_TXP | ED_CR_STA);
 	/* Point to next transmit buffer slot and wrap if necessary. */
 	if (++sc->txb_next_tx == sc->txb_cnt)
 		sc->txb_next_tx = 0;
 	/* Set a timer just in case we never hear from the board again. */
 	ifp->if_timer = 2;
+}
 /*
  * Start output on interface.
  * We make two assumptions here:
  *  1) that the current priority is set to splnet _before_ this code
  *     is called *and* is returned to the appropriate priority after
  *     return
  *  2) that the IFF_OACTIVE flag is checked before this code is called
  *     (i.e. that the output part of the interface is idle)
  */
 void
 dp8390_start(struct ifnet *ifp)
+{
 	struct dp8390_softc *sc = ifp->if_softc;
 	struct mbuf *m0;
 	int buffer;
 	int len;
 	if ((ifp->if_flags & (IFF_RUNNING | IFF_OACTIVE)) != IFF_RUNNING)
 		return;
  outloop:
 	/* See if there is room to put another packet in the buffer. */
 	if (sc->txb_inuse == sc->txb_cnt) {
 		/* No room.  Indicate this to the outside world and exit. */
 		ifp->if_flags |= IFF_OACTIVE;
 		return;
+	}
 	IFQ_DEQUEUE(&ifp->if_snd, m0);
 	if (m0 == NULL)
 		return;
 	/* We need to use m->m_pkthdr.len, so require the header */
 	if ((m0->m_flags & M_PKTHDR) == 0)
 		panic("dp8390_start: no header mbuf");
 	/* Tap off here if there is a BPF listener. */
 	bpf_mtap(ifp, m0, BPF_D_OUT);
 	/* txb_new points to next open buffer slot. */
 	buffer = sc->mem_start +
 	    ((sc->txb_new * ED_TXBUF_SIZE) << ED_PAGE_SHIFT);
 	len = (*sc->write_mbuf)(sc, m0, buffer);
 	m_freem(m0);
 	sc->txb_len[sc->txb_new] = len;
 	/* Point to next buffer slot and wrap if necessary. */
 	if (++sc->txb_new == sc->txb_cnt)
 		sc->txb_new = 0;
 	/* Start the first packet transmitting. */
 	if (sc->txb_inuse++ == 0)
 		dp8390_xmit(sc);
 	/* Loop back to the top to possibly buffer more packets. */
 	goto outloop;
+}
 /*
  * Ethernet interface receiver interrupt.
  */
 void
 dp8390_rint(struct dp8390_softc *sc)
+{
 	bus_space_tag_t regt = sc->sc_regt;
 	bus_space_handle_t regh = sc->sc_regh;
 	struct dp8390_ring packet_hdr;
 	int packet_ptr;
 	uint16_t len;
 	uint8_t boundary, current;
 	uint8_t nlen;
  loop:
 	/* Set NIC to page 1 registers to get 'current' pointer. */
 	NIC_BARRIER(regt, regh);
 	NIC_PUT(regt, regh, ED_P0_CR,
 	    sc->cr_proto | ED_CR_PAGE_1 | ED_CR_STA);
 	NIC_BARRIER(regt, regh);
 	/*
 	 * 'sc->next_packet' is the logical beginning of the ring-buffer - i.e.
 	 * it points to where new data has been buffered.  The 'CURR' (current)
 	 * register points to the logical end of the ring-buffer - i.e. it
 	 * points to where additional new data will be added.  We loop here
 	 * until the logical beginning equals the logical end (or in other
 	 * words, until the ring-buffer is empty).
 	 */
 	current = NIC_GET(regt, regh, ED_P1_CURR);
 	if (sc->next_packet == current)
 		return;
 	/* Set NIC to page 0 registers to update boundary register. */
 	NIC_BARRIER(regt, regh);
 	NIC_PUT(regt, regh, ED_P1_CR,
 	    sc->cr_proto | ED_CR_PAGE_0 | ED_CR_STA);
 	NIC_BARRIER(regt, regh);
 	do {
 		/* Get pointer to this buffer's header structure. */
 		packet_ptr = sc->mem_ring +
 		    ((sc->next_packet - sc->rec_page_start) << ED_PAGE_SHIFT);
 		(*sc->read_hdr)(sc, packet_ptr, &packet_hdr);
 		len = packet_hdr.count;
 		/*
 		 * Try do deal with old, buggy chips that sometimes duplicate
 		 * the low byte of the length into the high byte.  We do this
 		 * by simply ignoring the high byte of the length and always
 		 * recalculating it.
+		 *
 		 * NOTE: sc->next_packet is pointing at the current packet.
 		 */
 		if (packet_hdr.next_packet >= sc->next_packet)
 			nlen = (packet_hdr.next_packet - sc->next_packet);
 		else
 			nlen = ((packet_hdr.next_packet - sc->rec_page_start) +
 			    (sc->rec_page_stop - sc->next_packet));
 		--nlen;
 		if ((len & ED_PAGE_MASK) + sizeof(packet_hdr) > ED_PAGE_SIZE)
 			--nlen;
 		len = (len & ED_PAGE_MASK) | (nlen << ED_PAGE_SHIFT);
 #ifdef DIAGNOSTIC
 		if (len != packet_hdr.count) {
 			aprint_verbose_dev(sc->sc_dev, "length does not match "
 			    "next packet pointer\n");
 			aprint_verbose_dev(sc->sc_dev, "len %04x nlen %04x "
 			    "start %02x first %02x curr %02x next %02x "
 			    "stop %02x\n", packet_hdr.count, len,
 			    sc->rec_page_start, sc->next_packet, current,
 			    packet_hdr.next_packet, sc->rec_page_stop);
+		}
 #endif
 		/*
 		 * Be fairly liberal about what we allow as a "reasonable"
 		 * length so that a [crufty] packet will make it to BPF (and
 		 * can thus be analyzed).  Note that all that is really
 		 * important is that we have a length that will fit into one
 		 * mbuf cluster or less; the upper layer protocols can then
 		 * figure out the length from their own length field(s).
 		 */
 		if (len <= MCLBYTES &&
 		    packet_hdr.next_packet >= sc->rec_page_start &&
 		    packet_hdr.next_packet < sc->rec_page_stop) {
 			/* Go get packet. */
 			dp8390_read(sc,
 			    packet_ptr + sizeof(struct dp8390_ring),
 			    len - sizeof(struct dp8390_ring));
 		} else {
 			/* Really BAD.  The ring pointers are corrupted. */
 			log(LOG_ERR, "%s: NIC memory corrupt - "
 			    "invalid packet length %d\n",
 			    device_xname(sc->sc_dev), len);
-			++sc->sc_ec.ec_if.if_ierrors;
+			if_statinc(&sc->sc_ec.ec_if, if_ierrors);
 			dp8390_reset(sc);
 			return;
+		}
 		/* Update next packet pointer. */
 		sc->next_packet = packet_hdr.next_packet;
 		/*
 		 * Update NIC boundary pointer - being careful to keep it one
 		 * buffer behind (as recommended by NS databook).
 		 */
 		boundary = sc->next_packet - 1;
 		if (boundary < sc->rec_page_start)
 			boundary = sc->rec_page_stop - 1;
 		NIC_PUT(regt, regh, ED_P0_BNRY, boundary);
 	} while (sc->next_packet != current);
 	goto loop;
+}
 /* Ethernet interface interrupt processor. */
 int
 dp8390_intr(void *arg)
+{
 	struct dp8390_softc *sc = arg;
 	bus_space_tag_t regt = sc->sc_regt;
 	bus_space_handle_t regh = sc->sc_regh;
 	struct ifnet *ifp = &sc->sc_ec.ec_if;
 	uint8_t isr;
 	uint8_t rndisr;
 	if (sc->sc_enabled == 0 || !device_is_active(sc->sc_dev))
 		return 0;
 	/* Set NIC to page 0 registers. */
 	NIC_BARRIER(regt, regh);
 	NIC_PUT(regt, regh, ED_P0_CR, sc->cr_proto | ED_CR_PAGE_0 | ED_CR_STA);
 	NIC_BARRIER(regt, regh);
 	isr = NIC_GET(regt, regh, ED_P0_ISR);
 	if (isr == 0)
 		return 0;
 	rndisr = isr;
 	/* Loop until there are no more new interrupts. */
 	for (;;) {
 		/*
 		 * Reset all the bits that we are 'acknowledging' by writing a
 		 * '1' to each bit position that was set.
 		 * (Writing a '1' *clears* the bit.)
 		 */
 		NIC_PUT(regt, regh, ED_P0_ISR, isr);
 		/* Work around for AX88190 bug */
 		if ((sc->sc_flags & DP8390_DO_AX88190_WORKAROUND) != 0)
 			while ((NIC_GET(regt, regh, ED_P0_ISR) & isr) != 0) {
 				NIC_PUT(regt, regh, ED_P0_ISR, 0);
 				NIC_PUT(regt, regh, ED_P0_ISR, isr);
+			}
 		/*
 		 * Handle transmitter interrupts.  Handle these first because
 		 * the receiver will reset the board under some conditions.
+		 *
 		 * If the chip was reset while a packet was transmitting, it
 		 * may still deliver a TX interrupt.  In this case, just ignore
 		 * the interrupt.
 		 */
 		if ((isr & (ED_ISR_PTX | ED_ISR_TXE)) != 0 &&
 		    sc->txb_inuse != 0) {
 			net_stat_ref_t nsr = IF_STAT_GETREF(ifp);
 			uint8_t collisions =
 			    NIC_GET(regt, regh, ED_P0_NCR) & 0x0f;
 			/*
 			 * Check for transmit error.  If a TX completed with an
 			 * error, we end up throwing the packet away.  Really
 			 * the only error that is possible is excessive
 			 * collisions, and in this case it is best to allow the
 			 * automatic mechanisms of TCP to backoff the flow.  Of
 			 * course, with UDP we're screwed, but this is expected
 			 * when a network is heavily loaded.
 			 */
 			if ((isr & ED_ISR_TXE) != 0) {
 				/* Excessive collisions (16). */
 				if ((NIC_GET(regt, regh, ED_P0_TSR)
 				    & ED_TSR_ABT) && (collisions == 0)) {
 					/*
 					 * When collisions total 16, the P0_NCR
 					 * will indicate 0, and the TSR_ABT is
 					 * set.
 					 */
 					collisions = 16;
+				}
 				/* Update output errors counter. */
-				++ifp->if_oerrors;
+				if_statinc_ref(nsr, if_oerrors);
 			} else {
 				/*
 				 * Throw away the non-error status bits.
+				 *
 				 * XXX
 				 * It may be useful to detect loss of carrier
 				 * and late collisions here.
 				 */
 				(void)NIC_GET(regt, regh, ED_P0_TSR);
 				/*
 				 * Update total number of successfully
 				 * transmitted packets.
 				 */
-				++ifp->if_opackets;
+				if_statinc_ref(nsr, if_opackets);
+			}
 			/* Clear watchdog timer. */
 			ifp->if_timer = 0;
 			ifp->if_flags &= ~IFF_OACTIVE;
 			/*
 			 * Add in total number of collisions on last
 			 * transmission.
 			 */
-			ifp->if_collisions += collisions;
+			if (collisions)
 				if_statadd_ref(nsr, if_collisions, collisions);
 			IF_STAT_PUTREF(ifp);
 			/*
 			 * Decrement buffer in-use count if not zero (can only
 			 * be zero if a transmitter interrupt occurred while
 			 * not actually transmitting).
 			 * If data is ready to transmit, start it transmitting,
 			 * otherwise defer until after handling receiver.
 			 */
 			if (--sc->txb_inuse != 0)
 				dp8390_xmit(sc);
+		}
 		/* Handle receiver interrupts. */
 		if ((isr & (ED_ISR_PRX | ED_ISR_RXE | ED_ISR_OVW)) != 0) {
 			/*
 			 * Overwrite warning.  In order to make sure that a
 			 * lockup of the local DMA hasn't occurred, we reset
 			 * and re-init the NIC.  The NSC manual suggests only a
 			 * partial reset/re-init is necessary - but some chips
 			 * seem to want more.  The DMA lockup has been seen
 			 * only with early rev chips - Methinks this bug was
 			 * fixed in later revs.  -DG
 			 */
 			if ((isr & ED_ISR_OVW) != 0) {
-				++ifp->if_ierrors;
+				if_statinc(ifp, if_ierrors);
 #ifdef DIAGNOSTIC
 				log(LOG_WARNING, "%s: warning - receiver "
 				    "ring buffer overrun\n",
 				    device_xname(sc->sc_dev));
 #endif
 				/* Stop/reset/re-init NIC. */
 				dp8390_reset(sc);
 			} else {
 				/*
 				 * Receiver Error.  One or more of: CRC error,
 				 * frame alignment error FIFO overrun, or
 				 * missed packet.
 				 */
 				if ((isr & ED_ISR_RXE) != 0) {
-					++ifp->if_ierrors;
+					if_statinc(ifp, if_ierrors);
 #ifdef DEBUG
 					if (dp8390_debug) {
 						printf("%s: receive error %x\n",
 						    device_xname(sc->sc_dev),
 						    NIC_GET(regt, regh,
 							ED_P0_RSR));
+					}
 #endif
+				}
 				/*
 				 * Go get the packet(s)
 				 * XXX - Doing this on an error is dubious
 				 * because there shouldn't be any data to get
 				 * (we've configured the interface to not
 				 * accept packets with errors).
 				 */
 				(*sc->recv_int)(sc);
+			}
+		}
 		/*
 		 * If it looks like the transmitter can take more data, attempt
 		 * to start output on the interface.  This is done after
 		 * handling the receiver to give the receiver priority.
 		 */
 		if_schedule_deferred_start(ifp);
 		/*
 		 * Return NIC CR to standard state: page 0, remote DMA
 		 * complete, start (toggling the TXP bit off, even if was just
 		 * set in the transmit routine, is *okay* - it is 'edge'
 		 * triggered from low to high).
 		 */
 		NIC_BARRIER(regt, regh);
 		NIC_PUT(regt, regh, ED_P0_CR,
 		    sc->cr_proto | ED_CR_PAGE_0 | ED_CR_STA);
 		NIC_BARRIER(regt, regh);
 		/*
 		 * If the Network Talley Counters overflow, read them to reset
 		 * them.  It appears that old 8390's won't clear the ISR flag
 		 * otherwise - resulting in an infinite loop.
 		 */
 		if ((isr & ED_ISR_CNT) != 0) {
 			(void)NIC_GET(regt, regh, ED_P0_CNTR0);
 			(void)NIC_GET(regt, regh, ED_P0_CNTR1);
 			(void)NIC_GET(regt, regh, ED_P0_CNTR2);
+		}
 		isr = NIC_GET(regt, regh, ED_P0_ISR);
 		if (isr == 0)
 			goto out;
+	}
  out:
 	rnd_add_uint32(&sc->rnd_source, rndisr);
 	return 1;
+}
 /*
  * Process an ioctl request.  This code needs some work - it looks pretty ugly.
  */
 int
 dp8390_ioctl(struct ifnet *ifp, u_long cmd, void *data)
+{
 	struct dp8390_softc *sc = ifp->if_softc;
 	struct ifaddr *ifa = data;
 	int s, error = 0;
 	s = splnet();
 	switch (cmd) {
 	case SIOCINITIFADDR:
 		if ((error = dp8390_enable(sc)) != 0)
 			break;
 		ifp->if_flags |= IFF_UP;
 		dp8390_init(sc);
 		switch (ifa->ifa_addr->sa_family) {
 #ifdef INET
 		case AF_INET:
 			arp_ifinit(ifp, ifa);
 			break;
 #endif
 		default:
 			break;
+		}
 		break;
 	case SIOCSIFFLAGS:
 		if ((error = ifioctl_common(ifp, cmd, data)) != 0)
 			break;
 		switch (ifp->if_flags & (IFF_UP | IFF_RUNNING)) {
 		case IFF_RUNNING:
 			/*
 			 * If interface is marked down and it is running, then
 			 * stop it.
 			 */
 			dp8390_stop(sc);
 			ifp->if_flags &= ~IFF_RUNNING;
 			dp8390_disable(sc);
 			break;
 		case IFF_UP:
 			/*
 			 * If interface is marked up and it is stopped, then
 			 * start it.
 			 */
 			if ((error = dp8390_enable(sc)) != 0)
 				break;
 			dp8390_init(sc);
 			break;
 		case IFF_UP | IFF_RUNNING:
 			/*
 			 * Reset the interface to pick up changes in any other
 			 * flags that affect hardware registers.
 			 */
 			dp8390_stop(sc);
 			dp8390_init(sc);
 			break;
 		default:
 			break;
+		}
 		break;
 	case SIOCADDMULTI:
 	case SIOCDELMULTI:
 		if (sc->sc_enabled == 0) {
 			error = EIO;
 			break;
+		}
 		/* Update our multicast list. */
 		if ((error = ether_ioctl(ifp, cmd, data)) == ENETRESET) {
 			/*
 			 * Multicast list has changed; set the hardware filter
 			 * accordingly.
 			 */
 			if (ifp->if_flags & IFF_RUNNING) {
 				dp8390_stop(sc); /* XXX for ds_setmcaf? */
 				dp8390_init(sc);
+			}
 			error = 0;
+		}
 		break;
 	default:
 		error = ether_ioctl(ifp, cmd, data);
 		break;
+	}
 	splx(s);
 	return error;
+}
 /*
  * Retrieve packet from buffer memory and send to the next level up via
  * ether_input().  If there is a BPF listener, give a copy to BPF, too.
  */
 void
 dp8390_read(struct dp8390_softc *sc, int buf, u_short len)
+{
 	struct ifnet *ifp = &sc->sc_ec.ec_if;
 	struct mbuf *m;
 	/* Pull packet off interface. */
 	m = dp8390_get(sc, buf, len);
 	if (m == NULL) {
-		ifp->if_ierrors++;
+		if_statinc(ifp, if_ierrors);
 		return;
+	}
 	if_percpuq_enqueue(ifp->if_percpuq, m);
+}
 /*
  * Supporting routines.
  */
 /*
  * Compute the multicast address filter from the list of multicast addresses we
  * need to listen to.
  */
 void
 dp8390_getmcaf(struct ethercom *ec, uint8_t *af)
+{
 	struct ifnet *ifp = &ec->ec_if;
 	struct ether_multi *enm;
 	uint32_t crc;
 	int i;
 	struct ether_multistep step;
 	/*
 	 * Set up multicast address filter by passing all multicast addresses
 	 * through a crc generator, and then using the high order 6 bits as an
 	 * index into the 64 bit logical address filter.  The high order bit
 	 * selects the word, while the rest of the bits select the bit within
 	 * the word.
 	 */
 	if (ifp->if_flags & IFF_PROMISC) {
 		ifp->if_flags |= IFF_ALLMULTI;
 		for (i = 0; i < 8; i++)
 			af[i] = 0xff;
 		return;
+	}
 	for (i = 0; i < 8; i++)
 		af[i] = 0;
 	ETHER_LOCK(ec);
 	ETHER_FIRST_MULTI(step, ec, enm);
 	while (enm != NULL) {
 		if (memcmp(enm->enm_addrlo, enm->enm_addrhi,
 		    sizeof(enm->enm_addrlo)) != 0) {
 			/*
 			 * We must listen to a range of multicast addresses.
 			 * For now, just accept all multicasts, rather than
 			 * trying to set only those filter bits needed to match
 			 * the range.  (At this time, the only use of address
 			 * ranges is for IP multicast routing, for which the
 			 * range is big enough to require all bits set.)
 			 */
 			ifp->if_flags |= IFF_ALLMULTI;
 			for (i = 0; i < 8; i++)
 				af[i] = 0xff;
 			ETHER_UNLOCK(ec);
 			return;
+		}
 		crc = ether_crc32_be(enm->enm_addrlo, ETHER_ADDR_LEN);
 		/* Just want the 6 most significant bits. */
 		crc >>= 26;
 		/* Turn on the corresponding bit in the filter. */
 		af[crc >> 3] |= 1 << (crc & 0x7);
 		ETHER_NEXT_MULTI(step, enm);
+	}
 	ETHER_UNLOCK(ec);
 	ifp->if_flags &= ~IFF_ALLMULTI;
+}
 /*
  * Copy data from receive buffer to a new mbuf chain allocating mbufs
  * as needed.  Return pointer to first mbuf in chain.
  * sc = dp8390 info (softc)
  * src = pointer in dp8390 ring buffer
  * total_len = amount of data to copy
  */
 struct mbuf *
 dp8390_get(struct dp8390_softc *sc, int src, u_short total_len)
+{
 	struct ifnet *ifp = &sc->sc_ec.ec_if;
 	struct mbuf *m, *m0, *newm;
 	u_short len;
 	MGETHDR(m0, M_DONTWAIT, MT_DATA);
 	if (m0 == NULL)
 		return NULL;
 	m_set_rcvif(m0, ifp);
 	m0->m_pkthdr.len = total_len;
 	len = MHLEN;
 	m = m0;
 	while (total_len > 0) {
 		if (total_len >= MINCLSIZE) {
 			MCLGET(m, M_DONTWAIT);
 			if ((m->m_flags & M_EXT) == 0)
 				goto bad;
 			len = MCLBYTES;
+		}
 		/* Make sure the data after the Ethernet header is aligned. */
 		if (m == m0) {
 			char *newdata = (char *)
 			    ALIGN(m->m_data + sizeof(struct ether_header)) -
 			    sizeof(struct ether_header);
 			len -= newdata - m->m_data;
 			m->m_data = newdata;
+		}
 		m->m_len = len = uimin(total_len, len);
 		src = (*sc->ring_copy)(sc, src, mtod(m, void *), len);
 		total_len -= len;
 		if (total_len > 0) {
 			MGET(newm, M_DONTWAIT, MT_DATA);
 			if (newm == NULL)
 				goto bad;
 			len = MLEN;
 			m = m->m_next = newm;
+		}
+	}
 	return m0;
  bad:
 	m_freem(m0);
 	return NULL;
+}
 /*
  * Default driver support functions.
+ *
  * NOTE: all support functions assume 8-bit shared memory.
  */
 /*
  * Zero NIC buffer memory and verify that it is clear.
  */
 static int
 dp8390_test_mem(struct dp8390_softc *sc)
+{
 	bus_space_tag_t buft = sc->sc_buft;
 	bus_space_handle_t bufh = sc->sc_bufh;
 	int i;
 	bus_space_set_region_1(buft, bufh, sc->mem_start, 0, sc->mem_size);
 	for (i = 0; i < sc->mem_size; ++i) {
 		if (bus_space_read_1(buft, bufh, sc->mem_start + i)) {
 			printf(": failed to clear NIC buffer at offset %x - "
 			    "check configuration\n", (sc->mem_start + i));
 			return 1;
+		}
+	}
 	return 0;
+}
 /*
  * Read a packet header from the ring, given the source offset.
  */
 static void
 dp8390_read_hdr(struct dp8390_softc *sc, int src, struct dp8390_ring *hdrp)
+{
 	bus_space_tag_t buft = sc->sc_buft;
 	bus_space_handle_t bufh = sc->sc_bufh;
 	/*
 	 * The byte count includes a 4 byte header that was added by
 	 * the NIC.
 	 */
 	hdrp->rsr = bus_space_read_1(buft, bufh, src);
 	hdrp->next_packet = bus_space_read_1(buft, bufh, src + 1);
 	hdrp->count = bus_space_read_1(buft, bufh, src + 2) |
 	    (bus_space_read_1(buft, bufh, src + 3) << 8);
+}
 /*
  * Copy `amount' bytes from a packet in the ring buffer to a linear
  * destination buffer, given a source offset and destination address.
  * Takes into account ring-wrap.
  */
 static int
 dp8390_ring_copy(struct dp8390_softc *sc, int src, void *dst, u_short amount)
+{
 	bus_space_tag_t buft = sc->sc_buft;
 	bus_space_handle_t bufh = sc->sc_bufh;
 	u_short tmp_amount;
 	/* Does copy wrap to lower addr in ring buffer? */
 	if (src + amount > sc->mem_end) {
 		tmp_amount = sc->mem_end - src;
 		/* Copy amount up to end of NIC memory. */
 		bus_space_read_region_1(buft, bufh, src, dst, tmp_amount);
 		amount -= tmp_amount;
 		src = sc->mem_ring;
 		dst = (char *)dst + tmp_amount;
+	}
 	bus_space_read_region_1(buft, bufh, src, dst, amount);
 	return src + amount;
+}
 /*
  * Copy a packet from an mbuf to the transmit buffer on the card.
+ *
  * Currently uses an extra buffer/extra memory copy, unless the whole
  * packet fits in one mbuf.
  */
 static int
 dp8390_write_mbuf(struct dp8390_softc *sc, struct mbuf *m, int buf)
+{
 	bus_space_tag_t buft = sc->sc_buft;
 	bus_space_handle_t bufh = sc->sc_bufh;
 	uint8_t *data;
 	int len, totlen = 0;
 	for (; m ; m = m->m_next) {
 		data = mtod(m, uint8_t *);
 		len = m->m_len;
 		if (len > 0) {
 			bus_space_write_region_1(buft, bufh, buf, data, len);
 			totlen += len;
 			buf += len;
+		}
+	}
 	if (totlen < ETHER_MIN_LEN - ETHER_CRC_LEN) {
 		bus_space_set_region_1(buft, bufh, buf, 0,
 		    ETHER_MIN_LEN - ETHER_CRC_LEN - totlen);
 		totlen = ETHER_MIN_LEN - ETHER_CRC_LEN;
+	}
 	return totlen;
+}
 /*
  * Enable power on the interface.
  */
 int
 dp8390_enable(struct dp8390_softc *sc)
+{
 	if (sc->sc_enabled == 0 && sc->sc_enable != NULL) {
 		if ((*sc->sc_enable)(sc) != 0) {
 			aprint_error_dev(sc->sc_dev,
 			    "device enable failed\n");
 			return EIO;
+		}
+	}
 	sc->sc_enabled = 1;
 	return 0;
+}
 /*
  * Disable power on the interface.
  */
 void
 dp8390_disable(struct dp8390_softc *sc)
+{
 	if (sc->sc_enabled != 0 && sc->sc_disable != NULL) {
 		(*sc->sc_disable)(sc);
 		sc->sc_enabled = 0;
+	}
+}
 int
 dp8390_activate(device_t self, enum devact act)
+{
 	struct dp8390_softc *sc = device_private(self);
 	switch (act) {
 	case DVACT_DEACTIVATE:
 		if_deactivate(&sc->sc_ec.ec_if);
 		return 0;
 	default:
 		return EOPNOTSUPP;
+	}
+}
 int
 dp8390_detach(struct dp8390_softc *sc, int flags)
+{
 	struct ifnet *ifp = &sc->sc_ec.ec_if;
 	/* Succeed now if there's no work to do. */
 	if ((sc->sc_flags & DP8390_ATTACHED) == 0)
 		return 0;
 	/* dp8390_disable() checks sc->sc_enabled */
 	dp8390_disable(sc);
 	if (sc->sc_media_fini != NULL)
 		(*sc->sc_media_fini)(sc);
 	/* Delete all remaining media. */
 	ifmedia_delete_instance(&sc->sc_media, IFM_INST_ANY);
 	rnd_detach_source(&sc->rnd_source);
 	ether_ifdetach(ifp);
 	if_detach(ifp);
 	return 0;
+}

 @@ -1,1262 +1,1266 @@
-/*	$NetBSD: dp83932.c,v 1.44 2019/05/28 07:41:48 msaitoh Exp $	*/
+/*	$NetBSD: dp83932.c,v 1.45 2020/01/29 14:14:55 thorpej Exp $	*/
 /*-
  * Copyright (c) 2001 The NetBSD Foundation, Inc.
  * All rights reserved.
+ *
  * This code is derived from software contributed to The NetBSD Foundation
  * by Jason R. Thorpe.
+ *
  * Redistribution and use in source and binary forms, with or without
  * modification, are permitted provided that the following conditions
  * are met:
  * 1. Redistributions of source code must retain the above copyright
  *    notice, this list of conditions and the following disclaimer.
  * 2. Redistributions in binary form must reproduce the above copyright
  *    notice, this list of conditions and the following disclaimer in the
  *    documentation and/or other materials provided with the distribution.
+ *
  * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
  * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
  * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
  * PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
  * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
  * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
  * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
  * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
  * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
  * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
  * POSSIBILITY OF SUCH DAMAGE.
  */
 /*
  * Device driver for the National Semiconductor DP83932
  * Systems-Oriented Network Interface Controller (SONIC).
  */
 #include <sys/cdefs.h>
-__KERNEL_RCSID(0, "$NetBSD: dp83932.c,v 1.44 2019/05/28 07:41:48 msaitoh Exp $");
+__KERNEL_RCSID(0, "$NetBSD: dp83932.c,v 1.45 2020/01/29 14:14:55 thorpej Exp $");
 #include <sys/param.h>
 #include <sys/systm.h>
 #include <sys/mbuf.h>
 #include <sys/malloc.h>
 #include <sys/kernel.h>
 #include <sys/socket.h>
 #include <sys/ioctl.h>
 #include <sys/errno.h>
 #include <sys/device.h>
 #include <net/if.h>
 #include <net/if_dl.h>
 #include <net/if_ether.h>
 #include <net/bpf.h>
 #include <sys/bus.h>
 #include <sys/intr.h>
 #include <dev/ic/dp83932reg.h>
 #include <dev/ic/dp83932var.h>
 static void	sonic_start(struct ifnet *);
 static void	sonic_watchdog(struct ifnet *);
 static int	sonic_ioctl(struct ifnet *, u_long, void *);
 static int	sonic_init(struct ifnet *);
 static void	sonic_stop(struct ifnet *, int);
 static bool	sonic_shutdown(device_t, int);
 static void	sonic_reset(struct sonic_softc *);
 static void	sonic_rxdrain(struct sonic_softc *);
 static int	sonic_add_rxbuf(struct sonic_softc *, int);
 static void	sonic_set_filter(struct sonic_softc *);
 static uint16_t sonic_txintr(struct sonic_softc *);
 static void	sonic_rxintr(struct sonic_softc *);
 int	sonic_copy_small = 0;
 #define ETHER_PAD_LEN (ETHER_MIN_LEN - ETHER_CRC_LEN)
 /*
  * sonic_attach:
+ *
  *	Attach a SONIC interface to the system.
  */
 void
 sonic_attach(struct sonic_softc *sc, const uint8_t *enaddr)
+{
 	struct ifnet *ifp = &sc->sc_ethercom.ec_if;
 	int i, rseg, error;
 	bus_dma_segment_t seg;
 	size_t cdatasize;
 	uint8_t *nullbuf;
 	/*
 	 * Allocate the control data structures, and create and load the
 	 * DMA map for it.
 	 */
 	if (sc->sc_32bit)
 		cdatasize = sizeof(struct sonic_control_data32);
 	else
 		cdatasize = sizeof(struct sonic_control_data16);
 	if ((error = bus_dmamem_alloc(sc->sc_dmat, cdatasize + ETHER_PAD_LEN,
 	     PAGE_SIZE, (64 * 1024), &seg, 1, &rseg,
 	     BUS_DMA_NOWAIT)) != 0) {
 		aprint_error_dev(sc->sc_dev,
 		    "unable to allocate control data, error = %d\n", error);
 		goto fail_0;
+	}
 	if ((error = bus_dmamem_map(sc->sc_dmat, &seg, rseg,
 	    cdatasize + ETHER_PAD_LEN, (void **) &sc->sc_cdata16,
 	    BUS_DMA_NOWAIT | BUS_DMA_COHERENT)) != 0) {
 		aprint_error_dev(sc->sc_dev,
 		    "unable to map control data, error = %d\n", error);
 		goto fail_1;
+	}
 	nullbuf = (uint8_t *)sc->sc_cdata16 + cdatasize;
 	memset(nullbuf, 0, ETHER_PAD_LEN);
 	if ((error = bus_dmamap_create(sc->sc_dmat,
 	     cdatasize, 1, cdatasize, 0, BUS_DMA_NOWAIT,
 	     &sc->sc_cddmamap)) != 0) {
 		aprint_error_dev(sc->sc_dev,
 		    "unable to create control data DMA map, error = %d\n",
 		    error);
 		goto fail_2;
+	}
 	if ((error = bus_dmamap_load(sc->sc_dmat, sc->sc_cddmamap,
 	     sc->sc_cdata16, cdatasize, NULL, BUS_DMA_NOWAIT)) != 0) {
 		aprint_error_dev(sc->sc_dev,
 		    "unable to load control data DMA map, error = %d\n", error);
 		goto fail_3;
+	}
 	/*
 	 * Create the transmit buffer DMA maps.
 	 */
 	for (i = 0; i < SONIC_NTXDESC; i++) {
 		if ((error = bus_dmamap_create(sc->sc_dmat, MCLBYTES,
 		     SONIC_NTXFRAGS, MCLBYTES, 0, BUS_DMA_NOWAIT,
 		     &sc->sc_txsoft[i].ds_dmamap)) != 0) {
 			aprint_error_dev(sc->sc_dev,
 			    "unable to create tx DMA map %d, error = %d\n",
 			    i, error);
 			goto fail_4;
+		}
+	}
 	/*
 	 * Create the receive buffer DMA maps.
 	 */
 	for (i = 0; i < SONIC_NRXDESC; i++) {
 		if ((error = bus_dmamap_create(sc->sc_dmat, MCLBYTES, 1,
 		     MCLBYTES, 0, BUS_DMA_NOWAIT,
 		     &sc->sc_rxsoft[i].ds_dmamap)) != 0) {
 			aprint_error_dev(sc->sc_dev,
 			    "unable to create rx DMA map %d, error = %d\n",
 			    i, error);
 			goto fail_5;
+		}
 		sc->sc_rxsoft[i].ds_mbuf = NULL;
+	}
 	/*
 	 * create and map the pad buffer
 	 */
 	if ((error = bus_dmamap_create(sc->sc_dmat, ETHER_PAD_LEN, 1,
 	    ETHER_PAD_LEN, 0, BUS_DMA_NOWAIT, &sc->sc_nulldmamap)) != 0) {
 		aprint_error_dev(sc->sc_dev,
 		    "unable to create pad buffer DMA map, error = %d\n", error);
 		goto fail_5;
+	}
 	if ((error = bus_dmamap_load(sc->sc_dmat, sc->sc_nulldmamap,
 	    nullbuf, ETHER_PAD_LEN, NULL, BUS_DMA_NOWAIT)) != 0) {
 		aprint_error_dev(sc->sc_dev,
 		    "unable to load pad buffer DMA map, error = %d\n", error);
 		goto fail_6;
+	}
 	bus_dmamap_sync(sc->sc_dmat, sc->sc_nulldmamap, 0, ETHER_PAD_LEN,
 	    BUS_DMASYNC_PREWRITE);
 	/*
 	 * Reset the chip to a known state.
 	 */
 	sonic_reset(sc);
 	aprint_normal_dev(sc->sc_dev, "Ethernet address %s\n",
 	    ether_sprintf(enaddr));
 	strlcpy(ifp->if_xname, device_xname(sc->sc_dev), IFNAMSIZ);
 	ifp->if_softc = sc;
 	ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST;
 	ifp->if_ioctl = sonic_ioctl;
 	ifp->if_start = sonic_start;
 	ifp->if_watchdog = sonic_watchdog;
 	ifp->if_init = sonic_init;
 	ifp->if_stop = sonic_stop;
 	IFQ_SET_READY(&ifp->if_snd);
 	/*
 	 * We can support 802.1Q VLAN-sized frames.
 	 */
 	sc->sc_ethercom.ec_capabilities |= ETHERCAP_VLAN_MTU;
 	/*
 	 * Attach the interface.
 	 */
 	if_attach(ifp);
 	if_deferred_start_init(ifp, NULL);
 	ether_ifattach(ifp, enaddr);
 	/*
 	 * Make sure the interface is shutdown during reboot.
 	 */
 	if (pmf_device_register1(sc->sc_dev, NULL, NULL, sonic_shutdown))
 		pmf_class_network_register(sc->sc_dev, ifp);
 	else
 		aprint_error_dev(sc->sc_dev,
 		    "couldn't establish power handler\n");
 	return;
 	/*
 	 * Free any resources we've allocated during the failed attach
 	 * attempt.  Do this in reverse order and fall through.
 	 */
  fail_6:
 	bus_dmamap_destroy(sc->sc_dmat, sc->sc_nulldmamap);
  fail_5:
 	for (i = 0; i < SONIC_NRXDESC; i++) {
 		if (sc->sc_rxsoft[i].ds_dmamap != NULL)
 			bus_dmamap_destroy(sc->sc_dmat,
 			    sc->sc_rxsoft[i].ds_dmamap);
+	}
  fail_4:
 	for (i = 0; i < SONIC_NTXDESC; i++) {
 		if (sc->sc_txsoft[i].ds_dmamap != NULL)
 			bus_dmamap_destroy(sc->sc_dmat,
 			    sc->sc_txsoft[i].ds_dmamap);
+	}
 	bus_dmamap_unload(sc->sc_dmat, sc->sc_cddmamap);
  fail_3:
 	bus_dmamap_destroy(sc->sc_dmat, sc->sc_cddmamap);
  fail_2:
 	bus_dmamem_unmap(sc->sc_dmat, (void *)sc->sc_cdata16, cdatasize);
  fail_1:
 	bus_dmamem_free(sc->sc_dmat, &seg, rseg);
  fail_0:
 	return;
+}
 /*
  * sonic_shutdown:
+ *
  *	Make sure the interface is stopped at reboot.
  */
 bool
 sonic_shutdown(device_t self, int howto)
+{
 	struct sonic_softc *sc = device_private(self);
 	sonic_stop(&sc->sc_ethercom.ec_if, 1);
 	return true;
+}
 /*
  * sonic_start:		[ifnet interface function]
+ *
  *	Start packet transmission on the interface.
  */
 void
 sonic_start(struct ifnet *ifp)
+{
 	struct sonic_softc *sc = ifp->if_softc;
 	struct mbuf *m0, *m;
 	struct sonic_tda16 *tda16;
 	struct sonic_tda32 *tda32;
 	struct sonic_descsoft *ds;
 	bus_dmamap_t dmamap;
 	int error, olasttx, nexttx, opending, totlen, olseg;
 	int seg = 0;	/* XXX: gcc */
 	if ((ifp->if_flags & (IFF_RUNNING | IFF_OACTIVE)) != IFF_RUNNING)
 		return;
 	/*
 	 * Remember the previous txpending and the current "last txdesc
 	 * used" index.
 	 */
 	opending = sc->sc_txpending;
 	olasttx = sc->sc_txlast;
 	/*
 	 * Loop through the send queue, setting up transmit descriptors
 	 * until we drain the queue, or use up all available transmit
 	 * descriptors.  Leave one at the end for sanity's sake.
 	 */
 	while (sc->sc_txpending < (SONIC_NTXDESC - 1)) {
 		/*
 		 * Grab a packet off the queue.
 		 */
 		IFQ_POLL(&ifp->if_snd, m0);
 		if (m0 == NULL)
 			break;
 		m = NULL;
 		/*
 		 * Get the next available transmit descriptor.
 		 */
 		nexttx = SONIC_NEXTTX(sc->sc_txlast);
 		ds = &sc->sc_txsoft[nexttx];
 		dmamap = ds->ds_dmamap;
 		/*
 		 * Load the DMA map.  If this fails, the packet either
 		 * didn't fit in the allotted number of frags, or we were
 		 * short on resources.  In this case, we'll copy and try
 		 * again.
 		 */
 		if ((error = bus_dmamap_load_mbuf(sc->sc_dmat, dmamap, m0,
 		    BUS_DMA_WRITE | BUS_DMA_NOWAIT)) != 0 ||
 		    (m0->m_pkthdr.len < ETHER_PAD_LEN &&
 		    dmamap->dm_nsegs == SONIC_NTXFRAGS)) {
 			if (error == 0)
 				bus_dmamap_unload(sc->sc_dmat, dmamap);
 			MGETHDR(m, M_DONTWAIT, MT_DATA);
 			if (m == NULL) {
 				printf("%s: unable to allocate Tx mbuf\n",
 				    device_xname(sc->sc_dev));
 				break;
+			}
 			if (m0->m_pkthdr.len > MHLEN) {
 				MCLGET(m, M_DONTWAIT);
 				if ((m->m_flags & M_EXT) == 0) {
 					printf("%s: unable to allocate Tx "
 					    "cluster\n",
 					    device_xname(sc->sc_dev));
 					m_freem(m);
 					break;
+				}
+			}
 			m_copydata(m0, 0, m0->m_pkthdr.len, mtod(m, void *));
 			m->m_pkthdr.len = m->m_len = m0->m_pkthdr.len;
 			error = bus_dmamap_load_mbuf(sc->sc_dmat, dmamap,
 			    m, BUS_DMA_WRITE | BUS_DMA_NOWAIT);
 			if (error) {
 				printf("%s: unable to load Tx buffer, "
 				    "error = %d\n", device_xname(sc->sc_dev),
 				    error);
 				m_freem(m);
 				break;
+			}
+		}
 		IFQ_DEQUEUE(&ifp->if_snd, m0);
 		if (m != NULL) {
 			m_freem(m0);
 			m0 = m;
+		}
 		/*
 		 * WE ARE NOW COMMITTED TO TRANSMITTING THE PACKET.
 		 */
 		/* Sync the DMA map. */
 		bus_dmamap_sync(sc->sc_dmat, dmamap, 0, dmamap->dm_mapsize,
 		    BUS_DMASYNC_PREWRITE);
 		/*
 		 * Store a pointer to the packet so we can free it later.
 		 */
 		ds->ds_mbuf = m0;
 		/*
 		 * Initialize the transmit descriptor.
 		 */
 		totlen = 0;
 		if (sc->sc_32bit) {
 			tda32 = &sc->sc_tda32[nexttx];
 			for (seg = 0; seg < dmamap->dm_nsegs; seg++) {
 				tda32->tda_frags[seg].frag_ptr1 =
 				    htosonic32(sc,
 				    (dmamap->dm_segs[seg].ds_addr >> 16) &
 xffff);
 				tda32->tda_frags[seg].frag_ptr0 =
 				    htosonic32(sc,
 				    dmamap->dm_segs[seg].ds_addr & 0xffff);
 				tda32->tda_frags[seg].frag_size =
 				    htosonic32(sc, dmamap->dm_segs[seg].ds_len);
 				totlen += dmamap->dm_segs[seg].ds_len;
+			}
 			if (totlen < ETHER_PAD_LEN) {
 				tda32->tda_frags[seg].frag_ptr1 =
 				    htosonic32(sc,
 				    (sc->sc_nulldma >> 16) & 0xffff);
 				tda32->tda_frags[seg].frag_ptr0 =
 				    htosonic32(sc, sc->sc_nulldma & 0xffff);
 				tda32->tda_frags[seg].frag_size =
 				    htosonic32(sc, ETHER_PAD_LEN - totlen);
 				totlen = ETHER_PAD_LEN;
 				seg++;
+			}
 			tda32->tda_status = 0;
 			tda32->tda_pktconfig = 0;
 			tda32->tda_pktsize = htosonic32(sc, totlen);
 			tda32->tda_fragcnt = htosonic32(sc, seg);
 			/* Link it up. */
 			tda32->tda_frags[seg].frag_ptr0 =
 			    htosonic32(sc, SONIC_CDTXADDR32(sc,
 			    SONIC_NEXTTX(nexttx)) & 0xffff);
 			/* Sync the Tx descriptor. */
 			SONIC_CDTXSYNC32(sc, nexttx,
 			    BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
 		} else {
 			tda16 = &sc->sc_tda16[nexttx];
 			for (seg = 0; seg < dmamap->dm_nsegs; seg++) {
 				tda16->tda_frags[seg].frag_ptr1 =
 				    htosonic16(sc,
 				    (dmamap->dm_segs[seg].ds_addr >> 16) &
 xffff);
 				tda16->tda_frags[seg].frag_ptr0 =
 				    htosonic16(sc,
 				    dmamap->dm_segs[seg].ds_addr & 0xffff);
 				tda16->tda_frags[seg].frag_size =
 				    htosonic16(sc, dmamap->dm_segs[seg].ds_len);
 				totlen += dmamap->dm_segs[seg].ds_len;
+			}
 			if (totlen < ETHER_PAD_LEN) {
 				tda16->tda_frags[seg].frag_ptr1 =
 				    htosonic16(sc,
 				    (sc->sc_nulldma >> 16) & 0xffff);
 				tda16->tda_frags[seg].frag_ptr0 =
 				    htosonic16(sc, sc->sc_nulldma & 0xffff);
 				tda16->tda_frags[seg].frag_size =
 				    htosonic16(sc, ETHER_PAD_LEN - totlen);
 				totlen = ETHER_PAD_LEN;
 				seg++;
+			}
 			tda16->tda_status = 0;
 			tda16->tda_pktconfig = 0;
 			tda16->tda_pktsize = htosonic16(sc, totlen);
 			tda16->tda_fragcnt = htosonic16(sc, seg);
 			/* Link it up. */
 			tda16->tda_frags[seg].frag_ptr0 =
 			    htosonic16(sc, SONIC_CDTXADDR16(sc,
 			    SONIC_NEXTTX(nexttx)) & 0xffff);
 			/* Sync the Tx descriptor. */
 			SONIC_CDTXSYNC16(sc, nexttx,
 			    BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
+		}
 		/* Advance the Tx pointer. */
 		sc->sc_txpending++;
 		sc->sc_txlast = nexttx;
 		/*
 		 * Pass the packet to any BPF listeners.
 		 */
 		bpf_mtap(ifp, m0, BPF_D_OUT);
+	}
 	if (sc->sc_txpending == (SONIC_NTXDESC - 1)) {
 		/* No more slots left; notify upper layer. */
 		ifp->if_flags |= IFF_OACTIVE;
+	}
 	if (sc->sc_txpending != opending) {
 		/*
 		 * We enqueued packets.  If the transmitter was idle,
 		 * reset the txdirty pointer.
 		 */
 		if (opending == 0)
 			sc->sc_txdirty = SONIC_NEXTTX(olasttx);
 		/*
 		 * Stop the SONIC on the last packet we've set up,
 		 * and clear end-of-list on the descriptor previous
 		 * to our new chain.
+		 *
 		 * NOTE: our `seg' variable should still be valid!
 		 */
 		if (sc->sc_32bit) {
 			olseg =
 			    sonic32toh(sc, sc->sc_tda32[olasttx].tda_fragcnt);
 			sc->sc_tda32[sc->sc_txlast].tda_frags[seg].frag_ptr0 |=
 			    htosonic32(sc, TDA_LINK_EOL);
 			SONIC_CDTXSYNC32(sc, sc->sc_txlast,
 			    BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
 			sc->sc_tda32[olasttx].tda_frags[olseg].frag_ptr0 &=
 			    htosonic32(sc, ~TDA_LINK_EOL);
 			SONIC_CDTXSYNC32(sc, olasttx,
 			    BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
 		} else {
 			olseg =
 			    sonic16toh(sc, sc->sc_tda16[olasttx].tda_fragcnt);
 			sc->sc_tda16[sc->sc_txlast].tda_frags[seg].frag_ptr0 |=
 			    htosonic16(sc, TDA_LINK_EOL);
 			SONIC_CDTXSYNC16(sc, sc->sc_txlast,
 			    BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
 			sc->sc_tda16[olasttx].tda_frags[olseg].frag_ptr0 &=
 			    htosonic16(sc, ~TDA_LINK_EOL);
 			SONIC_CDTXSYNC16(sc, olasttx,
 			    BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
+		}
 		/* Start the transmitter. */
 		CSR_WRITE(sc, SONIC_CR, CR_TXP);
 		/* Set a watchdog timer in case the chip flakes out. */
 		ifp->if_timer = 5;
+	}
+}
 /*
  * sonic_watchdog:	[ifnet interface function]
+ *
  *	Watchdog timer handler.
  */
 void
 sonic_watchdog(struct ifnet *ifp)
+{
 	struct sonic_softc *sc = ifp->if_softc;
 	printf("%s: device timeout\n", device_xname(sc->sc_dev));
-	ifp->if_oerrors++;
+	if_statinc(ifp, if_oerrors);
 	(void)sonic_init(ifp);
+}
 /*
  * sonic_ioctl:		[ifnet interface function]
+ *
  *	Handle control requests from the operator.
  */
 int
 sonic_ioctl(struct ifnet *ifp, u_long cmd, void *data)
+{
 	int s, error;
 	s = splnet();
 	error = ether_ioctl(ifp, cmd, data);
 	if (error == ENETRESET) {
 		/*
 		 * Multicast list has changed; set the hardware
 		 * filter accordingly.
 		 */
 		if (ifp->if_flags & IFF_RUNNING)
 			(void)sonic_init(ifp);
 		error = 0;
+	}
 	splx(s);
 	return error;
+}
 /*
  * sonic_intr:
+ *
  *	Interrupt service routine.
  */
 int
 sonic_intr(void *arg)
+{
 	struct sonic_softc *sc = arg;
 	struct ifnet *ifp = &sc->sc_ethercom.ec_if;
 	uint16_t isr;
 	int handled = 0, wantinit;
 	for (wantinit = 0; wantinit == 0;) {
 		isr = CSR_READ(sc, SONIC_ISR) & sc->sc_imr;
 		if (isr == 0)
 			break;
 		CSR_WRITE(sc, SONIC_ISR, isr);	/* ACK */
 		handled = 1;
 		if (isr & IMR_PRX)
 			sonic_rxintr(sc);
 		if (isr & (IMR_PTX | IMR_TXER)) {
 			if (sonic_txintr(sc) & TCR_FU) {
 				printf("%s: transmit FIFO underrun\n",
 				    device_xname(sc->sc_dev));
 				wantinit = 1;
+			}
+		}
 		if (isr & (IMR_RFO | IMR_RBA | IMR_RBE | IMR_RDE)) {
 #define	PRINTERR(bit, str)						\
 			if (isr & (bit))				\
 				printf("%s: %s\n",device_xname(sc->sc_dev), str)
 			PRINTERR(IMR_RFO, "receive FIFO overrun");
 			PRINTERR(IMR_RBA, "receive buffer exceeded");
 			PRINTERR(IMR_RBE, "receive buffers exhausted");
 			PRINTERR(IMR_RDE, "receive descriptors exhausted");
 			wantinit = 1;
+		}
+	}
 	if (handled) {
 		if (wantinit)
 			(void)sonic_init(ifp);
 		if_schedule_deferred_start(ifp);
+	}
 	return handled;
+}
 /*
  * sonic_txintr:
+ *
  *	Helper; handle transmit complete interrupts.
  */
 uint16_t
 sonic_txintr(struct sonic_softc *sc)
+{
 	struct ifnet *ifp = &sc->sc_ethercom.ec_if;
 	struct sonic_descsoft *ds;
 	struct sonic_tda32 *tda32;
 	struct sonic_tda16 *tda16;
 	uint16_t status, totstat = 0;
 	int i;
 	ifp->if_flags &= ~IFF_OACTIVE;
 	for (i = sc->sc_txdirty; sc->sc_txpending != 0;
 	     i = SONIC_NEXTTX(i), sc->sc_txpending--) {
 		ds = &sc->sc_txsoft[i];
 		if (sc->sc_32bit) {
 			SONIC_CDTXSYNC32(sc, i,
 			    BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE);
 			tda32 = &sc->sc_tda32[i];
 			status = sonic32toh(sc, tda32->tda_status);
 			SONIC_CDTXSYNC32(sc, i, BUS_DMASYNC_PREREAD);
 		} else {
 			SONIC_CDTXSYNC16(sc, i,
 			    BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE);
 			tda16 = &sc->sc_tda16[i];
 			status = sonic16toh(sc, tda16->tda_status);
 			SONIC_CDTXSYNC16(sc, i, BUS_DMASYNC_PREREAD);
+		}
 		if ((status & ~(TCR_EXDIS |TCR_CRCI |TCR_POWC |TCR_PINT)) == 0)
 			break;
 		totstat |= status;
 		bus_dmamap_sync(sc->sc_dmat, ds->ds_dmamap, 0,
 		    ds->ds_dmamap->dm_mapsize, BUS_DMASYNC_POSTWRITE);
 		bus_dmamap_unload(sc->sc_dmat, ds->ds_dmamap);
 		m_freem(ds->ds_mbuf);
 		ds->ds_mbuf = NULL;
 		/*
 		 * Check for errors and collisions.
 		 */
 		net_stat_ref_t nsr = IF_STAT_GETREF(ifp);
 		if (status & TCR_PTX)
-			ifp->if_opackets++;
+			if_statinc_ref(nsr, if_opackets);
 		else
-			ifp->if_oerrors++;
+			if_statinc_ref(nsr, if_oerrors);
-		ifp->if_collisions += TDA_STATUS_NCOL(status);
+		if (TDA_STATUS_NCOL(status))
 			if_statadd_ref(nsr, if_collisions,
 			    TDA_STATUS_NCOL(status));
 		IF_STAT_PUTREF(ifp);
+	}
 	/* Update the dirty transmit buffer pointer. */
 	sc->sc_txdirty = i;
 	/*
 	 * Cancel the watchdog timer if there are no pending
 	 * transmissions.
 	 */
 	if (sc->sc_txpending == 0)
 		ifp->if_timer = 0;
 	return totstat;
+}
 /*
  * sonic_rxintr:
+ *
  *	Helper; handle receive interrupts.
  */
 void
 sonic_rxintr(struct sonic_softc *sc)
+{
 	struct ifnet *ifp = &sc->sc_ethercom.ec_if;
 	struct sonic_descsoft *ds;
 	struct sonic_rda32 *rda32;
 	struct sonic_rda16 *rda16;
 	struct mbuf *m;
 	int i, len;
 	uint16_t status, bytecount /*, ptr0, ptr1, seqno */;
 	for (i = sc->sc_rxptr;; i = SONIC_NEXTRX(i)) {
 		ds = &sc->sc_rxsoft[i];
 		if (sc->sc_32bit) {
 			SONIC_CDRXSYNC32(sc, i,
 			    BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE);
 			rda32 = &sc->sc_rda32[i];
 			SONIC_CDRXSYNC32(sc, i, BUS_DMASYNC_PREREAD);
 			if (rda32->rda_inuse != 0)
 				break;
 			status = sonic32toh(sc, rda32->rda_status);
 			bytecount = sonic32toh(sc, rda32->rda_bytecount);
 			/* ptr0 = sonic32toh(sc, rda32->rda_pkt_ptr0); */
 			/* ptr1 = sonic32toh(sc, rda32->rda_pkt_ptr1); */
 			/* seqno = sonic32toh(sc, rda32->rda_seqno); */
 		} else {
 			SONIC_CDRXSYNC16(sc, i,
 			    BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE);
 			rda16 = &sc->sc_rda16[i];
 			SONIC_CDRXSYNC16(sc, i, BUS_DMASYNC_PREREAD);
 			if (rda16->rda_inuse != 0)
 				break;
 			status = sonic16toh(sc, rda16->rda_status);
 			bytecount = sonic16toh(sc, rda16->rda_bytecount);
 			/* ptr0 = sonic16toh(sc, rda16->rda_pkt_ptr0); */
 			/* ptr1 = sonic16toh(sc, rda16->rda_pkt_ptr1); */
 			/* seqno = sonic16toh(sc, rda16->rda_seqno); */
+		}
 		/*
 		 * Make absolutely sure this is the only packet
 		 * in this receive buffer.  Our entire Rx buffer
 		 * management scheme depends on this, and if the
 		 * SONIC didn't follow our rule, it means we've
 		 * misconfigured it.
 		 */
 		KASSERT(status & RCR_LPKT);
 		/*
 		 * Make sure the packet arrived OK.  If an error occurred,
 		 * update stats and reset the descriptor.  The buffer will
 		 * be reused the next time the descriptor comes up in the
 		 * ring.
 		 */
 		if ((status & RCR_PRX) == 0) {
 			if (status & RCR_FAER)
 				printf("%s: Rx frame alignment error\n",
 				    device_xname(sc->sc_dev));
 			else if (status & RCR_CRCR)
 				printf("%s: Rx CRC error\n",
 				    device_xname(sc->sc_dev));
-			ifp->if_ierrors++;
+			if_statinc(ifp, if_ierrors);
 			SONIC_INIT_RXDESC(sc, i);
 			continue;
+		}
 		bus_dmamap_sync(sc->sc_dmat, ds->ds_dmamap, 0,
 		    ds->ds_dmamap->dm_mapsize, BUS_DMASYNC_POSTREAD);
 		/*
 		 * The SONIC includes the CRC with every packet.
 		 */
 		len = bytecount - ETHER_CRC_LEN;
 		/*
 		 * Ok, if the chip is in 32-bit mode, then receive
 		 * buffers must be aligned to 32-bit boundaries,
 		 * which means the payload is misaligned.  In this
 		 * case, we must allocate a new mbuf, and copy the
 		 * packet into it, scooted forward 2 bytes to ensure
 		 * proper alignment.
+		 *
 		 * Note, in 16-bit mode, we can configure the SONIC
 		 * to do what we want, and we have.
 		 */
 #ifndef __NO_STRICT_ALIGNMENT
 		if (sc->sc_32bit) {
 			MGETHDR(m, M_DONTWAIT, MT_DATA);
 			if (m == NULL)
 				goto dropit;
 			if (len > (MHLEN - 2)) {
 				MCLGET(m, M_DONTWAIT);
 				if ((m->m_flags & M_EXT) == 0) {
 					m_freem(m);
 					goto dropit;
+				}
+			}
 			m->m_data += 2;
 			/*
 			 * Note that we use a cluster for incoming frames,
 			 * so the buffer is virtually contiguous.
 			 */
 			memcpy(mtod(m, void *), mtod(ds->ds_mbuf, void *),
 			    len);
 			SONIC_INIT_RXDESC(sc, i);
 			bus_dmamap_sync(sc->sc_dmat, ds->ds_dmamap, 0,
 			    ds->ds_dmamap->dm_mapsize, BUS_DMASYNC_PREREAD);
 		} else
 #endif /* ! __NO_STRICT_ALIGNMENT */
 		/*
 		 * If the packet is small enough to fit in a single
 		 * header mbuf, allocate one and copy the data into
 		 * it.  This greatly reduces memory consumption when
 		 * we receive lots of small packets.
 		 */
 		if (sonic_copy_small != 0 && len <= (MHLEN - 2)) {
 			MGETHDR(m, M_DONTWAIT, MT_DATA);
 			if (m == NULL)
 				goto dropit;
 			m->m_data += 2;
 			/*
 			 * Note that we use a cluster for incoming frames,
 			 * so the buffer is virtually contiguous.
 			 */
 			memcpy(mtod(m, void *), mtod(ds->ds_mbuf, void *),
 			    len);
 			SONIC_INIT_RXDESC(sc, i);
 			bus_dmamap_sync(sc->sc_dmat, ds->ds_dmamap, 0,
 			    ds->ds_dmamap->dm_mapsize, BUS_DMASYNC_PREREAD);
 		} else {
 			m = ds->ds_mbuf;
 			if (sonic_add_rxbuf(sc, i) != 0) {
  dropit:
-				ifp->if_ierrors++;
+				if_statinc(ifp, if_ierrors);
 				SONIC_INIT_RXDESC(sc, i);
 				bus_dmamap_sync(sc->sc_dmat, ds->ds_dmamap, 0,
 				    ds->ds_dmamap->dm_mapsize,
 				    BUS_DMASYNC_PREREAD);
 				continue;
+			}
+		}
 		m_set_rcvif(m, ifp);
 		m->m_pkthdr.len = m->m_len = len;
 		/* Pass it on. */
 		if_percpuq_enqueue(ifp->if_percpuq, m);
+	}
 	/* Update the receive pointer. */
 	sc->sc_rxptr = i;
 	CSR_WRITE(sc, SONIC_RWR, SONIC_CDRRADDR(sc, SONIC_PREVRX(i)));
+}
 /*
  * sonic_reset:
+ *
  *	Perform a soft reset on the SONIC.
  */
 void
 sonic_reset(struct sonic_softc *sc)
+{
 	/* stop TX, RX and timer, and ensure RST is clear */
 	CSR_WRITE(sc, SONIC_CR, CR_STP | CR_RXDIS | CR_HTX);
 	delay(1000);
 	CSR_WRITE(sc, SONIC_CR, CR_RST);
 	delay(1000);
 	/* clear all interrupts */
 	CSR_WRITE(sc, SONIC_IMR, 0);
 	CSR_WRITE(sc, SONIC_ISR, IMR_ALL);
 	CSR_WRITE(sc, SONIC_CR, 0);
 	delay(1000);
+}
 /*
  * sonic_init:		[ifnet interface function]
+ *
  *	Initialize the interface.  Must be called at splnet().
  */
 int
 sonic_init(struct ifnet *ifp)
+{
 	struct sonic_softc *sc = ifp->if_softc;
 	struct sonic_descsoft *ds;
 	int i, error = 0;
 	uint16_t reg;
 	/*
 	 * Cancel any pending I/O.
 	 */
 	sonic_stop(ifp, 0);
 	/*
 	 * Reset the SONIC to a known state.
 	 */
 	sonic_reset(sc);
 	/*
 	 * Bring the SONIC into reset state, and program the DCR.
+	 *
 	 * Note: We don't bother optimizing the transmit and receive
 	 * thresholds, here. TFT/RFT values should be set in MD attachments.
 	 */
 	reg = sc->sc_dcr;
 	if (sc->sc_32bit)
 		reg |= DCR_DW;
 	CSR_WRITE(sc, SONIC_CR, CR_RST);
 	CSR_WRITE(sc, SONIC_DCR, reg);
 	CSR_WRITE(sc, SONIC_DCR2, sc->sc_dcr2);
 	CSR_WRITE(sc, SONIC_CR, 0);
 	/*
 	 * Initialize the transmit descriptors.
 	 */
 	if (sc->sc_32bit) {
 		for (i = 0; i < SONIC_NTXDESC; i++) {
 			memset(&sc->sc_tda32[i], 0, sizeof(struct sonic_tda32));
 			SONIC_CDTXSYNC32(sc, i,
 			    BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
+		}
 	} else {
 		for (i = 0; i < SONIC_NTXDESC; i++) {
 			memset(&sc->sc_tda16[i], 0, sizeof(struct sonic_tda16));
 			SONIC_CDTXSYNC16(sc, i,
 			    BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
+		}
+	}
 	sc->sc_txpending = 0;
 	sc->sc_txdirty = 0;
 	sc->sc_txlast = SONIC_NTXDESC - 1;
 	/*
 	 * Initialize the receive descriptor ring.
 	 */
 	for (i = 0; i < SONIC_NRXDESC; i++) {
 		ds = &sc->sc_rxsoft[i];
 		if (ds->ds_mbuf == NULL) {
 			if ((error = sonic_add_rxbuf(sc, i)) != 0) {
 				printf("%s: unable to allocate or map Rx "
 				    "buffer %d, error = %d\n",
 				    device_xname(sc->sc_dev), i, error);
 				/*
 				 * XXX Should attempt to run with fewer receive
 				 * XXX buffers instead of just failing.
 				 */
 				sonic_rxdrain(sc);
 				goto out;
+			}
 		} else
 			SONIC_INIT_RXDESC(sc, i);
+	}
 	sc->sc_rxptr = 0;
 	/* Give the transmit ring to the SONIC. */
 	CSR_WRITE(sc, SONIC_UTDAR, (SONIC_CDTXADDR(sc, 0) >> 16) & 0xffff);
 	CSR_WRITE(sc, SONIC_CTDAR, SONIC_CDTXADDR(sc, 0) & 0xffff);
 	/* Give the receive descriptor ring to the SONIC. */
 	CSR_WRITE(sc, SONIC_URDAR, (SONIC_CDRXADDR(sc, 0) >> 16) & 0xffff);
 	CSR_WRITE(sc, SONIC_CRDAR, SONIC_CDRXADDR(sc, 0) & 0xffff);
 	/* Give the receive buffer ring to the SONIC. */
 	CSR_WRITE(sc, SONIC_URRAR, (SONIC_CDRRADDR(sc, 0) >> 16) & 0xffff);
 	CSR_WRITE(sc, SONIC_RSAR, SONIC_CDRRADDR(sc, 0) & 0xffff);
 	if (sc->sc_32bit)
 		CSR_WRITE(sc, SONIC_REAR,
 		    (SONIC_CDRRADDR(sc, SONIC_NRXDESC - 1) +
 		    sizeof(struct sonic_rra32)) & 0xffff);
 	else
 		CSR_WRITE(sc, SONIC_REAR,
 		    (SONIC_CDRRADDR(sc, SONIC_NRXDESC - 1) +
 		    sizeof(struct sonic_rra16)) & 0xffff);
 	CSR_WRITE(sc, SONIC_RRR, SONIC_CDRRADDR(sc, 0) & 0xffff);
 	CSR_WRITE(sc, SONIC_RWR, SONIC_CDRRADDR(sc, SONIC_NRXDESC - 1));
 	/*
 	 * Set the End-Of-Buffer counter such that only one packet
 	 * will be placed into each buffer we provide.  Note we are
 	 * following the recommendation of section 3.4.4 of the manual
 	 * here, and have "lengthened" the receive buffers accordingly.
 	 */
 	if (sc->sc_32bit)
 		CSR_WRITE(sc, SONIC_EOBC, (ETHER_MAX_LEN + 2) / 2);
 	else
 		CSR_WRITE(sc, SONIC_EOBC, (ETHER_MAX_LEN / 2));
 	/* Reset the receive sequence counter. */
 	CSR_WRITE(sc, SONIC_RSC, 0);
 	/* Clear the tally registers. */
 	CSR_WRITE(sc, SONIC_CRCETC, 0xffff);
 	CSR_WRITE(sc, SONIC_FAET, 0xffff);
 	CSR_WRITE(sc, SONIC_MPT, 0xffff);
 	/* Set the receive filter. */
 	sonic_set_filter(sc);
 	/*
 	 * Set the interrupt mask register.
 	 */
 	sc->sc_imr = IMR_RFO | IMR_RBA | IMR_RBE | IMR_RDE |
 	    IMR_TXER | IMR_PTX | IMR_PRX;
 	CSR_WRITE(sc, SONIC_IMR, sc->sc_imr);
 	/*
 	 * Start the receive process in motion.  Note, we don't
 	 * start the transmit process until we actually try to
 	 * transmit packets.
 	 */
 	CSR_WRITE(sc, SONIC_CR, CR_RXEN | CR_RRRA);
 	/*
 	 * ...all done!
 	 */
 	ifp->if_flags |= IFF_RUNNING;
 	ifp->if_flags &= ~IFF_OACTIVE;
  out:
 	if (error)
 		printf("%s: interface not running\n", device_xname(sc->sc_dev));
 	return error;
+}
 /*
  * sonic_rxdrain:
+ *
  *	Drain the receive queue.
  */
 void
 sonic_rxdrain(struct sonic_softc *sc)
+{
 	struct sonic_descsoft *ds;
 	int i;
 	for (i = 0; i < SONIC_NRXDESC; i++) {
 		ds = &sc->sc_rxsoft[i];
 		if (ds->ds_mbuf != NULL) {
 			bus_dmamap_unload(sc->sc_dmat, ds->ds_dmamap);
 			m_freem(ds->ds_mbuf);
 			ds->ds_mbuf = NULL;
+		}
+	}
+}
 /*
  * sonic_stop:		[ifnet interface function]
+ *
  *	Stop transmission on the interface.
  */
 void
 sonic_stop(struct ifnet *ifp, int disable)
+{
 	struct sonic_softc *sc = ifp->if_softc;
 	struct sonic_descsoft *ds;
 	int i;
 	/*
 	 * Disable interrupts.
 	 */
 	CSR_WRITE(sc, SONIC_IMR, 0);
 	/*
 	 * Stop the transmitter, receiver, and timer.
 	 */
 	CSR_WRITE(sc, SONIC_CR, CR_HTX | CR_RXDIS | CR_STP);
 	for (i = 0; i < 1000; i++) {
 		if ((CSR_READ(sc, SONIC_CR) & (CR_TXP | CR_RXEN | CR_ST)) == 0)
 			break;
 		delay(2);
+	}
 	if ((CSR_READ(sc, SONIC_CR) & (CR_TXP | CR_RXEN | CR_ST)) != 0)
 		printf("%s: SONIC failed to stop\n", device_xname(sc->sc_dev));
 	/*
 	 * Release any queued transmit buffers.
 	 */
 	for (i = 0; i < SONIC_NTXDESC; i++) {
 		ds = &sc->sc_txsoft[i];
 		if (ds->ds_mbuf != NULL) {
 			bus_dmamap_unload(sc->sc_dmat, ds->ds_dmamap);
 			m_freem(ds->ds_mbuf);
 			ds->ds_mbuf = NULL;
+		}
+	}
 	/*
 	 * Mark the interface down and cancel the watchdog timer.
 	 */
 	ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE);
 	ifp->if_timer = 0;
 	if (disable)
 		sonic_rxdrain(sc);
+}
 /*
  * sonic_add_rxbuf:
+ *
  *	Add a receive buffer to the indicated descriptor.
  */
 int
 sonic_add_rxbuf(struct sonic_softc *sc, int idx)
+{
 	struct sonic_descsoft *ds = &sc->sc_rxsoft[idx];
 	struct mbuf *m;
 	int error;
 	MGETHDR(m, M_DONTWAIT, MT_DATA);
 	if (m == NULL)
 		return ENOBUFS;
 	MCLGET(m, M_DONTWAIT);
 	if ((m->m_flags & M_EXT) == 0) {
 		m_freem(m);
 		return ENOBUFS;
+	}
 	if (ds->ds_mbuf != NULL)
 		bus_dmamap_unload(sc->sc_dmat, ds->ds_dmamap);
 	ds->ds_mbuf = m;
 	error = bus_dmamap_load(sc->sc_dmat, ds->ds_dmamap,
 	    m->m_ext.ext_buf, m->m_ext.ext_size, NULL,
 	    BUS_DMA_READ | BUS_DMA_NOWAIT);
 	if (error) {
 		printf("%s: can't load rx DMA map %d, error = %d\n",
 		    device_xname(sc->sc_dev), idx, error);
 		panic("sonic_add_rxbuf");	/* XXX */
+	}
 	bus_dmamap_sync(sc->sc_dmat, ds->ds_dmamap, 0,
 	    ds->ds_dmamap->dm_mapsize, BUS_DMASYNC_PREREAD);
 	SONIC_INIT_RXDESC(sc, idx);
 	return 0;
+}
 static void
 sonic_set_camentry(struct sonic_softc *sc, int entry, const uint8_t *enaddr)
+{
 	if (sc->sc_32bit) {
 		struct sonic_cda32 *cda = &sc->sc_cda32[entry];
 		cda->cda_entry = htosonic32(sc, entry);
 		cda->cda_addr0 = htosonic32(sc, enaddr[0] | (enaddr[1] << 8));
 		cda->cda_addr1 = htosonic32(sc, enaddr[2] | (enaddr[3] << 8));
 		cda->cda_addr2 = htosonic32(sc, enaddr[4] | (enaddr[5] << 8));
 	} else {
 		struct sonic_cda16 *cda = &sc->sc_cda16[entry];
 		cda->cda_entry = htosonic16(sc, entry);
 		cda->cda_addr0 = htosonic16(sc, enaddr[0] | (enaddr[1] << 8));
 		cda->cda_addr1 = htosonic16(sc, enaddr[2] | (enaddr[3] << 8));
 		cda->cda_addr2 = htosonic16(sc, enaddr[4] | (enaddr[5] << 8));
+	}
+}
 /*
  * sonic_set_filter:
+ *
  *	Set the SONIC receive filter.
  */
 void
 sonic_set_filter(struct sonic_softc *sc)
+{
 	struct ethercom *ec = &sc->sc_ethercom;
 	struct ifnet *ifp = &sc->sc_ethercom.ec_if;
 	struct ether_multi *enm;
 	struct ether_multistep step;
 	int i, entry = 0;
 	uint16_t camvalid = 0;
 	uint16_t rcr = 0;
 	if (ifp->if_flags & IFF_BROADCAST)
 		rcr |= RCR_BRD;
 	if (ifp->if_flags & IFF_PROMISC) {
 		rcr |= RCR_PRO;
 		goto allmulti;
+	}
 	/* Put our station address in the first CAM slot. */
 	sonic_set_camentry(sc, entry, CLLADDR(ifp->if_sadl));
 	camvalid |= (1U << entry);
 	entry++;
 	/* Add the multicast addresses to the CAM. */
 	ETHER_LOCK(ec);
 	ETHER_FIRST_MULTI(step, ec, enm);
 	while (enm != NULL) {
 		if (memcmp(enm->enm_addrlo, enm->enm_addrhi, ETHER_ADDR_LEN)) {
 			/*
 			 * We must listen to a range of multicast addresses.
 			 * The only way to do this on the SONIC is to enable
 			 * reception of all multicast packets.
 			 */
 			ETHER_UNLOCK(ec);
 			goto allmulti;
+		}
 		if (entry == SONIC_NCAMENT) {
 			/*
 			 * Out of CAM slots.  Have to enable reception
 			 * of all multicast addresses.
 			 */
 			ETHER_UNLOCK(ec);
 			goto allmulti;
+		}
 		sonic_set_camentry(sc, entry, enm->enm_addrlo);
 		camvalid |= (1U << entry);
 		entry++;
 		ETHER_NEXT_MULTI(step, enm);
+	}
 	ETHER_UNLOCK(ec);
 	ifp->if_flags &= ~IFF_ALLMULTI;
 	goto setit;
  allmulti:
 	/* Use only the first CAM slot (station address). */
 	camvalid = 0x0001;
 	entry = 1;
 	rcr |= RCR_AMC;
  setit:
 	/* set mask for the CAM Enable register */
 	if (sc->sc_32bit) {
 		if (entry == SONIC_NCAMENT)
 			sc->sc_cdaenable32 = htosonic32(sc, camvalid);
 		else
 			sc->sc_cda32[entry].cda_entry =
 			    htosonic32(sc, camvalid);
 	} else {
 		if (entry == SONIC_NCAMENT)
 			sc->sc_cdaenable16 = htosonic16(sc, camvalid);
 		else
 			sc->sc_cda16[entry].cda_entry =
 			    htosonic16(sc, camvalid);
+	}
 	/* Load the CAM. */
 	SONIC_CDCAMSYNC(sc, BUS_DMASYNC_PREWRITE);
 	CSR_WRITE(sc, SONIC_CDP, SONIC_CDCAMADDR(sc) & 0xffff);
 	CSR_WRITE(sc, SONIC_CDC, entry);
 	CSR_WRITE(sc, SONIC_CR, CR_LCAM);
 	for (i = 0; i < 10000; i++) {
 		if ((CSR_READ(sc, SONIC_CR) & CR_LCAM) == 0)
 			break;
 		delay(2);
+	}
 	if (CSR_READ(sc, SONIC_CR) & CR_LCAM)
 		printf("%s: CAM load failed\n", device_xname(sc->sc_dev));
 	SONIC_CDCAMSYNC(sc, BUS_DMASYNC_POSTWRITE);
 	/* Set the receive control register. */
 	CSR_WRITE(sc, SONIC_RCR, rcr);
+}

 @@ -1,1740 +1,1740 @@
-/* $NetBSD: dwc_gmac.c,v 1.68 2019/10/19 06:40:20 tnn Exp $ */
+/* $NetBSD: dwc_gmac.c,v 1.69 2020/01/29 14:14:55 thorpej Exp $ */
 /*-
  * Copyright (c) 2013, 2014 The NetBSD Foundation, Inc.
  * All rights reserved.
+ *
  * This code is derived from software contributed to The NetBSD Foundation
  * by Matt Thomas of 3am Software Foundry and Martin Husemann.
+ *
  * Redistribution and use in source and binary forms, with or without
  * modification, are permitted provided that the following conditions
  * are met:
  * 1. Redistributions of source code must retain the above copyright
  *    notice, this list of conditions and the following disclaimer.
  * 2. Redistributions in binary form must reproduce the above copyright
  *    notice, this list of conditions and the following disclaimer in the
  *    documentation and/or other materials provided with the distribution.
+ *
  * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
  * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
  * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
  * PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
  * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
  * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
  * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
  * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
  * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
  * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
  * POSSIBILITY OF SUCH DAMAGE.
  */
 /*
  * This driver supports the Synopsis Designware GMAC core, as found
  * on Allwinner A20 cores and others.
+ *
  * Real documentation seems to not be available, the marketing product
  * documents could be found here:
+ *
  *  http://www.synopsys.com/dw/ipdir.php?ds=dwc_ether_mac10_100_1000_unive
  */
 #include <sys/cdefs.h>
-__KERNEL_RCSID(1, "$NetBSD: dwc_gmac.c,v 1.68 2019/10/19 06:40:20 tnn Exp $");
+__KERNEL_RCSID(1, "$NetBSD: dwc_gmac.c,v 1.69 2020/01/29 14:14:55 thorpej Exp $");
 /* #define	DWC_GMAC_DEBUG	1 */
 #ifdef _KERNEL_OPT
 #include "opt_inet.h"
 #include "opt_net_mpsafe.h"
 #endif
 #include <sys/param.h>
 #include <sys/bus.h>
 #include <sys/device.h>
 #include <sys/intr.h>
 #include <sys/systm.h>
 #include <sys/sockio.h>
 #include <sys/cprng.h>
 #include <sys/rndsource.h>
 #include <net/if.h>
 #include <net/if_ether.h>
 #include <net/if_media.h>
 #include <net/bpf.h>
 #ifdef INET
 #include <netinet/if_inarp.h>
 #endif
 #include <dev/mii/miivar.h>
 #include <dev/ic/dwc_gmac_reg.h>
 #include <dev/ic/dwc_gmac_var.h>
 static int dwc_gmac_miibus_read_reg(device_t, int, int, uint16_t *);
 static int dwc_gmac_miibus_write_reg(device_t, int, int, uint16_t);
 static void dwc_gmac_miibus_statchg(struct ifnet *);
 static int dwc_gmac_reset(struct dwc_gmac_softc *);
 static void dwc_gmac_write_hwaddr(struct dwc_gmac_softc *, uint8_t *);
 static int dwc_gmac_alloc_dma_rings(struct dwc_gmac_softc *);
 static void dwc_gmac_free_dma_rings(struct dwc_gmac_softc *);
 static int dwc_gmac_alloc_rx_ring(struct dwc_gmac_softc *, struct dwc_gmac_rx_ring *);
 static void dwc_gmac_reset_rx_ring(struct dwc_gmac_softc *, struct dwc_gmac_rx_ring *);
 static void dwc_gmac_free_rx_ring(struct dwc_gmac_softc *, struct dwc_gmac_rx_ring *);
 static int dwc_gmac_alloc_tx_ring(struct dwc_gmac_softc *, struct dwc_gmac_tx_ring *);
 static void dwc_gmac_reset_tx_ring(struct dwc_gmac_softc *, struct dwc_gmac_tx_ring *);
 static void dwc_gmac_free_tx_ring(struct dwc_gmac_softc *, struct dwc_gmac_tx_ring *);
 static void dwc_gmac_txdesc_sync(struct dwc_gmac_softc *, int, int, int);
 static int dwc_gmac_init(struct ifnet *);
 static int dwc_gmac_init_locked(struct ifnet *);
 static void dwc_gmac_stop(struct ifnet *, int);
 static void dwc_gmac_stop_locked(struct ifnet *, int);
 static void dwc_gmac_start(struct ifnet *);
 static void dwc_gmac_start_locked(struct ifnet *);
 static int dwc_gmac_queue(struct dwc_gmac_softc *, struct mbuf *);
 static int dwc_gmac_ioctl(struct ifnet *, u_long, void *);
 static void dwc_gmac_tx_intr(struct dwc_gmac_softc *);
 static void dwc_gmac_rx_intr(struct dwc_gmac_softc *);
 static void dwc_gmac_setmulti(struct dwc_gmac_softc *);
 static int dwc_gmac_ifflags_cb(struct ethercom *);
 static uint32_t	bitrev32(uint32_t);
 static void dwc_gmac_desc_set_owned_by_dev(struct dwc_gmac_dev_dmadesc *);
 static int  dwc_gmac_desc_is_owned_by_dev(struct dwc_gmac_dev_dmadesc *);
 static void dwc_gmac_desc_std_set_len(struct dwc_gmac_dev_dmadesc *, int);
 static uint32_t dwc_gmac_desc_std_get_len(struct dwc_gmac_dev_dmadesc *);
 static void dwc_gmac_desc_std_tx_init_flags(struct dwc_gmac_dev_dmadesc *);
 static void dwc_gmac_desc_std_tx_set_first_frag(struct dwc_gmac_dev_dmadesc *);
 static void dwc_gmac_desc_std_tx_set_last_frag(struct dwc_gmac_dev_dmadesc *);
 static void dwc_gmac_desc_std_rx_init_flags(struct dwc_gmac_dev_dmadesc *);
 static int  dwc_gmac_desc_std_rx_has_error(struct dwc_gmac_dev_dmadesc *);
 static void dwc_gmac_desc_enh_set_len(struct dwc_gmac_dev_dmadesc *, int);
 static uint32_t dwc_gmac_desc_enh_get_len(struct dwc_gmac_dev_dmadesc *);
 static void dwc_gmac_desc_enh_tx_init_flags(struct dwc_gmac_dev_dmadesc *);
 static void dwc_gmac_desc_enh_tx_set_first_frag(struct dwc_gmac_dev_dmadesc *);
 static void dwc_gmac_desc_enh_tx_set_last_frag(struct dwc_gmac_dev_dmadesc *);
 static void dwc_gmac_desc_enh_rx_init_flags(struct dwc_gmac_dev_dmadesc *);
 static int  dwc_gmac_desc_enh_rx_has_error(struct dwc_gmac_dev_dmadesc *);
 static const struct dwc_gmac_desc_methods desc_methods_standard = {
 	.tx_init_flags = dwc_gmac_desc_std_tx_init_flags,
 	.tx_set_owned_by_dev = dwc_gmac_desc_set_owned_by_dev,
 	.tx_is_owned_by_dev = dwc_gmac_desc_is_owned_by_dev,
 	.tx_set_len = dwc_gmac_desc_std_set_len,
 	.tx_set_first_frag = dwc_gmac_desc_std_tx_set_first_frag,
 	.tx_set_last_frag = dwc_gmac_desc_std_tx_set_last_frag,
 	.rx_init_flags = dwc_gmac_desc_std_rx_init_flags,
 	.rx_set_owned_by_dev = dwc_gmac_desc_set_owned_by_dev,
 	.rx_is_owned_by_dev = dwc_gmac_desc_is_owned_by_dev,
 	.rx_set_len = dwc_gmac_desc_std_set_len,
 	.rx_get_len = dwc_gmac_desc_std_get_len,
 	.rx_has_error = dwc_gmac_desc_std_rx_has_error
 };
 static const struct dwc_gmac_desc_methods desc_methods_enhanced = {
 	.tx_init_flags = dwc_gmac_desc_enh_tx_init_flags,
 	.tx_set_owned_by_dev = dwc_gmac_desc_set_owned_by_dev,
 	.tx_is_owned_by_dev = dwc_gmac_desc_is_owned_by_dev,
 	.tx_set_len = dwc_gmac_desc_enh_set_len,
 	.tx_set_first_frag = dwc_gmac_desc_enh_tx_set_first_frag,
 	.tx_set_last_frag = dwc_gmac_desc_enh_tx_set_last_frag,
 	.rx_init_flags = dwc_gmac_desc_enh_rx_init_flags,
 	.rx_set_owned_by_dev = dwc_gmac_desc_set_owned_by_dev,
 	.rx_is_owned_by_dev = dwc_gmac_desc_is_owned_by_dev,
 	.rx_set_len = dwc_gmac_desc_enh_set_len,
 	.rx_get_len = dwc_gmac_desc_enh_get_len,
 	.rx_has_error = dwc_gmac_desc_enh_rx_has_error
 };
 #define	TX_DESC_OFFSET(N)	((AWGE_RX_RING_COUNT+(N)) \
 				    *sizeof(struct dwc_gmac_dev_dmadesc))
 #define	TX_NEXT(N)		(((N)+1) & (AWGE_TX_RING_COUNT-1))
 #define RX_DESC_OFFSET(N)	((N)*sizeof(struct dwc_gmac_dev_dmadesc))
 #define	RX_NEXT(N)		(((N)+1) & (AWGE_RX_RING_COUNT-1))
 #define	GMAC_DEF_DMA_INT_MASK	(GMAC_DMA_INT_TIE | GMAC_DMA_INT_RIE | \
 				GMAC_DMA_INT_NIE | GMAC_DMA_INT_AIE | \
 				GMAC_DMA_INT_FBE | GMAC_DMA_INT_UNE)
 #define	GMAC_DMA_INT_ERRORS	(GMAC_DMA_INT_AIE | GMAC_DMA_INT_ERE | \
 				GMAC_DMA_INT_FBE |	\
 				GMAC_DMA_INT_RWE | GMAC_DMA_INT_RUE | \
 				GMAC_DMA_INT_UNE | GMAC_DMA_INT_OVE | \
 				GMAC_DMA_INT_TJE)
 #define	AWIN_DEF_MAC_INTRMASK	\
 	(AWIN_GMAC_MAC_INT_TSI | AWIN_GMAC_MAC_INT_ANEG |	\
 	AWIN_GMAC_MAC_INT_LINKCHG)
 #ifdef DWC_GMAC_DEBUG
 static void dwc_gmac_dump_dma(struct dwc_gmac_softc *);
 static void dwc_gmac_dump_tx_desc(struct dwc_gmac_softc *);
 static void dwc_gmac_dump_rx_desc(struct dwc_gmac_softc *);
 static void dwc_dump_and_abort(struct dwc_gmac_softc *, const char *);
 static void dwc_dump_status(struct dwc_gmac_softc *);
 static void dwc_gmac_dump_ffilt(struct dwc_gmac_softc *, uint32_t);
 #endif
 int
 dwc_gmac_attach(struct dwc_gmac_softc *sc, int phy_id, uint32_t mii_clk)
+{
 	uint8_t enaddr[ETHER_ADDR_LEN];
 	uint32_t maclo, machi, ver, hwft;
 	struct mii_data * const mii = &sc->sc_mii;
 	struct ifnet * const ifp = &sc->sc_ec.ec_if;
 	prop_dictionary_t dict;
 	int rv;
 	mutex_init(&sc->sc_mdio_lock, MUTEX_DEFAULT, IPL_NET);
 	sc->sc_mii_clk = mii_clk & 7;
 	dict = device_properties(sc->sc_dev);
 	prop_data_t ea = dict ? prop_dictionary_get(dict, "mac-address") : NULL;
 	if (ea != NULL) {
 		/*
 		 * If the MAC address is overriden by a device property,
 		 * use that.
 		 */
 		KASSERT(prop_object_type(ea) == PROP_TYPE_DATA);
 		KASSERT(prop_data_size(ea) == ETHER_ADDR_LEN);
 		memcpy(enaddr, prop_data_data_nocopy(ea), ETHER_ADDR_LEN);
 	} else {
 		/*
 		 * If we did not get an externaly configure address,
 		 * try to read one from the current filter setup,
 		 * before resetting the chip.
 		 */
 		maclo = bus_space_read_4(sc->sc_bst, sc->sc_bsh,
 		    AWIN_GMAC_MAC_ADDR0LO);
 		machi = bus_space_read_4(sc->sc_bst, sc->sc_bsh,
 		    AWIN_GMAC_MAC_ADDR0HI);
 		if (maclo == 0xffffffff && (machi & 0xffff) == 0xffff) {
 			/* fake MAC address */
 			maclo = 0x00f2 | (cprng_strong32() << 16);
 			machi = cprng_strong32();
+		}
 		enaddr[0] = maclo & 0x0ff;
 		enaddr[1] = (maclo >> 8) & 0x0ff;
 		enaddr[2] = (maclo >> 16) & 0x0ff;
 		enaddr[3] = (maclo >> 24) & 0x0ff;
 		enaddr[4] = machi & 0x0ff;
 		enaddr[5] = (machi >> 8) & 0x0ff;
+	}
 	ver = bus_space_read_4(sc->sc_bst, sc->sc_bsh, AWIN_GMAC_MAC_VERSION);
 	aprint_normal_dev(sc->sc_dev, "Core version: %08x\n", ver);
 	/*
 	 * Init chip and do initial setup
 	 */
 	if (dwc_gmac_reset(sc) != 0)
 		return ENXIO;	/* not much to cleanup, haven't attached yet */
 	dwc_gmac_write_hwaddr(sc, enaddr);
 	aprint_normal_dev(sc->sc_dev, "Ethernet address %s\n",
 	    ether_sprintf(enaddr));
 	hwft = 0;
 	if (ver >= 0x35) {
 		hwft = bus_space_read_4(sc->sc_bst, sc->sc_bsh,
 		    AWIN_GMAC_DMA_HWFEATURES);
 		aprint_normal_dev(sc->sc_dev,
 		    "HW feature mask: %x\n", hwft);
+	}
 	if (hwft & GMAC_DMA_FEAT_ENHANCED_DESC) {
 		aprint_normal_dev(sc->sc_dev,
 		    "Using enhanced descriptor format\n");
 		sc->sc_descm = &desc_methods_enhanced;
 	} else {
 		sc->sc_descm = &desc_methods_standard;
+	}
 	/*
 	 * Allocate Tx and Rx rings
 	 */
 	if (dwc_gmac_alloc_dma_rings(sc) != 0) {
 		aprint_error_dev(sc->sc_dev, "could not allocate DMA rings\n");
 		goto fail;
+	}
 	if (dwc_gmac_alloc_tx_ring(sc, &sc->sc_txq) != 0) {
 		aprint_error_dev(sc->sc_dev, "could not allocate Tx ring\n");
 		goto fail;
+	}
 	if (dwc_gmac_alloc_rx_ring(sc, &sc->sc_rxq) != 0) {
 		aprint_error_dev(sc->sc_dev, "could not allocate Rx ring\n");
 		goto fail;
+	}
 	sc->sc_lock = mutex_obj_alloc(MUTEX_DEFAULT, IPL_NET);
 	mutex_init(&sc->sc_txq.t_mtx, MUTEX_DEFAULT, IPL_NET);
 	mutex_init(&sc->sc_rxq.r_mtx, MUTEX_DEFAULT, IPL_NET);
 	/*
 	 * Prepare interface data
 	 */
 	ifp->if_softc = sc;
 	strlcpy(ifp->if_xname, device_xname(sc->sc_dev), IFNAMSIZ);
 	ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST;
 #ifdef DWCGMAC_MPSAFE
 	ifp->if_extflags = IFEF_MPSAFE;
 #endif
 	ifp->if_ioctl = dwc_gmac_ioctl;
 	ifp->if_start = dwc_gmac_start;
 	ifp->if_init = dwc_gmac_init;
 	ifp->if_stop = dwc_gmac_stop;
 	IFQ_SET_MAXLEN(&ifp->if_snd, IFQ_MAXLEN);
 	IFQ_SET_READY(&ifp->if_snd);
 	/*
 	 * Attach MII subdevices
 	 */
 	sc->sc_ec.ec_mii = &sc->sc_mii;
 	ifmedia_init(&mii->mii_media, 0, ether_mediachange, ether_mediastatus);
 	mii->mii_ifp = ifp;
 	mii->mii_readreg = dwc_gmac_miibus_read_reg;
 	mii->mii_writereg = dwc_gmac_miibus_write_reg;
 	mii->mii_statchg = dwc_gmac_miibus_statchg;
 	mii_attach(sc->sc_dev, mii, 0xffffffff, phy_id, MII_OFFSET_ANY,
 	    MIIF_DOPAUSE);
 	if (LIST_EMPTY(&mii->mii_phys)) {
 		aprint_error_dev(sc->sc_dev, "no PHY found!\n");
 		ifmedia_add(&mii->mii_media, IFM_ETHER | IFM_MANUAL, 0, NULL);
 		ifmedia_set(&mii->mii_media, IFM_ETHER | IFM_MANUAL);
 	} else {
 		ifmedia_set(&mii->mii_media, IFM_ETHER | IFM_AUTO);
+	}
 	/*
 	 * We can support 802.1Q VLAN-sized frames.
 	 */
 	sc->sc_ec.ec_capabilities |= ETHERCAP_VLAN_MTU;
 	/*
 	 * Ready, attach interface
 	 */
 	/* Attach the interface. */
 	rv = if_initialize(ifp);
 	if (rv != 0)
 		goto fail_2;
 	sc->sc_ipq = if_percpuq_create(&sc->sc_ec.ec_if);
 	if_deferred_start_init(ifp, NULL);
 	ether_ifattach(ifp, enaddr);
 	ether_set_ifflags_cb(&sc->sc_ec, dwc_gmac_ifflags_cb);
 	if_register(ifp);
 	rnd_attach_source(&sc->rnd_source, device_xname(sc->sc_dev),
 	    RND_TYPE_NET, RND_FLAG_DEFAULT);
 	/*
 	 * Enable interrupts
 	 */
 	mutex_enter(sc->sc_lock);
 	bus_space_write_4(sc->sc_bst, sc->sc_bsh, AWIN_GMAC_MAC_INTMASK,
 	    AWIN_DEF_MAC_INTRMASK);
 	bus_space_write_4(sc->sc_bst, sc->sc_bsh, AWIN_GMAC_DMA_INTENABLE,
 	    GMAC_DEF_DMA_INT_MASK);
 	mutex_exit(sc->sc_lock);
 	return 0;
 fail_2:
 	ifmedia_removeall(&mii->mii_media);
 	mii_detach(mii, MII_PHY_ANY, MII_OFFSET_ANY);
 	mutex_destroy(&sc->sc_txq.t_mtx);
 	mutex_destroy(&sc->sc_rxq.r_mtx);
 	mutex_obj_free(sc->sc_lock);
 fail:
 	dwc_gmac_free_rx_ring(sc, &sc->sc_rxq);
 	dwc_gmac_free_tx_ring(sc, &sc->sc_txq);
 	dwc_gmac_free_dma_rings(sc);
 	mutex_destroy(&sc->sc_mdio_lock);
 	return ENXIO;
+}
 static int
 dwc_gmac_reset(struct dwc_gmac_softc *sc)
+{
 	size_t cnt;
 	bus_space_write_4(sc->sc_bst, sc->sc_bsh, AWIN_GMAC_DMA_BUSMODE,
 	    bus_space_read_4(sc->sc_bst, sc->sc_bsh, AWIN_GMAC_DMA_BUSMODE)
 	    | GMAC_BUSMODE_RESET);
 	for (cnt = 0; cnt < 3000; cnt++) {
 		if ((bus_space_read_4(sc->sc_bst, sc->sc_bsh, AWIN_GMAC_DMA_BUSMODE)
 		    & GMAC_BUSMODE_RESET) == 0)
 			return 0;
 		delay(10);
+	}
 	aprint_error_dev(sc->sc_dev, "reset timed out\n");
 	return EIO;
+}
 static void
 dwc_gmac_write_hwaddr(struct dwc_gmac_softc *sc,
     uint8_t enaddr[ETHER_ADDR_LEN])
+{
 	uint32_t hi, lo;
 	hi = enaddr[4] | (enaddr[5] << 8);
 	lo = enaddr[0] | (enaddr[1] << 8) | (enaddr[2] << 16)
 	    | (enaddr[3] << 24);
 	bus_space_write_4(sc->sc_bst, sc->sc_bsh, AWIN_GMAC_MAC_ADDR0HI, hi);
 	bus_space_write_4(sc->sc_bst, sc->sc_bsh, AWIN_GMAC_MAC_ADDR0LO, lo);
+}
 static int
 dwc_gmac_miibus_read_reg(device_t self, int phy, int reg, uint16_t *val)
+{
 	struct dwc_gmac_softc * const sc = device_private(self);
 	uint16_t mii;
 	size_t cnt;
 	mii = __SHIFTIN(phy, GMAC_MII_PHY_MASK)
 	    | __SHIFTIN(reg, GMAC_MII_REG_MASK)
 	    | __SHIFTIN(sc->sc_mii_clk, GMAC_MII_CLKMASK)
 	    | GMAC_MII_BUSY;
 	mutex_enter(&sc->sc_mdio_lock);
 	bus_space_write_4(sc->sc_bst, sc->sc_bsh, AWIN_GMAC_MAC_MIIADDR, mii);
 	for (cnt = 0; cnt < 1000; cnt++) {
 		if (!(bus_space_read_4(sc->sc_bst, sc->sc_bsh,
 		    AWIN_GMAC_MAC_MIIADDR) & GMAC_MII_BUSY)) {
 			*val = bus_space_read_4(sc->sc_bst, sc->sc_bsh,
 			    AWIN_GMAC_MAC_MIIDATA);
 			break;
+		}
 		delay(10);
+	}
 	mutex_exit(&sc->sc_mdio_lock);
 	if (cnt >= 1000)
 		return ETIMEDOUT;
 	return 0;
+}
 static int
 dwc_gmac_miibus_write_reg(device_t self, int phy, int reg, uint16_t val)
+{
 	struct dwc_gmac_softc * const sc = device_private(self);
 	uint16_t mii;
 	size_t cnt;
 	mii = __SHIFTIN(phy, GMAC_MII_PHY_MASK)
 	    | __SHIFTIN(reg, GMAC_MII_REG_MASK)
 	    | __SHIFTIN(sc->sc_mii_clk, GMAC_MII_CLKMASK)
 	    | GMAC_MII_BUSY | GMAC_MII_WRITE;
 	mutex_enter(&sc->sc_mdio_lock);
 	bus_space_write_4(sc->sc_bst, sc->sc_bsh, AWIN_GMAC_MAC_MIIDATA, val);
 	bus_space_write_4(sc->sc_bst, sc->sc_bsh, AWIN_GMAC_MAC_MIIADDR, mii);
 	for (cnt = 0; cnt < 1000; cnt++) {
 		if (!(bus_space_read_4(sc->sc_bst, sc->sc_bsh,
 		    AWIN_GMAC_MAC_MIIADDR) & GMAC_MII_BUSY))
 			break;
 		delay(10);
+	}
 	mutex_exit(&sc->sc_mdio_lock);
 	if (cnt >= 1000)
 		return ETIMEDOUT;
 	return 0;
+}
 static int
 dwc_gmac_alloc_rx_ring(struct dwc_gmac_softc *sc,
 	struct dwc_gmac_rx_ring *ring)
+{
 	struct dwc_gmac_rx_data *data;
 	bus_addr_t physaddr;
 	const size_t descsize = AWGE_RX_RING_COUNT * sizeof(*ring->r_desc);
 	int error, i, next;
 	ring->r_cur = ring->r_next = 0;
 	memset(ring->r_desc, 0, descsize);
 	/*
 	 * Pre-allocate Rx buffers and populate Rx ring.
 	 */
 	for (i = 0; i < AWGE_RX_RING_COUNT; i++) {
 		struct dwc_gmac_dev_dmadesc *desc;
 		data = &sc->sc_rxq.r_data[i];
 		MGETHDR(data->rd_m, M_DONTWAIT, MT_DATA);
 		if (data->rd_m == NULL) {
 			aprint_error_dev(sc->sc_dev,
 			    "could not allocate rx mbuf #%d\n", i);
 			error = ENOMEM;
 			goto fail;
+		}
 		error = bus_dmamap_create(sc->sc_dmat, MCLBYTES, 1,
 		    MCLBYTES, 0, BUS_DMA_NOWAIT, &data->rd_map);
 		if (error != 0) {
 			aprint_error_dev(sc->sc_dev,
 			    "could not create DMA map\n");
 			data->rd_map = NULL;
 			goto fail;
+		}
 		MCLGET(data->rd_m, M_DONTWAIT);
 		if (!(data->rd_m->m_flags & M_EXT)) {
 			aprint_error_dev(sc->sc_dev,
 			    "could not allocate mbuf cluster #%d\n", i);
 			error = ENOMEM;
 			goto fail;
+		}
 		data->rd_m->m_len = data->rd_m->m_pkthdr.len
 		    = data->rd_m->m_ext.ext_size;
 		if (data->rd_m->m_len > AWGE_MAX_PACKET) {
 			data->rd_m->m_len = data->rd_m->m_pkthdr.len
 			    = AWGE_MAX_PACKET;
+		}
 		error = bus_dmamap_load_mbuf(sc->sc_dmat, data->rd_map,
 		    data->rd_m, BUS_DMA_READ | BUS_DMA_NOWAIT);
 		if (error != 0) {
 			aprint_error_dev(sc->sc_dev,
 			    "could not load rx buf DMA map #%d", i);
 			goto fail;
+		}
 		bus_dmamap_sync(sc->sc_dmat, data->rd_map, 0,
 		    data->rd_map->dm_mapsize, BUS_DMASYNC_PREREAD);
 		physaddr = data->rd_map->dm_segs[0].ds_addr;
 		desc = &sc->sc_rxq.r_desc[i];
 		desc->ddesc_data = htole32(physaddr);
 		next = RX_NEXT(i);
 		desc->ddesc_next = htole32(ring->r_physaddr
 		    + next * sizeof(*desc));
 		sc->sc_descm->rx_init_flags(desc);
 		sc->sc_descm->rx_set_len(desc, data->rd_m->m_len);
 		sc->sc_descm->rx_set_owned_by_dev(desc);
+	}
 	bus_dmamap_sync(sc->sc_dmat, sc->sc_dma_ring_map, 0,
 	    AWGE_RX_RING_COUNT*sizeof(struct dwc_gmac_dev_dmadesc),
 	    BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD);
 	bus_space_write_4(sc->sc_bst, sc->sc_bsh, AWIN_GMAC_DMA_RX_ADDR,
 	    ring->r_physaddr);
 	return 0;
 fail:
 	dwc_gmac_free_rx_ring(sc, ring);
 	return error;
+}
 static void
 dwc_gmac_reset_rx_ring(struct dwc_gmac_softc *sc,
 	struct dwc_gmac_rx_ring *ring)
+{
 	struct dwc_gmac_dev_dmadesc *desc;
 	struct dwc_gmac_rx_data *data;
 	int i;
 	mutex_enter(&ring->r_mtx);
 	for (i = 0; i < AWGE_RX_RING_COUNT; i++) {
 		desc = &sc->sc_rxq.r_desc[i];
 		data = &sc->sc_rxq.r_data[i];
 		sc->sc_descm->rx_init_flags(desc);
 		sc->sc_descm->rx_set_len(desc, data->rd_m->m_len);
 		sc->sc_descm->rx_set_owned_by_dev(desc);
+	}
 	bus_dmamap_sync(sc->sc_dmat, sc->sc_dma_ring_map, 0,
 	    AWGE_RX_RING_COUNT*sizeof(struct dwc_gmac_dev_dmadesc),
 	    BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
 	ring->r_cur = ring->r_next = 0;
 	/* reset DMA address to start of ring */
 	bus_space_write_4(sc->sc_bst, sc->sc_bsh, AWIN_GMAC_DMA_RX_ADDR,
 	    sc->sc_rxq.r_physaddr);
 	mutex_exit(&ring->r_mtx);
+}
 static int
 dwc_gmac_alloc_dma_rings(struct dwc_gmac_softc *sc)
+{
 	const size_t descsize = AWGE_TOTAL_RING_COUNT *
 		sizeof(struct dwc_gmac_dev_dmadesc);
 	int error, nsegs;
 	void *rings;
 	error = bus_dmamap_create(sc->sc_dmat, descsize, 1, descsize, 0,
 	    BUS_DMA_NOWAIT, &sc->sc_dma_ring_map);
 	if (error != 0) {
 		aprint_error_dev(sc->sc_dev,
 		    "could not create desc DMA map\n");
 		sc->sc_dma_ring_map = NULL;
 		goto fail;
+	}
 	error = bus_dmamem_alloc(sc->sc_dmat, descsize, PAGE_SIZE, 0,
 	    &sc->sc_dma_ring_seg, 1, &nsegs, BUS_DMA_NOWAIT |BUS_DMA_COHERENT);
 	if (error != 0) {
 		aprint_error_dev(sc->sc_dev,
 		    "could not map DMA memory\n");
 		goto fail;
+	}
 	error = bus_dmamem_map(sc->sc_dmat, &sc->sc_dma_ring_seg, nsegs,
 	    descsize, &rings, BUS_DMA_NOWAIT | BUS_DMA_COHERENT);
 	if (error != 0) {
 		aprint_error_dev(sc->sc_dev,
 		    "could not allocate DMA memory\n");
 		goto fail;
+	}
 	error = bus_dmamap_load(sc->sc_dmat, sc->sc_dma_ring_map, rings,
 	    descsize, NULL, BUS_DMA_NOWAIT | BUS_DMA_COHERENT);
 	if (error != 0) {
 		aprint_error_dev(sc->sc_dev,
 		    "could not load desc DMA map\n");
 		goto fail;
+	}
 	/* give first AWGE_RX_RING_COUNT to the RX side */
 	sc->sc_rxq.r_desc = rings;
 	sc->sc_rxq.r_physaddr = sc->sc_dma_ring_map->dm_segs[0].ds_addr;
 	/* and next rings to the TX side */
 	sc->sc_txq.t_desc = sc->sc_rxq.r_desc + AWGE_RX_RING_COUNT;
 	sc->sc_txq.t_physaddr = sc->sc_rxq.r_physaddr +
 	    AWGE_RX_RING_COUNT*sizeof(struct dwc_gmac_dev_dmadesc);
 	return 0;
 fail:
 	dwc_gmac_free_dma_rings(sc);
 	return error;
+}
 static void
 dwc_gmac_free_dma_rings(struct dwc_gmac_softc *sc)
+{
 	bus_dmamap_sync(sc->sc_dmat, sc->sc_dma_ring_map, 0,
 	    sc->sc_dma_ring_map->dm_mapsize, BUS_DMASYNC_POSTWRITE);
 	bus_dmamap_unload(sc->sc_dmat, sc->sc_dma_ring_map);
 	bus_dmamem_unmap(sc->sc_dmat, sc->sc_rxq.r_desc,
 	    AWGE_TOTAL_RING_COUNT * sizeof(struct dwc_gmac_dev_dmadesc));
 	bus_dmamem_free(sc->sc_dmat, &sc->sc_dma_ring_seg, 1);
+}
 static void
 dwc_gmac_free_rx_ring(struct dwc_gmac_softc *sc, struct dwc_gmac_rx_ring *ring)
+{
 	struct dwc_gmac_rx_data *data;
 	int i;
 	if (ring->r_desc == NULL)
 		return;
 	for (i = 0; i < AWGE_RX_RING_COUNT; i++) {
 		data = &ring->r_data[i];
 		if (data->rd_map != NULL) {
 			bus_dmamap_sync(sc->sc_dmat, data->rd_map, 0,
 			    AWGE_RX_RING_COUNT
 				*sizeof(struct dwc_gmac_dev_dmadesc),
 			    BUS_DMASYNC_POSTREAD);
 			bus_dmamap_unload(sc->sc_dmat, data->rd_map);
 			bus_dmamap_destroy(sc->sc_dmat, data->rd_map);
+		}
 		if (data->rd_m != NULL)
 			m_freem(data->rd_m);
+	}
+}
 static int
 dwc_gmac_alloc_tx_ring(struct dwc_gmac_softc *sc,
 	struct dwc_gmac_tx_ring *ring)
+{
 	int i, error = 0;
 	ring->t_queued = 0;
 	ring->t_cur = ring->t_next = 0;
 	memset(ring->t_desc, 0, AWGE_TX_RING_COUNT*sizeof(*ring->t_desc));
 	bus_dmamap_sync(sc->sc_dmat, sc->sc_dma_ring_map,
 	    TX_DESC_OFFSET(0),
 	    AWGE_TX_RING_COUNT*sizeof(struct dwc_gmac_dev_dmadesc),
 	    BUS_DMASYNC_POSTWRITE);
 	for (i = 0; i < AWGE_TX_RING_COUNT; i++) {
 		error = bus_dmamap_create(sc->sc_dmat, MCLBYTES,
 		    AWGE_TX_RING_COUNT, MCLBYTES, 0,
 		    BUS_DMA_NOWAIT | BUS_DMA_COHERENT,
 		    &ring->t_data[i].td_map);
 		if (error != 0) {
 			aprint_error_dev(sc->sc_dev,
 			    "could not create TX DMA map #%d\n", i);
 			ring->t_data[i].td_map = NULL;
 			goto fail;
+		}
 		ring->t_desc[i].ddesc_next = htole32(
 		    ring->t_physaddr + sizeof(struct dwc_gmac_dev_dmadesc)
 		    *TX_NEXT(i));
+	}
 	return 0;
 fail:
 	dwc_gmac_free_tx_ring(sc, ring);
 	return error;
+}
 static void
 dwc_gmac_txdesc_sync(struct dwc_gmac_softc *sc, int start, int end, int ops)
+{
 	/* 'end' is pointing one descriptor beyond the last we want to sync */
 	if (end > start) {
 		bus_dmamap_sync(sc->sc_dmat, sc->sc_dma_ring_map,
 		    TX_DESC_OFFSET(start),
 		    TX_DESC_OFFSET(end)-TX_DESC_OFFSET(start),
 		    ops);
 		return;
+	}
 	/* sync from 'start' to end of ring */
 	bus_dmamap_sync(sc->sc_dmat, sc->sc_dma_ring_map,
 	    TX_DESC_OFFSET(start),
 	    TX_DESC_OFFSET(AWGE_TX_RING_COUNT)-TX_DESC_OFFSET(start),
 	    ops);
 	if (TX_DESC_OFFSET(end) - TX_DESC_OFFSET(0) > 0) {
 		/* sync from start of ring to 'end' */
 		bus_dmamap_sync(sc->sc_dmat, sc->sc_dma_ring_map,
 		    TX_DESC_OFFSET(0),
 		    TX_DESC_OFFSET(end)-TX_DESC_OFFSET(0),
 		    ops);
+	}
+}
 static void
 dwc_gmac_reset_tx_ring(struct dwc_gmac_softc *sc,
 	struct dwc_gmac_tx_ring *ring)
+{
 	int i;
 	mutex_enter(&ring->t_mtx);
 	for (i = 0; i < AWGE_TX_RING_COUNT; i++) {
 		struct dwc_gmac_tx_data *data = &ring->t_data[i];
 		if (data->td_m != NULL) {
 			bus_dmamap_sync(sc->sc_dmat, data->td_active,
 , data->td_active->dm_mapsize,
 			    BUS_DMASYNC_POSTWRITE);
 			bus_dmamap_unload(sc->sc_dmat, data->td_active);
 			m_freem(data->td_m);
 			data->td_m = NULL;
+		}
+	}
 	bus_dmamap_sync(sc->sc_dmat, sc->sc_dma_ring_map,
 	    TX_DESC_OFFSET(0),
 	    AWGE_TX_RING_COUNT*sizeof(struct dwc_gmac_dev_dmadesc),
 	    BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
 	bus_space_write_4(sc->sc_bst, sc->sc_bsh, AWIN_GMAC_DMA_TX_ADDR,
 	    sc->sc_txq.t_physaddr);
 	ring->t_queued = 0;
 	ring->t_cur = ring->t_next = 0;
 	mutex_exit(&ring->t_mtx);
+}
 static void
 dwc_gmac_free_tx_ring(struct dwc_gmac_softc *sc,
 	struct dwc_gmac_tx_ring *ring)
+{
 	int i;
 	/* unload the maps */
 	for (i = 0; i < AWGE_TX_RING_COUNT; i++) {
 		struct dwc_gmac_tx_data *data = &ring->t_data[i];
 		if (data->td_m != NULL) {
 			bus_dmamap_sync(sc->sc_dmat, data->td_active,
 , data->td_map->dm_mapsize,
 			    BUS_DMASYNC_POSTWRITE);
 			bus_dmamap_unload(sc->sc_dmat, data->td_active);
 			m_freem(data->td_m);
 			data->td_m = NULL;
+		}
+	}
 	/* and actually free them */
 	for (i = 0; i < AWGE_TX_RING_COUNT; i++) {
 		struct dwc_gmac_tx_data *data = &ring->t_data[i];
 		bus_dmamap_destroy(sc->sc_dmat, data->td_map);
+	}
+}
 static void
 dwc_gmac_miibus_statchg(struct ifnet *ifp)
+{
 	struct dwc_gmac_softc * const sc = ifp->if_softc;
 	struct mii_data * const mii = &sc->sc_mii;
 	uint32_t conf, flow;
 	/*
 	 * Set MII or GMII interface based on the speed
 	 * negotiated by the PHY.
 	 */
 	conf = bus_space_read_4(sc->sc_bst, sc->sc_bsh, AWIN_GMAC_MAC_CONF);
 	conf &= ~(AWIN_GMAC_MAC_CONF_FES100 | AWIN_GMAC_MAC_CONF_MIISEL
 	    | AWIN_GMAC_MAC_CONF_FULLDPLX);
 	conf |= AWIN_GMAC_MAC_CONF_FRAMEBURST
 	    | AWIN_GMAC_MAC_CONF_DISABLERXOWN
 	    | AWIN_GMAC_MAC_CONF_DISABLEJABBER
 	    | AWIN_GMAC_MAC_CONF_ACS
 	    | AWIN_GMAC_MAC_CONF_RXENABLE
 	    | AWIN_GMAC_MAC_CONF_TXENABLE;
 	switch (IFM_SUBTYPE(mii->mii_media_active)) {
 	case IFM_10_T:
 		conf |= AWIN_GMAC_MAC_CONF_MIISEL;
 		break;
 	case IFM_100_TX:
 		conf |= AWIN_GMAC_MAC_CONF_FES100 |
 			AWIN_GMAC_MAC_CONF_MIISEL;
 		break;
 	case IFM_1000_T:
 		break;
+	}
 	if (sc->sc_set_speed)
 		sc->sc_set_speed(sc, IFM_SUBTYPE(mii->mii_media_active));
 	flow = 0;
 	if (IFM_OPTIONS(mii->mii_media_active) & IFM_FDX) {
 		conf |= AWIN_GMAC_MAC_CONF_FULLDPLX;
 		flow |= __SHIFTIN(0x200, AWIN_GMAC_MAC_FLOWCTRL_PAUSE);
+	}
 	if (mii->mii_media_active & IFM_ETH_TXPAUSE) {
 		flow |= AWIN_GMAC_MAC_FLOWCTRL_TFE;
+	}
 	if (mii->mii_media_active & IFM_ETH_RXPAUSE) {
 		flow |= AWIN_GMAC_MAC_FLOWCTRL_RFE;
+	}
 	bus_space_write_4(sc->sc_bst, sc->sc_bsh,
 	    AWIN_GMAC_MAC_FLOWCTRL, flow);
 #ifdef DWC_GMAC_DEBUG
 	aprint_normal_dev(sc->sc_dev,
 	    "setting MAC conf register: %08x\n", conf);
 #endif
 	bus_space_write_4(sc->sc_bst, sc->sc_bsh,
 	    AWIN_GMAC_MAC_CONF, conf);
+}
 static int
 dwc_gmac_init(struct ifnet *ifp)
+{
 	struct dwc_gmac_softc *sc = ifp->if_softc;
 	mutex_enter(sc->sc_lock);
 	int ret = dwc_gmac_init_locked(ifp);
 	mutex_exit(sc->sc_lock);
 	return ret;
+}
 static int
 dwc_gmac_init_locked(struct ifnet *ifp)
+{
 	struct dwc_gmac_softc *sc = ifp->if_softc;
 	uint32_t ffilt;
 	if (ifp->if_flags & IFF_RUNNING)
 		return 0;
 	dwc_gmac_stop_locked(ifp, 0);
 	/*
 	 * Configure DMA burst/transfer mode and RX/TX priorities.
 	 * XXX - the GMAC_BUSMODE_PRIORXTX bits are undocumented.
 	 */
 	bus_space_write_4(sc->sc_bst, sc->sc_bsh, AWIN_GMAC_DMA_BUSMODE,
 	    GMAC_BUSMODE_FIXEDBURST | GMAC_BUSMODE_4PBL |
 	    __SHIFTIN(2, GMAC_BUSMODE_RPBL) |
 	    __SHIFTIN(2, GMAC_BUSMODE_PBL));
 	/*
 	 * Set up address filter
 	 */
 	ffilt = bus_space_read_4(sc->sc_bst, sc->sc_bsh, AWIN_GMAC_MAC_FFILT);
 	if (ifp->if_flags & IFF_PROMISC) {
 		ffilt |= AWIN_GMAC_MAC_FFILT_PR;
 	} else {
 		ffilt &= ~AWIN_GMAC_MAC_FFILT_PR;
+	}
 	if (ifp->if_flags & IFF_BROADCAST) {
 		ffilt &= ~AWIN_GMAC_MAC_FFILT_DBF;
 	} else {
 		ffilt |= AWIN_GMAC_MAC_FFILT_DBF;
+	}
 	bus_space_write_4(sc->sc_bst, sc->sc_bsh, AWIN_GMAC_MAC_FFILT, ffilt);
 	/*
 	 * Set up multicast filter
 	 */
 	dwc_gmac_setmulti(sc);
 	/*
 	 * Set up dma pointer for RX and TX ring
 	 */
 	bus_space_write_4(sc->sc_bst, sc->sc_bsh, AWIN_GMAC_DMA_RX_ADDR,
 	    sc->sc_rxq.r_physaddr);
 	bus_space_write_4(sc->sc_bst, sc->sc_bsh, AWIN_GMAC_DMA_TX_ADDR,
 	    sc->sc_txq.t_physaddr);
 	/*
 	 * Start RX/TX part
 	 */
 	uint32_t opmode = GMAC_DMA_OP_RXSTART | GMAC_DMA_OP_TXSTART;
 	if ((sc->sc_flags & DWC_GMAC_FORCE_THRESH_DMA_MODE) == 0) {
 		opmode |= GMAC_DMA_OP_RXSTOREFORWARD | GMAC_DMA_OP_TXSTOREFORWARD;
+	}
 	bus_space_write_4(sc->sc_bst, sc->sc_bsh, AWIN_GMAC_DMA_OPMODE, opmode);
 	sc->sc_stopping = false;
 	ifp->if_flags |= IFF_RUNNING;
 	ifp->if_flags &= ~IFF_OACTIVE;
 	return 0;
+}
 static void
 dwc_gmac_start(struct ifnet *ifp)
+{
 	struct dwc_gmac_softc *sc = ifp->if_softc;
 #ifdef DWCGMAC_MPSAFE
 	KASSERT(if_is_mpsafe(ifp));
 #endif
 	mutex_enter(sc->sc_lock);
 	if (!sc->sc_stopping) {
 		mutex_enter(&sc->sc_txq.t_mtx);
 		dwc_gmac_start_locked(ifp);
 		mutex_exit(&sc->sc_txq.t_mtx);
+	}
 	mutex_exit(sc->sc_lock);
+}
 static void
 dwc_gmac_start_locked(struct ifnet *ifp)
+{
 	struct dwc_gmac_softc *sc = ifp->if_softc;
 	int old = sc->sc_txq.t_queued;
 	int start = sc->sc_txq.t_cur;
 	struct mbuf *m0;
 	if ((ifp->if_flags & (IFF_RUNNING | IFF_OACTIVE)) != IFF_RUNNING)
 		return;
 	for (;;) {
 		IFQ_POLL(&ifp->if_snd, m0);
 		if (m0 == NULL)
 			break;
 		if (dwc_gmac_queue(sc, m0) != 0) {
 			ifp->if_flags |= IFF_OACTIVE;
 			break;
+		}
 		IFQ_DEQUEUE(&ifp->if_snd, m0);
 		bpf_mtap(ifp, m0, BPF_D_OUT);
 		if (sc->sc_txq.t_queued == AWGE_TX_RING_COUNT) {
 			ifp->if_flags |= IFF_OACTIVE;
 			break;
+		}
+	}
 	if (sc->sc_txq.t_queued != old) {
 		/* packets have been queued, kick it off */
 		dwc_gmac_txdesc_sync(sc, start, sc->sc_txq.t_cur,
 		    BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
 #ifdef DWC_GMAC_DEBUG
 		dwc_dump_status(sc);
 #endif
 		bus_space_write_4(sc->sc_bst, sc->sc_bsh,
 		    AWIN_GMAC_DMA_TXPOLL, ~0U);
+	}
+}
 static void
 dwc_gmac_stop(struct ifnet *ifp, int disable)
+{
 	struct dwc_gmac_softc *sc = ifp->if_softc;
 	mutex_enter(sc->sc_lock);
 	dwc_gmac_stop_locked(ifp, disable);
 	mutex_exit(sc->sc_lock);
+}
 static void
 dwc_gmac_stop_locked(struct ifnet *ifp, int disable)
+{
 	struct dwc_gmac_softc *sc = ifp->if_softc;
 	sc->sc_stopping = true;
 	bus_space_write_4(sc->sc_bst, sc->sc_bsh,
 	    AWIN_GMAC_DMA_OPMODE,
 	    bus_space_read_4(sc->sc_bst, sc->sc_bsh,
 		AWIN_GMAC_DMA_OPMODE)
 		& ~(GMAC_DMA_OP_TXSTART | GMAC_DMA_OP_RXSTART));
 	bus_space_write_4(sc->sc_bst, sc->sc_bsh,
 	    AWIN_GMAC_DMA_OPMODE,
 	    bus_space_read_4(sc->sc_bst, sc->sc_bsh,
 		AWIN_GMAC_DMA_OPMODE) | GMAC_DMA_OP_FLUSHTX);
 	mii_down(&sc->sc_mii);
 	dwc_gmac_reset_tx_ring(sc, &sc->sc_txq);
 	dwc_gmac_reset_rx_ring(sc, &sc->sc_rxq);
 	ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE);
+}
 /*
  * Add m0 to the TX ring
  */
 static int
 dwc_gmac_queue(struct dwc_gmac_softc *sc, struct mbuf *m0)
+{
 	struct dwc_gmac_dev_dmadesc *desc = NULL;
 	struct dwc_gmac_tx_data *data = NULL;
 	bus_dmamap_t map;
 	int error, i, first;
 #ifdef DWC_GMAC_DEBUG
 	aprint_normal_dev(sc->sc_dev,
 	    "dwc_gmac_queue: adding mbuf chain %p\n", m0);
 #endif
 	first = sc->sc_txq.t_cur;
 	map = sc->sc_txq.t_data[first].td_map;
 	error = bus_dmamap_load_mbuf(sc->sc_dmat, map, m0,
 	    BUS_DMA_WRITE | BUS_DMA_NOWAIT);
 	if (error != 0) {
 		aprint_error_dev(sc->sc_dev, "could not map mbuf "
 		    "(len: %d, error %d)\n", m0->m_pkthdr.len, error);
 		return error;
+	}
 	if (sc->sc_txq.t_queued + map->dm_nsegs > AWGE_TX_RING_COUNT) {
 		bus_dmamap_unload(sc->sc_dmat, map);
 		return ENOBUFS;
+	}
 	for (i = 0; i < map->dm_nsegs; i++) {
 		data = &sc->sc_txq.t_data[sc->sc_txq.t_cur];
 		desc = &sc->sc_txq.t_desc[sc->sc_txq.t_cur];
 		desc->ddesc_data = htole32(map->dm_segs[i].ds_addr);
 #ifdef DWC_GMAC_DEBUG
 		aprint_normal_dev(sc->sc_dev, "enqueing desc #%d data %08lx "
 		    "len %lu\n", sc->sc_txq.t_cur,
 		    (unsigned long)map->dm_segs[i].ds_addr,
 		    (unsigned long)map->dm_segs[i].ds_len);
 #endif
 		sc->sc_descm->tx_init_flags(desc);
 		sc->sc_descm->tx_set_len(desc, map->dm_segs[i].ds_len);
 		if (i == 0)
 			sc->sc_descm->tx_set_first_frag(desc);
 		/*
 		 * Defer passing ownership of the first descriptor
 		 * until we are done.
 		 */
 		if (i != 0)
 			sc->sc_descm->tx_set_owned_by_dev(desc);
 		sc->sc_txq.t_queued++;
 		sc->sc_txq.t_cur = TX_NEXT(sc->sc_txq.t_cur);
+	}
 	sc->sc_descm->tx_set_last_frag(desc);
 	data->td_m = m0;
 	data->td_active = map;
 	bus_dmamap_sync(sc->sc_dmat, map, 0, map->dm_mapsize,
 	    BUS_DMASYNC_PREWRITE);
 	/* Pass first to device */
 	sc->sc_descm->tx_set_owned_by_dev(&sc->sc_txq.t_desc[first]);
 	bus_dmamap_sync(sc->sc_dmat, map, 0, map->dm_mapsize,
 	    BUS_DMASYNC_PREWRITE);
 	return 0;
+}
 /*
  * If the interface is up and running, only modify the receive
  * filter when setting promiscuous or debug mode.  Otherwise fall
  * through to ether_ioctl, which will reset the chip.
  */
 static int
 dwc_gmac_ifflags_cb(struct ethercom *ec)
+{
 	struct ifnet *ifp = &ec->ec_if;
 	struct dwc_gmac_softc *sc = ifp->if_softc;
 	int ret = 0;
 	mutex_enter(sc->sc_lock);
 	u_short change = ifp->if_flags ^ sc->sc_if_flags;
 	sc->sc_if_flags = ifp->if_flags;
 	if ((change & ~(IFF_CANTCHANGE | IFF_DEBUG)) != 0) {
 		ret = ENETRESET;
 		goto out;
+	}
 	if ((change & IFF_PROMISC) != 0) {
 		dwc_gmac_setmulti(sc);
+	}
 out:
 	mutex_exit(sc->sc_lock);
 	return ret;
+}
 static int
 dwc_gmac_ioctl(struct ifnet *ifp, u_long cmd, void *data)
+{
 	struct dwc_gmac_softc *sc = ifp->if_softc;
 	int error = 0;
 	int s = splnet();
 	error = ether_ioctl(ifp, cmd, data);
 #ifdef DWCGMAC_MPSAFE
 	splx(s);
 #endif
 	if (error == ENETRESET) {
 		error = 0;
 		if (cmd != SIOCADDMULTI && cmd != SIOCDELMULTI)
+			;
 		else if (ifp->if_flags & IFF_RUNNING) {
 			/*
 			 * Multicast list has changed; set the hardware filter
 			 * accordingly.
 			 */
 			mutex_enter(sc->sc_lock);
 			dwc_gmac_setmulti(sc);
 			mutex_exit(sc->sc_lock);
+		}
+	}
 	/* Try to get things going again */
 	if (ifp->if_flags & IFF_UP)
 		dwc_gmac_start(ifp);
 	sc->sc_if_flags = sc->sc_ec.ec_if.if_flags;
 #ifndef DWCGMAC_MPSAFE
 	splx(s);
 #endif
 	return error;
+}
 static void
 dwc_gmac_tx_intr(struct dwc_gmac_softc *sc)
+{
 	struct ifnet *ifp = &sc->sc_ec.ec_if;
 	struct dwc_gmac_tx_data *data;
 	struct dwc_gmac_dev_dmadesc *desc;
 	int i, nsegs;
 	mutex_enter(&sc->sc_txq.t_mtx);
 	for (i = sc->sc_txq.t_next; sc->sc_txq.t_queued > 0; i = TX_NEXT(i)) {
 #ifdef DWC_GMAC_DEBUG
 		aprint_normal_dev(sc->sc_dev,
 		    "dwc_gmac_tx_intr: checking desc #%d (t_queued: %d)\n",
 		    i, sc->sc_txq.t_queued);
 #endif
 		/*
 		 * i+1 does not need to be a valid descriptor,
 		 * this is just a special notion to just sync
 		 * a single tx descriptor (i)
 		 */
 		dwc_gmac_txdesc_sync(sc, i, i+1,
 		    BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE);
 		desc = &sc->sc_txq.t_desc[i];
 		if (sc->sc_descm->tx_is_owned_by_dev(desc))
 			break;
 		data = &sc->sc_txq.t_data[i];
 		if (data->td_m == NULL)
 			continue;
-		ifp->if_opackets++;
+		if_statinc(ifp, if_opackets);
 		nsegs = data->td_active->dm_nsegs;
 		bus_dmamap_sync(sc->sc_dmat, data->td_active, 0,
 		    data->td_active->dm_mapsize, BUS_DMASYNC_POSTWRITE);
 		bus_dmamap_unload(sc->sc_dmat, data->td_active);
 #ifdef DWC_GMAC_DEBUG
 		aprint_normal_dev(sc->sc_dev,
 		    "dwc_gmac_tx_intr: done with packet at desc #%d, "
 		    "freeing mbuf %p\n", i, data->td_m);
 #endif
 		m_freem(data->td_m);
 		data->td_m = NULL;
 		sc->sc_txq.t_queued -= nsegs;
+	}
 	sc->sc_txq.t_next = i;
 	if (sc->sc_txq.t_queued < AWGE_TX_RING_COUNT) {
 		ifp->if_flags &= ~IFF_OACTIVE;
+	}
 	mutex_exit(&sc->sc_txq.t_mtx);
+}
 static void
 dwc_gmac_rx_intr(struct dwc_gmac_softc *sc)
+{
 	struct ifnet *ifp = &sc->sc_ec.ec_if;
 	struct dwc_gmac_dev_dmadesc *desc;
 	struct dwc_gmac_rx_data *data;
 	bus_addr_t physaddr;
 	struct mbuf *m, *mnew;
 	int i, len, error;
 	mutex_enter(&sc->sc_rxq.r_mtx);
 	for (i = sc->sc_rxq.r_cur; ; i = RX_NEXT(i)) {
 		bus_dmamap_sync(sc->sc_dmat, sc->sc_dma_ring_map,
 		    RX_DESC_OFFSET(i), sizeof(*desc),
 		    BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE);
 		desc = &sc->sc_rxq.r_desc[i];
 		data = &sc->sc_rxq.r_data[i];
 		if (sc->sc_descm->rx_is_owned_by_dev(desc))
 			break;
 		if (sc->sc_descm->rx_has_error(desc)) {
 #ifdef DWC_GMAC_DEBUG
 			aprint_normal_dev(sc->sc_dev,
 			    "RX error: descriptor status %08x, skipping\n",
 			    le32toh(desc->ddesc_status0));
 #endif
-			ifp->if_ierrors++;
+			if_statinc(ifp, if_ierrors);
 			goto skip;
+		}
 		len = sc->sc_descm->rx_get_len(desc);
 #ifdef DWC_GMAC_DEBUG
 		aprint_normal_dev(sc->sc_dev,
 		    "rx int: device is done with descriptor #%d, len: %d\n",
 		    i, len);
 #endif
 		/*
 		 * Try to get a new mbuf before passing this one
 		 * up, if that fails, drop the packet and reuse
 		 * the existing one.
 		 */
 		MGETHDR(mnew, M_DONTWAIT, MT_DATA);
 		if (mnew == NULL) {
-			ifp->if_ierrors++;
+			if_statinc(ifp, if_ierrors);
 			goto skip;
+		}
 		MCLGET(mnew, M_DONTWAIT);
 		if ((mnew->m_flags & M_EXT) == 0) {
 			m_freem(mnew);
-			ifp->if_ierrors++;
+			if_statinc(ifp, if_ierrors);
 			goto skip;
+		}
 		mnew->m_len = mnew->m_pkthdr.len = mnew->m_ext.ext_size;
 		if (mnew->m_len > AWGE_MAX_PACKET) {
 			mnew->m_len = mnew->m_pkthdr.len = AWGE_MAX_PACKET;
+		}
 		/* unload old DMA map */
 		bus_dmamap_sync(sc->sc_dmat, data->rd_map, 0,
 		    data->rd_map->dm_mapsize, BUS_DMASYNC_POSTREAD);
 		bus_dmamap_unload(sc->sc_dmat, data->rd_map);
 		/* and reload with new mbuf */
 		error = bus_dmamap_load_mbuf(sc->sc_dmat, data->rd_map,
 		    mnew, BUS_DMA_READ | BUS_DMA_NOWAIT);
 		if (error != 0) {
 			m_freem(mnew);
 			/* try to reload old mbuf */
 			error = bus_dmamap_load_mbuf(sc->sc_dmat, data->rd_map,
 			    data->rd_m, BUS_DMA_READ | BUS_DMA_NOWAIT);
 			if (error != 0) {
 				panic("%s: could not load old rx mbuf",
 				    device_xname(sc->sc_dev));
+			}
-			ifp->if_ierrors++;
+			if_statinc(ifp, if_ierrors);
 			goto skip;
+		}
 		physaddr = data->rd_map->dm_segs[0].ds_addr;
 		/*
 		 * New mbuf loaded, update RX ring and continue
 		 */
 		m = data->rd_m;
 		data->rd_m = mnew;
 		desc->ddesc_data = htole32(physaddr);
 		/* finalize mbuf */
 		m->m_pkthdr.len = m->m_len = len;
 		m_set_rcvif(m, ifp);
 		m->m_flags |= M_HASFCS;
 		if_percpuq_enqueue(sc->sc_ipq, m);
 skip:
 		bus_dmamap_sync(sc->sc_dmat, data->rd_map, 0,
 		    data->rd_map->dm_mapsize, BUS_DMASYNC_PREREAD);
 		sc->sc_descm->rx_init_flags(desc);
 		sc->sc_descm->rx_set_len(desc, data->rd_m->m_len);
 		sc->sc_descm->rx_set_owned_by_dev(desc);
 		bus_dmamap_sync(sc->sc_dmat, sc->sc_dma_ring_map,
 		    RX_DESC_OFFSET(i), sizeof(*desc),
 		    BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
+	}
 	/* update RX pointer */
 	sc->sc_rxq.r_cur = i;
 	mutex_exit(&sc->sc_rxq.r_mtx);
+}
 /*
  * Reverse order of bits - http://aggregate.org/MAGIC/#Bit%20Reversal
  */
 static uint32_t
 bitrev32(uint32_t x)
+{
 	x = (((x & 0xaaaaaaaa) >> 1) | ((x & 0x55555555) << 1));
 	x = (((x & 0xcccccccc) >> 2) | ((x & 0x33333333) << 2));
 	x = (((x & 0xf0f0f0f0) >> 4) | ((x & 0x0f0f0f0f) << 4));
 	x = (((x & 0xff00ff00) >> 8) | ((x & 0x00ff00ff) << 8));
 	return (x >> 16) | (x << 16);
+}
 static void
 dwc_gmac_setmulti(struct dwc_gmac_softc *sc)
+{
 	struct ifnet * const ifp = &sc->sc_ec.ec_if;
 	struct ether_multi *enm;
 	struct ether_multistep step;
 	struct ethercom *ec = &sc->sc_ec;
 	uint32_t hashes[2] = { 0, 0 };
 	uint32_t ffilt, h;
 	int mcnt;
 	KASSERT(mutex_owned(sc->sc_lock));
 	ffilt = bus_space_read_4(sc->sc_bst, sc->sc_bsh, AWIN_GMAC_MAC_FFILT);
 	if (ifp->if_flags & IFF_PROMISC) {
 		ffilt |= AWIN_GMAC_MAC_FFILT_PR;
 		goto special_filter;
+	}
 	ffilt &= ~(AWIN_GMAC_MAC_FFILT_PM | AWIN_GMAC_MAC_FFILT_PR);
 	bus_space_write_4(sc->sc_bst, sc->sc_bsh, AWIN_GMAC_MAC_HTLOW, 0);
 	bus_space_write_4(sc->sc_bst, sc->sc_bsh, AWIN_GMAC_MAC_HTHIGH, 0);
 	ETHER_LOCK(ec);
 	ec->ec_flags &= ~ETHER_F_ALLMULTI;
 	ETHER_FIRST_MULTI(step, ec, enm);
 	mcnt = 0;
 	while (enm != NULL) {
 		if (memcmp(enm->enm_addrlo, enm->enm_addrhi,
 		    ETHER_ADDR_LEN) != 0) {
 			ffilt |= AWIN_GMAC_MAC_FFILT_PM;
 			ec->ec_flags |= ETHER_F_ALLMULTI;
 			ETHER_UNLOCK(ec);
 			goto special_filter;
+		}
 		h = bitrev32(
 			~ether_crc32_le(enm->enm_addrlo, ETHER_ADDR_LEN)
 		    ) >> 26;
 		hashes[h >> 5] |= (1 << (h & 0x1f));
 		mcnt++;
 		ETHER_NEXT_MULTI(step, enm);
+	}
 	ETHER_UNLOCK(ec);
 	if (mcnt)
 		ffilt |= AWIN_GMAC_MAC_FFILT_HMC;
 	else
 		ffilt &= ~AWIN_GMAC_MAC_FFILT_HMC;
 	bus_space_write_4(sc->sc_bst, sc->sc_bsh, AWIN_GMAC_MAC_FFILT, ffilt);
 	bus_space_write_4(sc->sc_bst, sc->sc_bsh, AWIN_GMAC_MAC_HTLOW,
 	    hashes[0]);
 	bus_space_write_4(sc->sc_bst, sc->sc_bsh, AWIN_GMAC_MAC_HTHIGH,
 	    hashes[1]);
 	sc->sc_if_flags = ifp->if_flags;
 #ifdef DWC_GMAC_DEBUG
 	dwc_gmac_dump_ffilt(sc, ffilt);
 #endif
 	return;
 special_filter:
 #ifdef DWC_GMAC_DEBUG
 	dwc_gmac_dump_ffilt(sc, ffilt);
 #endif
 	/* no MAC hashes, ALLMULTI or PROMISC */
 	bus_space_write_4(sc->sc_bst, sc->sc_bsh, AWIN_GMAC_MAC_FFILT,
 	    ffilt);
 	bus_space_write_4(sc->sc_bst, sc->sc_bsh, AWIN_GMAC_MAC_HTLOW,
 xffffffff);
 	bus_space_write_4(sc->sc_bst, sc->sc_bsh, AWIN_GMAC_MAC_HTHIGH,
 xffffffff);
 	sc->sc_if_flags = sc->sc_ec.ec_if.if_flags;
+}
 int
 dwc_gmac_intr(struct dwc_gmac_softc *sc)
+{
 	uint32_t status, dma_status;
 	int rv = 0;
 	if (sc->sc_stopping)
 		return 0;
 	status = bus_space_read_4(sc->sc_bst, sc->sc_bsh, AWIN_GMAC_MAC_INTR);
 	if (status & AWIN_GMAC_MII_IRQ) {
 		(void)bus_space_read_4(sc->sc_bst, sc->sc_bsh,
 		    AWIN_GMAC_MII_STATUS);
 		rv = 1;
 		mii_pollstat(&sc->sc_mii);
+	}
 	dma_status = bus_space_read_4(sc->sc_bst, sc->sc_bsh,
 	    AWIN_GMAC_DMA_STATUS);
 	if (dma_status & (GMAC_DMA_INT_NIE | GMAC_DMA_INT_AIE))
 		rv = 1;
 	if (dma_status & GMAC_DMA_INT_TIE)
 		dwc_gmac_tx_intr(sc);
 	if (dma_status & GMAC_DMA_INT_RIE)
 		dwc_gmac_rx_intr(sc);
 	/*
 	 * Check error conditions
 	 */
 	if (dma_status & GMAC_DMA_INT_ERRORS) {
-		sc->sc_ec.ec_if.if_oerrors++;
+		if_statinc(&sc->sc_ec.ec_if, if_oerrors);
 #ifdef DWC_GMAC_DEBUG
 		dwc_dump_and_abort(sc, "interrupt error condition");
 #endif
+	}
 	rnd_add_uint32(&sc->rnd_source, dma_status);
 	/* ack interrupt */
 	if (dma_status)
 		bus_space_write_4(sc->sc_bst, sc->sc_bsh,
 		    AWIN_GMAC_DMA_STATUS, dma_status & GMAC_DMA_INT_MASK);
 	/*
 	 * Get more packets
 	 */
 	if (rv)
 		if_schedule_deferred_start(&sc->sc_ec.ec_if);
 	return rv;
+}
 static void
 dwc_gmac_desc_set_owned_by_dev(struct dwc_gmac_dev_dmadesc *desc)
+{
 	desc->ddesc_status0 |= htole32(DDESC_STATUS_OWNEDBYDEV);
+}
 static int
 dwc_gmac_desc_is_owned_by_dev(struct dwc_gmac_dev_dmadesc *desc)
+{
 	return !!(le32toh(desc->ddesc_status0) & DDESC_STATUS_OWNEDBYDEV);
+}
 static void
 dwc_gmac_desc_std_set_len(struct dwc_gmac_dev_dmadesc *desc, int len)
+{
 	uint32_t cntl = le32toh(desc->ddesc_cntl1);
 	desc->ddesc_cntl1 = htole32((cntl & ~DDESC_CNTL_SIZE1MASK) |
 		__SHIFTIN(len, DDESC_CNTL_SIZE1MASK));
+}
 static uint32_t
 dwc_gmac_desc_std_get_len(struct dwc_gmac_dev_dmadesc *desc)
+{
 	return __SHIFTOUT(le32toh(desc->ddesc_status0), DDESC_STATUS_FRMLENMSK);
+}
 static void
 dwc_gmac_desc_std_tx_init_flags(struct dwc_gmac_dev_dmadesc *desc)
+{
 	desc->ddesc_status0 = 0;
 	desc->ddesc_cntl1 = htole32(DDESC_CNTL_TXCHAIN);
+}
 static void
 dwc_gmac_desc_std_tx_set_first_frag(struct dwc_gmac_dev_dmadesc *desc)
+{
 	uint32_t cntl = le32toh(desc->ddesc_cntl1);
 	desc->ddesc_cntl1 = htole32(cntl | DDESC_CNTL_TXFIRST);
+}
 static void
 dwc_gmac_desc_std_tx_set_last_frag(struct dwc_gmac_dev_dmadesc *desc)
+{
 	uint32_t cntl = le32toh(desc->ddesc_cntl1);
 	desc->ddesc_cntl1 = htole32(cntl |
 		DDESC_CNTL_TXLAST | DDESC_CNTL_TXINT);
+}
 static void
 dwc_gmac_desc_std_rx_init_flags(struct dwc_gmac_dev_dmadesc *desc)
+{
 	desc->ddesc_status0 = 0;
 	desc->ddesc_cntl1 = htole32(DDESC_CNTL_TXCHAIN);
+}
 static int
 dwc_gmac_desc_std_rx_has_error(struct dwc_gmac_dev_dmadesc *desc) {
 	return !!(le32toh(desc->ddesc_status0) &
 		(DDESC_STATUS_RXERROR | DDESC_STATUS_RXTRUNCATED));
+}
 static void
 dwc_gmac_desc_enh_set_len(struct dwc_gmac_dev_dmadesc *desc, int len)
+{
 	uint32_t tdes1 = le32toh(desc->ddesc_cntl1);
 	desc->ddesc_cntl1 = htole32((tdes1 & ~DDESC_DES1_SIZE1MASK) |
 		__SHIFTIN(len, DDESC_DES1_SIZE1MASK));
+}
 static uint32_t
 dwc_gmac_desc_enh_get_len(struct dwc_gmac_dev_dmadesc *desc)
+{
 	return __SHIFTOUT(le32toh(desc->ddesc_status0), DDESC_RDES0_FL);
+}
 static void
 dwc_gmac_desc_enh_tx_init_flags(struct dwc_gmac_dev_dmadesc *desc)
+{
 	desc->ddesc_status0 = htole32(DDESC_TDES0_TCH);
 	desc->ddesc_cntl1 = 0;
+}
 static void
 dwc_gmac_desc_enh_tx_set_first_frag(struct dwc_gmac_dev_dmadesc *desc)
+{
 	uint32_t tdes0 = le32toh(desc->ddesc_status0);
 	desc->ddesc_status0 = htole32(tdes0 | DDESC_TDES0_FS);
+}
 static void
 dwc_gmac_desc_enh_tx_set_last_frag(struct dwc_gmac_dev_dmadesc *desc)
+{
 	uint32_t tdes0 = le32toh(desc->ddesc_status0);
 	desc->ddesc_status0 = htole32(tdes0 | DDESC_TDES0_LS | DDESC_TDES0_IC);
+}
 static void
 dwc_gmac_desc_enh_rx_init_flags(struct dwc_gmac_dev_dmadesc *desc)
+{
 	desc->ddesc_status0 = 0;
 	desc->ddesc_cntl1 = htole32(DDESC_RDES1_RCH);
+}
 static int
 dwc_gmac_desc_enh_rx_has_error(struct dwc_gmac_dev_dmadesc *desc)
+{
 	return !!(le32toh(desc->ddesc_status0) &
 		(DDESC_RDES0_ES | DDESC_RDES0_LE));
+}
 #ifdef DWC_GMAC_DEBUG
 static void
 dwc_gmac_dump_dma(struct dwc_gmac_softc *sc)
+{
 	aprint_normal_dev(sc->sc_dev, "busmode: %08x\n",
 	    bus_space_read_4(sc->sc_bst, sc->sc_bsh, AWIN_GMAC_DMA_BUSMODE));
 	aprint_normal_dev(sc->sc_dev, "tx poll: %08x\n",
 	    bus_space_read_4(sc->sc_bst, sc->sc_bsh, AWIN_GMAC_DMA_TXPOLL));
 	aprint_normal_dev(sc->sc_dev, "rx poll: %08x\n",
 	    bus_space_read_4(sc->sc_bst, sc->sc_bsh, AWIN_GMAC_DMA_RXPOLL));
 	aprint_normal_dev(sc->sc_dev, "rx descriptors: %08x\n",
 	    bus_space_read_4(sc->sc_bst, sc->sc_bsh, AWIN_GMAC_DMA_RX_ADDR));
 	aprint_normal_dev(sc->sc_dev, "tx descriptors: %08x\n",
 	    bus_space_read_4(sc->sc_bst, sc->sc_bsh, AWIN_GMAC_DMA_TX_ADDR));
 	aprint_normal_dev(sc->sc_dev, "status: %08x\n",
 	    bus_space_read_4(sc->sc_bst, sc->sc_bsh, AWIN_GMAC_DMA_STATUS));
 	aprint_normal_dev(sc->sc_dev, "op mode: %08x\n",
 	    bus_space_read_4(sc->sc_bst, sc->sc_bsh, AWIN_GMAC_DMA_OPMODE));
 	aprint_normal_dev(sc->sc_dev, "int enable: %08x\n",
 	    bus_space_read_4(sc->sc_bst, sc->sc_bsh, AWIN_GMAC_DMA_INTENABLE));
 	aprint_normal_dev(sc->sc_dev, "cur tx: %08x\n",
 	    bus_space_read_4(sc->sc_bst, sc->sc_bsh, AWIN_GMAC_DMA_CUR_TX_DESC));
 	aprint_normal_dev(sc->sc_dev, "cur rx: %08x\n",
 	    bus_space_read_4(sc->sc_bst, sc->sc_bsh, AWIN_GMAC_DMA_CUR_RX_DESC));
 	aprint_normal_dev(sc->sc_dev, "cur tx buffer: %08x\n",
 	    bus_space_read_4(sc->sc_bst, sc->sc_bsh, AWIN_GMAC_DMA_CUR_TX_BUFADDR));
 	aprint_normal_dev(sc->sc_dev, "cur rx buffer: %08x\n",
 	    bus_space_read_4(sc->sc_bst, sc->sc_bsh, AWIN_GMAC_DMA_CUR_RX_BUFADDR));
+}
 static void
 dwc_gmac_dump_tx_desc(struct dwc_gmac_softc *sc)
+{
 	int i;
 	aprint_normal_dev(sc->sc_dev, "TX queue: cur=%d, next=%d, queued=%d\n",
 	    sc->sc_txq.t_cur, sc->sc_txq.t_next, sc->sc_txq.t_queued);
 	aprint_normal_dev(sc->sc_dev, "TX DMA descriptors:\n");
 	for (i = 0; i < AWGE_TX_RING_COUNT; i++) {
 		struct dwc_gmac_dev_dmadesc *desc = &sc->sc_txq.t_desc[i];
 		aprint_normal("#%d (%08lx): status: %08x cntl: %08x "
 		    "data: %08x next: %08x\n",
 		    i, sc->sc_txq.t_physaddr +
 			i*sizeof(struct dwc_gmac_dev_dmadesc),
 		    le32toh(desc->ddesc_status0), le32toh(desc->ddesc_cntl1),
 		    le32toh(desc->ddesc_data), le32toh(desc->ddesc_next));
+	}
+}
 static void
 dwc_gmac_dump_rx_desc(struct dwc_gmac_softc *sc)
+{
 	int i;
 	aprint_normal_dev(sc->sc_dev, "RX queue: cur=%d, next=%d\n",
 	    sc->sc_rxq.r_cur, sc->sc_rxq.r_next);
 	aprint_normal_dev(sc->sc_dev, "RX DMA descriptors:\n");
 	for (i = 0; i < AWGE_RX_RING_COUNT; i++) {
 		struct dwc_gmac_dev_dmadesc *desc = &sc->sc_rxq.r_desc[i];
 		aprint_normal("#%d (%08lx): status: %08x cntl: %08x "
 		    "data: %08x next: %08x\n",
 		    i, sc->sc_rxq.r_physaddr +
 			i*sizeof(struct dwc_gmac_dev_dmadesc),
 		    le32toh(desc->ddesc_status0), le32toh(desc->ddesc_cntl1),
 		    le32toh(desc->ddesc_data), le32toh(desc->ddesc_next));
+	}
+}
 static void
 dwc_dump_status(struct dwc_gmac_softc *sc)
+{
 	uint32_t status = bus_space_read_4(sc->sc_bst, sc->sc_bsh,
 	     AWIN_GMAC_MAC_INTR);
 	uint32_t dma_status = bus_space_read_4(sc->sc_bst, sc->sc_bsh,
 	     AWIN_GMAC_DMA_STATUS);
 	char buf[200];
 	/* print interrupt state */
 	snprintb(buf, sizeof(buf), "\177\20"
 	    "b\x10""NI\0"
 	    "b\x0f""AI\0"
 	    "b\x0e""ER\0"
 	    "b\x0d""FB\0"
 	    "b\x0a""ET\0"
 	    "b\x09""RW\0"
 	    "b\x08""RS\0"
 	    "b\x07""RU\0"
 	    "b\x06""RI\0"
 	    "b\x05""UN\0"
 	    "b\x04""OV\0"
 	    "b\x03""TJ\0"
 	    "b\x02""TU\0"
 	    "b\x01""TS\0"
 	    "b\x00""TI\0"
 	    "\0", dma_status);
 	aprint_normal_dev(sc->sc_dev, "INTR status: %08x, DMA status: %s\n",
 	    status, buf);
+}
 static void
 dwc_dump_and_abort(struct dwc_gmac_softc *sc, const char *msg)
+{
 	dwc_dump_status(sc);
 	dwc_gmac_dump_ffilt(sc,
 	    bus_space_read_4(sc->sc_bst, sc->sc_bsh, AWIN_GMAC_MAC_FFILT));
 	dwc_gmac_dump_dma(sc);
 	dwc_gmac_dump_tx_desc(sc);
 	dwc_gmac_dump_rx_desc(sc);
 	panic("%s", msg);
+}
 static void dwc_gmac_dump_ffilt(struct dwc_gmac_softc *sc, uint32_t ffilt)
+{
 	char buf[200];
 	/* print filter setup */
 	snprintb(buf, sizeof(buf), "\177\20"
 	    "b\x1f""RA\0"
 	    "b\x0a""HPF\0"
 	    "b\x09""SAF\0"
 	    "b\x08""SAIF\0"
 	    "b\x05""DBF\0"
 	    "b\x04""PM\0"
 	    "b\x03""DAIF\0"
 	    "b\x02""HMC\0"
 	    "b\x01""HUC\0"
 	    "b\x00""PR\0"
 	    "\0", ffilt);
 	aprint_normal_dev(sc->sc_dev, "FFILT: %s\n", buf);
+}
 #endif