 @@ -1,1767 +1,1767 @@
-/* $NetBSD: if_ti.c,v 1.116 2020/03/03 05:41:36 msaitoh Exp $ */
+/* $NetBSD: if_ti.c,v 1.117 2020/03/05 15:33:13 msaitoh Exp $ */
 /*
  * Copyright (c) 1997, 1998, 1999
  *	Bill Paul <wpaul@ctr.columbia.edu>.  All rights reserved.
+ *
  * Redistribution and use in source and binary forms, with or without
  * modification, are permitted provided that the following conditions
  * are met:
  * 1. Redistributions of source code must retain the above copyright
  *    notice, this list of conditions and the following disclaimer.
  * 2. Redistributions in binary form must reproduce the above copyright
  *    notice, this list of conditions and the following disclaimer in the
  *    documentation and/or other materials provided with the distribution.
  * 3. All advertising materials mentioning features or use of this software
  *    must display the following acknowledgement:
  *	This product includes software developed by Bill Paul.
  * 4. Neither the name of the author nor the names of any co-contributors
  *    may be used to endorse or promote products derived from this software
  *    without specific prior written permission.
+ *
  * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND
  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
  * ARE DISCLAIMED.  IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD
  * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
  * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
  * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
  * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
  * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
  * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
  * THE POSSIBILITY OF SUCH DAMAGE.
+ *
  *	FreeBSD Id: if_ti.c,v 1.15 1999/08/14 15:45:03 wpaul Exp
  */
 /*
  * Alteon Networks Tigon PCI gigabit ethernet driver for FreeBSD.
  * Manuals, sample driver and firmware source kits are available
  * from http://www.alteon.com/support/openkits.
+ *
  * Written by Bill Paul <wpaul@ctr.columbia.edu>
  * Electrical Engineering Department
  * Columbia University, New York City
  */
 /*
  * The Alteon Networks Tigon chip contains an embedded R4000 CPU,
  * gigabit MAC, dual DMA channels and a PCI interface unit. NICs
  * using the Tigon may have anywhere from 512K to 2MB of SRAM. The
  * Tigon supports hardware IP, TCP and UCP checksumming, multicast
  * filtering and jumbo (9014 byte) frames. The hardware is largely
  * controlled by firmware, which must be loaded into the NIC during
  * initialization.
+ *
  * The Tigon 2 contains 2 R4000 CPUs and requires a newer firmware
  * revision, which supports new features such as extended commands,
  * extended jumbo receive ring desciptors and a mini receive ring.
+ *
  * Alteon Networks is to be commended for releasing such a vast amount
  * of development material for the Tigon NIC without requiring an NDA
  * (although they really should have done it a long time ago). With
  * any luck, the other vendors will finally wise up and follow Alteon's
  * stellar example.
+ *
  * The firmware for the Tigon 1 and 2 NICs is compiled directly into
  * this driver by #including it as a C header file. This bloats the
  * driver somewhat, but it's the easiest method considering that the
  * driver code and firmware code need to be kept in sync. The source
  * for the firmware is not provided with the FreeBSD distribution since
  * compiling it requires a GNU toolchain targeted for mips-sgi-irix5.3.
+ *
  * The following people deserve special thanks:
  * - Terry Murphy of 3Com, for providing a 3c985 Tigon 1 board
  *   for testing
  * - Raymond Lee of Netgear, for providing a pair of Netgear
  *   GA620 Tigon 2 boards for testing
  * - Ulf Zimmermann, for bringing the GA620 to my attention and
  *   convincing me to write this driver.
  * - Andrew Gallatin for providing FreeBSD/Alpha support.
  */
 #include <sys/cdefs.h>
-__KERNEL_RCSID(0, "$NetBSD: if_ti.c,v 1.116 2020/03/03 05:41:36 msaitoh Exp $");
+__KERNEL_RCSID(0, "$NetBSD: if_ti.c,v 1.117 2020/03/05 15:33:13 msaitoh Exp $");
 #include "opt_inet.h"
 #include <sys/param.h>
 #include <sys/systm.h>
 #include <sys/sockio.h>
 #include <sys/mbuf.h>
 #include <sys/malloc.h>
 #include <sys/kernel.h>
 #include <sys/socket.h>
 #include <sys/queue.h>
 #include <sys/device.h>
 #include <sys/reboot.h>
 #include <net/if.h>
 #include <net/if_arp.h>
 #include <net/if_ether.h>
 #include <net/if_dl.h>
 #include <net/if_media.h>
 #include <net/bpf.h>
 #ifdef INET
 #include <netinet/in.h>
 #include <netinet/if_inarp.h>
 #include <netinet/in_systm.h>
 #include <netinet/ip.h>
 #endif
 #include <sys/bus.h>
 #include <dev/pci/pcireg.h>
 #include <dev/pci/pcivar.h>
 #include <dev/pci/pcidevs.h>
 #include <dev/pci/if_tireg.h>
 #include <dev/microcode/tigon/ti_fw.h>
 #include <dev/microcode/tigon/ti_fw2.h>
 #define	TI_HOSTADDR(x, y)						\
 	do {								\
 		(x).ti_addr_lo = (uint32_t)(y);				\
 		if (sizeof(bus_addr_t) == 8)				\
 			(x).ti_addr_hi =				\
 			    (uint32_t)(((uint64_t)(y) >> 32));		\
 		else							\
 			(x).ti_addr_hi = 0;				\
 	} while (/*CONSTCOND*/0)
 /*
  * Various supported device vendors/types and their names.
  */
 static const struct ti_type ti_devs[] = {
 	{ PCI_VENDOR_ALTEON,	PCI_PRODUCT_ALTEON_ACENIC,
 		"Alteon AceNIC 1000BASE-SX Ethernet" },
 	{ PCI_VENDOR_ALTEON,	PCI_PRODUCT_ALTEON_ACENIC_COPPER,
 		"Alteon AceNIC 1000BASE-T Ethernet" },
 	{ PCI_VENDOR_3COM,	PCI_PRODUCT_3COM_3C985,
 		"3Com 3c985-SX Gigabit Ethernet" },
 	{ PCI_VENDOR_NETGEAR, PCI_PRODUCT_NETGEAR_GA620,
 		"Netgear GA620 1000BASE-SX Ethernet" },
 	{ PCI_VENDOR_NETGEAR, PCI_PRODUCT_NETGEAR_GA620T,
 		"Netgear GA620 1000BASE-T Ethernet" },
 	{ PCI_VENDOR_SGI, PCI_PRODUCT_SGI_TIGON,
 		"Silicon Graphics Gigabit Ethernet" },
 	{ 0, 0, NULL }
 };
 static const struct ti_type *ti_type_match(struct pci_attach_args *);
 static int ti_probe(device_t, cfdata_t, void *);
 static void ti_attach(device_t, device_t, void *);
 static bool ti_shutdown(device_t, int);
 static void ti_txeof_tigon1(struct ti_softc *);
 static void ti_txeof_tigon2(struct ti_softc *);
 static void ti_rxeof(struct ti_softc *);
 static void ti_stats_update(struct ti_softc *);
 static int ti_encap_tigon1(struct ti_softc *, struct mbuf *, uint32_t *);
 static int ti_encap_tigon2(struct ti_softc *, struct mbuf *, uint32_t *);
 static int ti_intr(void *);
 static void ti_start(struct ifnet *);
 static int ti_ioctl(struct ifnet *, u_long, void *);
 static void ti_init(void *);
 static void ti_init2(struct ti_softc *);
 static void ti_stop(struct ti_softc *);
 static void ti_watchdog(struct ifnet *);
 static int ti_ifmedia_upd(struct ifnet *);
 static void ti_ifmedia_sts(struct ifnet *, struct ifmediareq *);
 static uint32_t ti_eeprom_putbyte(struct ti_softc *, int);
 static uint8_t	ti_eeprom_getbyte(struct ti_softc *, int, uint8_t *);
 static int ti_read_eeprom(struct ti_softc *, void *, int, int);
 static void ti_add_mcast(struct ti_softc *, struct ether_addr *);
 static void ti_del_mcast(struct ti_softc *, struct ether_addr *);
 static void ti_setmulti(struct ti_softc *);
 static void ti_mem(struct ti_softc *, uint32_t, uint32_t, const void *);
 static void ti_loadfw(struct ti_softc *);
 static void ti_cmd(struct ti_softc *, struct ti_cmd_desc *);
 static void ti_cmd_ext(struct ti_softc *, struct ti_cmd_desc *, void *, int);
 static void ti_handle_events(struct ti_softc *);
 static int ti_alloc_jumbo_mem(struct ti_softc *);
 static void *ti_jalloc(struct ti_softc *);
 static void ti_jfree(struct mbuf *, void *, size_t, void *);
 static int ti_newbuf_std(struct ti_softc *, int, struct mbuf *, bus_dmamap_t);
 static int ti_newbuf_mini(struct ti_softc *, int, struct mbuf *, bus_dmamap_t);
 static int ti_newbuf_jumbo(struct ti_softc *, int, struct mbuf *);
 static int ti_init_rx_ring_std(struct ti_softc *);
 static void ti_free_rx_ring_std(struct ti_softc *);
 static int ti_init_rx_ring_jumbo(struct ti_softc *);
 static void ti_free_rx_ring_jumbo(struct ti_softc *);
 static int ti_init_rx_ring_mini(struct ti_softc *);
 static void ti_free_rx_ring_mini(struct ti_softc *);
 static void ti_free_tx_ring(struct ti_softc *);
 static int ti_init_tx_ring(struct ti_softc *);
 static int ti_64bitslot_war(struct ti_softc *);
 static int ti_chipinit(struct ti_softc *);
 static int ti_gibinit(struct ti_softc *);
 static int ti_ether_ioctl(struct ifnet *, u_long, void *);
 CFATTACH_DECL_NEW(ti, sizeof(struct ti_softc),
     ti_probe, ti_attach, NULL, NULL);
 /*
  * Send an instruction or address to the EEPROM, check for ACK.
  */
 static uint32_t
 ti_eeprom_putbyte(struct ti_softc *sc, int byte)
+{
 	int i, ack = 0;
 	/*
 	 * Make sure we're in TX mode.
 	 */
 	TI_SETBIT(sc, TI_MISC_LOCAL_CTL, TI_MLC_EE_TXEN);
 	/*
 	 * Feed in each bit and stobe the clock.
 	 */
 	for (i = 0x80; i; i >>= 1) {
 		if (byte & i) {
 			TI_SETBIT(sc, TI_MISC_LOCAL_CTL, TI_MLC_EE_DOUT);
 		} else {
 			TI_CLRBIT(sc, TI_MISC_LOCAL_CTL, TI_MLC_EE_DOUT);
+		}
 		DELAY(1);
 		TI_SETBIT(sc, TI_MISC_LOCAL_CTL, TI_MLC_EE_CLK);
 		DELAY(1);
 		TI_CLRBIT(sc, TI_MISC_LOCAL_CTL, TI_MLC_EE_CLK);
+	}
 	/*
 	 * Turn off TX mode.
 	 */
 	TI_CLRBIT(sc, TI_MISC_LOCAL_CTL, TI_MLC_EE_TXEN);
 	/*
 	 * Check for ack.
 	 */
 	TI_SETBIT(sc, TI_MISC_LOCAL_CTL, TI_MLC_EE_CLK);
 	ack = CSR_READ_4(sc, TI_MISC_LOCAL_CTL) & TI_MLC_EE_DIN;
 	TI_CLRBIT(sc, TI_MISC_LOCAL_CTL, TI_MLC_EE_CLK);
 	return (ack);
+}
 /*
  * Read a byte of data stored in the EEPROM at address 'addr.'
  * We have to send two address bytes since the EEPROM can hold
  * more than 256 bytes of data.
  */
 static uint8_t
 ti_eeprom_getbyte(struct ti_softc *sc, int addr, uint8_t *dest)
+{
 	int		i;
 	uint8_t		byte = 0;
 	EEPROM_START();
 	/*
 	 * Send write control code to EEPROM.
 	 */
 	if (ti_eeprom_putbyte(sc, EEPROM_CTL_WRITE)) {
 		printf("%s: failed to send write command, status: %x\n",
 		    device_xname(sc->sc_dev), CSR_READ_4(sc, TI_MISC_LOCAL_CTL));
 		return (1);
+	}
 	/*
 	 * Send first byte of address of byte we want to read.
 	 */
 	if (ti_eeprom_putbyte(sc, (addr >> 8) & 0xFF)) {
 		printf("%s: failed to send address, status: %x\n",
 		    device_xname(sc->sc_dev), CSR_READ_4(sc, TI_MISC_LOCAL_CTL));
 		return (1);
+	}
 	/*
 	 * Send second byte address of byte we want to read.
 	 */
 	if (ti_eeprom_putbyte(sc, addr & 0xFF)) {
 		printf("%s: failed to send address, status: %x\n",
 		    device_xname(sc->sc_dev), CSR_READ_4(sc, TI_MISC_LOCAL_CTL));
 		return (1);
+	}
 	EEPROM_STOP();
 	EEPROM_START();
 	/*
 	 * Send read control code to EEPROM.
 	 */
 	if (ti_eeprom_putbyte(sc, EEPROM_CTL_READ)) {
 		printf("%s: failed to send read command, status: %x\n",
 		    device_xname(sc->sc_dev), CSR_READ_4(sc, TI_MISC_LOCAL_CTL));
 		return (1);
+	}
 	/*
 	 * Start reading bits from EEPROM.
 	 */
 	TI_CLRBIT(sc, TI_MISC_LOCAL_CTL, TI_MLC_EE_TXEN);
 	for (i = 0x80; i; i >>= 1) {
 		TI_SETBIT(sc, TI_MISC_LOCAL_CTL, TI_MLC_EE_CLK);
 		DELAY(1);
 		if (CSR_READ_4(sc, TI_MISC_LOCAL_CTL) & TI_MLC_EE_DIN)
 			byte |= i;
 		TI_CLRBIT(sc, TI_MISC_LOCAL_CTL, TI_MLC_EE_CLK);
 		DELAY(1);
+	}
 	EEPROM_STOP();
 	/*
 	 * No ACK generated for read, so just return byte.
 	 */
 	*dest = byte;
 	return (0);
+}
 /*
  * Read a sequence of bytes from the EEPROM.
  */
 static int
 ti_read_eeprom(struct ti_softc *sc, void *destv, int off, int cnt)
+{
 	char *dest = destv;
 	int err = 0, i;
 	uint8_t byte = 0;
 	for (i = 0; i < cnt; i++) {
 		err = ti_eeprom_getbyte(sc, off + i, &byte);
 		if (err)
 			break;
 		*(dest + i) = byte;
+	}
 	return (err ? 1 : 0);
+}
 /*
  * NIC memory access function. Can be used to either clear a section
  * of NIC local memory or (if tbuf is non-NULL) copy data into it.
  */
 static void
 ti_mem(struct ti_softc *sc, uint32_t addr, uint32_t len, const void *xbuf)
+{
 	int			segptr, segsize, cnt;
 	const void		*ptr;
 	segptr = addr;
 	cnt = len;
 	ptr = xbuf;
 	while (cnt) {
 		if (cnt < TI_WINLEN)
 			segsize = cnt;
 		else
 			segsize = TI_WINLEN - (segptr % TI_WINLEN);
 		CSR_WRITE_4(sc, TI_WINBASE, (segptr & ~(TI_WINLEN - 1)));
 		if (xbuf == NULL) {
 			bus_space_set_region_4(sc->ti_btag, sc->ti_bhandle,
 			    TI_WINDOW + (segptr & (TI_WINLEN - 1)), 0,
 			    segsize / 4);
 		} else {
 #ifdef __BUS_SPACE_HAS_STREAM_METHODS
 			bus_space_write_region_stream_4(sc->ti_btag,
 			    sc->ti_bhandle,
 			    TI_WINDOW + (segptr & (TI_WINLEN - 1)),
 			    (const uint32_t *)ptr, segsize / 4);
 #else
 			bus_space_write_region_4(sc->ti_btag, sc->ti_bhandle,
 			    TI_WINDOW + (segptr & (TI_WINLEN - 1)),
 			    (const uint32_t *)ptr, segsize / 4);
 #endif
 			ptr = (const char *)ptr + segsize;
+		}
 		segptr += segsize;
 		cnt -= segsize;
+	}
 	return;
+}
 /*
  * Load firmware image into the NIC. Check that the firmware revision
  * is acceptable and see if we want the firmware for the Tigon 1 or
  * Tigon 2.
  */
 static void
 ti_loadfw(struct ti_softc *sc)
+{
 	switch (sc->ti_hwrev) {
 	case TI_HWREV_TIGON:
 		if (tigonFwReleaseMajor != TI_FIRMWARE_MAJOR ||
 		    tigonFwReleaseMinor != TI_FIRMWARE_MINOR ||
 		    tigonFwReleaseFix != TI_FIRMWARE_FIX) {
 			printf("%s: firmware revision mismatch; want "
 			    "%d.%d.%d, got %d.%d.%d\n", device_xname(sc->sc_dev),
 			    TI_FIRMWARE_MAJOR, TI_FIRMWARE_MINOR,
 			    TI_FIRMWARE_FIX, tigonFwReleaseMajor,
 			    tigonFwReleaseMinor, tigonFwReleaseFix);
 			return;
+		}
 		ti_mem(sc, tigonFwTextAddr, tigonFwTextLen, tigonFwText);
 		ti_mem(sc, tigonFwDataAddr, tigonFwDataLen, tigonFwData);
 		ti_mem(sc, tigonFwRodataAddr, tigonFwRodataLen, tigonFwRodata);
 		ti_mem(sc, tigonFwBssAddr, tigonFwBssLen, NULL);
 		ti_mem(sc, tigonFwSbssAddr, tigonFwSbssLen, NULL);
 		CSR_WRITE_4(sc, TI_CPU_PROGRAM_COUNTER, tigonFwStartAddr);
 		break;
 	case TI_HWREV_TIGON_II:
 		if (tigon2FwReleaseMajor != TI_FIRMWARE_MAJOR ||
 		    tigon2FwReleaseMinor != TI_FIRMWARE_MINOR ||
 		    tigon2FwReleaseFix != TI_FIRMWARE_FIX) {
 			printf("%s: firmware revision mismatch; want "
 			    "%d.%d.%d, got %d.%d.%d\n", device_xname(sc->sc_dev),
 			    TI_FIRMWARE_MAJOR, TI_FIRMWARE_MINOR,
 			    TI_FIRMWARE_FIX, tigon2FwReleaseMajor,
 			    tigon2FwReleaseMinor, tigon2FwReleaseFix);
 			return;
+		}
 		ti_mem(sc, tigon2FwTextAddr, tigon2FwTextLen, tigon2FwText);
 		ti_mem(sc, tigon2FwDataAddr, tigon2FwDataLen, tigon2FwData);
 		ti_mem(sc, tigon2FwRodataAddr, tigon2FwRodataLen,
 		    tigon2FwRodata);
 		ti_mem(sc, tigon2FwBssAddr, tigon2FwBssLen, NULL);
 		ti_mem(sc, tigon2FwSbssAddr, tigon2FwSbssLen, NULL);
 		CSR_WRITE_4(sc, TI_CPU_PROGRAM_COUNTER, tigon2FwStartAddr);
 		break;
 	default:
 		printf("%s: can't load firmware: unknown hardware rev\n",
 		    device_xname(sc->sc_dev));
 		break;
+	}
 	return;
+}
 /*
  * Send the NIC a command via the command ring.
  */
 static void
 ti_cmd(struct ti_softc *sc, struct ti_cmd_desc *cmd)
+{
 	uint32_t		index;
 	index = sc->ti_cmd_saved_prodidx;
 	CSR_WRITE_4(sc, TI_GCR_CMDRING + (index * 4), *(uint32_t *)(cmd));
 	TI_INC(index, TI_CMD_RING_CNT);
 	CSR_WRITE_4(sc, TI_MB_CMDPROD_IDX, index);
 	sc->ti_cmd_saved_prodidx = index;
+}
 /*
  * Send the NIC an extended command. The 'len' parameter specifies the
  * number of command slots to include after the initial command.
  */
 static void
 ti_cmd_ext(struct ti_softc *sc, struct ti_cmd_desc *cmd, void *argv, int len)
+{
 	char		*arg = argv;
 	uint32_t	index;
 	int		i;
 	index = sc->ti_cmd_saved_prodidx;
 	CSR_WRITE_4(sc, TI_GCR_CMDRING + (index * 4), *(uint32_t *)(cmd));
 	TI_INC(index, TI_CMD_RING_CNT);
 	for (i = 0; i < len; i++) {
 		CSR_WRITE_4(sc, TI_GCR_CMDRING + (index * 4),
 		    *(uint32_t *)(&arg[i * 4]));
 		TI_INC(index, TI_CMD_RING_CNT);
+	}
 	CSR_WRITE_4(sc, TI_MB_CMDPROD_IDX, index);
 	sc->ti_cmd_saved_prodidx = index;
+}
 /*
  * Handle events that have triggered interrupts.
  */
 static void
 ti_handle_events(struct ti_softc *sc)
+{
 	struct ti_event_desc	*e;
 	while (sc->ti_ev_saved_considx != sc->ti_ev_prodidx.ti_idx) {
 		e = &sc->ti_rdata->ti_event_ring[sc->ti_ev_saved_considx];
 		switch (TI_EVENT_EVENT(e)) {
 		case TI_EV_LINKSTAT_CHANGED:
 			sc->ti_linkstat = TI_EVENT_CODE(e);
 			if (sc->ti_linkstat == TI_EV_CODE_LINK_UP)
 				printf("%s: 10/100 link up\n",
 				       device_xname(sc->sc_dev));
 			else if (sc->ti_linkstat == TI_EV_CODE_GIG_LINK_UP)
 				printf("%s: gigabit link up\n",
 				       device_xname(sc->sc_dev));
 			else if (sc->ti_linkstat == TI_EV_CODE_LINK_DOWN)
 				printf("%s: link down\n",
 				       device_xname(sc->sc_dev));
 			break;
 		case TI_EV_ERROR:
 			if (TI_EVENT_CODE(e) == TI_EV_CODE_ERR_INVAL_CMD)
 				printf("%s: invalid command\n",
 				       device_xname(sc->sc_dev));
 			else if (TI_EVENT_CODE(e) == TI_EV_CODE_ERR_UNIMP_CMD)
 				printf("%s: unknown command\n",
 				       device_xname(sc->sc_dev));
 			else if (TI_EVENT_CODE(e) == TI_EV_CODE_ERR_BADCFG)
 				printf("%s: bad config data\n",
 				       device_xname(sc->sc_dev));
 			break;
 		case TI_EV_FIRMWARE_UP:
 			ti_init2(sc);
 			break;
 		case TI_EV_STATS_UPDATED:
 			ti_stats_update(sc);
 			break;
 		case TI_EV_RESET_JUMBO_RING:
 		case TI_EV_MCAST_UPDATED:
 			/* Who cares. */
 			break;
 		default:
 			printf("%s: unknown event: %d\n",
 			    device_xname(sc->sc_dev), TI_EVENT_EVENT(e));
 			break;
+		}
 		/* Advance the consumer index. */
 		TI_INC(sc->ti_ev_saved_considx, TI_EVENT_RING_CNT);
 		CSR_WRITE_4(sc, TI_GCR_EVENTCONS_IDX, sc->ti_ev_saved_considx);
+	}
 	return;
+}
 /*
  * Memory management for the jumbo receive ring is a pain in the
  * butt. We need to allocate at least 9018 bytes of space per frame,
  * _and_ it has to be contiguous (unless you use the extended
  * jumbo descriptor format). Using malloc() all the time won't
  * work: malloc() allocates memory in powers of two, which means we
  * would end up wasting a considerable amount of space by allocating
  * 9K chunks. We don't have a jumbo mbuf cluster pool. Thus, we have
  * to do our own memory management.
+ *
  * The driver needs to allocate a contiguous chunk of memory at boot
  * time. We then chop this up ourselves into 9K pieces and use them
  * as external mbuf storage.
+ *
  * One issue here is how much memory to allocate. The jumbo ring has
  * 256 slots in it, but at 9K per slot than can consume over 2MB of
  * RAM. This is a bit much, especially considering we also need
  * RAM for the standard ring and mini ring (on the Tigon 2). To
  * save space, we only actually allocate enough memory for 64 slots
  * by default, which works out to between 500 and 600K. This can
  * be tuned by changing a #define in if_tireg.h.
  */
 static int
 ti_alloc_jumbo_mem(struct ti_softc *sc)
+{
 	char *ptr;
 	int i;
 	struct ti_jpool_entry	*entry;
 	bus_dma_segment_t dmaseg;
 	int error, dmanseg;
 	/* Grab a big chunk o' storage. */
 	if ((error = bus_dmamem_alloc(sc->sc_dmat,
 	    TI_JMEM, PAGE_SIZE, 0, &dmaseg, 1, &dmanseg,
 	    BUS_DMA_NOWAIT)) != 0) {
 		aprint_error_dev(sc->sc_dev,
 		    "can't allocate jumbo buffer, error = %d\n", error);
 		return (error);
+	}
 	if ((error = bus_dmamem_map(sc->sc_dmat, &dmaseg, dmanseg,
 	    TI_JMEM, (void **)&sc->ti_cdata.ti_jumbo_buf,
 	    BUS_DMA_NOWAIT | BUS_DMA_COHERENT)) != 0) {
 		aprint_error_dev(sc->sc_dev,
 		    "can't map jumbo buffer, error = %d\n", error);
 		return (error);
+	}
 	if ((error = bus_dmamap_create(sc->sc_dmat,
 	    TI_JMEM, 1,
 	    TI_JMEM, 0, BUS_DMA_NOWAIT,
 	    &sc->jumbo_dmamap)) != 0) {
 		aprint_error_dev(sc->sc_dev,
 		    "can't create jumbo buffer DMA map, error = %d\n", error);
 		return (error);
+	}
 	if ((error = bus_dmamap_load(sc->sc_dmat, sc->jumbo_dmamap,
 	    sc->ti_cdata.ti_jumbo_buf, TI_JMEM, NULL,
 	    BUS_DMA_NOWAIT)) != 0) {
 		aprint_error_dev(sc->sc_dev,
 		    "can't load jumbo buffer DMA map, error = %d\n", error);
 		return (error);
+	}
 	sc->jumbo_dmaaddr = sc->jumbo_dmamap->dm_segs[0].ds_addr;
 	SIMPLEQ_INIT(&sc->ti_jfree_listhead);
 	SIMPLEQ_INIT(&sc->ti_jinuse_listhead);
 	/*
 	 * Now divide it up into 9K pieces and save the addresses
 	 * in an array.
 	 */
 	ptr = sc->ti_cdata.ti_jumbo_buf;
 	for (i = 0; i < TI_JSLOTS; i++) {
 		sc->ti_cdata.ti_jslots[i] = ptr;
 		ptr += TI_JLEN;
 		entry = malloc(sizeof(struct ti_jpool_entry),
 			       M_DEVBUF, M_WAITOK);
 		entry->slot = i;
 		SIMPLEQ_INSERT_HEAD(&sc->ti_jfree_listhead, entry,
 				    jpool_entries);
+	}
 	return (0);
+}
 /*
  * Allocate a jumbo buffer.
  */
 static void *
 ti_jalloc(struct ti_softc *sc)
+{
 	struct ti_jpool_entry	*entry;
 	entry = SIMPLEQ_FIRST(&sc->ti_jfree_listhead);
 	if (entry == NULL) {
 		printf("%s: no free jumbo buffers\n", device_xname(sc->sc_dev));
 		return (NULL);
+	}
 	SIMPLEQ_REMOVE_HEAD(&sc->ti_jfree_listhead, jpool_entries);
 	SIMPLEQ_INSERT_HEAD(&sc->ti_jinuse_listhead, entry, jpool_entries);
 	return (sc->ti_cdata.ti_jslots[entry->slot]);
+}
 /*
  * Release a jumbo buffer.
  */
 static void
 ti_jfree(struct mbuf *m, void *tbuf, size_t size, void *arg)
+{
 	struct ti_softc		*sc;
 	int			i, s;
 	struct ti_jpool_entry	*entry;
 	/* Extract the softc struct pointer. */
 	sc = (struct ti_softc *)arg;
 	if (sc == NULL)
 		panic("ti_jfree: didn't get softc pointer!");
 	/* calculate the slot this buffer belongs to */
 	i = ((char *)tbuf
 	     - (char *)sc->ti_cdata.ti_jumbo_buf) / TI_JLEN;
 	if ((i < 0) || (i >= TI_JSLOTS))
 		panic("ti_jfree: asked to free buffer that we don't manage!");
 	s = splvm();
 	entry = SIMPLEQ_FIRST(&sc->ti_jinuse_listhead);
 	if (entry == NULL)
 		panic("ti_jfree: buffer not in use!");
 	entry->slot = i;
 	SIMPLEQ_REMOVE_HEAD(&sc->ti_jinuse_listhead, jpool_entries);
 	SIMPLEQ_INSERT_HEAD(&sc->ti_jfree_listhead, entry, jpool_entries);
 	if (__predict_true(m != NULL))
 		pool_cache_put(mb_cache, m);
 	splx(s);
+}
 /*
  * Initialize a standard receive ring descriptor.
  */
 static int
 ti_newbuf_std(struct ti_softc *sc, int i, struct mbuf *m, bus_dmamap_t dmamap)
+{
 	struct mbuf		*m_new = NULL;
 	struct ti_rx_desc	*r;
 	int error;
 	if (dmamap == NULL) {
 		/* if (m) panic() */
 		if ((error = bus_dmamap_create(sc->sc_dmat, MCLBYTES, 1,
 					       MCLBYTES, 0, BUS_DMA_NOWAIT,
 					       &dmamap)) != 0) {
 			aprint_error_dev(sc->sc_dev,
 			    "can't create recv map, error = %d\n", error);
 			return (ENOMEM);
+		}
+	}
 	sc->std_dmamap[i] = dmamap;
 	if (m == NULL) {
 		MGETHDR(m_new, M_DONTWAIT, MT_DATA);
 		if (m_new == NULL) {
 			aprint_error_dev(sc->sc_dev,
 			    "mbuf allocation failed -- packet dropped!\n");
 			return (ENOBUFS);
+		}
 		MCLGET(m_new, M_DONTWAIT);
 		if (!(m_new->m_flags & M_EXT)) {
 			aprint_error_dev(sc->sc_dev,
 			    "cluster allocation failed -- packet dropped!\n");
 			m_freem(m_new);
 			return (ENOBUFS);
+		}
 		m_new->m_len = m_new->m_pkthdr.len = MCLBYTES;
 		m_adj(m_new, ETHER_ALIGN);
 		if ((error = bus_dmamap_load(sc->sc_dmat, dmamap,
 				mtod(m_new, void *), m_new->m_len, NULL,
 				BUS_DMA_READ | BUS_DMA_NOWAIT)) != 0) {
 			aprint_error_dev(sc->sc_dev,
 			    "can't load recv map, error = %d\n", error);
 			m_freem(m_new);
 			return (ENOMEM);
+		}
 	} else {
 		m_new = m;
 		m_new->m_len = m_new->m_pkthdr.len = MCLBYTES;
 		m_new->m_data = m_new->m_ext.ext_buf;
 		m_adj(m_new, ETHER_ALIGN);
 		/* reuse the dmamap */
+	}
 	sc->ti_cdata.ti_rx_std_chain[i] = m_new;
 	r = &sc->ti_rdata->ti_rx_std_ring[i];
 	TI_HOSTADDR(r->ti_addr, dmamap->dm_segs[0].ds_addr);
 	r->ti_type = TI_BDTYPE_RECV_BD;
 	r->ti_flags = 0;
 	if (sc->ethercom.ec_if.if_capenable & IFCAP_CSUM_IPv4_Rx)
 		r->ti_flags |= TI_BDFLAG_IP_CKSUM;
 	if (sc->ethercom.ec_if.if_capenable &
 	    (IFCAP_CSUM_TCPv4_Rx | IFCAP_CSUM_UDPv4_Rx))
 		r->ti_flags |= TI_BDFLAG_TCP_UDP_CKSUM;
 	r->ti_len = m_new->m_len; /* == ds_len */
 	r->ti_idx = i;
 	return (0);
+}
 /*
- * Intialize a mini receive ring descriptor. This only applies to
+ * Initialize a mini receive ring descriptor. This only applies to
  * the Tigon 2.
  */
 static int
 ti_newbuf_mini(struct ti_softc *sc, int i, struct mbuf *m, bus_dmamap_t dmamap)
+{
 	struct mbuf		*m_new = NULL;
 	struct ti_rx_desc	*r;
 	int error;
 	if (dmamap == NULL) {
 		/* if (m) panic() */
 		if ((error = bus_dmamap_create(sc->sc_dmat, MHLEN, 1,
 					       MHLEN, 0, BUS_DMA_NOWAIT,
 					       &dmamap)) != 0) {
 			aprint_error_dev(sc->sc_dev,
 			    "can't create recv map, error = %d\n", error);
 			return (ENOMEM);
+		}
+	}
 	sc->mini_dmamap[i] = dmamap;
 	if (m == NULL) {
 		MGETHDR(m_new, M_DONTWAIT, MT_DATA);
 		if (m_new == NULL) {
 			aprint_error_dev(sc->sc_dev,
 			    "mbuf allocation failed -- packet dropped!\n");
 			return (ENOBUFS);
+		}
 		m_new->m_len = m_new->m_pkthdr.len = MHLEN;
 		m_adj(m_new, ETHER_ALIGN);
 		if ((error = bus_dmamap_load(sc->sc_dmat, dmamap,
 				mtod(m_new, void *), m_new->m_len, NULL,
 				BUS_DMA_READ | BUS_DMA_NOWAIT)) != 0) {
 			aprint_error_dev(sc->sc_dev,
 			    "can't load recv map, error = %d\n", error);
 			m_freem(m_new);
 			return (ENOMEM);
+		}
 	} else {
 		m_new = m;
 		m_new->m_data = m_new->m_pktdat;
 		m_new->m_len = m_new->m_pkthdr.len = MHLEN;
 		m_adj(m_new, ETHER_ALIGN);
 		/* reuse the dmamap */
+	}
 	r = &sc->ti_rdata->ti_rx_mini_ring[i];
 	sc->ti_cdata.ti_rx_mini_chain[i] = m_new;
 	TI_HOSTADDR(r->ti_addr, dmamap->dm_segs[0].ds_addr);
 	r->ti_type = TI_BDTYPE_RECV_BD;
 	r->ti_flags = TI_BDFLAG_MINI_RING;
 	if (sc->ethercom.ec_if.if_capenable & IFCAP_CSUM_IPv4_Rx)
 		r->ti_flags |= TI_BDFLAG_IP_CKSUM;
 	if (sc->ethercom.ec_if.if_capenable &
 	    (IFCAP_CSUM_TCPv4_Rx | IFCAP_CSUM_UDPv4_Rx))
 		r->ti_flags |= TI_BDFLAG_TCP_UDP_CKSUM;
 	r->ti_len = m_new->m_len; /* == ds_len */
 	r->ti_idx = i;
 	return (0);
+}
 /*
  * Initialize a jumbo receive ring descriptor. This allocates
  * a jumbo buffer from the pool managed internally by the driver.
  */
 static int
 ti_newbuf_jumbo(struct ti_softc *sc, int i, struct mbuf *m)
+{
 	struct mbuf		*m_new = NULL;
 	struct ti_rx_desc	*r;
 	if (m == NULL) {
 		void *		tbuf = NULL;
 		/* Allocate the mbuf. */
 		MGETHDR(m_new, M_DONTWAIT, MT_DATA);
 		if (m_new == NULL) {
 			aprint_error_dev(sc->sc_dev,
 			    "mbuf allocation failed -- packet dropped!\n");
 			return (ENOBUFS);
+		}
 		/* Allocate the jumbo buffer */
 		tbuf = ti_jalloc(sc);
 		if (tbuf == NULL) {
 			m_freem(m_new);
 			aprint_error_dev(sc->sc_dev,
 			    "jumbo allocation failed -- packet dropped!\n");
 			return (ENOBUFS);
+		}
 		/* Attach the buffer to the mbuf. */
 		MEXTADD(m_new, tbuf, ETHER_MAX_LEN_JUMBO,
 		    M_DEVBUF, ti_jfree, sc);
 		m_new->m_flags |= M_EXT_RW;
 		m_new->m_len = m_new->m_pkthdr.len = ETHER_MAX_LEN_JUMBO;
 	} else {
 		m_new = m;
 		m_new->m_data = m_new->m_ext.ext_buf;
 		m_new->m_ext.ext_size = ETHER_MAX_LEN_JUMBO;
+	}
 	m_adj(m_new, ETHER_ALIGN);
 	/* Set up the descriptor. */
 	r = &sc->ti_rdata->ti_rx_jumbo_ring[i];
 	sc->ti_cdata.ti_rx_jumbo_chain[i] = m_new;
 	TI_HOSTADDR(r->ti_addr, sc->jumbo_dmaaddr +
 	    (mtod(m_new, char *) - (char *)sc->ti_cdata.ti_jumbo_buf));
 	r->ti_type = TI_BDTYPE_RECV_JUMBO_BD;
 	r->ti_flags = TI_BDFLAG_JUMBO_RING;
 	if (sc->ethercom.ec_if.if_capenable & IFCAP_CSUM_IPv4_Rx)
 		r->ti_flags |= TI_BDFLAG_IP_CKSUM;
 	if (sc->ethercom.ec_if.if_capenable &
 	    (IFCAP_CSUM_TCPv4_Rx | IFCAP_CSUM_UDPv4_Rx))
 		r->ti_flags |= TI_BDFLAG_TCP_UDP_CKSUM;
 	r->ti_len = m_new->m_len;
 	r->ti_idx = i;
 	return (0);
+}
 /*
  * The standard receive ring has 512 entries in it. At 2K per mbuf cluster,
  * that's 1MB or memory, which is a lot. For now, we fill only the first
  * 256 ring entries and hope that our CPU is fast enough to keep up with
  * the NIC.
  */
 static int
 ti_init_rx_ring_std(struct ti_softc *sc)
+{
 	int		i;
 	struct ti_cmd_desc	cmd;
 	for (i = 0; i < TI_SSLOTS; i++) {
 		if (ti_newbuf_std(sc, i, NULL, 0) == ENOBUFS)
 			return (ENOBUFS);
 	};
 	TI_UPDATE_STDPROD(sc, i - 1);
 	sc->ti_std = i - 1;
 	return (0);
+}
 static void
 ti_free_rx_ring_std(struct ti_softc *sc)
+{
 	int		i;
 	for (i = 0; i < TI_STD_RX_RING_CNT; i++) {
 		if (sc->ti_cdata.ti_rx_std_chain[i] != NULL) {
 			m_freem(sc->ti_cdata.ti_rx_std_chain[i]);
 			sc->ti_cdata.ti_rx_std_chain[i] = NULL;
 			/* if (sc->std_dmamap[i] == 0) panic() */
 			bus_dmamap_destroy(sc->sc_dmat, sc->std_dmamap[i]);
 			sc->std_dmamap[i] = 0;
+		}
 		memset((char *)&sc->ti_rdata->ti_rx_std_ring[i], 0,
 		    sizeof(struct ti_rx_desc));
+	}
 	return;
+}
 static int
 ti_init_rx_ring_jumbo(struct ti_softc *sc)
+{
 	int		i;
 	struct ti_cmd_desc	cmd;
 	for (i = 0; i < TI_JUMBO_RX_RING_CNT; i++) {
 		if (ti_newbuf_jumbo(sc, i, NULL) == ENOBUFS)
 			return (ENOBUFS);
 	};
 	TI_UPDATE_JUMBOPROD(sc, i - 1);
 	sc->ti_jumbo = i - 1;
 	return (0);
+}
 static void
 ti_free_rx_ring_jumbo(struct ti_softc *sc)
+{
 	int		i;
 	for (i = 0; i < TI_JUMBO_RX_RING_CNT; i++) {
 		if (sc->ti_cdata.ti_rx_jumbo_chain[i] != NULL) {
 			m_freem(sc->ti_cdata.ti_rx_jumbo_chain[i]);
 			sc->ti_cdata.ti_rx_jumbo_chain[i] = NULL;
+		}
 		memset((char *)&sc->ti_rdata->ti_rx_jumbo_ring[i], 0,
 		    sizeof(struct ti_rx_desc));
+	}
 	return;
+}
 static int
 ti_init_rx_ring_mini(struct ti_softc *sc)
+{
 	int		i;
 	for (i = 0; i < TI_MSLOTS; i++) {
 		if (ti_newbuf_mini(sc, i, NULL, 0) == ENOBUFS)
 			return (ENOBUFS);
 	};
 	TI_UPDATE_MINIPROD(sc, i - 1);
 	sc->ti_mini = i - 1;
 	return (0);
+}
 static void
 ti_free_rx_ring_mini(struct ti_softc *sc)
+{
 	int		i;
 	for (i = 0; i < TI_MINI_RX_RING_CNT; i++) {
 		if (sc->ti_cdata.ti_rx_mini_chain[i] != NULL) {
 			m_freem(sc->ti_cdata.ti_rx_mini_chain[i]);
 			sc->ti_cdata.ti_rx_mini_chain[i] = NULL;
 			/* if (sc->mini_dmamap[i] == 0) panic() */
 			bus_dmamap_destroy(sc->sc_dmat, sc->mini_dmamap[i]);
 			sc->mini_dmamap[i] = 0;
+		}
 		memset((char *)&sc->ti_rdata->ti_rx_mini_ring[i], 0,
 		    sizeof(struct ti_rx_desc));
+	}
 	return;
+}
 static void
 ti_free_tx_ring(struct ti_softc *sc)
+{
 	int		i;
 	struct txdmamap_pool_entry *dma;
 	for (i = 0; i < TI_TX_RING_CNT; i++) {
 		if (sc->ti_cdata.ti_tx_chain[i] != NULL) {
 			m_freem(sc->ti_cdata.ti_tx_chain[i]);
 			sc->ti_cdata.ti_tx_chain[i] = NULL;
 			/* if (sc->txdma[i] == 0) panic() */
 			SIMPLEQ_INSERT_HEAD(&sc->txdma_list, sc->txdma[i],
 					    link);
 			sc->txdma[i] = 0;
+		}
 		memset((char *)&sc->ti_rdata->ti_tx_ring[i], 0,
 		    sizeof(struct ti_tx_desc));
+	}
 	while ((dma = SIMPLEQ_FIRST(&sc->txdma_list))) {
 		SIMPLEQ_REMOVE_HEAD(&sc->txdma_list, link);
 		bus_dmamap_destroy(sc->sc_dmat, dma->dmamap);
 		free(dma, M_DEVBUF);
+	}
 	return;
+}
 static int
 ti_init_tx_ring(struct ti_softc *sc)
+{
 	int i, error;
 	bus_dmamap_t dmamap;
 	struct txdmamap_pool_entry *dma;
 	sc->ti_txcnt = 0;
 	sc->ti_tx_saved_considx = 0;
 	CSR_WRITE_4(sc, TI_MB_SENDPROD_IDX, 0);
 	SIMPLEQ_INIT(&sc->txdma_list);
 	for (i = 0; i < TI_RSLOTS; i++) {
 		/* I've seen mbufs with 30 fragments. */
 		if ((error = bus_dmamap_create(sc->sc_dmat,
 			    ETHER_MAX_LEN_JUMBO, 40, ETHER_MAX_LEN_JUMBO, 0,
 			    BUS_DMA_NOWAIT, &dmamap)) != 0) {
 			aprint_error_dev(sc->sc_dev,
 			    "can't create tx map, error = %d\n", error);
 			return (ENOMEM);
+		}
 		dma = malloc(sizeof(*dma), M_DEVBUF, M_NOWAIT);
 		if (!dma) {
 			aprint_error_dev(sc->sc_dev,
 			    "can't alloc txdmamap_pool_entry\n");
 			bus_dmamap_destroy(sc->sc_dmat, dmamap);
 			return (ENOMEM);
+		}
 		dma->dmamap = dmamap;
 		SIMPLEQ_INSERT_HEAD(&sc->txdma_list, dma, link);
+	}
 	return (0);
+}
 /*
  * The Tigon 2 firmware has a new way to add/delete multicast addresses,
  * but we have to support the old way too so that Tigon 1 cards will
  * work.
  */
 static void
 ti_add_mcast(struct ti_softc *sc, struct ether_addr *addr)
+{
 	struct ti_cmd_desc	cmd;
 	uint16_t		*m;
 	uint32_t		ext[2] = {0, 0};
 	m = (uint16_t *)&addr->ether_addr_octet[0]; /* XXX */
 	switch (sc->ti_hwrev) {
 	case TI_HWREV_TIGON:
 		CSR_WRITE_4(sc, TI_GCR_MAR0, htons(m[0]));
 		CSR_WRITE_4(sc, TI_GCR_MAR1, (htons(m[1]) << 16) | htons(m[2]));
 		TI_DO_CMD(TI_CMD_ADD_MCAST_ADDR, 0, 0);
 		break;
 	case TI_HWREV_TIGON_II:
 		ext[0] = htons(m[0]);
 		ext[1] = (htons(m[1]) << 16) | htons(m[2]);
 		TI_DO_CMD_EXT(TI_CMD_EXT_ADD_MCAST, 0, 0, (void *)&ext, 2);
 		break;
 	default:
 		printf("%s: unknown hwrev\n", device_xname(sc->sc_dev));
 		break;
+	}
 	return;
+}
 static void
 ti_del_mcast(struct ti_softc *sc, struct ether_addr *addr)
+{
 	struct ti_cmd_desc	cmd;
 	uint16_t		*m;
 	uint32_t		ext[2] = {0, 0};
 	m = (uint16_t *)&addr->ether_addr_octet[0]; /* XXX */
 	switch (sc->ti_hwrev) {
 	case TI_HWREV_TIGON:
 		CSR_WRITE_4(sc, TI_GCR_MAR0, htons(m[0]));
 		CSR_WRITE_4(sc, TI_GCR_MAR1, (htons(m[1]) << 16) | htons(m[2]));
 		TI_DO_CMD(TI_CMD_DEL_MCAST_ADDR, 0, 0);
 		break;
 	case TI_HWREV_TIGON_II:
 		ext[0] = htons(m[0]);
 		ext[1] = (htons(m[1]) << 16) | htons(m[2]);
 		TI_DO_CMD_EXT(TI_CMD_EXT_DEL_MCAST, 0, 0, (void *)&ext, 2);
 		break;
 	default:
 		printf("%s: unknown hwrev\n", device_xname(sc->sc_dev));
 		break;
+	}
 	return;
+}
 /*
  * Configure the Tigon's multicast address filter.
+ *
  * The actual multicast table management is a bit of a pain, thanks to
  * slight brain damage on the part of both Alteon and us. With our
  * multicast code, we are only alerted when the multicast address table
  * changes and at that point we only have the current list of addresses:
  * we only know the current state, not the previous state, so we don't
  * actually know what addresses were removed or added. The firmware has
  * state, but we can't get our grubby mits on it, and there is no 'delete
  * all multicast addresses' command. Hence, we have to maintain our own
  * state so we know what addresses have been programmed into the NIC at
  * any given time.
  */
 static void
 ti_setmulti(struct ti_softc *sc)
+{
 	struct ethercom		*ec = &sc->ethercom;
 	struct ifnet		*ifp = &ec->ec_if;
 	struct ti_cmd_desc	cmd;
 	struct ti_mc_entry	*mc;
 	uint32_t		intrs;
 	struct ether_multi	*enm;
 	struct ether_multistep	step;
 	/* Disable interrupts. */
 	intrs = CSR_READ_4(sc, TI_MB_HOSTINTR);
 	CSR_WRITE_4(sc, TI_MB_HOSTINTR, 1);
 	/* First, zot all the existing filters. */
 	while ((mc = SIMPLEQ_FIRST(&sc->ti_mc_listhead)) != NULL) {
 		ti_del_mcast(sc, &mc->mc_addr);
 		SIMPLEQ_REMOVE_HEAD(&sc->ti_mc_listhead, mc_entries);
 		free(mc, M_DEVBUF);
+	}
 	/*
 	 * Remember all multicast addresses so that we can delete them
 	 * later.  Punt if there is a range of addresses or memory shortage.
 	 */
 	ETHER_LOCK(ec);
 	ETHER_FIRST_MULTI(step, ec, enm);
 	while (enm != NULL) {
 		if (memcmp(enm->enm_addrlo, enm->enm_addrhi,
 		    ETHER_ADDR_LEN) != 0) {
 			ETHER_UNLOCK(ec);
 			goto allmulti;
+		}
 		if ((mc = malloc(sizeof(struct ti_mc_entry), M_DEVBUF,
 		    M_NOWAIT)) == NULL) {
 			ETHER_UNLOCK(ec);
 			goto allmulti;
+		}
 		memcpy(&mc->mc_addr, enm->enm_addrlo, ETHER_ADDR_LEN);
 		SIMPLEQ_INSERT_HEAD(&sc->ti_mc_listhead, mc, mc_entries);
 		ETHER_NEXT_MULTI(step, enm);
+	}
 	ETHER_UNLOCK(ec);
 	/* Accept only programmed multicast addresses */
 	ifp->if_flags &= ~IFF_ALLMULTI;
 	TI_DO_CMD(TI_CMD_SET_ALLMULTI, TI_CMD_CODE_ALLMULTI_DIS, 0);
 	/* Now program new ones. */
 	SIMPLEQ_FOREACH(mc, &sc->ti_mc_listhead, mc_entries)
 		ti_add_mcast(sc, &mc->mc_addr);
 	/* Re-enable interrupts. */
 	CSR_WRITE_4(sc, TI_MB_HOSTINTR, intrs);
 	return;
 allmulti:
 	/* No need to keep individual multicast addresses */
 	while ((mc = SIMPLEQ_FIRST(&sc->ti_mc_listhead)) != NULL) {
 		SIMPLEQ_REMOVE_HEAD(&sc->ti_mc_listhead, mc_entries);
 		free(mc, M_DEVBUF);
+	}
 	/* Accept all multicast addresses */
 	ifp->if_flags |= IFF_ALLMULTI;
 	TI_DO_CMD(TI_CMD_SET_ALLMULTI, TI_CMD_CODE_ALLMULTI_ENB, 0);
 	/* Re-enable interrupts. */
 	CSR_WRITE_4(sc, TI_MB_HOSTINTR, intrs);
+}
 /*
  * Check to see if the BIOS has configured us for a 64 bit slot when
  * we aren't actually in one. If we detect this condition, we can work
  * around it on the Tigon 2 by setting a bit in the PCI state register,
  * but for the Tigon 1 we must give up and abort the interface attach.
  */
 static int
 ti_64bitslot_war(struct ti_softc *sc)
+{
 	if (!(CSR_READ_4(sc, TI_PCI_STATE) & TI_PCISTATE_32BIT_BUS)) {
 		CSR_WRITE_4(sc, 0x600, 0);
 		CSR_WRITE_4(sc, 0x604, 0);
 		CSR_WRITE_4(sc, 0x600, 0x5555AAAA);
 		if (CSR_READ_4(sc, 0x604) == 0x5555AAAA) {
 			if (sc->ti_hwrev == TI_HWREV_TIGON)
 				return (EINVAL);
 			else {
 				TI_SETBIT(sc, TI_PCI_STATE,
 				    TI_PCISTATE_32BIT_BUS);
 				return (0);
+			}
+		}
+	}
 	return (0);
+}
 /*
  * Do endian, PCI and DMA initialization. Also check the on-board ROM
  * self-test results.
  */
 static int
 ti_chipinit(struct ti_softc *sc)
+{
 	uint32_t	cacheline;
 	uint32_t	pci_writemax = 0;
 	uint32_t	rev;
 	/* Initialize link to down state. */
 	sc->ti_linkstat = TI_EV_CODE_LINK_DOWN;
 	/* Set endianness before we access any non-PCI registers. */
 #if BYTE_ORDER == BIG_ENDIAN
 	CSR_WRITE_4(sc, TI_MISC_HOST_CTL,
 	    TI_MHC_BIGENDIAN_INIT | (TI_MHC_BIGENDIAN_INIT << 24));
 #else
 	CSR_WRITE_4(sc, TI_MISC_HOST_CTL,
 	    TI_MHC_LITTLEENDIAN_INIT | (TI_MHC_LITTLEENDIAN_INIT << 24));
 #endif
 	/* Check the ROM failed bit to see if self-tests passed. */
 	if (CSR_READ_4(sc, TI_CPU_STATE) & TI_CPUSTATE_ROMFAIL) {
 		printf("%s: board self-diagnostics failed!\n",
 		       device_xname(sc->sc_dev));
 		return (ENODEV);
+	}
 	/* Halt the CPU. */
 	TI_SETBIT(sc, TI_CPU_STATE, TI_CPUSTATE_HALT);
 	/* Figure out the hardware revision. */
 	rev = CSR_READ_4(sc, TI_MISC_HOST_CTL) & TI_MHC_CHIP_REV_MASK;
 	switch (rev) {
 	case TI_REV_TIGON_I:
 		sc->ti_hwrev = TI_HWREV_TIGON;
 		break;
 	case TI_REV_TIGON_II:
 		sc->ti_hwrev = TI_HWREV_TIGON_II;
 		break;
 	default:
 		printf("%s: unsupported chip revision 0x%x\n",
 		    device_xname(sc->sc_dev), rev);
 		return (ENODEV);
+	}
 	/* Do special setup for Tigon 2. */
 	if (sc->ti_hwrev == TI_HWREV_TIGON_II) {
 		TI_SETBIT(sc, TI_CPU_CTL_B, TI_CPUSTATE_HALT);
 		TI_SETBIT(sc, TI_MISC_LOCAL_CTL, TI_MLC_SRAM_BANK_256K);
 		TI_SETBIT(sc, TI_MISC_CONF, TI_MCR_SRAM_SYNCHRONOUS);
+	}
 	/* Set up the PCI state register. */
 	CSR_WRITE_4(sc, TI_PCI_STATE, TI_PCI_READ_CMD | TI_PCI_WRITE_CMD);
 	if (sc->ti_hwrev == TI_HWREV_TIGON_II) {
 		TI_SETBIT(sc, TI_PCI_STATE, TI_PCISTATE_USE_MEM_RD_MULT);
+	}
 	/* Clear the read/write max DMA parameters. */
 	TI_CLRBIT(sc, TI_PCI_STATE,
 	    (TI_PCISTATE_WRITE_MAXDMA | TI_PCISTATE_READ_MAXDMA));
 	/* Get cache line size. */
 	cacheline = PCI_CACHELINE(CSR_READ_4(sc, PCI_BHLC_REG));
 	/*
 	 * If the system has set enabled the PCI memory write
 	 * and invalidate command in the command register, set
 	 * the write max parameter accordingly. This is necessary
 	 * to use MWI with the Tigon 2.
 	 */
 	if (CSR_READ_4(sc, PCI_COMMAND_STATUS_REG)
 	    & PCI_COMMAND_INVALIDATE_ENABLE) {
 		switch (cacheline) {
 		case 1:
 		case 4:
 		case 8:
 		case 16:
 		case 32:
 		case 64:
 			break;
 		default:
 		/* Disable PCI memory write and invalidate. */
 			if (bootverbose)
 				printf("%s: cache line size %d not "
 				    "supported; disabling PCI MWI\n",
 				    device_xname(sc->sc_dev), cacheline);
 			CSR_WRITE_4(sc, PCI_COMMAND_STATUS_REG,
 				    CSR_READ_4(sc, PCI_COMMAND_STATUS_REG)
 				    & ~PCI_COMMAND_INVALIDATE_ENABLE);
 			break;
+		}
+	}
 #ifdef __brokenalpha__
 	/*
 	 * From the Alteon sample driver:
 	 * Must insure that we do not cross an 8K (bytes) boundary
 	 * for DMA reads.  Our highest limit is 1K bytes.  This is a
 	 * restriction on some ALPHA platforms with early revision
 	 * 21174 PCI chipsets, such as the AlphaPC 164lx
 	 */
 	TI_SETBIT(sc, TI_PCI_STATE, pci_writemax | TI_PCI_READMAX_1024);
 #else
 	TI_SETBIT(sc, TI_PCI_STATE, pci_writemax);
 #endif
 	/* This sets the min dma param all the way up (0xff). */
 	TI_SETBIT(sc, TI_PCI_STATE, TI_PCISTATE_MINDMA);
 	/* Configure DMA variables. */
 #if BYTE_ORDER == BIG_ENDIAN
 	CSR_WRITE_4(sc, TI_GCR_OPMODE, TI_OPMODE_BYTESWAP_BD |
 	    TI_OPMODE_BYTESWAP_DATA | TI_OPMODE_WORDSWAP_BD |
 	    TI_OPMODE_WARN_ENB | TI_OPMODE_FATAL_ENB |
 	    TI_OPMODE_DONT_FRAG_JUMBO);
 #else
 	CSR_WRITE_4(sc, TI_GCR_OPMODE, TI_OPMODE_BYTESWAP_DATA |
 	    TI_OPMODE_WORDSWAP_BD | TI_OPMODE_DONT_FRAG_JUMBO |
 	    TI_OPMODE_WARN_ENB | TI_OPMODE_FATAL_ENB);
 #endif
 	/*
 	 * Only allow 1 DMA channel to be active at a time.
 	 * I don't think this is a good idea, but without it
 	 * the firmware racks up lots of nicDmaReadRingFull
 	 * errors.
 	 * Incompatible with hardware assisted checksums.
 	 */
 	if ((sc->ethercom.ec_if.if_capenable &
 	    (IFCAP_CSUM_TCPv4_Tx | IFCAP_CSUM_TCPv4_Rx |
 	     IFCAP_CSUM_UDPv4_Tx | IFCAP_CSUM_UDPv4_Rx |
 	     IFCAP_CSUM_IPv4_Tx | IFCAP_CSUM_IPv4_Rx)) == 0)
 		TI_SETBIT(sc, TI_GCR_OPMODE, TI_OPMODE_1_DMA_ACTIVE);
 	/* Recommended settings from Tigon manual. */
 	CSR_WRITE_4(sc, TI_GCR_DMA_WRITECFG, TI_DMA_STATE_THRESH_8W);
 	CSR_WRITE_4(sc, TI_GCR_DMA_READCFG, TI_DMA_STATE_THRESH_8W);
 	if (ti_64bitslot_war(sc)) {
 		printf("%s: bios thinks we're in a 64 bit slot, "
 		    "but we aren't", device_xname(sc->sc_dev));
 		return (EINVAL);
+	}
 	return (0);
+}
 /*
  * Initialize the general information block and firmware, and
  * start the CPU(s) running.
  */
 static int
 ti_gibinit(struct ti_softc *sc)
+{
 	struct ti_rcb		*rcb;
 	int			i;
 	struct ifnet		*ifp;
 	ifp = &sc->ethercom.ec_if;
 	/* Disable interrupts for now. */
 	CSR_WRITE_4(sc, TI_MB_HOSTINTR, 1);
 	/* Tell the chip where to find the general information block. */
 	CSR_WRITE_4(sc, TI_GCR_GENINFO_HI, 0);
 	CSR_WRITE_4(sc, TI_GCR_GENINFO_LO, TI_CDGIBADDR(sc));
 	/* Load the firmware into SRAM. */
 	ti_loadfw(sc);
 	/* Set up the contents of the general info and ring control blocks. */
 	/* Set up the event ring and producer pointer. */
 	rcb = &sc->ti_rdata->ti_info.ti_ev_rcb;
 	TI_HOSTADDR(rcb->ti_hostaddr, TI_CDEVENTADDR(sc, 0));
 	rcb->ti_flags = 0;
 	TI_HOSTADDR(sc->ti_rdata->ti_info.ti_ev_prodidx_ptr,
 	    TI_CDEVPRODADDR(sc));
 	sc->ti_ev_prodidx.ti_idx = 0;
 	CSR_WRITE_4(sc, TI_GCR_EVENTCONS_IDX, 0);
 	sc->ti_ev_saved_considx = 0;
 	/* Set up the command ring and producer mailbox. */
 	rcb = &sc->ti_rdata->ti_info.ti_cmd_rcb;
 	TI_HOSTADDR(rcb->ti_hostaddr, TI_GCR_NIC_ADDR(TI_GCR_CMDRING));
 	rcb->ti_flags = 0;
 	rcb->ti_max_len = 0;
 	for (i = 0; i < TI_CMD_RING_CNT; i++) {
 		CSR_WRITE_4(sc, TI_GCR_CMDRING + (i * 4), 0);
+	}
 	CSR_WRITE_4(sc, TI_GCR_CMDCONS_IDX, 0);
 	CSR_WRITE_4(sc, TI_MB_CMDPROD_IDX, 0);
 	sc->ti_cmd_saved_prodidx = 0;
 	/*
 	 * Assign the address of the stats refresh buffer.
 	 * We re-use the current stats buffer for this to
 	 * conserve memory.
 	 */
 	TI_HOSTADDR(sc->ti_rdata->ti_info.ti_refresh_stats_ptr,
 	    TI_CDSTATSADDR(sc));
 	/* Set up the standard receive ring. */
 	rcb = &sc->ti_rdata->ti_info.ti_std_rx_rcb;
 	TI_HOSTADDR(rcb->ti_hostaddr, TI_CDRXSTDADDR(sc, 0));
 	rcb->ti_max_len = ETHER_MAX_LEN;
 	rcb->ti_flags = 0;
 	if (ifp->if_capenable & IFCAP_CSUM_IPv4_Rx)
 		rcb->ti_flags |= TI_RCB_FLAG_IP_CKSUM;
 	if (ifp->if_capenable & (IFCAP_CSUM_TCPv4_Rx | IFCAP_CSUM_UDPv4_Rx))
 		rcb->ti_flags |= TI_RCB_FLAG_TCP_UDP_CKSUM;
 	if (VLAN_ATTACHED(&sc->ethercom))
 		rcb->ti_flags |= TI_RCB_FLAG_VLAN_ASSIST;
 	/* Set up the jumbo receive ring. */
 	rcb = &sc->ti_rdata->ti_info.ti_jumbo_rx_rcb;
 	TI_HOSTADDR(rcb->ti_hostaddr, TI_CDRXJUMBOADDR(sc, 0));
 	rcb->ti_max_len = ETHER_MAX_LEN_JUMBO;
 	rcb->ti_flags = 0;
 	if (ifp->if_capenable & IFCAP_CSUM_IPv4_Rx)
 		rcb->ti_flags |= TI_RCB_FLAG_IP_CKSUM;
 	if (ifp->if_capenable & (IFCAP_CSUM_TCPv4_Rx | IFCAP_CSUM_UDPv4_Rx))
 		rcb->ti_flags |= TI_RCB_FLAG_TCP_UDP_CKSUM;
 	if (VLAN_ATTACHED(&sc->ethercom))
 		rcb->ti_flags |= TI_RCB_FLAG_VLAN_ASSIST;
 	/*
 	 * Set up the mini ring. Only activated on the
 	 * Tigon 2 but the slot in the config block is
 	 * still there on the Tigon 1.
 	 */
 	rcb = &sc->ti_rdata->ti_info.ti_mini_rx_rcb;
 	TI_HOSTADDR(rcb->ti_hostaddr, TI_CDRXMINIADDR(sc, 0));
 	rcb->ti_max_len = MHLEN - ETHER_ALIGN;
 	if (sc->ti_hwrev == TI_HWREV_TIGON)
 		rcb->ti_flags = TI_RCB_FLAG_RING_DISABLED;
 	else
 		rcb->ti_flags = 0;
 	if (ifp->if_capenable & IFCAP_CSUM_IPv4_Rx)
 		rcb->ti_flags |= TI_RCB_FLAG_IP_CKSUM;
 	if (ifp->if_capenable & (IFCAP_CSUM_TCPv4_Rx | IFCAP_CSUM_UDPv4_Rx))
 		rcb->ti_flags |= TI_RCB_FLAG_TCP_UDP_CKSUM;
 	if (VLAN_ATTACHED(&sc->ethercom))
 		rcb->ti_flags |= TI_RCB_FLAG_VLAN_ASSIST;
 	/*
 	 * Set up the receive return ring.
 	 */
 	rcb = &sc->ti_rdata->ti_info.ti_return_rcb;
 	TI_HOSTADDR(rcb->ti_hostaddr, TI_CDRXRTNADDR(sc, 0));
 	rcb->ti_flags = 0;
 	rcb->ti_max_len = TI_RETURN_RING_CNT;
 	TI_HOSTADDR(sc->ti_rdata->ti_info.ti_return_prodidx_ptr,
 	    TI_CDRTNPRODADDR(sc));
 	/*
 	 * Set up the tx ring. Note: for the Tigon 2, we have the option
 	 * of putting the transmit ring in the host's address space and
 	 * letting the chip DMA it instead of leaving the ring in the NIC's
 	 * memory and accessing it through the shared memory region. We
 	 * do this for the Tigon 2, but it doesn't work on the Tigon 1,
 	 * so we have to revert to the shared memory scheme if we detect
 	 * a Tigon 1 chip.
 	 */
 	CSR_WRITE_4(sc, TI_WINBASE, TI_TX_RING_BASE);
 	if (sc->ti_hwrev == TI_HWREV_TIGON) {
 		sc->ti_tx_ring_nic =
 		    (struct ti_tx_desc *)(sc->ti_vhandle + TI_WINDOW);
+	}
 	memset((char *)sc->ti_rdata->ti_tx_ring, 0,
 	    TI_TX_RING_CNT * sizeof(struct ti_tx_desc));
 	rcb = &sc->ti_rdata->ti_info.ti_tx_rcb;
 	if (sc->ti_hwrev == TI_HWREV_TIGON)
 		rcb->ti_flags = 0;
 	else
 		rcb->ti_flags = TI_RCB_FLAG_HOST_RING;
 	if (ifp->if_capenable & IFCAP_CSUM_IPv4_Tx)
 		rcb->ti_flags |= TI_RCB_FLAG_IP_CKSUM;
 	/*
 	 * When we get the packet, there is a pseudo-header seed already
 	 * in the th_sum or uh_sum field.  Make sure the firmware doesn't
 	 * compute the pseudo-header checksum again!
 	 */
 	if (ifp->if_capenable & (IFCAP_CSUM_TCPv4_Tx | IFCAP_CSUM_UDPv4_Tx))
 		rcb->ti_flags |= TI_RCB_FLAG_TCP_UDP_CKSUM |
 		    TI_RCB_FLAG_NO_PHDR_CKSUM;
 	if (VLAN_ATTACHED(&sc->ethercom))
 		rcb->ti_flags |= TI_RCB_FLAG_VLAN_ASSIST;
 	rcb->ti_max_len = TI_TX_RING_CNT;
 	if (sc->ti_hwrev == TI_HWREV_TIGON)
 		TI_HOSTADDR(rcb->ti_hostaddr, TI_TX_RING_BASE);
 	else
 		TI_HOSTADDR(rcb->ti_hostaddr, TI_CDTXADDR(sc, 0));
 	TI_HOSTADDR(sc->ti_rdata->ti_info.ti_tx_considx_ptr,
 	    TI_CDTXCONSADDR(sc));
 	/*
 	 * We're done frobbing the General Information Block.  Sync
 	 * it.  Note we take care of the first stats sync here, as
 	 * well.
 	 */
 	TI_CDGIBSYNC(sc, BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
 	/* Set up tuneables */
 	if (ifp->if_mtu > (ETHERMTU + ETHER_HDR_LEN + ETHER_CRC_LEN) ||
 	    (sc->ethercom.ec_capenable & ETHERCAP_VLAN_MTU))
 		CSR_WRITE_4(sc, TI_GCR_RX_COAL_TICKS,
 		    (sc->ti_rx_coal_ticks / 10));
 	else
 		CSR_WRITE_4(sc, TI_GCR_RX_COAL_TICKS, sc->ti_rx_coal_ticks);
 	CSR_WRITE_4(sc, TI_GCR_TX_COAL_TICKS, sc->ti_tx_coal_ticks);
 	CSR_WRITE_4(sc, TI_GCR_STAT_TICKS, sc->ti_stat_ticks);
 	CSR_WRITE_4(sc, TI_GCR_RX_MAX_COAL_BD, sc->ti_rx_max_coal_bds);
 	CSR_WRITE_4(sc, TI_GCR_TX_MAX_COAL_BD, sc->ti_tx_max_coal_bds);
 	CSR_WRITE_4(sc, TI_GCR_TX_BUFFER_RATIO, sc->ti_tx_buf_ratio);
 	/* Turn interrupts on. */
 	CSR_WRITE_4(sc, TI_GCR_MASK_INTRS, 0);
 	CSR_WRITE_4(sc, TI_MB_HOSTINTR, 0);
 	/* Start CPU. */
 	TI_CLRBIT(sc, TI_CPU_STATE, (TI_CPUSTATE_HALT | TI_CPUSTATE_STEP));
 	return (0);
+}
 /*
  * look for id in the device list, returning the first match
  */
 static const struct ti_type *
 ti_type_match(struct pci_attach_args *pa)
+{
 	const struct ti_type	      *t;
 	t = ti_devs;
 	while (t->ti_name != NULL) {
 		if ((PCI_VENDOR(pa->pa_id) == t->ti_vid) &&
 		    (PCI_PRODUCT(pa->pa_id) == t->ti_did)) {
 			return (t);
+		}
 		t++;
+	}
 	return (NULL);
+}
 /*
  * Probe for a Tigon chip. Check the PCI vendor and device IDs
  * against our list and return its name if we find a match.
  */
 static int
 ti_probe(device_t parent, cfdata_t match, void *aux)
+{
 	struct pci_attach_args	*pa = aux;
 	const struct ti_type	*t;
 	t = ti_type_match(pa);
 	return ((t == NULL) ? 0 : 1);
+}
 static void
 ti_attach(device_t parent, device_t self, void *aux)
+{
 	uint32_t		command;
 	struct ifnet		*ifp;
 	struct ti_softc		*sc;
 	uint8_t eaddr[ETHER_ADDR_LEN];
 	struct pci_attach_args *pa = aux;
 	pci_chipset_tag_t pc = pa->pa_pc;
 	pci_intr_handle_t ih;
 	const char *intrstr = NULL;
 	bus_dma_segment_t dmaseg;
 	int error, dmanseg, nolinear;
 	const struct ti_type		*t;
 	char intrbuf[PCI_INTRSTR_LEN];
 	t = ti_type_match(pa);
 	if (t == NULL) {
 		aprint_error("ti_attach: were did the card go ?\n");
 		return;
+	}
 	aprint_normal(": %s (rev. 0x%02x)\n", t->ti_name,
 	    PCI_REVISION(pa->pa_class));
 	sc = device_private(self);
 	sc->sc_dev = self;
 	/*
 	 * Map control/status registers.
 	 */
 	nolinear = 0;
 	if (pci_mapreg_map(pa, 0x10,
 	    PCI_MAPREG_TYPE_MEM | PCI_MAPREG_MEM_TYPE_32BIT,
 	    BUS_SPACE_MAP_LINEAR , &sc->ti_btag, &sc->ti_bhandle,
 	    NULL, NULL)) {
 		nolinear = 1;
 		if (pci_mapreg_map(pa, 0x10,
 		    PCI_MAPREG_TYPE_MEM | PCI_MAPREG_MEM_TYPE_32BIT,
 , &sc->ti_btag, &sc->ti_bhandle, NULL, NULL)) {
 			aprint_error_dev(self, "can't map memory space\n");
 			return;
+		}
+	}
 	if (nolinear == 0)
 		sc->ti_vhandle = bus_space_vaddr(sc->ti_btag, sc->ti_bhandle);
 	else
 		sc->ti_vhandle = NULL;
 	command = pci_conf_read(pc, pa->pa_tag, PCI_COMMAND_STATUS_REG);
 	command |= PCI_COMMAND_MASTER_ENABLE;
 	pci_conf_write(pc, pa->pa_tag, PCI_COMMAND_STATUS_REG, command);
 	/* Allocate interrupt */
 	if (pci_intr_map(pa, &ih)) {
 		aprint_error_dev(sc->sc_dev, "couldn't map interrupt\n");
 		return;
+	}
 	intrstr = pci_intr_string(pc, ih, intrbuf, sizeof(intrbuf));
 	sc->sc_ih = pci_intr_establish_xname(pc, ih, IPL_NET, ti_intr, sc,
 	    device_xname(self));
 	if (sc->sc_ih == NULL) {
 		aprint_error_dev(sc->sc_dev, "couldn't establish interrupt");
 		if (intrstr != NULL)
 			aprint_error(" at %s", intrstr);
 		aprint_error("\n");
 		return;
+	}
 	aprint_normal_dev(sc->sc_dev, "interrupting at %s\n", intrstr);
 	if (ti_chipinit(sc)) {
 		aprint_error_dev(self, "chip initialization failed\n");
 		goto fail2;
+	}
 	/*
 	 * Deal with some chip diffrences.
 	 */
 	switch (sc->ti_hwrev) {
 	case TI_HWREV_TIGON:
 		sc->sc_tx_encap = ti_encap_tigon1;
 		sc->sc_tx_eof = ti_txeof_tigon1;
 		if (nolinear == 1)
 			aprint_error_dev(self,
 			    "memory space not mapped linear\n");
 		break;
 	case TI_HWREV_TIGON_II:
 		sc->sc_tx_encap = ti_encap_tigon2;
 		sc->sc_tx_eof = ti_txeof_tigon2;
 		break;
 	default:
 		aprint_error_dev(self, "Unknown chip version: %d\n",
 		    sc->ti_hwrev);
 		goto fail2;
+	}
 	/* Zero out the NIC's on-board SRAM. */
 	ti_mem(sc, 0x2000, 0x100000 - 0x2000,  NULL);
 	/* Init again -- zeroing memory may have clobbered some registers. */
 	if (ti_chipinit(sc)) {
 		aprint_error_dev(self, "chip initialization failed\n");
 		goto fail2;
+	}
 	/*
 	 * Get station address from the EEPROM. Note: the manual states
 	 * that the MAC address is at offset 0x8c, however the data is
 	 * stored as two longwords (since that's how it's loaded into
 	 * the NIC). This means the MAC address is actually preceded
 	 * by two zero bytes. We need to skip over those.
 	 */
 	if (ti_read_eeprom(sc, (void *)&eaddr,
 				TI_EE_MAC_OFFSET + 2, ETHER_ADDR_LEN)) {
 		aprint_error_dev(self, "failed to read station address\n");
 		goto fail2;
+	}
 	/*
 	 * A Tigon chip was detected. Inform the world.
 	 */
 	aprint_normal_dev(self, "Ethernet address %s\n", ether_sprintf(eaddr));
 	if (pci_dma64_available(pa))
 		sc->sc_dmat = pa->pa_dmat64;
 	else
 		sc->sc_dmat = pa->pa_dmat;
 	/* Allocate the general information block and ring buffers. */
 	if ((error = bus_dmamem_alloc(sc->sc_dmat,
 	    sizeof(struct ti_ring_data), PAGE_SIZE, 0, &dmaseg, 1, &dmanseg,
 	    BUS_DMA_NOWAIT)) != 0) {
 		aprint_error_dev(self,
 		    "can't allocate ring buffer, error = %d\n", error);
 		goto fail2;
+	}
 	if ((error = bus_dmamem_map(sc->sc_dmat, &dmaseg, dmanseg,
 	    sizeof(struct ti_ring_data), (void **)&sc->ti_rdata,
 	    BUS_DMA_NOWAIT | BUS_DMA_COHERENT)) != 0) {
 		aprint_error_dev(self,
 		    "can't map ring buffer, error = %d\n", error);
 		goto fail2;
+	}
 	if ((error = bus_dmamap_create(sc->sc_dmat,
 	    sizeof(struct ti_ring_data), 1,
 	    sizeof(struct ti_ring_data), 0, BUS_DMA_NOWAIT,
 	    &sc->info_dmamap)) != 0) {
 		aprint_error_dev(self,

 @@ -1,2029 +1,2029 @@
-/*	$NetBSD: qat.c,v 1.4 2020/02/01 13:48:18 riastradh Exp $	*/
+/*	$NetBSD: qat.c,v 1.5 2020/03/05 15:33:13 msaitoh Exp $	*/
 /*
  * Copyright (c) 2019 Internet Initiative Japan, Inc.
  * All rights reserved.
+ *
  * Redistribution and use in source and binary forms, with or without
  * modification, are permitted provided that the following conditions
  * are met:
  * 1. Redistributions of source code must retain the above copyright
  *    notice, this list of conditions and the following disclaimer.
  * 2. Redistributions in binary form must reproduce the above copyright
  *    notice, this list of conditions and the following disclaimer in the
  *    documentation and/or other materials provided with the distribution.
+ *
  * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
  * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
  * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
  * PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
  * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
  * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
  * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
  * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
  * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
  * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
  * POSSIBILITY OF SUCH DAMAGE.
  */
 /*
  *   Copyright(c) 2007-2019 Intel Corporation. All rights reserved.
+ *
  *   Redistribution and use in source and binary forms, with or without
  *   modification, are permitted provided that the following conditions
  *   are met:
+ *
  *     * Redistributions of source code must retain the above copyright
  *       notice, this list of conditions and the following disclaimer.
  *     * Redistributions in binary form must reproduce the above copyright
  *       notice, this list of conditions and the following disclaimer in
  *       the documentation and/or other materials provided with the
  *       distribution.
  *     * Neither the name of Intel Corporation nor the names of its
  *       contributors may be used to endorse or promote products derived
  *       from this software without specific prior written permission.
+ *
  *   THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  *   "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  *   LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  *   A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  *   OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  *   SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  *   LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  *   DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  *   THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  *   (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  *   OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  */
 #include <sys/cdefs.h>
-__KERNEL_RCSID(0, "$NetBSD: qat.c,v 1.4 2020/02/01 13:48:18 riastradh Exp $");
+__KERNEL_RCSID(0, "$NetBSD: qat.c,v 1.5 2020/03/05 15:33:13 msaitoh Exp $");
 #include <sys/param.h>
 #include <sys/systm.h>
 #include <sys/kernel.h>
 #include <sys/device.h>
 #include <sys/module.h>
 #include <sys/kmem.h>
 #include <sys/mutex.h>
 #include <sys/bitops.h>
 #include <sys/atomic.h>
 #include <sys/mbuf.h>
 #include <sys/cprng.h>
 #include <sys/cpu.h>
 #include <sys/interrupt.h>
 #include <sys/md5.h>
 #include <sys/sha1.h>
 #include <sys/sha2.h>
 #include <opencrypto/cryptodev.h>
 #include <opencrypto/cryptosoft.h>
 #include <opencrypto/xform.h>
 /* XXX same as sys/arch/x86/x86/via_padlock.c */
 #include <opencrypto/cryptosoft_xform.c>
 #include <dev/pci/pcireg.h>
 #include <dev/pci/pcivar.h>
 #include <dev/pci/pcidevs.h>
 #include "qatreg.h"
 #include "qatvar.h"
 #include "qat_aevar.h"
 extern struct qat_hw qat_hw_c2xxx;
 extern struct qat_hw qat_hw_c3xxx;
 extern struct qat_hw qat_hw_c62x;
 extern struct qat_hw qat_hw_d15xx;
 static const struct qat_product {
 	pci_vendor_id_t qatp_vendor;
 	pci_product_id_t qatp_product;
 	const char *qatp_name;
 	enum qat_chip_type qatp_chip;
 	const struct qat_hw *qatp_hw;
 } qat_products[] = {
 	{ PCI_VENDOR_INTEL,	PCI_PRODUCT_INTEL_C2000_IQIA_PHYS,
 	  "Intel C2000 QuickAssist Physical Function",
 	  QAT_CHIP_C2XXX, &qat_hw_c2xxx },
 	{ PCI_VENDOR_INTEL,	PCI_PRODUCT_INTEL_C3K_QAT,
 	  "Intel C3000 QuickAssist Physical Function",
 	  QAT_CHIP_C3XXX, &qat_hw_c3xxx },
 #ifdef notyet
 	{ PCI_VENDOR_INTEL,	PCI_PRODUCT_INTEL_C3K_QAT_VF,
 	  "Intel C3000 QuickAssist Virtual Function",
 	  QAT_CHIP_C3XXX_IOV, &qat_hw_c3xxxvf },
 #endif
 	{ PCI_VENDOR_INTEL,	PCI_PRODUCT_INTEL_C620_QAT,
 	  "Intel C620/Xeon D-2100 QuickAssist Physical Function",
 	  QAT_CHIP_C62X, &qat_hw_c62x },
 #ifdef notyet
 	{ PCI_VENDOR_INTEL,	PCI_PRODUCT_INTEL_C620_QAT_VF,
 	  "Intel C620/Xeon D-2100 QuickAssist Virtual Function",
 	  QAT_CHIP_C62X_IOV, &qat_hw_c62xvf },
 #endif
 	{ PCI_VENDOR_INTEL,	PCI_PRODUCT_INTEL_XEOND_QAT,
 	  "Intel Xeon D-1500 QuickAssist Physical Function",
 	  QAT_CHIP_D15XX, &qat_hw_d15xx },
 #ifdef notyet
 	{ PCI_VENDOR_INTEL,	PCI_PRODUCT_INTEL_XEOND_QAT_VF,
 	  "Intel Xeon D-1500 QuickAssist Virtual Function",
 	  QAT_CHIP_D15XX_IOV, &qat_hw_d15xxvf },
 #endif
 	{ 0, 0, NULL, 0, NULL },
 };
 /* md5 16 bytes - Initialiser state can be found in RFC 1321*/
 static const uint8_t md5_initial_state[QAT_HASH_MD5_STATE_SIZE] = {
 x01, 0x23, 0x45, 0x67,
 x89, 0xab, 0xcd, 0xef,
 xfe, 0xdc, 0xba, 0x98,
 x76, 0x54, 0x32, 0x10,
 };
 /* SHA1 - 20 bytes - Initialiser state can be found in FIPS stds 180-2 */
 static const uint8_t sha1_initial_state[QAT_HASH_SHA1_STATE_SIZE] = {
 x67, 0x45, 0x23, 0x01,
 xef, 0xcd, 0xab, 0x89,
 x98, 0xba, 0xdc, 0xfe,
 x10, 0x32, 0x54, 0x76,
 xc3, 0xd2, 0xe1, 0xf0
 };
 /* SHA 256 - 32 bytes - Initialiser state can be found in FIPS stds 180-2 */
 static const uint8_t sha256_initial_state[QAT_HASH_SHA256_STATE_SIZE] = {
 x6a, 0x09, 0xe6, 0x67,
 xbb, 0x67, 0xae, 0x85,
 x3c, 0x6e, 0xf3, 0x72,
 xa5, 0x4f, 0xf5, 0x3a,
 x51, 0x0e, 0x52, 0x7f,
 x9b, 0x05, 0x68, 0x8c,
 x1f, 0x83, 0xd9, 0xab,
 x5b, 0xe0, 0xcd, 0x19
 };
 /* SHA 384 - 64 bytes - Initialiser state can be found in FIPS stds 180-2 */
 static const uint8_t sha384_initial_state[QAT_HASH_SHA384_STATE_SIZE] = {
 xcb, 0xbb, 0x9d, 0x5d, 0xc1, 0x05, 0x9e, 0xd8,
 x62, 0x9a, 0x29, 0x2a, 0x36, 0x7c, 0xd5, 0x07,
 x91, 0x59, 0x01, 0x5a, 0x30, 0x70, 0xdd, 0x17,
 x15, 0x2f, 0xec, 0xd8, 0xf7, 0x0e, 0x59, 0x39,
 x67, 0x33, 0x26, 0x67, 0xff, 0xc0, 0x0b, 0x31,
 x8e, 0xb4, 0x4a, 0x87, 0x68, 0x58, 0x15, 0x11,
 xdb, 0x0c, 0x2e, 0x0d, 0x64, 0xf9, 0x8f, 0xa7,
 x47, 0xb5, 0x48, 0x1d, 0xbe, 0xfa, 0x4f, 0xa4
 };
 /* SHA 512 - 64 bytes - Initialiser state can be found in FIPS stds 180-2 */
 static const uint8_t sha512_initial_state[QAT_HASH_SHA512_STATE_SIZE] = {
 x6a, 0x09, 0xe6, 0x67, 0xf3, 0xbc, 0xc9, 0x08,
 xbb, 0x67, 0xae, 0x85, 0x84, 0xca, 0xa7, 0x3b,
 x3c, 0x6e, 0xf3, 0x72, 0xfe, 0x94, 0xf8, 0x2b,
 xa5, 0x4f, 0xf5, 0x3a, 0x5f, 0x1d, 0x36, 0xf1,
 x51, 0x0e, 0x52, 0x7f, 0xad, 0xe6, 0x82, 0xd1,
 x9b, 0x05, 0x68, 0x8c, 0x2b, 0x3e, 0x6c, 0x1f,
 x1f, 0x83, 0xd9, 0xab, 0xfb, 0x41, 0xbd, 0x6b,
 x5b, 0xe0, 0xcd, 0x19, 0x13, 0x7e, 0x21, 0x79
 };
 /* Hash Algorithm specific structure */
 static const struct qat_sym_hash_alg_info md5_info = {
 	QAT_HASH_MD5_DIGEST_SIZE,
 	QAT_HASH_MD5_BLOCK_SIZE,
 	md5_initial_state,
 	QAT_HASH_MD5_STATE_SIZE,
 	&swcr_auth_hash_hmac_md5_96,
 	offsetof(MD5_CTX, state),
 ,
 };
 static const struct qat_sym_hash_alg_info sha1_info = {
 	QAT_HASH_SHA1_DIGEST_SIZE,
 	QAT_HASH_SHA1_BLOCK_SIZE,
 	sha1_initial_state,
 	QAT_HASH_SHA1_STATE_SIZE,
 	&swcr_auth_hash_hmac_sha1_96,
 	offsetof(SHA1_CTX, state),
 ,
 };
 static const struct qat_sym_hash_alg_info sha256_info = {
 	QAT_HASH_SHA256_DIGEST_SIZE,
 	QAT_HASH_SHA256_BLOCK_SIZE,
 	sha256_initial_state,
 	QAT_HASH_SHA256_STATE_SIZE,
 	&swcr_auth_hash_hmac_sha2_256,
 	offsetof(SHA256_CTX, state),
 ,
 };
 static const struct qat_sym_hash_alg_info sha384_info = {
 	QAT_HASH_SHA384_DIGEST_SIZE,
 	QAT_HASH_SHA384_BLOCK_SIZE,
 	sha384_initial_state,
 	QAT_HASH_SHA384_STATE_SIZE,
 	&swcr_auth_hash_hmac_sha2_384,
 	offsetof(SHA384_CTX, state),
 ,
 };
 static const struct qat_sym_hash_alg_info sha512_info = {
 	QAT_HASH_SHA512_DIGEST_SIZE,
 	QAT_HASH_SHA512_BLOCK_SIZE,
 	sha512_initial_state,
 	QAT_HASH_SHA512_STATE_SIZE,
 	&swcr_auth_hash_hmac_sha2_512,
 	offsetof(SHA512_CTX, state),
 ,
 };
 static const struct qat_sym_hash_alg_info aes_gcm_info = {
 	QAT_HASH_AES_GCM_DIGEST_SIZE,
 	QAT_HASH_AES_GCM_BLOCK_SIZE,
 	NULL, 0,
 	NULL, 0, 0, /* XXX */
 };
 /* Hash QAT specific structures */
 static const struct qat_sym_hash_qat_info md5_config = {
 	HW_AUTH_ALGO_MD5,
 	QAT_HASH_MD5_BLOCK_SIZE,
 	HW_MD5_STATE1_SZ,
 	HW_MD5_STATE2_SZ
 };
 static const struct qat_sym_hash_qat_info sha1_config = {
 	HW_AUTH_ALGO_SHA1,
 	QAT_HASH_SHA1_BLOCK_SIZE,
 	HW_SHA1_STATE1_SZ,
 	HW_SHA1_STATE2_SZ
 };
 static const struct qat_sym_hash_qat_info sha256_config = {
 	HW_AUTH_ALGO_SHA256,
 	QAT_HASH_SHA256_BLOCK_SIZE,
 	HW_SHA256_STATE1_SZ,
 	HW_SHA256_STATE2_SZ
 };
 static const struct qat_sym_hash_qat_info sha384_config = {
 	HW_AUTH_ALGO_SHA384,
 	QAT_HASH_SHA384_BLOCK_SIZE,
 	HW_SHA384_STATE1_SZ,
 	HW_SHA384_STATE2_SZ
 };
 static const struct qat_sym_hash_qat_info sha512_config = {
 	HW_AUTH_ALGO_SHA512,
 	QAT_HASH_SHA512_BLOCK_SIZE,
 	HW_SHA512_STATE1_SZ,
 	HW_SHA512_STATE2_SZ
 };
 static const struct qat_sym_hash_qat_info aes_gcm_config = {
 	HW_AUTH_ALGO_GALOIS_128,
 ,
 	HW_GALOIS_128_STATE1_SZ,
 	HW_GALOIS_H_SZ +
 	HW_GALOIS_LEN_A_SZ +
 	HW_GALOIS_E_CTR0_SZ
 };
 static const struct qat_sym_hash_def qat_sym_hash_defs[] = {
 	[QAT_SYM_HASH_MD5] = { &md5_info, &md5_config },
 	[QAT_SYM_HASH_SHA1] = { &sha1_info, &sha1_config },
 	[QAT_SYM_HASH_SHA256] = { &sha256_info, &sha256_config },
 	[QAT_SYM_HASH_SHA384] = { &sha384_info, &sha384_config },
 	[QAT_SYM_HASH_SHA512] = { &sha512_info, &sha512_config },
 	[QAT_SYM_HASH_AES_GCM] = { &aes_gcm_info, &aes_gcm_config },
 };
 const struct qat_product *
 		qat_lookup(const struct pci_attach_args *);
 int		qat_match(struct device *, struct cfdata *, void *);
 void		qat_attach(struct device *, struct device *, void *);
 void		qat_init(struct device *);
 int		qat_start(struct device *);
 int		qat_detach(struct device *, int);
 int		qat_alloc_msix_intr(struct qat_softc *,
 		    struct pci_attach_args *);
 void *		qat_establish_msix_intr(struct qat_softc *, pci_intr_handle_t,
 			int (*)(void *), void *, const char *, int);
 int		qat_setup_msix_intr(struct qat_softc *);
 int		qat_etr_init(struct qat_softc *);
 int		qat_etr_bank_init(struct qat_softc *, int);
 int		qat_etr_ap_bank_init(struct qat_softc *);
 void		qat_etr_ap_bank_set_ring_mask(uint32_t *, uint32_t, int);
 void		qat_etr_ap_bank_set_ring_dest(struct qat_softc *, uint32_t *,
 		    uint32_t, int);
 void		qat_etr_ap_bank_setup_ring(struct qat_softc *,
 		    struct qat_ring *);
 int		qat_etr_verify_ring_size(uint32_t, uint32_t);
 int		qat_etr_ring_intr(struct qat_softc *, struct qat_bank *,
 		    struct qat_ring *);
 int		qat_etr_bank_intr(void *);
 void		qat_arb_update(struct qat_softc *, struct qat_bank *);
 struct qat_sym_cookie *
 		qat_crypto_alloc_sym_cookie(struct qat_crypto_bank *);
 void		qat_crypto_free_sym_cookie(struct qat_crypto_bank *,
 		    struct qat_sym_cookie *);
 int		qat_crypto_load_buf(struct qat_softc *, struct cryptop *,
 		    struct qat_sym_cookie *, struct qat_crypto_desc const *,
 		    uint8_t *, int, bus_addr_t *);
 int		qat_crypto_load_iv(struct qat_sym_cookie *, struct cryptop *,
 		    struct cryptodesc *, struct qat_crypto_desc const *);
 int		qat_crypto_process(void *, struct cryptop *, int);
 int		qat_crypto_setup_ring(struct qat_softc *,
 		    struct qat_crypto_bank *);
 int		qat_crypto_new_session(void *, uint32_t *, struct cryptoini *);
 int		qat_crypto_free_session0(struct qat_crypto *,
 		    struct qat_session *);
 void		qat_crypto_check_free_session(struct qat_crypto *,
 		    struct qat_session *);
 int		qat_crypto_free_session(void *, uint64_t);
 int		qat_crypto_bank_init(struct qat_softc *,
 		    struct qat_crypto_bank *);
 int		qat_crypto_init(struct qat_softc *);
 int		qat_crypto_start(struct qat_softc *);
 int		qat_crypto_sym_rxintr(struct qat_softc *, void *, void *);
 CFATTACH_DECL_NEW(qat, sizeof(struct qat_softc),
     qat_match, qat_attach, qat_detach, NULL);
 struct qat_softc *gsc = NULL;
 #ifdef QAT_DUMP
 int qat_dump = QAT_DUMP;
 #endif
 const struct qat_product *
 qat_lookup(const struct pci_attach_args *pa)
+{
 	const struct qat_product *qatp;
 	for (qatp = qat_products; qatp->qatp_name != NULL; qatp++) {
 		if (PCI_VENDOR(pa->pa_id) == qatp->qatp_vendor &&
 		    PCI_PRODUCT(pa->pa_id) == qatp->qatp_product)
 			return qatp;
+	}
 	return NULL;
+}
 int
 qat_match(struct device *parent, struct cfdata *cf, void *aux)
+{
 	struct pci_attach_args *pa = aux;
 	if (qat_lookup(pa) != NULL)
 		return 1;
 	return 0;
+}
 void
 qat_attach(struct device *parent, struct device *self, void *aux)
+{
 	struct qat_softc *sc = device_private(self);
 	struct pci_attach_args *pa = aux;
 	pci_chipset_tag_t pc = pa->pa_pc;
 	const struct qat_product *qatp;
 	char cap[256];
 	pcireg_t cmd, memtype, msixoff, fusectl;
 	bus_size_t msixtbl_offset;
 	int i, bar, msixtbl_bar;
 	sc->sc_dev = self;
 	sc->sc_pc = pc;
 	sc->sc_pcitag = pa->pa_tag;
 	gsc = sc; /* for debug */
 	qatp = qat_lookup(pa);
 	KASSERT(qatp != NULL);
 	if (pci_dma64_available(pa))
 		sc->sc_dmat = pa->pa_dmat64;
 	else
 		sc->sc_dmat = pa->pa_dmat;
 	aprint_naive(": Crypto processor\n");
 	sc->sc_rev = PCI_REVISION(pa->pa_class);
 	aprint_normal(": %s (rev. 0x%02x)\n", qatp->qatp_name, sc->sc_rev);
 	memcpy(&sc->sc_hw, qatp->qatp_hw, sizeof(struct qat_hw));
 	/* Determine active accelerators and engines */
 	sc->sc_accel_mask = sc->sc_hw.qhw_get_accel_mask(sc);
 	sc->sc_ae_mask = sc->sc_hw.qhw_get_ae_mask(sc);
 	sc->sc_accel_num = 0;
 	for (i = 0; i < sc->sc_hw.qhw_num_accel; i++) {
 		if (sc->sc_accel_mask & (1 << i))
 			sc->sc_accel_num++;
+	}
 	sc->sc_ae_num = 0;
 	for (i = 0; i < sc->sc_hw.qhw_num_engines; i++) {
 		if (sc->sc_ae_mask & (1 << i)) {
 			sc->sc_ae_num++;
+		}
+	}
 	if (!sc->sc_accel_mask || (sc->sc_ae_mask & 0x01) == 0) {
 		aprint_error_dev(sc->sc_dev, "couldn't find acceleration");
 		goto fail;
+	}
 	KASSERT(sc->sc_accel_num <= MAX_NUM_ACCEL);
 	KASSERT(sc->sc_ae_num <= MAX_NUM_AE);
 	/* Determine SKU and capabilities */
 	sc->sc_sku = sc->sc_hw.qhw_get_sku(sc);
 	sc->sc_accel_cap = sc->sc_hw.qhw_get_accel_cap(sc);
 	sc->sc_fw_uof_name = sc->sc_hw.qhw_get_fw_uof_name(sc);
 	aprint_normal_dev(sc->sc_dev,
 	    "sku %d accel %d accel_mask 0x%x ae %d ae_mask 0x%x\n",
 	    sc->sc_sku, sc->sc_accel_num, sc->sc_accel_mask,
 	    sc->sc_ae_num, sc->sc_ae_mask);
 	snprintb(cap, sizeof(cap), QAT_ACCEL_CAP_BITS, sc->sc_accel_cap);
 	aprint_normal_dev(sc->sc_dev, "accel capabilities %s\n", cap);
 	/* Map BARs */
 	msixtbl_bar = 0;
 	msixtbl_offset = 0;
 	if (pci_get_capability(pc, pa->pa_tag, PCI_CAP_MSIX, &msixoff, NULL)) {
 		pcireg_t msixtbl;
 		msixtbl = pci_conf_read(pc, pa->pa_tag,
 		    msixoff + PCI_MSIX_TBLOFFSET);
 		msixtbl_offset = msixtbl & PCI_MSIX_TBLOFFSET_MASK;
 		msixtbl_bar = PCI_MAPREG_START +
 		    ((msixtbl & PCI_MSIX_TBLBIR_MASK) << 2);
+	}
 	i = 0;
 	if (sc->sc_hw.qhw_sram_bar_id != NO_PCI_REG) {
 		KASSERT(sc->sc_hw.qhw_sram_bar_id == 0);
 		fusectl = pci_conf_read(sc->sc_pc, sc->sc_pcitag, FUSECTL_REG);
 		/* Skip SRAM BAR */
 		i = (fusectl & FUSECTL_MASK) ? 1 : 0;
+	}
 	for (bar = PCI_MAPREG_START; bar <= PCI_MAPREG_END; bar += 4) {
 		bus_size_t size;
 		bus_addr_t addr;
 		if (pci_mapreg_probe(pc, pa->pa_tag, bar, &memtype) == 0)
 			continue;
 		if (PCI_MAPREG_TYPE(memtype) != PCI_MAPREG_TYPE_MEM)
 			continue;
 		/* MSI-X table will be mapped by pci_msix_alloc_map */
 		if (bar == msixtbl_bar)
 			size = msixtbl_offset;
 		else
 			size = 0;
 		if (pci_mapreg_submap(pa, bar, memtype, 0, size, 0,
 		    &sc->sc_csrt[i], &sc->sc_csrh[i], &addr, &sc->sc_csrs[i])) {
 			aprint_error_dev(sc->sc_dev,
 			    "couldn't map bar 0x%02x\n", bar);
 			goto fail;
+		}
 		aprint_verbose_dev(sc->sc_dev,
 		    "region #%d bar 0x%02x size 0x%x at 0x%llx"
 		    " mapped to %p\n", i, bar,
 		    (int)sc->sc_csrs[i], (unsigned long long)addr,
 		    bus_space_vaddr(sc->sc_csrt[i], sc->sc_csrh[i]));
 		i++;
 		if (PCI_MAPREG_MEM_TYPE(memtype) == PCI_MAPREG_MEM_TYPE_64BIT)
 			bar += 4;
+	}
 	/* XXX Enable advanced error reporting */
 	/* Enable bus mastering */
 	cmd = pci_conf_read(pc, pa->pa_tag, PCI_COMMAND_STATUS_REG);
 	cmd |= PCI_COMMAND_MASTER_ENABLE;
 	pci_conf_write(pc, pa->pa_tag, PCI_COMMAND_STATUS_REG, cmd);
 	if (qat_alloc_msix_intr(sc, pa))
 		goto fail;
 	config_mountroot(self, qat_init);
 fail:
 	/* XXX */
 	return;
+}
 void
 qat_init(struct device *self)
+{
 	int error;
 	struct qat_softc *sc = device_private(self);
 	aprint_verbose_dev(sc->sc_dev, "Initializing ETR\n");
 	error = qat_etr_init(sc);
 	if (error) {
 		aprint_error_dev(sc->sc_dev,
 		    "Could not initialize ETR: %d\n", error);
 		return;
+	}
 	aprint_verbose_dev(sc->sc_dev, "Initializing admin comms\n");
 	if (sc->sc_hw.qhw_init_admin_comms != NULL &&
 	    (error = sc->sc_hw.qhw_init_admin_comms(sc)) != 0) {
 		aprint_error_dev(sc->sc_dev,
 		    "Could not initialize admin comms: %d\n", error);
 		return;
+	}
 	aprint_verbose_dev(sc->sc_dev, "Initializing hw arbiter\n");
 	if (sc->sc_hw.qhw_init_arb != NULL &&
 	    (error = sc->sc_hw.qhw_init_arb(sc)) != 0) {
 		aprint_error_dev(sc->sc_dev,
 		    "Could not initialize hw arbiter: %d\n", error);
 		return;
+	}
 	aprint_verbose_dev(sc->sc_dev, "Initializing acceleration engine\n");
 	error = qat_ae_init(sc);
 	if (error) {
 		aprint_error_dev(sc->sc_dev,
 		    "Could not initialize Acceleration Engine: %d\n", error);
 		return;
+	}
 	aprint_verbose_dev(sc->sc_dev, "Loading acceleration engine firmware\n");
 	error = qat_aefw_load(sc);
 	if (error) {
 		aprint_error_dev(sc->sc_dev,
 		    "Could not load firmware: %d\n", error);
 		return;
+	}
 	aprint_verbose_dev(sc->sc_dev, "Establishing interrupts\n");
 	error = qat_setup_msix_intr(sc);
 	if (error) {
 		aprint_error_dev(sc->sc_dev,
 		    "Could not setup interrupts: %d\n", error);
 		return;
+	}
 	sc->sc_hw.qhw_enable_intr(sc);
 	error = qat_crypto_init(sc);
 	if (error) {
 		aprint_error_dev(sc->sc_dev,
 		    "Could not initialize service: %d\n", error);
 		return;
+	}
 	aprint_verbose_dev(sc->sc_dev, "Enabling error correction\n");
 	if (sc->sc_hw.qhw_enable_error_correction != NULL)
 		sc->sc_hw.qhw_enable_error_correction(sc);
 	aprint_verbose_dev(sc->sc_dev, "Initializing watchdog timer\n");
 	if (sc->sc_hw.qhw_set_ssm_wdtimer != NULL &&
 	    (error = sc->sc_hw.qhw_set_ssm_wdtimer(sc)) != 0) {
 		aprint_error_dev(sc->sc_dev,
 		    "Could not initialize watchdog timer: %d\n", error);
 		return;
+	}
 	error = qat_start(self);
 	if (error) {
 		aprint_error_dev(sc->sc_dev,
 		    "Could not start: %d\n", error);
 		return;
+	}
+}
 int
 qat_start(struct device *self)
+{
 	struct qat_softc *sc = device_private(self);
 	int error;
 	error = qat_ae_start(sc);
 	if (error)
 		return error;
 	if (sc->sc_hw.qhw_send_admin_init != NULL &&
 	    (error = sc->sc_hw.qhw_send_admin_init(sc)) != 0) {
 		return error;
+	}
 	error = qat_crypto_start(sc);
 	if (error)
 		return error;
 	return 0;
+}
 int
 qat_detach(struct device *self, int flags)
+{
 	return 0;
+}
 void *
 qat_alloc_mem(size_t size)
+{
 	size_t *sptr;
 	sptr = kmem_zalloc(size + sizeof(size), KM_SLEEP);
 	*sptr = size;
 	return ++sptr;
+}
 void
 qat_free_mem(void *ptr)
+{
 	size_t *sptr = ptr, size;
 	size = *(--sptr);
 	kmem_free(sptr, size + sizeof(size));
+}
 void
 qat_free_dmamem(struct qat_softc *sc, struct qat_dmamem *qdm)
+{
 	bus_dmamap_unload(sc->sc_dmat, qdm->qdm_dma_map);
 	bus_dmamap_destroy(sc->sc_dmat, qdm->qdm_dma_map);
 	bus_dmamem_unmap(sc->sc_dmat, qdm->qdm_dma_vaddr, qdm->qdm_dma_size);
 	bus_dmamem_free(sc->sc_dmat, &qdm->qdm_dma_seg, 1);
 	explicit_memset(qdm, 0, sizeof(*qdm));
+}
 int
 qat_alloc_dmamem(struct qat_softc *sc, struct qat_dmamem *qdm,
 	bus_size_t size, bus_size_t alignment)
+{
 	int error = 0, nseg;
 	error = bus_dmamem_alloc(sc->sc_dmat, size, alignment,
 , &qdm->qdm_dma_seg, 1, &nseg, BUS_DMA_NOWAIT);
 	if (error) {
 		aprint_error_dev(sc->sc_dev,
 		    "couldn't allocate dmamem, error = %d\n", error);
 		goto fail_0;
+	}
 	KASSERT(nseg == 1);
 	error = bus_dmamem_map(sc->sc_dmat, &qdm->qdm_dma_seg,
 	    nseg, size, &qdm->qdm_dma_vaddr,
 	    BUS_DMA_COHERENT | BUS_DMA_NOWAIT);
 	if (error) {
 		aprint_error_dev(sc->sc_dev,
 		    "couldn't map dmamem, error = %d\n", error);
 		goto fail_1;
+	}
 	qdm->qdm_dma_size = size;
 	error = bus_dmamap_create(sc->sc_dmat, size, nseg, size,
 , BUS_DMA_NOWAIT, &qdm->qdm_dma_map);
 	if (error) {
 		aprint_error_dev(sc->sc_dev,
 		    "couldn't create dmamem map, error = %d\n", error);
 		goto fail_2;
+	}
 	error = bus_dmamap_load(sc->sc_dmat, qdm->qdm_dma_map,
 	    qdm->qdm_dma_vaddr, size, NULL, BUS_DMA_NOWAIT);
 	if (error) {
 		aprint_error_dev(sc->sc_dev,
 		    "couldn't load dmamem map, error = %d\n", error);
 		goto fail_3;
+	}
 	return 0;
 fail_3:
 	bus_dmamap_destroy(sc->sc_dmat, qdm->qdm_dma_map);
 	qdm->qdm_dma_map = NULL;
 fail_2:
 	bus_dmamem_unmap(sc->sc_dmat, qdm->qdm_dma_vaddr, size);
 	qdm->qdm_dma_vaddr = NULL;
 	qdm->qdm_dma_size = 0;
 fail_1:
 	bus_dmamem_free(sc->sc_dmat, &qdm->qdm_dma_seg, 1);
 fail_0:
 	return error;
+}
 int
 qat_alloc_msix_intr(struct qat_softc *sc, struct pci_attach_args *pa)
+{
 	u_int *ih_map, vec;
 	int error, count, ihi;
 	count = sc->sc_hw.qhw_num_banks + 1;
 	ih_map = qat_alloc_mem(sizeof(*ih_map) * count);
 	ihi = 0;
 	for (vec = 0; vec < sc->sc_hw.qhw_num_banks; vec++)
 		ih_map[ihi++] = vec;
 	vec += sc->sc_hw.qhw_msix_ae_vec_gap;
 	ih_map[ihi++] = vec;
 	error = pci_msix_alloc_map(pa, &sc->sc_ih, ih_map, count);
 	qat_free_mem(ih_map);
 	if (error) {
 		aprint_error_dev(sc->sc_dev, "couldn't allocate msix %d: %d\n",
 		    count, error);
+	}
 	return error;
+}
 void *
 qat_establish_msix_intr(struct qat_softc *sc, pci_intr_handle_t ih,
 	int (*func)(void *), void *arg,
 	const char *name, int index)
+{
 	kcpuset_t *affinity;
 	int error;
 	char buf[PCI_INTRSTR_LEN];
 	char intrxname[INTRDEVNAMEBUF];
 	const char *intrstr;
 	void *cookie;
 	snprintf(intrxname, sizeof(intrxname), "%s%s%d",
 	    device_xname(sc->sc_dev), name, index);
 	intrstr = pci_intr_string(sc->sc_pc, ih, buf, sizeof(buf));
 	pci_intr_setattr(sc->sc_pc, &ih, PCI_INTR_MPSAFE, true);
 	cookie = pci_intr_establish_xname(sc->sc_pc, ih,
 	    IPL_NET, func, arg, intrxname);
 	aprint_normal_dev(sc->sc_dev, "%s%d interrupting at %s\n",
 	    name, index, intrstr);
 	kcpuset_create(&affinity, true);
 	kcpuset_set(affinity, index % ncpu);
 	error = interrupt_distribute(cookie, affinity, NULL);
 	if (error) {
 		aprint_error_dev(sc->sc_dev,
 		    "couldn't distribute interrupt: %s%d\n", name, index);
+	}
 	kcpuset_destroy(affinity);
 	return cookie;
+}
 int
 qat_setup_msix_intr(struct qat_softc *sc)
+{
 	int i;
 	pci_intr_handle_t ih;
 	for (i = 0; i < sc->sc_hw.qhw_num_banks; i++) {
 		struct qat_bank *qb = &sc->sc_etr_banks[i];
 		ih = sc->sc_ih[i];
 		qb->qb_ih_cookie = qat_establish_msix_intr(sc, ih,
 		    qat_etr_bank_intr, qb, "bank", i);
 		if (qb->qb_ih_cookie == NULL)
 			return ENOMEM;
+	}
 	sc->sc_ae_ih_cookie = qat_establish_msix_intr(sc, sc->sc_ih[i],
 	    qat_ae_cluster_intr, sc, "aeclust", 0);
 	if (sc->sc_ae_ih_cookie == NULL)
 		return ENOMEM;
 	return 0;
+}
 int
 qat_etr_init(struct qat_softc *sc)
+{
 	int i;
 	int error = 0;
 	sc->sc_etr_banks = qat_alloc_mem(
 	    sizeof(struct qat_bank) * sc->sc_hw.qhw_num_banks);
 	for (i = 0; i < sc->sc_hw.qhw_num_banks; i++) {
 		error = qat_etr_bank_init(sc, i);
 		if (error) {
 			goto fail;
+		}
+	}
 	if (sc->sc_hw.qhw_num_ap_banks) {
 		sc->sc_etr_ap_banks = qat_alloc_mem(
 		    sizeof(struct qat_ap_bank) * sc->sc_hw.qhw_num_ap_banks);
 		error = qat_etr_ap_bank_init(sc);
 		if (error) {
 			goto fail;
+		}
+	}
 	return 0;
 fail:
 	if (sc->sc_etr_banks != NULL) {
 		qat_free_mem(sc->sc_etr_banks);
 		sc->sc_etr_banks = NULL;
+	}
 	if (sc->sc_etr_ap_banks != NULL) {
 		qat_free_mem(sc->sc_etr_ap_banks);
 		sc->sc_etr_ap_banks = NULL;
+	}
 	return error;
+}
 int
 qat_etr_bank_init(struct qat_softc *sc, int bank)
+{
 	struct qat_bank *qb = &sc->sc_etr_banks[bank];
 	int i, tx_rx_gap = sc->sc_hw.qhw_tx_rx_gap;
 	KASSERT(bank < sc->sc_hw.qhw_num_banks);
 	mutex_init(&qb->qb_bank_mtx, MUTEX_DEFAULT, IPL_NET);
 	qb->qb_sc = sc;
 	qb->qb_bank = bank;
 	qb->qb_coalescing_time = COALESCING_TIME_INTERVAL_DEFAULT;
 	QAT_EVCNT_ATTACH(sc, &qb->qb_ev_rxintr, EVCNT_TYPE_INTR,
 	    qb->qb_ev_rxintr_name, "bank%d rxintr", bank);
 	/* Clean CSRs for all rings within the bank */
 	for (i = 0; i < sc->sc_hw.qhw_num_rings_per_bank; i++) {
 		struct qat_ring *qr = &qb->qb_et_rings[i];
 		qat_etr_bank_ring_write_4(sc, bank, i,
 		    ETR_RING_CONFIG, 0);
 		qat_etr_bank_ring_base_write_8(sc, bank, i, 0);
 		if (sc->sc_hw.qhw_tx_rings_mask & (1 << i)) {
 			qr->qr_inflight = qat_alloc_mem(sizeof(uint32_t));
 		} else if (sc->sc_hw.qhw_tx_rings_mask &
 		    (1 << (i - tx_rx_gap))) {
 			/* Share inflight counter with rx and tx */
 			qr->qr_inflight =
 			    qb->qb_et_rings[i - tx_rx_gap].qr_inflight;
+		}
+	}
 	if (sc->sc_hw.qhw_init_etr_intr != NULL) {
 		sc->sc_hw.qhw_init_etr_intr(sc, bank);
 	} else {
 		/* common code in qat 1.7 */
 		qat_etr_bank_write_4(sc, bank, ETR_INT_REG,
 		    ETR_INT_REG_CLEAR_MASK);
 		for (i = 0; i < sc->sc_hw.qhw_num_rings_per_bank /
 		    ETR_RINGS_PER_INT_SRCSEL; i++) {
 			qat_etr_bank_write_4(sc, bank, ETR_INT_SRCSEL +
 			    (i * ETR_INT_SRCSEL_NEXT_OFFSET),
 			    ETR_INT_SRCSEL_MASK);
+		}
+	}
 	return 0;
+}
 int
 qat_etr_ap_bank_init(struct qat_softc *sc)
+{
 	int ap_bank;
 	for (ap_bank = 0; ap_bank < sc->sc_hw.qhw_num_ap_banks; ap_bank++) {
 		struct qat_ap_bank *qab = &sc->sc_etr_ap_banks[ap_bank];
 		qat_etr_ap_bank_write_4(sc, ap_bank, ETR_AP_NF_MASK,
 		    ETR_AP_NF_MASK_INIT);
 		qat_etr_ap_bank_write_4(sc, ap_bank, ETR_AP_NF_DEST, 0);
 		qat_etr_ap_bank_write_4(sc, ap_bank, ETR_AP_NE_MASK,
 		    ETR_AP_NE_MASK_INIT);
 		qat_etr_ap_bank_write_4(sc, ap_bank, ETR_AP_NE_DEST, 0);
 		memset(qab, 0, sizeof(*qab));
+	}
 	return 0;
+}
 void
 qat_etr_ap_bank_set_ring_mask(uint32_t *ap_mask, uint32_t ring, int set_mask)
+{
 	if (set_mask)
 		*ap_mask |= (1 << ETR_RING_NUMBER_IN_AP_BANK(ring));
 	else
 		*ap_mask &= ~(1 << ETR_RING_NUMBER_IN_AP_BANK(ring));
+}
 void
 qat_etr_ap_bank_set_ring_dest(struct qat_softc *sc, uint32_t *ap_dest,
 	uint32_t ring, int set_dest)
+{
 	uint32_t ae_mask;
 	uint8_t mailbox, ae, nae;
 	uint8_t *dest = (uint8_t *)ap_dest;
 	mailbox = ETR_RING_AP_MAILBOX_NUMBER(ring);
 	nae = 0;
 	ae_mask = sc->sc_ae_mask;
 	for (ae = 0; ae < sc->sc_hw.qhw_num_engines; ae++) {
 		if ((ae_mask & (1 << ae)) == 0)
 			continue;
 		if (set_dest) {
 			dest[nae] = __SHIFTIN(ae, ETR_AP_DEST_AE) |
 			    __SHIFTIN(mailbox, ETR_AP_DEST_MAILBOX) |
 			    ETR_AP_DEST_ENABLE;
 		} else {
 			dest[nae] = 0;
+		}
 		nae++;
 		if (nae == ETR_MAX_AE_PER_MAILBOX)
 			break;
+	}
+}
 void
 qat_etr_ap_bank_setup_ring(struct qat_softc *sc, struct qat_ring *qr)
+{
 	struct qat_ap_bank *qab;
 	int ap_bank;
 	if (sc->sc_hw.qhw_num_ap_banks == 0)
 		return;
 	ap_bank = ETR_RING_AP_BANK_NUMBER(qr->qr_ring);
 	KASSERT(ap_bank < sc->sc_hw.qhw_num_ap_banks);
 	qab = &sc->sc_etr_ap_banks[ap_bank];
 	if (qr->qr_cb == NULL) {
 		qat_etr_ap_bank_set_ring_mask(&qab->qab_ne_mask, qr->qr_ring, 1);
 		if (!qab->qab_ne_dest) {
 			qat_etr_ap_bank_set_ring_dest(sc, &qab->qab_ne_dest,
 			    qr->qr_ring, 1);
 			qat_etr_ap_bank_write_4(sc, ap_bank, ETR_AP_NE_DEST,
 			    qab->qab_ne_dest);
+		}
 	} else {
 		qat_etr_ap_bank_set_ring_mask(&qab->qab_nf_mask, qr->qr_ring, 1);
 		if (!qab->qab_nf_dest) {
 			qat_etr_ap_bank_set_ring_dest(sc, &qab->qab_nf_dest,
 			    qr->qr_ring, 1);
 			qat_etr_ap_bank_write_4(sc, ap_bank, ETR_AP_NF_DEST,
 			    qab->qab_nf_dest);
+		}
+	}
+}
 int
 qat_etr_verify_ring_size(uint32_t msg_size, uint32_t num_msgs)
+{
 	int i = QAT_MIN_RING_SIZE;
 	for (; i <= QAT_MAX_RING_SIZE; i++)
 		if ((msg_size * num_msgs) == QAT_SIZE_TO_RING_SIZE_IN_BYTES(i))
 			return i;
 	return QAT_DEFAULT_RING_SIZE;
+}
 int
 qat_etr_setup_ring(struct qat_softc *sc, int bank, uint32_t ring,
 	uint32_t num_msgs, uint32_t msg_size, qat_cb_t cb, void *cb_arg,
 	const char *name, struct qat_ring **rqr)
+{
 	struct qat_bank *qb;
 	struct qat_ring *qr = NULL;
 	int error;
 	uint32_t ring_size_bytes, ring_config;
 	uint64_t ring_base;
 	uint32_t wm_nf = ETR_RING_CONFIG_NEAR_WM_512;
 	uint32_t wm_ne = ETR_RING_CONFIG_NEAR_WM_0;
 	KASSERT(bank < sc->sc_hw.qhw_num_banks);
 	/* Allocate a ring from specified bank */
 	qb = &sc->sc_etr_banks[bank];
 	if (ring >= sc->sc_hw.qhw_num_rings_per_bank)
 		return EINVAL;
 	if (qb->qb_allocated_rings & (1 << ring))
 		return ENOENT;
 	qr = &qb->qb_et_rings[ring];
 	qb->qb_allocated_rings |= 1 << ring;
-	/* Intialize allocated ring */
+	/* Initialize allocated ring */
 	qr->qr_ring = ring;
 	qr->qr_bank = bank;
 	qr->qr_name = name;
 	qr->qr_ring_id = qr->qr_bank * sc->sc_hw.qhw_num_rings_per_bank + ring;
 	qr->qr_ring_mask = (1 << ring);
 	qr->qr_cb = cb;
 	qr->qr_cb_arg = cb_arg;
 	QAT_EVCNT_ATTACH(sc, &qr->qr_ev_rxintr, EVCNT_TYPE_INTR,
 	    qr->qr_ev_rxintr_name, "bank%d ring%d rxintr", bank, ring);
 	QAT_EVCNT_ATTACH(sc, &qr->qr_ev_rxmsg, EVCNT_TYPE_MISC,
 	    qr->qr_ev_rxmsg_name, "bank%d ring%d rxmsg", bank, ring);
 	QAT_EVCNT_ATTACH(sc, &qr->qr_ev_txmsg, EVCNT_TYPE_MISC,
 	    qr->qr_ev_txmsg_name, "bank%d ring%d txmsg", bank, ring);
 	QAT_EVCNT_ATTACH(sc, &qr->qr_ev_txfull, EVCNT_TYPE_MISC,
 	    qr->qr_ev_txfull_name, "bank%d ring%d txfull", bank, ring);
 	/* Setup the shadow variables */
 	qr->qr_head = 0;
 	qr->qr_tail = 0;
 	qr->qr_msg_size = QAT_BYTES_TO_MSG_SIZE(msg_size);
 	qr->qr_ring_size = qat_etr_verify_ring_size(msg_size, num_msgs);
 	/*
 	 * To make sure that ring is alligned to ring size allocate
 	 * at least 4k and then tell the user it is smaller.
 	 */
 	ring_size_bytes = QAT_SIZE_TO_RING_SIZE_IN_BYTES(qr->qr_ring_size);
 	ring_size_bytes = QAT_RING_SIZE_BYTES_MIN(ring_size_bytes);
 	error = qat_alloc_dmamem(sc, &qr->qr_dma,
 	    ring_size_bytes, ring_size_bytes);
 	if (error)
 		return error;
 	KASSERT(qr->qr_dma.qdm_dma_map->dm_nsegs == 1);
 	qr->qr_ring_vaddr = qr->qr_dma.qdm_dma_vaddr;
 	qr->qr_ring_paddr = qr->qr_dma.qdm_dma_map->dm_segs[0].ds_addr;
 	aprint_verbose_dev(sc->sc_dev,
 	    "allocate ring %d of bank %d for %s "
 	    "size %d %d at vaddr %p paddr 0x%llx\n",
 	    ring, bank, name, ring_size_bytes,
 	    (int)qr->qr_dma.qdm_dma_map->dm_segs[0].ds_len,
 	    qr->qr_ring_vaddr,
 	    (unsigned long long)qr->qr_ring_paddr);
 	memset(qr->qr_ring_vaddr, QAT_RING_PATTERN,
 	    qr->qr_dma.qdm_dma_map->dm_segs[0].ds_len);
 	bus_dmamap_sync(sc->sc_dmat, qr->qr_dma.qdm_dma_map, 0,
 	    qr->qr_dma.qdm_dma_map->dm_mapsize,
 	    BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD);
 	if (((uintptr_t)qr->qr_ring_paddr & (ring_size_bytes - 1)) != 0) {
 		aprint_error_dev(sc->sc_dev, "ring address not aligned\n");
 		return EFAULT;
+	}
 	if (cb == NULL) {
 		ring_config = ETR_RING_CONFIG_BUILD(qr->qr_ring_size);
 	} else {
 		ring_config =
 		    ETR_RING_CONFIG_BUILD_RESP(qr->qr_ring_size, wm_nf, wm_ne);
+	}
 	qat_etr_bank_ring_write_4(sc, bank, ring, ETR_RING_CONFIG, ring_config);
 	ring_base = ETR_RING_BASE_BUILD(qr->qr_ring_paddr, qr->qr_ring_size);
 	qat_etr_bank_ring_base_write_8(sc, bank, ring, ring_base);
 	if (sc->sc_hw.qhw_init_arb != NULL)
 		qat_arb_update(sc, qb);
 	mutex_init(&qr->qr_ring_mtx, MUTEX_DEFAULT, IPL_NET);
 	qat_etr_ap_bank_setup_ring(sc, qr);
 	if (cb != NULL) {
 		uint32_t intr_mask;
 		qb->qb_intr_mask |= qr->qr_ring_mask;
 		intr_mask = qb->qb_intr_mask;
 		aprint_verbose_dev(sc->sc_dev,
 		    "update intr mask for bank %d "
 		    "(coalescing time %dns): 0x%08x\n",
 		    bank, qb->qb_coalescing_time, intr_mask);
 		qat_etr_bank_write_4(sc, bank, ETR_INT_COL_EN,
 		    intr_mask);
 		qat_etr_bank_write_4(sc, bank, ETR_INT_COL_CTL,
 		    ETR_INT_COL_CTL_ENABLE | qb->qb_coalescing_time);
+	}
 	*rqr = qr;
 	return 0;
+}
 static inline u_int
 qat_modulo(u_int data, u_int shift)
+{
 	u_int div = data >> shift;
 	u_int mult = div << shift;
 	return data - mult;
+}
 int
 qat_etr_put_msg(struct qat_softc *sc, struct qat_ring *qr, uint32_t *msg)
+{
 	uint32_t inflight;
 	uint32_t *addr;
 	mutex_spin_enter(&qr->qr_ring_mtx);
 	inflight = atomic_inc_32_nv(qr->qr_inflight);
 	if (inflight > QAT_MAX_INFLIGHTS(qr->qr_ring_size, qr->qr_msg_size)) {
 		atomic_dec_32(qr->qr_inflight);
 		QAT_EVCNT_INCR(&qr->qr_ev_txfull);
 		mutex_spin_exit(&qr->qr_ring_mtx);
 		return EBUSY;
+	}
 	QAT_EVCNT_INCR(&qr->qr_ev_txmsg);
 	addr = (uint32_t *)((uintptr_t)qr->qr_ring_vaddr + qr->qr_tail);
 	memcpy(addr, msg, QAT_MSG_SIZE_TO_BYTES(qr->qr_msg_size));
 #ifdef QAT_DUMP
 	qat_dump_raw(QAT_DUMP_RING_MSG, "put_msg", addr,
 	    QAT_MSG_SIZE_TO_BYTES(qr->qr_msg_size));
 #endif
 	bus_dmamap_sync(sc->sc_dmat, qr->qr_dma.qdm_dma_map, qr->qr_tail,
 	    QAT_MSG_SIZE_TO_BYTES(qr->qr_msg_size),
 	    BUS_DMASYNC_PREWRITE);
 	qr->qr_tail = qat_modulo(qr->qr_tail +
 	    QAT_MSG_SIZE_TO_BYTES(qr->qr_msg_size),
 	    QAT_RING_SIZE_MODULO(qr->qr_ring_size));
 	qat_etr_bank_ring_write_4(sc, qr->qr_bank, qr->qr_ring,
 	    ETR_RING_TAIL_OFFSET, qr->qr_tail);
 	mutex_spin_exit(&qr->qr_ring_mtx);
 	return 0;
+}
 int
 qat_etr_ring_intr(struct qat_softc *sc, struct qat_bank *qb,
     struct qat_ring *qr)
+{
 	int handled = 0;
 	uint32_t *msg;
 	uint32_t nmsg = 0;
 	mutex_spin_enter(&qr->qr_ring_mtx);
 	QAT_EVCNT_INCR(&qr->qr_ev_rxintr);
 	msg = (uint32_t *)((uintptr_t)qr->qr_ring_vaddr + qr->qr_head);
 	bus_dmamap_sync(sc->sc_dmat, qr->qr_dma.qdm_dma_map, qr->qr_head,
 	    QAT_MSG_SIZE_TO_BYTES(qr->qr_msg_size),
 	    BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE);
 	while (*msg != ETR_RING_EMPTY_ENTRY_SIG) {
 		atomic_dec_32(qr->qr_inflight);
 		QAT_EVCNT_INCR(&qr->qr_ev_rxmsg);
 		if (qr->qr_cb != NULL) {
 			mutex_spin_exit(&qr->qr_ring_mtx);
 			handled |= qr->qr_cb(sc, qr->qr_cb_arg, msg);
 			mutex_spin_enter(&qr->qr_ring_mtx);
+		}
 		*msg = ETR_RING_EMPTY_ENTRY_SIG;
 		bus_dmamap_sync(sc->sc_dmat, qr->qr_dma.qdm_dma_map, qr->qr_head,
 		    QAT_MSG_SIZE_TO_BYTES(qr->qr_msg_size),
 		    BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD);
 		qr->qr_head = qat_modulo(qr->qr_head +
 		    QAT_MSG_SIZE_TO_BYTES(qr->qr_msg_size),
 		    QAT_RING_SIZE_MODULO(qr->qr_ring_size));
 		nmsg++;
 		msg = (uint32_t *)((uintptr_t)qr->qr_ring_vaddr + qr->qr_head);
 		bus_dmamap_sync(sc->sc_dmat, qr->qr_dma.qdm_dma_map, qr->qr_head,
 		    QAT_MSG_SIZE_TO_BYTES(qr->qr_msg_size),
 		    BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE);
+	}
 	if (nmsg > 0) {
 		qat_etr_bank_ring_write_4(sc, qr->qr_bank, qr->qr_ring,
 		    ETR_RING_HEAD_OFFSET, qr->qr_head);
+	}
 	mutex_spin_exit(&qr->qr_ring_mtx);
 	return handled;
+}
 int
 qat_etr_bank_intr(void *arg)
+{
 	struct qat_bank *qb = arg;
 	struct qat_softc *sc = qb->qb_sc;
 	uint32_t estat;
 	int i, handled = 0;
 	mutex_spin_enter(&qb->qb_bank_mtx);
 	QAT_EVCNT_INCR(&qb->qb_ev_rxintr);
 	qat_etr_bank_write_4(sc, qb->qb_bank, ETR_INT_COL_CTL, 0);
 	/* Now handle all the responses */
 	estat = ~qat_etr_bank_read_4(sc, qb->qb_bank, ETR_E_STAT);
 	estat &= qb->qb_intr_mask;
 	qat_etr_bank_write_4(sc, qb->qb_bank, ETR_INT_COL_CTL,
 	    ETR_INT_COL_CTL_ENABLE | qb->qb_coalescing_time);
 	mutex_spin_exit(&qb->qb_bank_mtx);
 	while ((i = ffs32(estat)) != 0) {
 		struct qat_ring *qr = &qb->qb_et_rings[--i];
 		estat &= ~(1 << i);
 		handled |= qat_etr_ring_intr(sc, qb, qr);
+	}
 	return handled;
+}
 void
 qat_arb_update(struct qat_softc *sc, struct qat_bank *qb)
+{
 	qat_arb_ringsrvarben_write_4(sc, qb->qb_bank,
 	    qb->qb_allocated_rings & 0xff);
+}
 struct qat_sym_cookie *
 qat_crypto_alloc_sym_cookie(struct qat_crypto_bank *qcb)
+{
 	struct qat_sym_cookie *qsc;
 	mutex_spin_enter(&qcb->qcb_bank_mtx);
 	if (qcb->qcb_symck_free_count == 0) {
 		QAT_EVCNT_INCR(&qcb->qcb_ev_no_symck);
 		mutex_spin_exit(&qcb->qcb_bank_mtx);
 		return NULL;
+	}
 	qsc = qcb->qcb_symck_free[--qcb->qcb_symck_free_count];
 	mutex_spin_exit(&qcb->qcb_bank_mtx);
 	return qsc;
+}
 void
 qat_crypto_free_sym_cookie(struct qat_crypto_bank *qcb, struct qat_sym_cookie *qsc)
+{
 	mutex_spin_enter(&qcb->qcb_bank_mtx);
 	qcb->qcb_symck_free[qcb->qcb_symck_free_count++] = qsc;
 	mutex_spin_exit(&qcb->qcb_bank_mtx);
+}
 void
 qat_memcpy_htobe64(void *dst, const void *src, size_t len)
+{
 	uint64_t *dst0 = dst;
 	const uint64_t *src0 = src;
 	size_t i;
 	KASSERT(len % sizeof(*dst0) == 0);
 	for (i = 0; i < len / sizeof(*dst0); i++)
 		*(dst0 + i) = htobe64(*(src0 + i));
+}
 void
 qat_memcpy_htobe32(void *dst, const void *src, size_t len)
+{
 	uint32_t *dst0 = dst;
 	const uint32_t *src0 = src;
 	size_t i;
 	KASSERT(len % sizeof(*dst0) == 0);
 	for (i = 0; i < len / sizeof(*dst0); i++)
 		*(dst0 + i) = htobe32(*(src0 + i));
+}
 void
 qat_memcpy_htobe(void *dst, const void *src, size_t len, uint32_t wordbyte)
+{
 	switch (wordbyte) {
 	case 4:
 		qat_memcpy_htobe32(dst, src, len);
 		break;
 	case 8:
 		qat_memcpy_htobe64(dst, src, len);
 		break;
 	default:
 		KASSERT(0);
+	}
+}
 void
 qat_crypto_hmac_precompute(struct qat_crypto_desc *desc, struct cryptoini *cria,
     struct qat_sym_hash_def const *hash_def, uint8_t *state1, uint8_t *state2)
+{
 	int i, state_swap;
 	struct swcr_auth_hash const *sah = hash_def->qshd_alg->qshai_sah;
 	uint32_t blklen = hash_def->qshd_alg->qshai_block_len;
 	uint32_t state_offset = hash_def->qshd_alg->qshai_state_offset;
 	uint32_t state_size = hash_def->qshd_alg->qshai_state_size;
 	uint32_t state_word = hash_def->qshd_alg->qshai_state_word;
 	uint32_t keylen = cria->cri_klen / 8;
 	uint32_t padlen = blklen - keylen;
 	uint8_t *ipad = desc->qcd_hash_state_prefix_buf;
 	uint8_t *opad = desc->qcd_hash_state_prefix_buf +
 	    sizeof(desc->qcd_hash_state_prefix_buf) / 2;
 	/* XXX
 	 * For "stack protector not protecting local variables" error,
 	 * use constant variable.
 	 * Currently, the max length is sizeof(aesxcbc_ctx) used by
 	 * swcr_auth_hash_aes_xcbc_mac
 	 */
 	uint8_t ctx[sizeof(aesxcbc_ctx)];
 	memcpy(ipad, cria->cri_key, keylen);
 	memcpy(opad, cria->cri_key, keylen);
 	if (padlen > 0) {
 		memset(ipad + keylen, 0, padlen);
 		memset(opad + keylen, 0, padlen);
+	}
 	for (i = 0; i < blklen; i++) {
 		ipad[i] ^= 0x36;
 		opad[i] ^= 0x5c;
+	}
 	/* ipad */
 	sah->Init(ctx);
 	/* Check the endian of kernel built-in hash state */
 	state_swap = memcmp(hash_def->qshd_alg->qshai_init_state,
 	    ((uint8_t *)ctx) + state_offset, state_word);
 	sah->Update(ctx, ipad, blklen);
 	if (state_swap == 0) {
 		memcpy(state1, ((uint8_t *)ctx) + state_offset, state_size);
 	} else {
 		qat_memcpy_htobe(state1, ((uint8_t *)ctx) + state_offset,
 		    state_size, state_word);
+	}
 	/* opad */
 	sah->Init(ctx);
 	sah->Update(ctx, opad, blklen);
 	if (state_swap == 0) {
 		memcpy(state2, ((uint8_t *)ctx) + state_offset, state_size);
 	} else {
 		qat_memcpy_htobe(state2, ((uint8_t *)ctx) + state_offset,
 		    state_size, state_word);
+	}
+}
 uint16_t
 qat_crypto_load_cipher_cryptoini(
     struct qat_crypto_desc *desc, struct cryptoini *crie)
+{
 	enum hw_cipher_algo algo = HW_CIPHER_ALGO_NULL;
 	enum hw_cipher_mode mode = HW_CIPHER_CBC_MODE;
 	enum hw_cipher_convert key_convert = HW_CIPHER_NO_CONVERT;
 	switch (crie->cri_alg) {
 	case CRYPTO_DES_CBC:
 		algo = HW_CIPHER_ALGO_DES;
 		desc->qcd_cipher_blk_sz = HW_DES_BLK_SZ;
 		break;
 	case CRYPTO_3DES_CBC:
 		algo = HW_CIPHER_ALGO_3DES;
 		desc->qcd_cipher_blk_sz = HW_3DES_BLK_SZ;
 		break;
 	case CRYPTO_AES_CBC:
 		switch (crie->cri_klen / 8) {
 		case HW_AES_128_KEY_SZ:
 			algo = HW_CIPHER_ALGO_AES128;
 			break;
 		case HW_AES_192_KEY_SZ:
 			algo = HW_CIPHER_ALGO_AES192;
 			break;
 		case HW_AES_256_KEY_SZ:
 			algo = HW_CIPHER_ALGO_AES256;
 			break;
 		default:
 			KASSERT(0);
 			break;
+		}
 		desc->qcd_cipher_blk_sz = HW_AES_BLK_SZ;
 		/*
 		 * AES decrypt key needs to be reversed.
 		 * Instead of reversing the key at session registration,
 		 * it is instead reversed on-the-fly by setting the KEY_CONVERT
 		 * bit here
 		 */
 		if (desc->qcd_cipher_dir == HW_CIPHER_DECRYPT)
 			key_convert = HW_CIPHER_KEY_CONVERT;
 		break;
 	default:
 		KASSERT(0);
 		break;
+	}
 	return HW_CIPHER_CONFIG_BUILD(mode, algo, key_convert,
 	    desc->qcd_cipher_dir);
+}
 uint16_t
 qat_crypto_load_auth_cryptoini(
     struct qat_crypto_desc *desc, struct cryptoini *cria,
     struct qat_sym_hash_def const **hash_def)
+{
 	const struct swcr_auth_hash *sah;
 	enum qat_sym_hash_algorithm algo = 0;
 	switch (cria->cri_alg) {
 	case CRYPTO_MD5_HMAC_96:
 		algo = QAT_SYM_HASH_MD5;
 		break;
 	case CRYPTO_SHA1_HMAC_96:
 		algo = QAT_SYM_HASH_SHA1;
 		break;
 	case CRYPTO_SHA2_256_HMAC:
 		algo = QAT_SYM_HASH_SHA256;
 		break;
 	case CRYPTO_SHA2_384_HMAC:
 		algo = QAT_SYM_HASH_SHA384;
 		break;
 	case CRYPTO_SHA2_512_HMAC:
 		algo = QAT_SYM_HASH_SHA512;
 		break;
 	default:
 		KASSERT(0);
 		break;
+	}
 	*hash_def = &qat_sym_hash_defs[algo];
 	sah = (*hash_def)->qshd_alg->qshai_sah;
 	KASSERT(sah != NULL);
 	desc->qcd_auth_sz = sah->auth_hash->authsize;
 	return HW_AUTH_CONFIG_BUILD(HW_AUTH_MODE1,
 	    (*hash_def)->qshd_qat->qshqi_algo_enc,
 	    (*hash_def)->qshd_alg->qshai_digest_len);
+}
 int
 qat_crypto_load_buf(struct qat_softc *sc, struct cryptop *crp,
     struct qat_sym_cookie *qsc, struct qat_crypto_desc const *desc,
     uint8_t *icv_buf, int icv_offset, bus_addr_t *icv_paddr)
+{
 	int error, i, nsegs;
 	if (crp->crp_flags & CRYPTO_F_IMBUF) {
 		struct mbuf *m = (struct mbuf *)crp->crp_buf;
 		if (icv_offset >= 0) {
 			if (m_length(m) == icv_offset) {
 				m_copyback(m, icv_offset, desc->qcd_auth_sz,
 				    icv_buf);
 				if (m_length(m) == icv_offset)
 					return ENOBUFS;
 			} else {
 				struct mbuf *m0;
 				m0 = m_pulldown(m, icv_offset,
 				    desc->qcd_auth_sz, NULL);
 				if (m0 == NULL)
 					return ENOBUFS;
+			}
+		}
 		error = bus_dmamap_load_mbuf(sc->sc_dmat, qsc->qsc_buf_dmamap,
 		    m, BUS_DMA_WRITE | BUS_DMA_NOWAIT);
 		if (error == EFBIG) {
 			struct mbuf *m_new;
 			m_new = m_defrag(m, M_DONTWAIT);
 			if (m_new != NULL) {
 				crp->crp_buf = m_new;
 				qsc->qsc_buf = m_new;
 				error = bus_dmamap_load_mbuf(sc->sc_dmat,
 				    qsc->qsc_buf_dmamap, m_new,
 				    BUS_DMA_WRITE | BUS_DMA_NOWAIT);
 				if (error) {
 					m_freem(m_new);
 					crp->crp_buf = NULL;
+				}
+			}
+		}
 	} else if (crp->crp_flags & CRYPTO_F_IOV) {
 		error = bus_dmamap_load_uio(sc->sc_dmat, qsc->qsc_buf_dmamap,
 		    (struct uio *)crp->crp_buf, BUS_DMA_WRITE | BUS_DMA_NOWAIT);
 	} else {
 		error = bus_dmamap_load(sc->sc_dmat, qsc->qsc_buf_dmamap,
 		    crp->crp_buf, crp->crp_ilen, NULL, BUS_DMA_NOWAIT);
+	}
 	if (error) {
 		aprint_debug_dev(sc->sc_dev,
 		    "can't load crp_buf, error %d\n", error);
 		crp->crp_etype = error;
 		return error;
+	}
 	nsegs = qsc->qsc_buf_dmamap->dm_nsegs;
 	qsc->qsc_buf_list.num_buffers = nsegs;
 	for (i = 0; i < nsegs; i++) {
 		struct flat_buffer_desc *flatbuf =
 		    &qsc->qsc_buf_list.phy_buffers[i];
 		bus_addr_t paddr = qsc->qsc_buf_dmamap->dm_segs[i].ds_addr;
 		bus_size_t len = qsc->qsc_buf_dmamap->dm_segs[i].ds_len;
 		flatbuf->data_len_in_bytes = len;
 		flatbuf->phy_buffer = (uint64_t)paddr;
 		if (icv_offset >= 0) {
 			if (icv_offset < len)
 				*icv_paddr = paddr + icv_offset;
 			else
 				icv_offset -= len;
+		}
+	}
 	bus_dmamap_sync(sc->sc_dmat, qsc->qsc_buf_dmamap, 0,
 	    qsc->qsc_buf_dmamap->dm_mapsize,
 	    BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
 	return 0;
+}
 int
 qat_crypto_load_iv(struct qat_sym_cookie *qsc, struct cryptop *crp,
     struct cryptodesc *crde, struct qat_crypto_desc const *desc)
+{
 	uint32_t rand;
 	uint32_t ivlen = desc->qcd_cipher_blk_sz;
 	int i;
 	if (crde->crd_flags & CRD_F_IV_EXPLICIT) {
 		memcpy(qsc->qsc_iv_buf, crde->crd_iv, ivlen);
 	} else {
 		if (crde->crd_flags & CRD_F_ENCRYPT) {
 			for (i = 0; i + sizeof(rand) <= ivlen;
 			    i += sizeof(rand)) {
 				rand = cprng_fast32();
 				memcpy(qsc->qsc_iv_buf + i, &rand, sizeof(rand));
+			}
 			if (sizeof(qsc->qsc_iv_buf) % sizeof(rand) != 0) {
 				rand = cprng_fast32();
 				memcpy(qsc->qsc_iv_buf + i, &rand,
 				       sizeof(qsc->qsc_iv_buf) - i);
+			}
 		} else if (crp->crp_flags & CRYPTO_F_IMBUF) {
 			/* get iv from buf */
 			m_copydata(qsc->qsc_buf, crde->crd_inject, ivlen,
 			    qsc->qsc_iv_buf);
 		} else if (crp->crp_flags & CRYPTO_F_IOV) {
 			cuio_copydata(qsc->qsc_buf, crde->crd_inject, ivlen,
 			    qsc->qsc_iv_buf);
+		}
+	}
 	if ((crde->crd_flags & CRD_F_ENCRYPT) != 0 &&
 	    (crde->crd_flags & CRD_F_IV_PRESENT) == 0) {
 		if (crp->crp_flags & CRYPTO_F_IMBUF) {
 			m_copyback(qsc->qsc_buf, crde->crd_inject, ivlen,
 			    qsc->qsc_iv_buf);
 		} else if (crp->crp_flags & CRYPTO_F_IOV) {
 			cuio_copyback(qsc->qsc_buf, crde->crd_inject, ivlen,
 			    qsc->qsc_iv_buf);
+		}
+	}
 	return 0;
+}
 static inline struct qat_crypto_bank *
 qat_crypto_select_bank(struct qat_crypto *qcy)
+{
 	u_int cpuid = cpu_index(curcpu());
 	return &qcy->qcy_banks[cpuid % qcy->qcy_num_banks];
+}
 int
 qat_crypto_process(void *arg, struct cryptop *crp, int hint)
+{
 	struct qat_crypto *qcy = arg;
 	struct qat_crypto_bank *qcb;
 	struct qat_session *qs = NULL;
 	struct qat_crypto_desc const *desc;
 	struct qat_sym_cookie *qsc = NULL;
 	struct qat_sym_bulk_cookie *qsbc;
 	struct cryptodesc *crd, *crda = NULL, *crde = NULL;
 	bus_addr_t icv_paddr = 0;
 	int error, icv_offset = -1;
 	uint8_t icv_buf[CRYPTO_MAX_MAC_LEN];
 	qs = qcy->qcy_sessions[CRYPTO_SESID2LID(crp->crp_sid)];
 	mutex_spin_enter(&qs->qs_session_mtx);
 	KASSERT(qs->qs_status & QAT_SESSION_STATUS_ACTIVE);
 	qs->qs_inflight++;
 	mutex_spin_exit(&qs->qs_session_mtx);
 	qcb = qat_crypto_select_bank(qcy);
 	qsc = qat_crypto_alloc_sym_cookie(qcb);
 	if (qsc == NULL) {
 		error = ENOBUFS;
 		goto fail;
+	}
 	error = 0;
 	desc = &qs->qs_dec_desc;
 	crd = crp->crp_desc;
 	while (crd != NULL) {
 		switch (crd->crd_alg) {
 		case CRYPTO_DES_CBC:
 		case CRYPTO_3DES_CBC:
 		case CRYPTO_AES_CBC:
 			if (crde != NULL)
 				error = EINVAL;
 			if (crd->crd_flags & CRD_F_ENCRYPT) {
 				/* use encrypt desc */
 				desc = &qs->qs_enc_desc;
 				if (crda != NULL)
 					error = ENOTSUP;
+			}
 			crde = crd;
 			break;
 		case CRYPTO_MD5_HMAC_96:
 		case CRYPTO_SHA1_HMAC_96:
 		case CRYPTO_SHA2_256_HMAC:
 		case CRYPTO_SHA2_384_HMAC:
 		case CRYPTO_SHA2_512_HMAC:
 			if (crda != NULL)
 				error = EINVAL;
 			if (crde != NULL &&
 			    (crde->crd_flags & CRD_F_ENCRYPT) == 0)
 				error = EINVAL;
 			crda = crd;
 			icv_offset = crd->crd_inject;
 			break;
+		}
 		if (error)
 			goto fail;
 		crd = crd->crd_next;
+	}
 	qsc->qsc_buf = crp->crp_buf;
 	if (crde != NULL) {
 		error = qat_crypto_load_iv(qsc, crp, crde, desc);
 		if (error)
 			goto fail;
+	}
 	error = qat_crypto_load_buf(qcy->qcy_sc, crp, qsc, desc, icv_buf,
 	    icv_offset, &icv_paddr);
 	if (error)
 		goto fail;
 	qsbc = &qsc->u.qsc_bulk_cookie;
 	qsbc->qsbc_crypto = qcy;
 	qsbc->qsbc_session = qs;
 	qsbc->qsbc_cb_tag = crp;
 	qcy->qcy_sc->sc_hw.qhw_crypto_setup_req_params(qcb, qs, desc, qsc,
 	    crde, crda, icv_paddr);
 	bus_dmamap_sync(qcy->qcy_sc->sc_dmat, *qsc->qsc_self_dmamap, 0,
 	    offsetof(struct qat_sym_cookie, qsc_self_dmamap),
 	    BUS_DMASYNC_PREWRITE);
 	error = qat_etr_put_msg(qcy->qcy_sc, qcb->qcb_sym_tx,
 	    (uint32_t *)qsbc->qsbc_msg);
 	if (error)
 		goto fail;
 	return 0;
 fail:
 	if (qsc)
 		qat_crypto_free_sym_cookie(qcb, qsc);
 	mutex_spin_enter(&qs->qs_session_mtx);
 	qs->qs_inflight--;
 	qat_crypto_check_free_session(qcy, qs);
 	crp->crp_etype = error;
 	crypto_done(crp);
 	return 0;
+}
 int
 qat_crypto_setup_ring(struct qat_softc *sc, struct qat_crypto_bank *qcb)
+{
 	int error, i, bank;
 	int curname = 0;
 	char *name;
 	bank = qcb->qcb_bank;
 	name = qcb->qcb_ring_names[curname++];
 	snprintf(name, QAT_RING_NAME_SIZE, "bank%d sym_tx", bank);
 	error = qat_etr_setup_ring(sc, qcb->qcb_bank,
 	    sc->sc_hw.qhw_ring_sym_tx, QAT_NSYMREQ, sc->sc_hw.qhw_fw_req_size,
 	    NULL, NULL, name, &qcb->qcb_sym_tx);
 	if (error)
 		return error;
 	name = qcb->qcb_ring_names[curname++];
 	snprintf(name, QAT_RING_NAME_SIZE, "bank%d sym_rx", bank);
 	error = qat_etr_setup_ring(sc, qcb->qcb_bank,
 	    sc->sc_hw.qhw_ring_sym_rx, QAT_NSYMREQ, sc->sc_hw.qhw_fw_resp_size,
 	    qat_crypto_sym_rxintr, qcb, name, &qcb->qcb_sym_rx);
 	if (error)
 		return error;
 	for (i = 0; i < QAT_NSYMCOOKIE; i++) {
 		struct qat_dmamem *qdm = &qcb->qcb_symck_dmamems[i];
 		struct qat_sym_cookie *qsc;
 		error = qat_alloc_dmamem(sc, qdm, sizeof(struct qat_sym_cookie),
 		    QAT_OPTIMAL_ALIGN);
 		if (error)
 			return error;
 		qsc = qdm->qdm_dma_vaddr;
 		qsc->qsc_self_dmamap = &qdm->qdm_dma_map;
 		qsc->qsc_bulk_req_params_buf_paddr =
 		    qdm->qdm_dma_seg.ds_addr + offsetof(struct qat_sym_cookie,
 		    u.qsc_bulk_cookie.qsbc_req_params_buf);
 		qsc->qsc_buffer_list_desc_paddr =
 		    qdm->qdm_dma_seg.ds_addr + offsetof(struct qat_sym_cookie,
 		    qsc_buf_list);
 		qsc->qsc_iv_buf_paddr =
 		    qdm->qdm_dma_seg.ds_addr + offsetof(struct qat_sym_cookie,
 		    qsc_iv_buf);
 		qcb->qcb_symck_free[i] = qsc;
 		qcb->qcb_symck_free_count++;
 		error = bus_dmamap_create(sc->sc_dmat, QAT_MAXLEN,
 		    QAT_MAXSEG, MCLBYTES, 0, 0, &qsc->qsc_buf_dmamap);
 		if (error)
 			return error;
+	}
 	return 0;
+}
 int
 qat_crypto_bank_init(struct qat_softc *sc, struct qat_crypto_bank *qcb)
+{
 	int error;
 	mutex_init(&qcb->qcb_bank_mtx, MUTEX_DEFAULT, IPL_NET);
 	QAT_EVCNT_ATTACH(sc, &qcb->qcb_ev_no_symck, EVCNT_TYPE_MISC,
 	    qcb->qcb_ev_no_symck_name, "crypto no_symck");
 	error = qat_crypto_setup_ring(sc, qcb);
 	if (error)
 		return error;
 	return 0;
+}
 int
 qat_crypto_init(struct qat_softc *sc)
+{
 	struct qat_crypto *qcy = &sc->sc_crypto;
 	int error, bank, i;
 	int num_banks;
 	qcy->qcy_sc = sc;
 	if (sc->sc_hw.qhw_init_arb != NULL)
 		num_banks = uimin(ncpu, sc->sc_hw.qhw_num_banks);
 	else
 		num_banks = sc->sc_ae_num;
 	qcy->qcy_num_banks = num_banks;
 	qcy->qcy_banks =
 	    qat_alloc_mem(sizeof(struct qat_crypto_bank) * num_banks);
 	for (bank = 0; bank < num_banks; bank++) {
 		struct qat_crypto_bank *qcb = &qcy->qcy_banks[bank];
 		qcb->qcb_bank = bank;
 		qcb->qcb_crypto = qcy;
 		error = qat_crypto_bank_init(sc, qcb);
 		if (error)
 			return error;
+	}
 	mutex_init(&qcy->qcy_crypto_mtx, MUTEX_DEFAULT, IPL_NET);
 	for (i = 0; i < QAT_NSESSION; i++) {
 		struct qat_dmamem *qdm = &qcy->qcy_session_dmamems[i];
 		struct qat_session *qs;
 		error = qat_alloc_dmamem(sc, qdm, sizeof(struct qat_session),
 		    QAT_OPTIMAL_ALIGN);
 		if (error)
 			return error;
 		qs = qdm->qdm_dma_vaddr;
 		qs->qs_lid = i;
 		qs->qs_dec_desc.qcd_desc_paddr = qdm->qdm_dma_seg.ds_addr;
 		qs->qs_dec_desc.qcd_hash_state_paddr =
 		    qs->qs_dec_desc.qcd_desc_paddr +
 		    offsetof(struct qat_crypto_desc, qcd_hash_state_prefix_buf);
 		qs->qs_enc_desc.qcd_desc_paddr = qdm->qdm_dma_seg.ds_addr +
 		    offsetof(struct qat_session, qs_enc_desc);
 		qs->qs_enc_desc.qcd_hash_state_paddr =
 		    qs->qs_enc_desc.qcd_desc_paddr +
 		    offsetof(struct qat_crypto_desc, qcd_hash_state_prefix_buf);
 		mutex_init(&qs->qs_session_mtx, MUTEX_DEFAULT, IPL_NET);
 		qcy->qcy_sessions[i] = qs;
 		qcy->qcy_session_free[i] = qs;
 		qcy->qcy_session_free_count++;
+	}
 	QAT_EVCNT_ATTACH(sc, &qcy->qcy_ev_new_sess, EVCNT_TYPE_MISC,
 	    qcy->qcy_ev_new_sess_name, "crypto new_sess");
 	QAT_EVCNT_ATTACH(sc, &qcy->qcy_ev_free_sess, EVCNT_TYPE_MISC,
 	    qcy->qcy_ev_free_sess_name, "crypto free_sess");
 	QAT_EVCNT_ATTACH(sc, &qcy->qcy_ev_no_sess, EVCNT_TYPE_MISC,
 	    qcy->qcy_ev_no_sess_name, "crypto no_sess");
 	return 0;
+}
 int
 qat_crypto_new_session(void *arg, uint32_t *lid, struct cryptoini *cri)
+{
 	struct qat_crypto *qcy = arg;
 	struct qat_session *qs = NULL;
 	struct cryptoini *crie = NULL;
 	struct cryptoini *cria = NULL;
 	int slice, error;
 	mutex_spin_enter(&qcy->qcy_crypto_mtx);
 	if (qcy->qcy_session_free_count == 0) {
 		QAT_EVCNT_INCR(&qcy->qcy_ev_no_sess);
 		mutex_spin_exit(&qcy->qcy_crypto_mtx);
 		return ENOBUFS;
+	}
 	qs = qcy->qcy_session_free[--qcy->qcy_session_free_count];
 	QAT_EVCNT_INCR(&qcy->qcy_ev_new_sess);
 	mutex_spin_exit(&qcy->qcy_crypto_mtx);
 	qs->qs_status = QAT_SESSION_STATUS_ACTIVE;
 	qs->qs_inflight = 0;
 	*lid = qs->qs_lid;
 	error = 0;
 	while (cri) {
 		switch (cri->cri_alg) {
 		case CRYPTO_DES_CBC:
 		case CRYPTO_3DES_CBC:
 		case CRYPTO_AES_CBC:
 			if (crie != NULL)
 				error = EINVAL;
 			crie = cri;
 			break;
 		case CRYPTO_MD5_HMAC_96:
 		case CRYPTO_SHA1_HMAC_96:
 		case CRYPTO_SHA2_256_HMAC:
 		case CRYPTO_SHA2_384_HMAC:
 		case CRYPTO_SHA2_512_HMAC:
 			if (cria != NULL)
 				error = EINVAL;
 			cria = cri;
 			break;
 		default:
 			error = EINVAL;
+		}
 		if (error)
 			goto fail;
 		cri = cri->cri_next;
+	}
 	slice = 1;
 	if (crie != NULL && cria != NULL) {
 		slice = 2;
 		/* auth then decrypt */
 		qs->qs_dec_desc.qcd_slices[0] = FW_SLICE_AUTH;
 		qs->qs_dec_desc.qcd_slices[1] = FW_SLICE_CIPHER;
 		qs->qs_dec_desc.qcd_cipher_dir = HW_CIPHER_DECRYPT;
 		qs->qs_dec_desc.qcd_cmd_id = FW_LA_CMD_HASH_CIPHER;
 		/* encrypt then auth */
 		qs->qs_enc_desc.qcd_slices[0] = FW_SLICE_CIPHER;
 		qs->qs_enc_desc.qcd_slices[1] = FW_SLICE_AUTH;
 		qs->qs_enc_desc.qcd_cipher_dir = HW_CIPHER_ENCRYPT;
 		qs->qs_enc_desc.qcd_cmd_id = FW_LA_CMD_CIPHER_HASH;
 	} else if (crie != NULL) {
 		/* decrypt */
 		qs->qs_dec_desc.qcd_slices[0] = FW_SLICE_CIPHER;
 		qs->qs_dec_desc.qcd_cipher_dir = HW_CIPHER_DECRYPT;
 		qs->qs_dec_desc.qcd_cmd_id = FW_LA_CMD_CIPHER;
 		/* encrypt */
 		qs->qs_enc_desc.qcd_slices[0] = FW_SLICE_CIPHER;
 		qs->qs_enc_desc.qcd_cipher_dir = HW_CIPHER_ENCRYPT;
 		qs->qs_enc_desc.qcd_cmd_id = FW_LA_CMD_CIPHER;
 	} else if (cria != NULL) {
 		/* auth */
 		qs->qs_dec_desc.qcd_slices[0] = FW_SLICE_AUTH;
 		qs->qs_dec_desc.qcd_cmd_id = FW_LA_CMD_AUTH;
 		/* auth */
 		qs->qs_enc_desc.qcd_slices[0] = FW_SLICE_AUTH;
 		qs->qs_enc_desc.qcd_cmd_id = FW_LA_CMD_AUTH;
 	} else {
 		error = EINVAL;
 		goto fail;
+	}
 	qs->qs_dec_desc.qcd_slices[slice] = FW_SLICE_DRAM_WR;
 	qs->qs_enc_desc.qcd_slices[slice] = FW_SLICE_DRAM_WR;
 	qcy->qcy_sc->sc_hw.qhw_crypto_setup_desc(qcy, qs, &qs->qs_dec_desc, crie, cria);
 	qcy->qcy_sc->sc_hw.qhw_crypto_setup_desc(qcy, qs, &qs->qs_enc_desc, crie, cria);
 	return 0;
 fail:
 	if (qs != NULL) {
 		mutex_spin_enter(&qs->qs_session_mtx);
 		qat_crypto_free_session0(qcy, qs);
+	}
 	return error;
+}
 static inline void
 qat_crypto_clean_desc(struct qat_crypto_desc *desc)
+{
 	explicit_memset(desc->qcd_content_desc, 0,
 	    sizeof(desc->qcd_content_desc));
 	explicit_memset(desc->qcd_hash_state_prefix_buf, 0,
 	    sizeof(desc->qcd_hash_state_prefix_buf));
 	explicit_memset(desc->qcd_req_cache, 0,
 	    sizeof(desc->qcd_req_cache));
+}
 int
 qat_crypto_free_session0(struct qat_crypto *qcy, struct qat_session *qs)
+{
 	qat_crypto_clean_desc(&qs->qs_dec_desc);
 	qat_crypto_clean_desc(&qs->qs_enc_desc);
 	qs->qs_status &= ~QAT_SESSION_STATUS_ACTIVE;
 	mutex_spin_exit(&qs->qs_session_mtx);
 	mutex_spin_enter(&qcy->qcy_crypto_mtx);
 	qcy->qcy_session_free[qcy->qcy_session_free_count++] = qs;
 	QAT_EVCNT_INCR(&qcy->qcy_ev_free_sess);
 	mutex_spin_exit(&qcy->qcy_crypto_mtx);
 	return 0;
+}
 void
 qat_crypto_check_free_session(struct qat_crypto *qcy, struct qat_session *qs)
+{
 	if ((qs->qs_status & QAT_SESSION_STATUS_FREEING) &&
 	    qs->qs_inflight == 0) {
 		qat_crypto_free_session0(qcy, qs);
 	} else {
 		mutex_spin_exit(&qs->qs_session_mtx);
+	}
+}
 int
 qat_crypto_free_session(void *arg, uint64_t sid)
+{
 	struct qat_crypto *qcy = arg;
 	struct qat_session *qs;
 	int error;