 @@ -1,14 +1,14 @@
-/* $NetBSD: if_ti.c,v 1.117 2020/03/05 15:33:13 msaitoh Exp $ */
+/* $NetBSD: if_ti.c,v 1.118 2020/03/05 15:36:39 msaitoh Exp $ */
 /*
  * Copyright (c) 1997, 1998, 1999
  *	Bill Paul <wpaul@ctr.columbia.edu>.  All rights reserved.
+ *
  * Redistribution and use in source and binary forms, with or without
  * modification, are permitted provided that the following conditions
  * are met:
  * 1. Redistributions of source code must retain the above copyright
  *    notice, this list of conditions and the following disclaimer.
  * 2. Redistributions in binary form must reproduce the above copyright
  *    notice, this list of conditions and the following disclaimer in the
  *    documentation and/or other materials provided with the distribution.
 @@ -71,27 +71,27 @@
  * compiling it requires a GNU toolchain targeted for mips-sgi-irix5.3.
+ *
  * The following people deserve special thanks:
  * - Terry Murphy of 3Com, for providing a 3c985 Tigon 1 board
  *   for testing
  * - Raymond Lee of Netgear, for providing a pair of Netgear
  *   GA620 Tigon 2 boards for testing
  * - Ulf Zimmermann, for bringing the GA620 to my attention and
  *   convincing me to write this driver.
  * - Andrew Gallatin for providing FreeBSD/Alpha support.
  */
 #include <sys/cdefs.h>
-__KERNEL_RCSID(0, "$NetBSD: if_ti.c,v 1.117 2020/03/05 15:33:13 msaitoh Exp $");
+__KERNEL_RCSID(0, "$NetBSD: if_ti.c,v 1.118 2020/03/05 15:36:39 msaitoh Exp $");
 #include "opt_inet.h"
 #include <sys/param.h>
 #include <sys/systm.h>
 #include <sys/sockio.h>
 #include <sys/mbuf.h>
 #include <sys/malloc.h>
 #include <sys/kernel.h>
 #include <sys/socket.h>
 #include <sys/queue.h>
 #include <sys/device.h>
 #include <sys/reboot.h>
 @@ -216,27 +216,27 @@ CFATTACH_DECL_NEW(ti, sizeof(struct ti_s
  * Send an instruction or address to the EEPROM, check for ACK.
  */
 static uint32_t
 ti_eeprom_putbyte(struct ti_softc *sc, int byte)
+{
 	int i, ack = 0;
 	/*
 	 * Make sure we're in TX mode.
 	 */
 	TI_SETBIT(sc, TI_MISC_LOCAL_CTL, TI_MLC_EE_TXEN);
 	/*
-	 * Feed in each bit and stobe the clock.
+	 * Feed in each bit and strobe the clock.
 	 */
 	for (i = 0x80; i; i >>= 1) {
 		if (byte & i) {
 			TI_SETBIT(sc, TI_MISC_LOCAL_CTL, TI_MLC_EE_DOUT);
 		} else {
 			TI_CLRBIT(sc, TI_MISC_LOCAL_CTL, TI_MLC_EE_DOUT);
+		}
 		DELAY(1);
 		TI_SETBIT(sc, TI_MISC_LOCAL_CTL, TI_MLC_EE_CLK);
 		DELAY(1);
 		TI_CLRBIT(sc, TI_MISC_LOCAL_CTL, TI_MLC_EE_CLK);
+	}
 @@ -2198,27 +2198,27 @@ ti_stats_update(struct ti_softc *sc)
 	uint64_t collisions =
 	   (sc->ti_rdata->ti_info.ti_stats.dot3StatsSingleCollisionFrames +
 	    sc->ti_rdata->ti_info.ti_stats.dot3StatsMultipleCollisionFrames +
 	    sc->ti_rdata->ti_info.ti_stats.dot3StatsExcessiveCollisions +
 	    sc->ti_rdata->ti_info.ti_stats.dot3StatsLateCollisions);
 	if_statadd(ifp, if_collisions, collisions - sc->ti_if_collisions);
 	sc->ti_if_collisions = collisions;
 	TI_CDSTATSSYNC(sc, BUS_DMASYNC_PREREAD);
+}
 /*
- * Encapsulate an mbuf chain in the tx ring  by coupling the mbuf data
+ * Encapsulate an mbuf chain in the tx ring by coupling the mbuf data
  * pointers to descriptors.
  */
 static int
 ti_encap_tigon1(struct ti_softc *sc, struct mbuf *m_head, uint32_t *txidx)
+{
 	struct ti_tx_desc	*f = NULL;
 	uint32_t		frag, cur, cnt = 0;
 	struct txdmamap_pool_entry *dma;
 	bus_dmamap_t dmamap;
 	int error, i;
 	uint16_t csum_flags = 0;
 	dma = SIMPLEQ_FIRST(&sc->txdma_list);
 @@ -2677,27 +2677,27 @@ ti_ifmedia_sts(struct ifnet *ifp, struct
 		if (media & TI_LNK_FULL_DUPLEX)
 			ifmr->ifm_active |= IFM_FDX;
 		if (media & TI_LNK_HALF_DUPLEX)
 			ifmr->ifm_active |= IFM_HDX;
+	}
 	sc->ethercom.ec_if.if_baudrate =
 	    ifmedia_baudrate(sc->ifmedia.ifm_media);
+}
 static int
 ti_ether_ioctl(struct ifnet *ifp, u_long cmd, void *data)
+{
-	struct ifaddr *ifa = (struct ifaddr *) data;
+	struct ifaddr *ifa = (struct ifaddr *)data;
 	struct ti_softc *sc = ifp->if_softc;
 	if ((ifp->if_flags & IFF_UP) == 0) {
 		ifp->if_flags |= IFF_UP;
 		ti_init(sc);
+	}
 	switch (cmd) {
 	case SIOCINITIFADDR:
 		switch (ifa->ifa_addr->sa_family) {
 #ifdef INET
 		case AF_INET:
 @@ -2710,27 +2710,27 @@ ti_ether_ioctl(struct ifnet *ifp, u_long
 		break;
 	default:
 		return (EINVAL);
+	}
 	return (0);
+}
 static int
 ti_ioctl(struct ifnet *ifp, u_long command, void *data)
+{
 	struct ti_softc		*sc = ifp->if_softc;
-	struct ifreq		*ifr = (struct ifreq *) data;
+	struct ifreq		*ifr = (struct ifreq *)data;
 	int			s, error = 0;
 	struct ti_cmd_desc	cmd;
 	s = splnet();
 	switch (command) {
 	case SIOCINITIFADDR:
 		error = ti_ether_ioctl(ifp, command, data);
 		break;
 	case SIOCSIFMTU:
 		if (ifr->ifr_mtu < ETHERMIN || ifr->ifr_mtu > ETHERMTU_JUMBO)
 			error = EINVAL;
 		else if ((error = ifioctl_common(ifp, command, data))

 @@ -1,14 +1,14 @@
-/* $NetBSD: if_tireg.h,v 1.25 2020/02/29 19:29:38 thorpej Exp $ */
+/* $NetBSD: if_tireg.h,v 1.26 2020/03/05 15:36:39 msaitoh Exp $ */
 /*
  * Copyright (c) 1997, 1998, 1999
  *	Bill Paul <wpaul@ctr.columbia.edu>.  All rights reserved.
+ *
  * Redistribution and use in source and binary forms, with or without
  * modification, are permitted provided that the following conditions
  * are met:
  * 1. Redistributions of source code must retain the above copyright
  *    notice, this list of conditions and the following disclaimer.
  * 2. Redistributions in binary form must reproduce the above copyright
  *    notice, this list of conditions and the following disclaimer in the
  *    documentation and/or other materials provided with the distribution.
 @@ -29,27 +29,27 @@
  * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
  * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
  * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
  * THE POSSIBILITY OF SUCH DAMAGE.
+ *
  *	FreeBSD Id: if_tireg.h,v 1.9 1999/07/27 03:54:48 wpaul Exp
  */
 /*
  * Tigon register offsets. These are memory mapped registers
  * which can be accessed with the CSR_READ_4()/CSR_WRITE_4() macros.
  * Each register must be accessed using 32 bit operations.
+ *
- * All reegisters are accessed through a 16K shared memory block.
+ * All registers are accessed through a 16K shared memory block.
  * The first group of registers are actually copies of the PCI
  * configuration space registers.
  */
 /*
  * Tigon configuration and control registers.
  */
 #define TI_MISC_HOST_CTL		0x040
 #define TI_MISC_LOCAL_CTL		0x044
 #define TI_SEM_AB			0x048 /* Tigon 2 only */
 #define TI_MISC_CONF			0x050 /* Tigon 2 only */
 #define TI_TIMER_BITS			0x054
 #define TI_TIMERREF			0x058