 @@ -1,14 +1,14 @@
-/* $NetBSD: armreg.h,v 1.36 2020/02/29 21:29:23 ryo Exp $ */
+/* $NetBSD: armreg.h,v 1.37 2020/03/06 20:13:24 ryo Exp $ */
 /*-
  * Copyright (c) 2014 The NetBSD Foundation, Inc.
  * All rights reserved.
+ *
  * This code is derived from software contributed to The NetBSD Foundation
  * by Matt Thomas of 3am Software Foundry.
+ *
  * Redistribution and use in source and binary forms, with or without
  * modification, are permitted provided that the following conditions
  * are met:
  * 1. Redistributions of source code must retain the above copyright
  *    notice, this list of conditions and the following disclaimer.
 @@ -86,26 +86,27 @@ reg_##regname##_write(uint64_t __val)
 #define AARCH64REG_ATWRITE_INLINE(regname)			\
 	AARCH64REG_ATWRITE_INLINE2(regname, regname)
 /*
  * System registers available at EL0 (user)
  */
 AARCH64REG_READ_INLINE(ctr_el0)		// Cache Type Register
 #define	CTR_EL0_CWG_LINE	__BITS(27,24)	// Cacheback Writeback Granule
 #define	CTR_EL0_ERG_LINE	__BITS(23,20)	// Exclusives Reservation Granule
 #define	CTR_EL0_DMIN_LINE	__BITS(19,16)	// Dcache MIN LINE size (log2 - 2)
 #define	CTR_EL0_L1IP_MASK	__BITS(15,14)
 #define	 CTR_EL0_L1IP_VPIPT	0		//  VMID-aware Physical Index, Physical Tag
 #define	 CTR_EL0_L1IP_AIVIVT	1		//  ASID-tagged Virtual Index, Virtual Tag
 #define	 CTR_EL0_L1IP_VIPT	2		//  Virtual Index, Physical Tag
 #define	 CTR_EL0_L1IP_PIPT	3		//  Physical Index, Physical Tag
 #define	CTR_EL0_IMIN_LINE	__BITS(3,0)	// Icache MIN LINE size (log2 - 2)
 AARCH64REG_READ_INLINE(dczid_el0)	// Data Cache Zero ID Register
 #define	DCZID_DZP		__BIT(4)	// Data Zero Prohibited
 #define	DCZID_BS		__BITS(3,0)	// Block Size (log2 - 2)
 AARCH64REG_READ_INLINE(fpcr)		// Floating Point Control Register
 AARCH64REG_WRITE_INLINE(fpcr)
 @@ -162,80 +163,121 @@ AARCH64REG_READ_INLINE(tpidrro_el0)	// T
  */
 /*
  * These are readonly registers
  */
 AARCH64REG_READ_INLINE(aidr_el1)
 AARCH64REG_READ_INLINE2(cbar_el1, s3_1_c15_c3_0)	// Cortex-A57
 #define	CBAR_PA			__BITS(47,18)
 AARCH64REG_READ_INLINE(ccsidr_el1)
-#define	CCSIDR_WT		__BIT(31)	// Write-through supported
+#define	CCSIDR_WT		__BIT(31)	// OBSOLETE: Write-through supported
-#define	CCSIDR_WB		__BIT(30)	// Write-back supported
+#define	CCSIDR_WB		__BIT(30)	// OBSOLETE: Write-back supported
-#define	CCSIDR_RA		__BIT(29)	// Read-allocation supported
+#define	CCSIDR_RA		__BIT(29)	// OBSOLETE: Read-allocation supported
-#define	CCSIDR_WA		__BIT(28)	// Write-allocation supported
+#define	CCSIDR_WA		__BIT(28)	// OBSOLETE: Write-allocation supported
 #define	CCSIDR_NUMSET		__BITS(27,13)	// (Number of sets in cache) - 1
 #define	CCSIDR_ASSOC		__BITS(12,3)	// (Associativity of cache) - 1
 #define	CCSIDR_LINESIZE 	__BITS(2,0)	// Number of bytes in cache line
 AARCH64REG_READ_INLINE(clidr_el1)
 #define	CLIDR_ICB		__BITS(32,30)	// Inner cache boundary
 #define	CLIDR_LOUU		__BITS(29,27)	// Level of Unification Uniprocessor
 #define	CLIDR_LOC		__BITS(26,24)	// Level of Coherency
 #define	CLIDR_LOUIS		__BITS(23,21)	// Level of Unification InnerShareable*/
 #define	CLIDR_CTYPE7		__BITS(20,18)	// Cache Type field for level7
 #define	CLIDR_CTYPE6		__BITS(17,15)	// Cache Type field for level6
 #define	CLIDR_CTYPE5		__BITS(14,12)	// Cache Type field for level5
 #define	CLIDR_CTYPE4		__BITS(11,9)	// Cache Type field for level4
 #define	CLIDR_CTYPE3		__BITS(8,6)	// Cache Type field for level3
 #define	CLIDR_CTYPE2		__BITS(5,3)	// Cache Type field for level2
 #define	CLIDR_CTYPE1		__BITS(2,0)	// Cache Type field for level1
 #define	 CLIDR_TYPE_NOCACHE	 0		//  No cache
 #define	 CLIDR_TYPE_ICACHE	 1		//  Instruction cache only
 #define	 CLIDR_TYPE_DCACHE	 2		//  Data cache only
 #define	 CLIDR_TYPE_IDCACHE	 3		//  Separate inst and data caches
 #define	 CLIDR_TYPE_UNIFIEDCACHE 4		//  Unified cache
 AARCH64REG_READ_INLINE(currentel)
 AARCH64REG_READ_INLINE(id_aa64afr0_el1)
 AARCH64REG_READ_INLINE(id_aa64afr1_el1)
 AARCH64REG_READ_INLINE(id_aa64dfr0_el1)
 #define	ID_AA64DFR0_EL1_TRACEFILT	__BITS(43,40)
 #define	 ID_AA64DFR0_EL1_TRACEFILT_NONE	 0
 #define	 ID_AA64DFR0_EL1_TRACEFILT_IMPL	 1
 #define	ID_AA64DFR0_EL1_DBLLOCK		__BITS(39,36
 #define	 ID_AA64DFR0_EL1_DBLLOCK_IMPL	 0
 #define	 ID_AA64DFR0_EL1_DBLLOCK_NONE	 15
 #define	ID_AA64DFR0_EL1_PMSVER		__BITS(35,32)
 #define	ID_AA64DFR0_EL1_CTX_CMPS	__BITS(31,28)
 #define	ID_AA64DFR0_EL1_WRPS		__BITS(20,23)
 #define	ID_AA64DFR0_EL1_BRPS		__BITS(12,15)
 #define	ID_AA64DFR0_EL1_PMUVER		__BITS(8,11)
 #define	 ID_AA64DFR0_EL1_PMUVER_NONE	 0
 #define	 ID_AA64DFR0_EL1_PMUVER_V3	 1
 #define	 ID_AA64DFR0_EL1_PMUVER_NOV3	 2
 #define	ID_AA64DFR0_EL1_TRACEVER	__BITS(4,7)
 #define	 ID_AA64DFR0_EL1_TRACEVER_NONE	 0
 #define	 ID_AA64DFR0_EL1_TRACEVER_IMPL	 1
 #define	ID_AA64DFR0_EL1_DEBUGVER	__BITS(0,3)
 #define	 ID_AA64DFR0_EL1_DEBUGVER_V8A	 6
 AARCH64REG_READ_INLINE(id_aa64dfr1_el1)
 AARCH64REG_READ_INLINE(id_aa64isar0_el1)
 #define	ID_AA64ISAR0_EL1_RNDR		__BITS(63,30)
 #define	 ID_AA64ISAR0_EL1_RNDR_NONE	 0
 #define	 ID_AA64ISAR0_EL1_RNDR_RNDRRS	 1
 #define	ID_AA64ISAR0_EL1_TLB		__BITS(59,56)
 #define	 ID_AA64ISAR0_EL1_TLB_NONE	 0
 #define	 ID_AA64ISAR0_EL1_TLB_OS	 1
 #define	 ID_AA64ISAR0_EL1_TLB_OS_TLB	 2
 #define	ID_AA64ISAR0_EL1_TS		__BITS(55,52)
 #define	 ID_AA64ISAR0_EL1_TS_NONE	 0
 #define	 ID_AA64ISAR0_EL1_TS_CFINV	 1
 #define	 ID_AA64ISAR0_EL1_TS_AXFLAG	 2
 #define	ID_AA64ISAR0_EL1_FHM		__BITS(51,48)
 #define	 ID_AA64ISAR0_EL1_FHM_NONE	 0
 #define	 ID_AA64ISAR0_EL1_FHM_FMLAL	 1
 #define	ID_AA64ISAR0_EL1_DP		__BITS(47,44)
 #define	 ID_AA64ISAR0_EL1_DP_NONE	 0
 #define	 ID_AA64ISAR0_EL1_DP_UDOT	 1
 #define	ID_AA64ISAR0_EL1_SM4		__BITS(43,40)
 #define	 ID_AA64ISAR0_EL1_SM4_NONE	 0
 #define	 ID_AA64ISAR0_EL1_SM4_SM4	 1
 #define	ID_AA64ISAR0_EL1_SM3		__BITS(39,36)
 #define	 ID_AA64ISAR0_EL1_SM3_NONE	 0
 #define	 ID_AA64ISAR0_EL1_SM3_SM3	 1
 #define	ID_AA64ISAR0_EL1_SHA3		__BITS(35,32)
 #define	 ID_AA64ISAR0_EL1_SHA3_NONE	 0
 #define	 ID_AA64ISAR0_EL1_SHA3_EOR3	 1
 #define	ID_AA64ISAR0_EL1_RDM		__BITS(31,28)
 #define	 ID_AA64ISAR0_EL1_RDM_NONE	 0
 #define	 ID_AA64ISAR0_EL1_RDM_SQRDML	 1
 #define	ID_AA64ISAR0_EL1_ATOMIC		__BITS(23,20)
 #define	 ID_AA64ISAR0_EL1_ATOMIC_NONE	 0
 #define	 ID_AA64ISAR0_EL1_ATOMIC_SWP	 1
 #define	ID_AA64ISAR0_EL1_CRC32		__BITS(19,16)
 #define	 ID_AA64ISAR0_EL1_CRC32_NONE	 0
 #define	 ID_AA64ISAR0_EL1_CRC32_CRC32X	 1
 #define	ID_AA64ISAR0_EL1_SHA2		__BITS(15,12)
 #define	 ID_AA64ISAR0_EL1_SHA2_NONE	 0
 #define	 ID_AA64ISAR0_EL1_SHA2_SHA256HSU 1
 #define	 ID_AA64ISAR0_EL1_SHA2_SHA512HSU 2
 #define	ID_AA64ISAR0_EL1_SHA1		__BITS(11,8)
 #define	 ID_AA64ISAR0_EL1_SHA1_NONE	 0
 #define	 ID_AA64ISAR0_EL1_SHA1_SHA1CPMHSU 1
 #define	ID_AA64ISAR0_EL1_AES		__BITS(7,4)
 #define	 ID_AA64ISAR0_EL1_AES_NONE	 0
 #define	 ID_AA64ISAR0_EL1_AES_AES	 1
 #define	 ID_AA64ISAR0_EL1_AES_PMUL	 2
 AARCH64REG_READ_INLINE(id_aa64isar1_el1)
 #define	ID_AA64ISAR1_EL1_SPECRES	__BITS(43,40)
 #define	 ID_AA64ISAR1_EL1_SPECRES_NONE	 0
 #define	 ID_AA64ISAR1_EL1_SPECRES_SUPPORTED 1
 @@ -266,26 +308,27 @@ AARCH64REG_READ_INLINE(id_aa64isar1_el1)
 #define	 ID_AA64ISAR1_EL1_API_SUPPORTED	 1
 #define	 ID_AA64ISAR1_EL1_API_ENHANCED	 2
 #define	ID_AA64ISAR1_EL1_APA		__BITS(7,4)
 #define	 ID_AA64ISAR1_EL1_APA_NONE	 0
 #define	 ID_AA64ISAR1_EL1_APA_QARMA	 1
 #define	 ID_AA64ISAR1_EL1_APA_QARMA_ENH	 2
 #define	ID_AA64ISAR1_EL1_DPB		__BITS(3,0)
 #define	 ID_AA64ISAR1_EL1_DPB_NONE	 0
 #define	 ID_AA64ISAR1_EL1_DPB_CVAP	 1
 #define	 ID_AA64ISAR1_EL1_DPB_CVAP_CVADP 2
 AARCH64REG_READ_INLINE(id_aa64mmfr0_el1)
 #define	ID_AA64MMFR0_EL1_EXS		__BITS(43,40)
 #define	ID_AA64MMFR0_EL1_TGRAN4		__BITS(31,28)
 #define	 ID_AA64MMFR0_EL1_TGRAN4_4KB	 0
 #define	 ID_AA64MMFR0_EL1_TGRAN4_NONE	 15
 #define	ID_AA64MMFR0_EL1_TGRAN64	__BITS(24,27)
 #define	 ID_AA64MMFR0_EL1_TGRAN64_64KB	 0
 #define	 ID_AA64MMFR0_EL1_TGRAN64_NONE	 15
 #define	ID_AA64MMFR0_EL1_TGRAN16	__BITS(20,23)
 #define	 ID_AA64MMFR0_EL1_TGRAN16_NONE	 0
 #define	 ID_AA64MMFR0_EL1_TGRAN16_16KB	 1
 #define	ID_AA64MMFR0_EL1_BIGENDEL0	__BITS(16,19)
 #define	 ID_AA64MMFR0_EL1_BIGENDEL0_NONE 0
 #define	 ID_AA64MMFR0_EL1_BIGENDEL0_MIX	 1
 #define	ID_AA64MMFR0_EL1_SNSMEM		__BITS(12,15)
 @@ -294,26 +337,27 @@ AARCH64REG_READ_INLINE(id_aa64mmfr0_el1)
 #define	ID_AA64MMFR0_EL1_BIGEND		__BITS(8,11)
 #define	 ID_AA64MMFR0_EL1_BIGEND_NONE	 0
 #define	 ID_AA64MMFR0_EL1_BIGEND_MIX	 1
 #define	ID_AA64MMFR0_EL1_ASIDBITS	__BITS(4,7)
 #define	 ID_AA64MMFR0_EL1_ASIDBITS_8BIT	 0
 #define	 ID_AA64MMFR0_EL1_ASIDBITS_16BIT 2
 #define	ID_AA64MMFR0_EL1_PARANGE	__BITS(0,3)
 #define	 ID_AA64MMFR0_EL1_PARANGE_4G	 0
 #define	 ID_AA64MMFR0_EL1_PARANGE_64G	 1
 #define	 ID_AA64MMFR0_EL1_PARANGE_1T	 2
 #define	 ID_AA64MMFR0_EL1_PARANGE_4T	 3
 #define	 ID_AA64MMFR0_EL1_PARANGE_16T	 4
 #define	 ID_AA64MMFR0_EL1_PARANGE_256T	 5
 #define	 ID_AA64MMFR0_EL1_PARANGE_4P	 6
 AARCH64REG_READ_INLINE(id_aa64mmfr1_el1)
 #define	ID_AA64MMFR1_EL1_XNX		__BITS(31,28)
 #define	 ID_AA64MMFR1_EL1_XNX_NONE	 0
 #define	 ID_AA64MMFR1_EL1_XNX_SUPPORTED	 1
 #define	ID_AA64MMFR1_EL1_SPECSEI	__BITS(27,24)
 #define	 ID_AA64MMFR1_EL1_SPECSEI_NONE	 0
 #define	 ID_AA64MMFR1_EL1_SPECSEI_EXTINT 1
 #define	ID_AA64MMFR1_EL1_PAN		__BITS(23,20)
 #define	 ID_AA64MMFR1_EL1_PAN_NONE	 0
 #define	 ID_AA64MMFR1_EL1_PAN_SUPPORTED	 1
 #define	 ID_AA64MMFR1_EL1_PAN_S1E1	 2
 @@ -1178,35 +1222,44 @@ AARCH64REG_READ_INLINE(cntv_ctl_el0)
 AARCH64REG_WRITE_INLINE(cntv_ctl_el0)
 AARCH64REG_READ_INLINE(cntv_cval_el0)
 AARCH64REG_WRITE_INLINE(cntv_cval_el0)
 AARCH64REG_READ_INLINE(cntv_tval_el0)
 AARCH64REG_WRITE_INLINE(cntv_tval_el0)
 AARCH64REG_READ_INLINE(cntvct_el0)
 AARCH64REG_WRITE_INLINE(cntvct_el0)
 #define	CNTCTL_ISTATUS		__BIT(2)	// Interrupt Asserted
 #define	CNTCTL_IMASK		__BIT(1)	// Timer Interrupt is Masked
 #define	CNTCTL_ENABLE		__BIT(0)	// Timer Enabled
 // ID_AA64PFR0_EL1: AArch64 Processor Feature Register 0
 #define	ID_AA64PFR0_EL1_SVE		__BITS(35,32) // Scalable Vector
 #define	 ID_AA64PFR0_EL1_SVE_NONE	 0
 #define	 ID_AA64PFR0_EL1_SVE_IMPL	 1
 #define	ID_AA64PFR0_EL1_RAS		__BITS(31,28) // RAS Extension
 #define	 ID_AA64PFR0_EL1_RAS_NONE	 0
 #define	 ID_AA64PFR0_EL1_RAS_IMPL	 1
 #define	 ID_AA64PFR0_EL1_RAS_ERX	 2
 #define	ID_AA64PFR0_EL1_GIC		__BITS(24,27) // GIC CPU IF
 #define	ID_AA64PFR0_EL1_GIC_SHIFT	24
 #define	 ID_AA64PFR0_EL1_GIC_CPUIF_EN	 1
 #define	 ID_AA64PFR0_EL1_GIC_CPUIF_NONE	 0
 #define	ID_AA64PFR0_EL1_ADVSIMD		__BITS(23,20) // SIMD
 #define	 ID_AA64PFR0_EL1_ADV_SIMD_IMPL	 0x0
 #define	 ID_AA64PFR0_EL1_ADV_SIMD_HP	 0x1
 #define	 ID_AA64PFR0_EL1_ADV_SIMD_NONE	 0xf
 #define	ID_AA64PFR0_EL1_FP		__BITS(19,16) // FP
 #define	 ID_AA64PFR0_EL1_FP_IMPL	 0x0
 #define	 ID_AA64PFR0_EL1_FP_HP		 0x1
 #define	 ID_AA64PFR0_EL1_FP_NONE	 0xf
 #define	ID_AA64PFR0_EL1_EL3		__BITS(15,12) // EL3 handling
 #define	 ID_AA64PFR0_EL1_EL3_NONE	 0
 #define	 ID_AA64PFR0_EL1_EL3_64		 1
 #define	 ID_AA64PFR0_EL1_EL3_64_32	 2
 #define	ID_AA64PFR0_EL1_EL2		__BITS(11,8) // EL2 handling
 #define	 ID_AA64PFR0_EL1_EL2_NONE	 0
 #define	 ID_AA64PFR0_EL1_EL2_64	 	 1
 #define	 ID_AA64PFR0_EL1_EL2_64_32	 2
 #define	ID_AA64PFR0_EL1_EL1		__BITS(7,4) // EL1 handling
 #define	 ID_AA64PFR0_EL1_EL1_64	 	 1
 #define	 ID_AA64PFR0_EL1_EL1_64_32	 2
 #define	ID_AA64PFR0_EL1_EL0		__BITS(3,0) // EL0 handling