Fri Mar 6 20:28:26 2020 UTC ()
fix missing paren


(ryo)
diff -r1.37 -r1.38 src/sys/arch/aarch64/include/armreg.h
cvs diff -r1.37 -r1.38 src/sys/arch/aarch64/include/armreg.h (expand / switch to unified diff)

--- src/sys/arch/aarch64/include/armreg.h 2020/03/06 20:13:24 1.37
+++ src/sys/arch/aarch64/include/armreg.h 2020/03/06 20:28:26 1.38
@@ -1,14 +1,14 @@ @@ -1,14 +1,14 @@
1/* $NetBSD: armreg.h,v 1.37 2020/03/06 20:13:24 ryo Exp $ */ 1/* $NetBSD: armreg.h,v 1.38 2020/03/06 20:28:26 ryo Exp $ */
2 2
3/*- 3/*-
4 * Copyright (c) 2014 The NetBSD Foundation, Inc. 4 * Copyright (c) 2014 The NetBSD Foundation, Inc.
5 * All rights reserved. 5 * All rights reserved.
6 * 6 *
7 * This code is derived from software contributed to The NetBSD Foundation 7 * This code is derived from software contributed to The NetBSD Foundation
8 * by Matt Thomas of 3am Software Foundry. 8 * by Matt Thomas of 3am Software Foundry.
9 * 9 *
10 * Redistribution and use in source and binary forms, with or without 10 * Redistribution and use in source and binary forms, with or without
11 * modification, are permitted provided that the following conditions 11 * modification, are permitted provided that the following conditions
12 * are met: 12 * are met:
13 * 1. Redistributions of source code must retain the above copyright 13 * 1. Redistributions of source code must retain the above copyright
14 * notice, this list of conditions and the following disclaimer. 14 * notice, this list of conditions and the following disclaimer.
@@ -198,27 +198,27 @@ AARCH64REG_READ_INLINE(clidr_el1) @@ -198,27 +198,27 @@ AARCH64REG_READ_INLINE(clidr_el1)
198#define CLIDR_TYPE_ICACHE 1 // Instruction cache only 198#define CLIDR_TYPE_ICACHE 1 // Instruction cache only
199#define CLIDR_TYPE_DCACHE 2 // Data cache only 199#define CLIDR_TYPE_DCACHE 2 // Data cache only
200#define CLIDR_TYPE_IDCACHE 3 // Separate inst and data caches 200#define CLIDR_TYPE_IDCACHE 3 // Separate inst and data caches
201#define CLIDR_TYPE_UNIFIEDCACHE 4 // Unified cache 201#define CLIDR_TYPE_UNIFIEDCACHE 4 // Unified cache
202 202
203AARCH64REG_READ_INLINE(currentel) 203AARCH64REG_READ_INLINE(currentel)
204AARCH64REG_READ_INLINE(id_aa64afr0_el1) 204AARCH64REG_READ_INLINE(id_aa64afr0_el1)
205AARCH64REG_READ_INLINE(id_aa64afr1_el1) 205AARCH64REG_READ_INLINE(id_aa64afr1_el1)
206AARCH64REG_READ_INLINE(id_aa64dfr0_el1) 206AARCH64REG_READ_INLINE(id_aa64dfr0_el1)
207 207
208#define ID_AA64DFR0_EL1_TRACEFILT __BITS(43,40) 208#define ID_AA64DFR0_EL1_TRACEFILT __BITS(43,40)
209#define ID_AA64DFR0_EL1_TRACEFILT_NONE 0 209#define ID_AA64DFR0_EL1_TRACEFILT_NONE 0
210#define ID_AA64DFR0_EL1_TRACEFILT_IMPL 1 210#define ID_AA64DFR0_EL1_TRACEFILT_IMPL 1
211#define ID_AA64DFR0_EL1_DBLLOCK __BITS(39,36 211#define ID_AA64DFR0_EL1_DBLLOCK __BITS(39,36)
212#define ID_AA64DFR0_EL1_DBLLOCK_IMPL 0 212#define ID_AA64DFR0_EL1_DBLLOCK_IMPL 0
213#define ID_AA64DFR0_EL1_DBLLOCK_NONE 15 213#define ID_AA64DFR0_EL1_DBLLOCK_NONE 15
214#define ID_AA64DFR0_EL1_PMSVER __BITS(35,32) 214#define ID_AA64DFR0_EL1_PMSVER __BITS(35,32)
215#define ID_AA64DFR0_EL1_CTX_CMPS __BITS(31,28) 215#define ID_AA64DFR0_EL1_CTX_CMPS __BITS(31,28)
216#define ID_AA64DFR0_EL1_WRPS __BITS(20,23) 216#define ID_AA64DFR0_EL1_WRPS __BITS(20,23)
217#define ID_AA64DFR0_EL1_BRPS __BITS(12,15) 217#define ID_AA64DFR0_EL1_BRPS __BITS(12,15)
218#define ID_AA64DFR0_EL1_PMUVER __BITS(8,11) 218#define ID_AA64DFR0_EL1_PMUVER __BITS(8,11)
219#define ID_AA64DFR0_EL1_PMUVER_NONE 0 219#define ID_AA64DFR0_EL1_PMUVER_NONE 0
220#define ID_AA64DFR0_EL1_PMUVER_V3 1 220#define ID_AA64DFR0_EL1_PMUVER_V3 1
221#define ID_AA64DFR0_EL1_PMUVER_NOV3 2 221#define ID_AA64DFR0_EL1_PMUVER_NOV3 2
222#define ID_AA64DFR0_EL1_TRACEVER __BITS(4,7) 222#define ID_AA64DFR0_EL1_TRACEVER __BITS(4,7)
223#define ID_AA64DFR0_EL1_TRACEVER_NONE 0 223#define ID_AA64DFR0_EL1_TRACEVER_NONE 0
224#define ID_AA64DFR0_EL1_TRACEVER_IMPL 1 224#define ID_AA64DFR0_EL1_TRACEVER_IMPL 1