 @@ -1,14 +1,14 @@
-/*	$NetBSD: if_cas.c,v 1.41 2020/03/01 05:39:05 thorpej Exp $	*/
+/*	$NetBSD: if_cas.c,v 1.42 2020/03/08 03:16:20 thorpej Exp $	*/
 /*	$OpenBSD: if_cas.c,v 1.29 2009/11/29 16:19:38 kettenis Exp $	*/
 /*
+ *
  * Copyright (C) 2007 Mark Kettenis.
  * Copyright (C) 2001 Eduardo Horvath.
  * All rights reserved.
+ *
+ *
  * Redistribution and use in source and binary forms, with or without
  * modification, are permitted provided that the following conditions
  * are met:
  * 1. Redistributions of source code must retain the above copyright
 @@ -34,27 +34,27 @@
 /*
  * Driver for Sun Cassini ethernet controllers.
+ *
  * There are basically two variants of this chip: Cassini and
  * Cassini+.  We can distinguish between the two by revision: 0x10 and
  * up are Cassini+.  The most important difference is that Cassini+
  * has a second RX descriptor ring.  Cassini+ will not work without
  * configuring that second ring.  However, since we don't use it we
  * don't actually fill the descriptors, and only hand off the first
  * four to the chip.
  */
 #include <sys/cdefs.h>
-__KERNEL_RCSID(0, "$NetBSD: if_cas.c,v 1.41 2020/03/01 05:39:05 thorpej Exp $");
+__KERNEL_RCSID(0, "$NetBSD: if_cas.c,v 1.42 2020/03/08 03:16:20 thorpej Exp $");
 #ifndef _MODULE
 #include "opt_inet.h"
 #endif
 #include <sys/param.h>
 #include <sys/systm.h>
 #include <sys/callout.h>
 #include <sys/mbuf.h>
 #include <sys/syslog.h>
 #include <sys/malloc.h>
 #include <sys/kernel.h>
 #include <sys/socket.h>
 @@ -1201,45 +1201,48 @@ cas_init(struct ifnet *ifp)
 	/* step 4. TX MAC registers & counters */
 	cas_init_regs(sc);
 	max_frame_size = ETHER_MAX_LEN + ETHER_VLAN_ENCAP_LEN;
 	v = (max_frame_size) | (0x2000 << 16) /* Burst size */;
 	bus_space_write_4(t, h, CAS_MAC_MAC_MAX_FRAME, v);
 	/* step 5. RX MAC registers & counters */
 	cas_iff(sc);
 	/* step 6 & 7. Program Descriptor Ring Base Addresses */
 	KASSERT((CAS_CDTXADDR(sc, 0) & 0x1fff) == 0);
 	bus_space_write_4(t, h, CAS_TX_RING_PTR_HI,
-	    (((uint64_t)CAS_CDTXADDR(sc, 0)) >> 32));
+	    BUS_ADDR_HI32(CAS_CDTXADDR(sc, 0)));
-	bus_space_write_4(t, h, CAS_TX_RING_PTR_LO, CAS_CDTXADDR(sc, 0));
+	bus_space_write_4(t, h, CAS_TX_RING_PTR_LO,
 	    BUS_ADDR_LO32(CAS_CDTXADDR(sc, 0)));
 	KASSERT((CAS_CDRXADDR(sc, 0) & 0x1fff) == 0);
 	bus_space_write_4(t, h, CAS_RX_DRING_PTR_HI,
-	    (((uint64_t)CAS_CDRXADDR(sc, 0)) >> 32));
+	    BUS_ADDR_HI32(CAS_CDRXADDR(sc, 0)));
-	bus_space_write_4(t, h, CAS_RX_DRING_PTR_LO, CAS_CDRXADDR(sc, 0));
+	bus_space_write_4(t, h, CAS_RX_DRING_PTR_LO,
 	    BUS_ADDR_LO32(CAS_CDRXADDR(sc, 0)));
 	KASSERT((CAS_CDRXCADDR(sc, 0) & 0x1fff) == 0);
 	bus_space_write_4(t, h, CAS_RX_CRING_PTR_HI,
-	    (((uint64_t)CAS_CDRXCADDR(sc, 0)) >> 32));
+	    BUS_ADDR_HI32(CAS_CDRXCADDR(sc, 0)));
-	bus_space_write_4(t, h, CAS_RX_CRING_PTR_LO, CAS_CDRXCADDR(sc, 0));
+	bus_space_write_4(t, h, CAS_RX_CRING_PTR_LO,
 	    BUS_ADDR_LO32(CAS_CDRXCADDR(sc, 0)));
 	if (CAS_PLUS(sc)) {
 		KASSERT((CAS_CDRXADDR2(sc, 0) & 0x1fff) == 0);
 		bus_space_write_4(t, h, CAS_RX_DRING_PTR_HI2,
-		    (((uint64_t)CAS_CDRXADDR2(sc, 0)) >> 32));
+		    BUS_ADDR_HI32(CAS_CDRXADDR2(sc, 0)));
 		bus_space_write_4(t, h, CAS_RX_DRING_PTR_LO2,
-		    CAS_CDRXADDR2(sc, 0));
+		    BUS_ADDR_LO32(CAS_CDRXADDR2(sc, 0)));
+	}
 	/* step 8. Global Configuration & Interrupt Mask */
 	cas_estintr(sc, CAS_INTR_REG);
 	/* step 9. ETX Configuration: use mostly default values */
 	/* Enable DMA */
 	v = cas_ringsize(CAS_NTXDESC /*XXX*/) << 10;
 	bus_space_write_4(t, h, CAS_TX_CONFIG,
 	    v | CAS_TX_CONFIG_TXDMA_EN | (1 << 24) | (1 << 29));
 	bus_space_write_4(t, h, CAS_TX_KICK, 0);