Tue Mar 24 03:47:39 2020 UTC ()
Calculate DDR3's tRAS correctly.


(msaitoh)
diff -r1.34 -r1.35 src/sys/dev/ic/spdmem.c
cvs diff -r1.34 -r1.35 src/sys/dev/ic/spdmem.c (expand / switch to unified diff)

--- src/sys/dev/ic/spdmem.c 2020/03/24 03:45:25 1.34
+++ src/sys/dev/ic/spdmem.c 2020/03/24 03:47:39 1.35
@@ -1,14 +1,14 @@ @@ -1,14 +1,14 @@
1/* $NetBSD: spdmem.c,v 1.34 2020/03/24 03:45:25 msaitoh Exp $ */ 1/* $NetBSD: spdmem.c,v 1.35 2020/03/24 03:47:39 msaitoh Exp $ */
2 2
3/* 3/*
4 * Copyright (c) 2007 Nicolas Joly 4 * Copyright (c) 2007 Nicolas Joly
5 * Copyright (c) 2007 Paul Goyette 5 * Copyright (c) 2007 Paul Goyette
6 * Copyright (c) 2007 Tobias Nygren 6 * Copyright (c) 2007 Tobias Nygren
7 * All rights reserved. 7 * All rights reserved.
8 * 8 *
9 * Redistribution and use in source and binary forms, with or without 9 * Redistribution and use in source and binary forms, with or without
10 * modification, are permitted provided that the following conditions 10 * modification, are permitted provided that the following conditions
11 * are met: 11 * are met:
12 * 1. Redistributions of source code must retain the above copyright 12 * 1. Redistributions of source code must retain the above copyright
13 * notice, this list of conditions and the following disclaimer. 13 * notice, this list of conditions and the following disclaimer.
14 * 2. Redistributions in binary form must reproduce the above copyright 14 * 2. Redistributions in binary form must reproduce the above copyright
@@ -25,27 +25,27 @@ @@ -25,27 +25,27 @@
25 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 25 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
26 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 26 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
27 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 27 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
28 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 28 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
29 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 29 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
30 * POSSIBILITY OF SUCH DAMAGE. 30 * POSSIBILITY OF SUCH DAMAGE.
31 */ 31 */
32 32
33/* 33/*
34 * Serial Presence Detect (SPD) memory identification 34 * Serial Presence Detect (SPD) memory identification
35 */ 35 */
36 36
37#include <sys/cdefs.h> 37#include <sys/cdefs.h>
38__KERNEL_RCSID(0, "$NetBSD: spdmem.c,v 1.34 2020/03/24 03:45:25 msaitoh Exp $"); 38__KERNEL_RCSID(0, "$NetBSD: spdmem.c,v 1.35 2020/03/24 03:47:39 msaitoh Exp $");
39 39
40#include <sys/param.h> 40#include <sys/param.h>
41#include <sys/device.h> 41#include <sys/device.h>
42#include <sys/endian.h> 42#include <sys/endian.h>
43#include <sys/sysctl.h> 43#include <sys/sysctl.h>
44#include <machine/bswap.h> 44#include <machine/bswap.h>
45 45
46#include <dev/i2c/i2cvar.h> 46#include <dev/i2c/i2cvar.h>
47#include <dev/ic/spdmemreg.h> 47#include <dev/ic/spdmemreg.h>
48#include <dev/ic/spdmemvar.h> 48#include <dev/ic/spdmemvar.h>
49 49
50/* Routines for decoding spd data */ 50/* Routines for decoding spd data */
51static void decode_edofpm(const struct sysctlnode *, device_t, struct spdmem *); 51static void decode_edofpm(const struct sysctlnode *, device_t, struct spdmem *);
@@ -820,28 +820,29 @@ decode_ddr3(const struct sysctlnode *nod @@ -820,28 +820,29 @@ decode_ddr3(const struct sysctlnode *nod
820 "%d.%03dns cycle time\n", 820 "%d.%03dns cycle time\n",
821 s->sm_ddr3.ddr3_rows + 12, s->sm_ddr3.ddr3_cols + 9, 821 s->sm_ddr3.ddr3_rows + 12, s->sm_ddr3.ddr3_cols + 9,
822 1 << (s->sm_ddr3.ddr3_logbanks + 3), 822 1 << (s->sm_ddr3.ddr3_logbanks + 3),
823 s->sm_ddr3.ddr3_physbanks + 1, 823 s->sm_ddr3.ddr3_physbanks + 1,
824 cycle_time/1000, cycle_time % 1000); 824 cycle_time/1000, cycle_time % 1000);
825 825
826#define __DDR3_CYCLES(val) \ 826#define __DDR3_CYCLES(val) \
827 ((val / cycle_time) + ((val % cycle_time) ? 1 : 0)) 827 ((val / cycle_time) + ((val % cycle_time) ? 1 : 0))
828 828
829 aprint_verbose_dev(self, LATENCY, 829 aprint_verbose_dev(self, LATENCY,
830 __DDR3_CYCLES(__DDR3_VALUE_PICO(s, tAAmin)), 830 __DDR3_CYCLES(__DDR3_VALUE_PICO(s, tAAmin)),
831 __DDR3_CYCLES(__DDR3_VALUE_PICO(s, tRCDmin)), 831 __DDR3_CYCLES(__DDR3_VALUE_PICO(s, tRCDmin)),
832 __DDR3_CYCLES(__DDR3_VALUE_PICO(s, tRPmin)), 832 __DDR3_CYCLES(__DDR3_VALUE_PICO(s, tRPmin)),
833 (s->sm_ddr3.ddr3_tRAS_msb * 256 + s->sm_ddr3.ddr3_tRAS_lsb) / 833 __DDR3_CYCLES((s->sm_ddr3.ddr3_tRAS_msb * 256
834 s->sm_ddr3.ddr3_tCKmin_mtb); 834 + s->sm_ddr3.ddr3_tRAS_lsb) * s->sm_ddr3.ddr3_mtb_dividend
 835 / s->sm_ddr3.ddr3_mtb_divisor * 1000));
835 836
836#undef __DDR3_CYCLES 837#undef __DDR3_CYCLES
837 838
838 /* For DDR3, Voltage is written in another area */ 839 /* For DDR3, Voltage is written in another area */
839 if (!s->sm_ddr3.ddr3_NOT15V || s->sm_ddr3.ddr3_135V 840 if (!s->sm_ddr3.ddr3_NOT15V || s->sm_ddr3.ddr3_135V
840 || s->sm_ddr3.ddr3_125V) { 841 || s->sm_ddr3.ddr3_125V) {
841 aprint_verbose("%s:", device_xname(self)); 842 aprint_verbose("%s:", device_xname(self));
842 if (!s->sm_ddr3.ddr3_NOT15V) 843 if (!s->sm_ddr3.ddr3_NOT15V)
843 aprint_verbose(" 1.5V"); 844 aprint_verbose(" 1.5V");
844 if (s->sm_ddr3.ddr3_135V) 845 if (s->sm_ddr3.ddr3_135V)
845 aprint_verbose(" 1.35V"); 846 aprint_verbose(" 1.35V");
846 if (s->sm_ddr3.ddr3_125V) 847 if (s->sm_ddr3.ddr3_125V)
847 aprint_verbose(" 1.25V"); 848 aprint_verbose(" 1.25V");