 @@ -1,14 +1,14 @@
-/*	$NetBSD: if_scx.c,v 1.16 2020/03/26 08:28:50 nisimura Exp $	*/
+/*	$NetBSD: if_scx.c,v 1.17 2020/03/26 10:38:16 nisimura Exp $	*/
 /*-
  * Copyright (c) 2020 The NetBSD Foundation, Inc.
  * All rights reserved.
+ *
  * This code is derived from software contributed to The NetBSD Foundation
  * by Tohru Nishimura.
+ *
  * Redistribution and use in source and binary forms, with or without
  * modification, are permitted provided that the following conditions
  * are met:
  * 1. Redistributions of source code must retain the above copyright
  *    notice, this list of conditions and the following disclaimer.
 @@ -30,44 +30,44 @@
  */
 #define NOT_MP_SAFE	0
 /*
  * Socionext SC2A11 SynQuacer NetSec GbE driver
+ *
  *   (possibly incorrect notes to be removed eventually)
  * - 32 byte descriptor for 64 bit paddr design.
  * - multiple rings seems available. There are special descriptor fields
  *   to designify ring number from which to arrive or to which go.
  * - memory mapped EEPROM to hold MAC address. The rest of the area is
  *   occupied by a set of ucode for two DMA engines and one packet engine.
- * - The size of frame address filter is unknown. Might be 16 or even 128.
+ * - The size of frame address filter is 16 plus 32.
  * - The first slot is my own station address. Always enabled to perform
  *   to identify oneself.
  * - 1~16 are for supplimental MAC addresses. Independently enabled for
  *   use. Good to catch multicast. Byte-wise selective match available.
  *   Use the mask to catch { 0x01, 0x00, 0x00 } and/or { 0x33, 0x33 }.
- * - 16~128 might be exact match without byte-mask.
+ * - 16~32 might be exact match without byte-mask.
- * - The size of multicast hash filter store is unknown. Might be 256 bit.
+ * - The size of multicast hash filter store is 64 bit.
  * - Socionext/Linaro "NetSec" code makes many cut shorts. Some constants
  *   are left unexplained. The values should be handled via external
  *   controls like FDT descriptions. Fortunately, Intel/Altera CycloneV PDFs
  *   describe every detail of "such the instance of" DW EMAC IP and
  *   most of them are likely applicable to SC2A11 GbE.
  * - DW EMAC implmentation (0x20) is 0x10.0x36
  */
 #include <sys/cdefs.h>
-__KERNEL_RCSID(0, "$NetBSD: if_scx.c,v 1.16 2020/03/26 08:28:50 nisimura Exp $");
+__KERNEL_RCSID(0, "$NetBSD: if_scx.c,v 1.17 2020/03/26 10:38:16 nisimura Exp $");
 #include <sys/param.h>
 #include <sys/bus.h>
 #include <sys/intr.h>
 #include <sys/device.h>
 #include <sys/callout.h>
 #include <sys/mbuf.h>
 #include <sys/malloc.h>
 #include <sys/errno.h>
 #include <sys/rndsource.h>
 #include <sys/kernel.h>
 #include <sys/systm.h>
 @@ -76,26 +76,28 @@ __KERNEL_RCSID(0, "$NetBSD: if_scx.c,v 1
 #include <net/if_dl.h>
 #include <net/if_ether.h>
 #include <dev/mii/mii.h>
 #include <dev/mii/miivar.h>
 #include <net/bpf.h>
 #include <dev/fdt/fdtvar.h>
 #include <dev/acpi/acpireg.h>
 #include <dev/acpi/acpivar.h>
 #include <dev/acpi/acpi_intr.h>
 /* SC2A11 register block */
 #define SWRESET		0x104
 #define MACADRH		0x10c
 #define MACADRL		0x110
 #define COMINIT		0x120
 #define INTRST		0x200
 #define  IRQ_RX		(1U<<1)
 #define  IRQ_TX		(1U<<0)
 #define INTREN		0x204
 #define INTR_SET	0x234
 #define INTR_CLR	0x238
 #define TXINTST		0x400
 #define TXINTEN		0x404
 #define TXINT_SET	0x428
 #define TXINT_CLR	0x42c
 #define  TXI_NTOWNR	(1U<<17)
 #define  TXI_TR_ERR	(1U<<16)
 @@ -105,28 +107,28 @@ __KERNEL_RCSID(0, "$NetBSD: if_scx.c,v 1
 #define RXINTEN		0x444
 #define RXINT_SET	0x468
 #define RXINT_CLR	0x46c
 #define  RXI_RC_ERR	(1U<<16)
 #define  RXI_PKTCNT	(1U<<15)
 #define  RXI_TMREXP	(1U<<14)
 #define TXTIMER		0x41c
 #define RXTIMER		0x45c
 #define TXCOUNT		0x410
 #define RXCOUNT		0x454
 #define H2MENG		0x210		/* DMAC host2media ucode port */
 #define M2HENG		0x21c		/* DMAC media2host ucode port */
 #define PKTENG		0x0d0		/* packet engine ucode port */
-#define HWVER0		0x22c
+#define MCVER		0x22c		/* micro controller version */
-#define HWVER1		0x230
+#define HWVER		0x230		/* hardware version */
 #define MACSTAT		0x1024		/* gmac status */
 #define MACDATA		0x11c0		/* gmac rd/wr data */
 #define MACCMD		0x11c4		/* gmac operation */
 #define  CMD_IOWR	(1U<<28)	/* write op */
 #define  CMD_BUSY	(1U<<31)	/* busy bit */
 #define DESCENG_INIT	0x11fc
 #define DESCENG_SRST	0x1204
 /* GMAC register block. use mac_write()/mac_read() to handle */
 #define GMACMCR		0x0000		/* MAC configuration */
 #define  MCR_IBN	(1U<<30)	/* */
 #define  MCR_CST	(1U<<25)	/* strip CRC */
 @@ -144,59 +146,59 @@ __KERNEL_RCSID(0, "$NetBSD: if_scx.c,v 1
 #define GMACAFR		0x0004		/* frame DA/SA address filter */
 #define  AFR_RA		(1U<<31)	/* receive block all on */
 #define  AFR_HPF	(1U<<10)	/* activate hash or perfect filter */
 #define  AFR_SAF	(1U<<9)		/* source address filter */
 #define  AFR_SAIF	(1U<<8)		/* SA inverse filtering */
 #define  AFR_PCF	(3U<<6)		/* */
 #define  AFR_RB		(1U<<5)		/* reject broadcast frame */
 #define  AFR_AM		(1U<<4)		/* accept all multicast frame */
 #define  AFR_DAIF	(1U<<3)		/* DA inverse filtering */
 #define  AFR_MHTE	(1U<<2)		/* use multicast hash table */
 #define  AFR_UHTE	(1U<<1)		/* use additional MAC addresses */
 #define  AFR_PM		(1U<<0)		/* run promisc mode */
 #define  _AFR		0x80000001	/* XXX TBD */
-#define GMACMHTH	0x0008		/* XXX multicast hash table 63:32 */
+#define GMACMHTH	0x0008		/* multicast hash table 63:32 */
-#define GMACMHTL	0x000c		/* XXX multicast hash table 31:0 */
+#define GMACMHTL	0x000c		/* multicast hash table 31:0 */
 #define GMACGAR		0x0010		/* MDIO operation */
 #define  GAR_PHY	(11)		/* mii phy 15:11 */
 #define  GAR_REG	(6)		/* mii reg 10:6 */
 #define  GAR_CTL	(2)		/* control 5:2 */
 #define  GAR_IOWR	(1U<<1)		/* MDIO write op */
 #define  GAR_BUSY	(1U)		/* busy bit */
 #define GMACGDR		0x0014		/* MDIO rd/wr data */
 #define GMACFCR		0x0018		/* 802.3x flowcontrol */
 #define  FCR_RFE	(1U<<2)		/* accept PAUSE to throttle Tx */
 #define  FCR_TFE	(1U<<1)		/* generate PAUSE to moderate Rx lvl */
 #define GMACVTAG	0x001c		/* VLAN tag control */
 #define GMACIMPL	0x0020		/* implementation number XX.YY */
 #define GMACMAH0	0x0040		/* MAC address 0 47:32 */
 #define GMACMAL0	0x0044		/* MAC address 0 31:0 */
 #define GMACMAH(i) 	((i)*8+0x40)	/* supplimental MAC addr 1 - 15 */
 #define GMACMAL(i) 	((i)*8+0x44)
 #define GMACMIISR	0x00d8		/* resolved xMII link status */
 					/*  3   link up detected
 					 *  2:1 resovled speed
 					 *      0 2.5Mhz (10Mbps)
 					 *	1 25Mhz  (100Mbps)
 					 *	2 125Mhz (1000Mbps)
 					 *  1   full duplex detected */
-#define GMACMHT0	0x0500		/* multicast hash table 0 - 7 */
+#define GMACMHT0	0x0500		/* XXX multicast hash table 0 - 7 */
 #define GMACMHT(i)	((i)*4+0x500)
 #define GMACVHT		0x0588		/* VLAN tag hash */
-#define GMACAMAH(i)	((i)*8+0x800)	/* supplimental MAC addr 16-127 */
+#define GMACAMAH(i)	((i)*8+0x800)	/* supplimental MAC addr 16-31 */
 #define GMACAMAL(i)	((i)*8+0x804)
 #define GMACEVCTL	0x0100		/* event counter control */
 #define GMACEVCNT(i)	((i)*4+0x114)	/* event counter 0x114~284 */
 #define GMACEVCTL	0x0100		/* clear event counter registers */
 #define GMACBMR		0x1000		/* DMA bus mode control
 					 * 24    4PBL
 					 * 22:17 RPBL
 					 * 16    fix burst
 					 * 15:14 priority between Rx and Tx
 					 *  3    rxtx ratio 41
 					 *  2    rxtx ratio 31
 					 *  1    rxtx ratio 21
 					 *  0    rxtx ratio 11
 					 * 13:8  PBL possible DMA burst len
 					 *  0    reset op. self clear
 					 */
 @@ -603,27 +605,27 @@ aprint_normal_dev(self,
 static void
 scx_attach_i(struct scx_softc *sc)
+{
 	struct ifnet * const ifp = &sc->sc_ethercom.ec_if;
 	struct mii_data * const mii = &sc->sc_mii;
 	struct ifmedia * const ifm = &mii->mii_media;
 	uint32_t hwver, dwimp;
 	uint8_t enaddr[ETHER_ADDR_LEN];
 	bus_dma_segment_t seg;
 	uint32_t csr;
 	int i, nseg, error = 0;
-	hwver = CSR_READ(sc, HWVER1);	/* Socionext HW */
+	hwver = CSR_READ(sc, HWVER);	/* Socionext HW */
 	/* stored in big endian order */
 	csr = bus_space_read_4(sc->sc_st, sc->sc_eesh, 0);
 	enaddr[0] = csr >> 24;
 	enaddr[1] = csr >> 16;
 	enaddr[2] = csr >> 8;
 	enaddr[3] = csr;
 	csr = bus_space_read_4(sc->sc_st, sc->sc_eesh, 4);
 	enaddr[4] = csr >> 24;
 	enaddr[5] = csr >> 16;
 	dwimp = mac_read(sc, GMACIMPL);	/* DW EMAC XX.YY */
 	aprint_normal_dev(sc->sc_dev,
 	    "Socionext NetSec GbE hw %d.%d impl 0x%x\n",
 @@ -943,48 +945,47 @@ scx_ioctl(struct ifnet *ifp, u_long cmd,
+	}
 	splx(s);
 	return error;
+}
 static void
 scx_set_rcvfilt(struct scx_softc *sc)
+{
 	struct ethercom * const ec = &sc->sc_ethercom;
 	struct ifnet * const ifp = &ec->ec_if;
 	struct ether_multistep step;
 	struct ether_multi *enm;
-	uint32_t mchash[8]; 	/* 8x 32 = 256 bit */
+	uint32_t mchash[2]; 	/* 2x 32 = 64 bit */
 	uint32_t csr, crc;
 	int i;
 	csr = mac_read(sc, GMACAFR);
 	csr &= ~(AFR_PM | AFR_AM | AFR_MHTE);
 	mac_write(sc, GMACAFR, csr);
 	ETHER_LOCK(ec);
 	if (ifp->if_flags & IFF_PROMISC) {
 		ec->ec_flags |= ETHER_F_ALLMULTI;
 		ETHER_UNLOCK(ec);
 		goto update;
+	}
 	ec->ec_flags &= ~ETHER_F_ALLMULTI;
 	/* clear 15 entry supplimental perfect match filter */
 	for (i = 1; i < 16; i++)
 		 mac_write(sc, GMACMAH(i), 0);
-	/* build 256 bit multicast hash filter */
+	/* build 64 bit multicast hash filter */
-	memset(mchash, 0, sizeof(mchash));
+	crc = mchash[1] = mchash[0] = 0;
 	crc = 0;
 	ETHER_FIRST_MULTI(step, ec, enm);
 	i = 1; /* slot 0 is occupied */
 	while (enm != NULL) {
 		if (memcmp(enm->enm_addrlo, enm->enm_addrhi, ETHER_ADDR_LEN)) {
 			/*
 			 * We must listen to a range of multicast addresses.
 			 * For now, just accept all multicasts, rather than
 			 * trying to set only those filter bits needed to match
 			 * the range.  (At this time, the only use of address
 			 * ranges is for IP multicast routing, for which the
 			 * range is big enough to require all bits set.)
 			 */
 @@ -996,38 +997,38 @@ printf("[%d] %s\n", i, ether_sprintf(enm
 		if (i < 16) {
 			/* use 15 entry perfect match filter */
 			uint32_t addr;
 			uint8_t *ep = enm->enm_addrlo;
 			addr = (ep[3] << 24) | (ep[2] << 16)
 			     | (ep[1] <<  8) |  ep[0];
 			mac_write(sc, GMACMAL(i), addr);
 			addr = (ep[5] << 8) | ep[4];
 			mac_write(sc, GMACMAH(i), addr | 1U<<31);
 		} else {
 			/* use hash table when too many */
 			/* bit_reserve_32(~crc) !? */
 			crc = ether_crc32_le(enm->enm_addrlo, ETHER_ADDR_LEN);
-			/* 3(31:29) 5(28:24) bit sampling */
+			/* 1(31) 5(30:26) bit sampling */
-			mchash[crc >> 29] |= 1 << ((crc >> 24) & 0x1f);
+			mchash[crc >> 31] |= 1 << ((crc >> 26) & 0x1f);
+		}
 		ETHER_NEXT_MULTI(step, enm);
 		i++;
+	}
 	ETHER_UNLOCK(ec);
 	if (crc)
 		csr |= AFR_MHTE;
-	for (i = 0; i < __arraycount(mchash); i++)
+	mac_write(sc, GMACMHTH, mchash[1]);
-		mac_write(sc, GMACMHT(i), mchash[i]);
+	mac_write(sc, GMACMHTL, mchash[0]);
 	mac_write(sc, GMACAFR, csr);
 	return;
  update:
 	/* With PM or AM, MHTE/MHT0-7 are never consulted. really? */
 	if (ifp->if_flags & IFF_PROMISC)
 		csr |= AFR_PM;	/* run promisc. mode */
 	else
 		csr |= AFR_AM;	/* accept all multicast */
 	mac_write(sc, GMACAFR, csr);
 	return;
+}