 @@ -1,14 +1,14 @@
-/*	$NetBSD: specialreg.h,v 1.158 2019/11/17 15:31:05 msaitoh Exp $	*/
+/*	$NetBSD: specialreg.h,v 1.159 2020/04/01 08:21:38 msaitoh Exp $	*/
 /*
  * Copyright (c) 2014-2019 The NetBSD Foundation, Inc.
  * All rights reserved.
+ *
  * Redistribution and use in source and binary forms, with or without
  * modification, are permitted provided that the following conditions
  * are met:
  * 1. Redistributions of source code must retain the above copyright
  *    notice, this list of conditions and the following disclaimer.
  * 2. Redistributions in binary form must reproduce the above copyright
  *    notice, this list of conditions and the following disclaimer in the
  *    documentation and/or other materials provided with the distribution.
 @@ -465,42 +465,46 @@
 	"b\0PREFETCHWT1\0" "b\1AVX512_VBMI\0" "b\2UMIP\0" "b\3PKU\0"	\
 	"b\4OSPKE\0"	"b\5WAITPKG\0"	"b\6AVX512_VBMI2\0" "b\7CET_SS\0" \
 	"b\10GFNI\0"	"b\11VAES\0"	"b\12VPCLMULQDQ\0" "b\13AVX512_VNNI\0"\
 	"b\14AVX512_BITALG\0"		"b\16AVX512_VPOPCNTDQ\0"	\
 	"f\21\5MAWAU\0"							\
 					"b\26RDPID\0"			\
 			"b\31CLDEMOTE\0"		"b\33MOVDIRI\0"	\
 	"b\34MOVDIR64B\0"		"b\36SGXLC\0"
 /* %edx */
 #define CPUID_SEF_AVX512_4VNNIW	__BIT(2)
 #define CPUID_SEF_AVX512_4FMAPS	__BIT(3)
 #define CPUID_SEF_FSREP_MOV	__BIT(4)  /* Fast Short REP MOV */
 #define CPUID_SEF_AVX512_VP2INTERSECT __BIT(8)
 #define CPUID_SEF_MD_CLEAR	__BIT(10)
 #define CPUID_SEF_TSX_FORCE_ABORT __BIT(13) /* MSR_TSX_FORCE_ABORT bit 0 */
 #define CPUID_SEF_SERIALIZE	__BIT(14)
 #define CPUID_SEF_HYBRID	__BIT(15) /* Hybrid part */
 #define CPUID_SEF_TSXLDTRK	__BIT(16) /* TSX suspend load addr tracking */
 #define CPUID_SEF_CET_IBT	__BIT(20) /* CET Indirect Branch Tracking */
 #define CPUID_SEF_IBRS		__BIT(26) /* IBRS / IBPB Speculation Control */
 #define CPUID_SEF_STIBP		__BIT(27) /* STIBP Speculation Control */
 #define CPUID_SEF_L1D_FLUSH	__BIT(28) /* IA32_FLUSH_CMD MSR */
 #define CPUID_SEF_ARCH_CAP	__BIT(29) /* IA32_ARCH_CAPABILITIES */
 #define CPUID_SEF_CORE_CAP	__BIT(30) /* IA32_CORE_CAPABILITIES */
 #define CPUID_SEF_SSBD		__BIT(31) /* Speculative Store Bypass Disable */
 #define CPUID_SEF_FLAGS2	"\20" \
 				"\3" "AVX512_4VNNIW" "\4" "AVX512_4FMAPS" \
 	"\5" "FSREP_MOV"						\
-				"\13" "MD_CLEAR"			\
+	"\11" "VP2INTERSECT"	"\13" "MD_CLEAR"			\
-			"\16" "TSX_FORCE_ABORT"		"\20" "HYBRID"	\
+			"\16TSX_FORCE_ABORT" "\17SERIALIZE" "\20HYBRID"	\
 	"\21" "TSXLDTRK"						\
 	"\25" "CET_IBT"							\
 	"\33" "IBRS"	"\34" "STIBP"					\
 	"\35" "L1D_FLUSH" "\36" "ARCH_CAP" "\37CORE_CAP"	"\40" "SSBD"
 /*
  * Intel CPUID Architectural Performance Monitoring Fn0000000a
+ *
  * See also src/usr.sbin/tprof/arch/tprof_x86.c
  */
 /* %eax */
 #define CPUID_PERF_VERSION	__BITS(7, 0)   /* Version ID */
 #define CPUID_PERF_NGPPC	__BITS(15, 8)  /* Num of G.P. perf counter */

 @@ -1,14 +1,14 @@
-/*	$NetBSD: procfs_machdep.c,v 1.35 2020/01/17 04:48:21 msaitoh Exp $ */
+/*	$NetBSD: procfs_machdep.c,v 1.36 2020/04/01 08:21:38 msaitoh Exp $ */
 /*
  * Copyright (c) 2001 Wasabi Systems, Inc.
  * All rights reserved.
+ *
  * Written by Frank van der Linden and Jason R. Thorpe for
  * Wasabi Systems, Inc.
+ *
  * Redistribution and use in source and binary forms, with or without
  * modification, are permitted provided that the following conditions
  * are met:
  * 1. Redistributions of source code must retain the above copyright
  *    notice, this list of conditions and the following disclaimer.
 @@ -32,27 +32,27 @@
  * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
  * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
  * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
  * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
  * POSSIBILITY OF SUCH DAMAGE.
  */
 /*
  * NOTE: We simply use the primary CPU's cpuid_level and tsc_freq
  * here.  Might want to change this later.
  */
 #include <sys/cdefs.h>
-__KERNEL_RCSID(0, "$NetBSD: procfs_machdep.c,v 1.35 2020/01/17 04:48:21 msaitoh Exp $");
+__KERNEL_RCSID(0, "$NetBSD: procfs_machdep.c,v 1.36 2020/04/01 08:21:38 msaitoh Exp $");
 #include <sys/param.h>
 #include <sys/systm.h>
 #include <sys/mount.h>
 #include <sys/stat.h>
 #include <sys/vnode.h>
 #include <miscfs/procfs/procfs.h>
 #include <machine/cpu.h>
 #include <machine/reg.h>
 #include <machine/specialreg.h>
 #include <x86/cputypes.h>
 @@ -179,27 +179,27 @@ static const char * const x86_features[]
 	"gfni", "vaes", "vpclmulqdq", "avx512_vnni",
 	"avx512_bitalg", "tme", "avx512_vpopcntdq", NULL,
 	"la57", NULL, NULL, NULL, NULL, NULL, "rdpid", NULL,
 	NULL, "cldemote", NULL, "movdiri", "movdir64b", NULL, NULL, NULL},
 	{ /* (17) 0x80000007 ebx */
 	"overflow_recov", "succor", NULL, "smca", NULL, NULL, NULL, NULL,
 	NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL,
 	NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL,
 	NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL},
 	{ /* (18) Intel 0x00000007 edx */
 	NULL, NULL, "avx512_4vnniw", "avx512_4fmaps", "fsrm", NULL, NULL, NULL,
-	NULL, NULL, "md_clear", NULL, NULL, NULL, NULL, NULL,
+	"vp2intersect", NULL, "md_clear", NULL, NULL, NULL, NULL, NULL,
 	NULL, NULL, "pconfig", NULL, NULL, NULL, NULL, NULL,
 	NULL, NULL, NULL, NULL,
 	"flush_l1d", "arch_capabilities", NULL, "ssbd"},
 };
 static int	procfs_getonecpu(int, struct cpu_info *, char *, size_t *);
 /*
  * Linux-style /proc/cpuinfo.
  * Only used when procfs is mounted with -o linux.
+ *
  * In the multiprocessor case, this should be a loop over all CPUs.
  */