Tue Apr 14 16:43:12 2020 UTC ()
Pull up following revision(s) (requested by msaitoh in ticket #831):

	sys/dev/mii/rdcphy.c: revision 1.6
	sys/dev/mii/rdcphy.c: revision 1.8
	sys/dev/mii/miidevs: revision 1.162
	sys/dev/mii/miidevs: revision 1.163
	sys/dev/mii/miidevs: revision 1.164
	sys/dev/mii/miidevs: revision 1.165
	sys/dev/mii/miidevs: revision 1.167
	sys/dev/mii/brgphy.c: revision 1.87

  Change the OUI macro name of RDC to xxRDC. 0x00d02d is non-bitreverse value
of official 0x000bb4. From Andrius V.
RDC -> xxRDC. No functional change.

Add BCM54213PE

Match BCM54213PE

  Use xxVIA instead of VIA.
0x004063 is VIA's official OUI but VT6103 use 0x0002c6.
0x0002c6 is non-bitreversed value of 0x004063. Reported by Andrius V.

- Add Quake Technologies and Aeluros' OUI
- Add Teranetics TN1010 10GBase-T PHY
  Add two new RDC PHYs from Andrius V.
  Add two new RDC PHYs from Andrius V.


(martin)
diff -r1.84 -r1.84.4.1 src/sys/dev/mii/brgphy.c
diff -r1.153.2.5 -r1.153.2.6 src/sys/dev/mii/miidevs
diff -r1.4 -r1.4.4.1 src/sys/dev/mii/rdcphy.c
cvs diff -r1.84 -r1.84.4.1 src/sys/dev/mii/brgphy.c (switch to unified diff)

--- src/sys/dev/mii/brgphy.c 2019/04/11 08:50:20 1.84
+++ src/sys/dev/mii/brgphy.c 2020/04/14 16:43:12 1.84.4.1
@@ -1,1179 +1,1180 @@ @@ -1,1179 +1,1180 @@
1/* $NetBSD: brgphy.c,v 1.84 2019/04/11 08:50:20 msaitoh Exp $ */ 1/* $NetBSD: brgphy.c,v 1.84.4.1 2020/04/14 16:43:12 martin Exp $ */
2 2
3/*- 3/*-
4 * Copyright (c) 1998, 1999, 2000, 2001 The NetBSD Foundation, Inc. 4 * Copyright (c) 1998, 1999, 2000, 2001 The NetBSD Foundation, Inc.
5 * All rights reserved. 5 * All rights reserved.
6 * 6 *
7 * This code is derived from software contributed to The NetBSD Foundation 7 * This code is derived from software contributed to The NetBSD Foundation
8 * by Jason R. Thorpe of the Numerical Aerospace Simulation Facility, 8 * by Jason R. Thorpe of the Numerical Aerospace Simulation Facility,
9 * NASA Ames Research Center. 9 * NASA Ames Research Center.
10 * 10 *
11 * Redistribution and use in source and binary forms, with or without 11 * Redistribution and use in source and binary forms, with or without
12 * modification, are permitted provided that the following conditions 12 * modification, are permitted provided that the following conditions
13 * are met: 13 * are met:
14 * 1. Redistributions of source code must retain the above copyright 14 * 1. Redistributions of source code must retain the above copyright
15 * notice, this list of conditions and the following disclaimer. 15 * notice, this list of conditions and the following disclaimer.
16 * 2. Redistributions in binary form must reproduce the above copyright 16 * 2. Redistributions in binary form must reproduce the above copyright
17 * notice, this list of conditions and the following disclaimer in the 17 * notice, this list of conditions and the following disclaimer in the
18 * documentation and/or other materials provided with the distribution. 18 * documentation and/or other materials provided with the distribution.
19 * 19 *
20 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 20 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
21 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 21 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
22 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 22 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
23 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 23 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
24 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 24 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
25 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 25 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
26 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 26 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
27 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 27 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
28 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 28 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
29 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 29 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
30 * POSSIBILITY OF SUCH DAMAGE. 30 * POSSIBILITY OF SUCH DAMAGE.
31 */ 31 */
32 32
33/* 33/*
34 * Copyright (c) 1997 Manuel Bouyer. All rights reserved. 34 * Copyright (c) 1997 Manuel Bouyer. All rights reserved.
35 * 35 *
36 * Redistribution and use in source and binary forms, with or without 36 * Redistribution and use in source and binary forms, with or without
37 * modification, are permitted provided that the following conditions 37 * modification, are permitted provided that the following conditions
38 * are met: 38 * are met:
39 * 1. Redistributions of source code must retain the above copyright 39 * 1. Redistributions of source code must retain the above copyright
40 * notice, this list of conditions and the following disclaimer. 40 * notice, this list of conditions and the following disclaimer.
41 * 2. Redistributions in binary form must reproduce the above copyright 41 * 2. Redistributions in binary form must reproduce the above copyright
42 * notice, this list of conditions and the following disclaimer in the 42 * notice, this list of conditions and the following disclaimer in the
43 * documentation and/or other materials provided with the distribution. 43 * documentation and/or other materials provided with the distribution.
44 * 44 *
45 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 45 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
46 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 46 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
47 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 47 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
48 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 48 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
49 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 49 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
50 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 50 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
51 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 51 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
52 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 52 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
53 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 53 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
54 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 54 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
55 */ 55 */
56 56
57/* 57/*
58 * driver for the Broadcom BCM5400 and BCM5700 Gig-E PHYs. 58 * driver for the Broadcom BCM5400 and BCM5700 Gig-E PHYs.
59 * 59 *
60 * Programming information for this PHY was gleaned from FreeBSD 60 * Programming information for this PHY was gleaned from FreeBSD
61 * (they were apparently able to get a datasheet from Broadcom). 61 * (they were apparently able to get a datasheet from Broadcom).
62 */ 62 */
63 63
64#include <sys/cdefs.h> 64#include <sys/cdefs.h>
65__KERNEL_RCSID(0, "$NetBSD: brgphy.c,v 1.84 2019/04/11 08:50:20 msaitoh Exp $"); 65__KERNEL_RCSID(0, "$NetBSD: brgphy.c,v 1.84.4.1 2020/04/14 16:43:12 martin Exp $");
66 66
67#include <sys/param.h> 67#include <sys/param.h>
68#include <sys/systm.h> 68#include <sys/systm.h>
69#include <sys/kernel.h> 69#include <sys/kernel.h>
70#include <sys/device.h> 70#include <sys/device.h>
71#include <sys/socket.h> 71#include <sys/socket.h>
72#include <sys/errno.h> 72#include <sys/errno.h>
73#include <prop/proplib.h> 73#include <prop/proplib.h>
74 74
75#include <net/if.h> 75#include <net/if.h>
76#include <net/if_media.h> 76#include <net/if_media.h>
77 77
78#include <dev/mii/mii.h> 78#include <dev/mii/mii.h>
79#include <dev/mii/miivar.h> 79#include <dev/mii/miivar.h>
80#include <dev/mii/miidevs.h> 80#include <dev/mii/miidevs.h>
81#include <dev/mii/brgphyreg.h> 81#include <dev/mii/brgphyreg.h>
82 82
83#include <dev/pci/if_bgereg.h> 83#include <dev/pci/if_bgereg.h>
84#include <dev/pci/if_bnxreg.h> 84#include <dev/pci/if_bnxreg.h>
85 85
86static int brgphymatch(device_t, cfdata_t, void *); 86static int brgphymatch(device_t, cfdata_t, void *);
87static void brgphyattach(device_t, device_t, void *); 87static void brgphyattach(device_t, device_t, void *);
88 88
89struct brgphy_softc { 89struct brgphy_softc {
90 struct mii_softc sc_mii; 90 struct mii_softc sc_mii;
91 bool sc_isbge; 91 bool sc_isbge;
92 bool sc_isbnx; 92 bool sc_isbnx;
93 uint32_t sc_chipid; /* parent's chipid */ 93 uint32_t sc_chipid; /* parent's chipid */
94 uint32_t sc_phyflags; /* parent's phyflags */ 94 uint32_t sc_phyflags; /* parent's phyflags */
95 uint32_t sc_shared_hwcfg; /* shared hw config */ 95 uint32_t sc_shared_hwcfg; /* shared hw config */
96 uint32_t sc_port_hwcfg; /* port specific hw config */ 96 uint32_t sc_port_hwcfg; /* port specific hw config */
97}; 97};
98 98
99CFATTACH_DECL3_NEW(brgphy, sizeof(struct brgphy_softc), 99CFATTACH_DECL3_NEW(brgphy, sizeof(struct brgphy_softc),
100 brgphymatch, brgphyattach, mii_phy_detach, mii_phy_activate, NULL, NULL, 100 brgphymatch, brgphyattach, mii_phy_detach, mii_phy_activate, NULL, NULL,
101 DVF_DETACH_SHUTDOWN); 101 DVF_DETACH_SHUTDOWN);
102 102
103static int brgphy_service(struct mii_softc *, struct mii_data *, int); 103static int brgphy_service(struct mii_softc *, struct mii_data *, int);
104static void brgphy_copper_status(struct mii_softc *); 104static void brgphy_copper_status(struct mii_softc *);
105static void brgphy_fiber_status(struct mii_softc *); 105static void brgphy_fiber_status(struct mii_softc *);
106static void brgphy_5708s_status(struct mii_softc *); 106static void brgphy_5708s_status(struct mii_softc *);
107static void brgphy_5709s_status(struct mii_softc *); 107static void brgphy_5709s_status(struct mii_softc *);
108static int brgphy_mii_phy_auto(struct mii_softc *); 108static int brgphy_mii_phy_auto(struct mii_softc *);
109static void brgphy_loop(struct mii_softc *); 109static void brgphy_loop(struct mii_softc *);
110static void brgphy_reset(struct mii_softc *); 110static void brgphy_reset(struct mii_softc *);
111static void brgphy_bcm5401_dspcode(struct mii_softc *); 111static void brgphy_bcm5401_dspcode(struct mii_softc *);
112static void brgphy_bcm5411_dspcode(struct mii_softc *); 112static void brgphy_bcm5411_dspcode(struct mii_softc *);
113static void brgphy_bcm5421_dspcode(struct mii_softc *); 113static void brgphy_bcm5421_dspcode(struct mii_softc *);
114static void brgphy_bcm54k2_dspcode(struct mii_softc *); 114static void brgphy_bcm54k2_dspcode(struct mii_softc *);
115static void brgphy_adc_bug(struct mii_softc *); 115static void brgphy_adc_bug(struct mii_softc *);
116static void brgphy_5704_a0_bug(struct mii_softc *); 116static void brgphy_5704_a0_bug(struct mii_softc *);
117static void brgphy_ber_bug(struct mii_softc *); 117static void brgphy_ber_bug(struct mii_softc *);
118static void brgphy_crc_bug(struct mii_softc *); 118static void brgphy_crc_bug(struct mii_softc *);
119static void brgphy_disable_early_dac(struct mii_softc *); 119static void brgphy_disable_early_dac(struct mii_softc *);
120static void brgphy_jumbo_settings(struct mii_softc *); 120static void brgphy_jumbo_settings(struct mii_softc *);
121static void brgphy_eth_wirespeed(struct mii_softc *); 121static void brgphy_eth_wirespeed(struct mii_softc *);
122 122
123 123
124static const struct mii_phy_funcs brgphy_copper_funcs = { 124static const struct mii_phy_funcs brgphy_copper_funcs = {
125 brgphy_service, brgphy_copper_status, brgphy_reset, 125 brgphy_service, brgphy_copper_status, brgphy_reset,
126}; 126};
127 127
128static const struct mii_phy_funcs brgphy_fiber_funcs = { 128static const struct mii_phy_funcs brgphy_fiber_funcs = {
129 brgphy_service, brgphy_fiber_status, brgphy_reset, 129 brgphy_service, brgphy_fiber_status, brgphy_reset,
130}; 130};
131 131
132static const struct mii_phy_funcs brgphy_5708s_funcs = { 132static const struct mii_phy_funcs brgphy_5708s_funcs = {
133 brgphy_service, brgphy_5708s_status, brgphy_reset, 133 brgphy_service, brgphy_5708s_status, brgphy_reset,
134}; 134};
135 135
136static const struct mii_phy_funcs brgphy_5709s_funcs = { 136static const struct mii_phy_funcs brgphy_5709s_funcs = {
137 brgphy_service, brgphy_5709s_status, brgphy_reset, 137 brgphy_service, brgphy_5709s_status, brgphy_reset,
138}; 138};
139 139
140static const struct mii_phydesc brgphys[] = { 140static const struct mii_phydesc brgphys[] = {
141 MII_PHY_DESC(BROADCOM, BCM5400), 141 MII_PHY_DESC(BROADCOM, BCM5400),
142 MII_PHY_DESC(BROADCOM, BCM5401), 142 MII_PHY_DESC(BROADCOM, BCM5401),
143 MII_PHY_DESC(BROADCOM, BCM5402), 143 MII_PHY_DESC(BROADCOM, BCM5402),
144 MII_PHY_DESC(BROADCOM, BCM5404), 144 MII_PHY_DESC(BROADCOM, BCM5404),
145 MII_PHY_DESC(BROADCOM, BCM5411), 145 MII_PHY_DESC(BROADCOM, BCM5411),
146 MII_PHY_DESC(BROADCOM, BCM5421), 146 MII_PHY_DESC(BROADCOM, BCM5421),
147 MII_PHY_DESC(BROADCOM, BCM5424), 147 MII_PHY_DESC(BROADCOM, BCM5424),
148 MII_PHY_DESC(BROADCOM, BCM5461), 148 MII_PHY_DESC(BROADCOM, BCM5461),
149 MII_PHY_DESC(BROADCOM, BCM5462), 149 MII_PHY_DESC(BROADCOM, BCM5462),
150 MII_PHY_DESC(BROADCOM, BCM5464), 150 MII_PHY_DESC(BROADCOM, BCM5464),
151 MII_PHY_DESC(BROADCOM, BCM5466), 151 MII_PHY_DESC(BROADCOM, BCM5466),
152 MII_PHY_DESC(BROADCOM, BCM54K2), 152 MII_PHY_DESC(BROADCOM, BCM54K2),
153 MII_PHY_DESC(BROADCOM, BCM5701), 153 MII_PHY_DESC(BROADCOM, BCM5701),
154 MII_PHY_DESC(BROADCOM, BCM5703), 154 MII_PHY_DESC(BROADCOM, BCM5703),
155 MII_PHY_DESC(BROADCOM, BCM5704), 155 MII_PHY_DESC(BROADCOM, BCM5704),
156 MII_PHY_DESC(BROADCOM, BCM5705), 156 MII_PHY_DESC(BROADCOM, BCM5705),
157 MII_PHY_DESC(BROADCOM, BCM5706), 157 MII_PHY_DESC(BROADCOM, BCM5706),
158 MII_PHY_DESC(BROADCOM, BCM5714), 158 MII_PHY_DESC(BROADCOM, BCM5714),
159 MII_PHY_DESC(BROADCOM, BCM5750), 159 MII_PHY_DESC(BROADCOM, BCM5750),
160 MII_PHY_DESC(BROADCOM, BCM5752), 160 MII_PHY_DESC(BROADCOM, BCM5752),
161 MII_PHY_DESC(BROADCOM, BCM5780), 161 MII_PHY_DESC(BROADCOM, BCM5780),
162 MII_PHY_DESC(BROADCOM, BCM5708C), 162 MII_PHY_DESC(BROADCOM, BCM5708C),
163 MII_PHY_DESC(BROADCOM2, BCM5481), 163 MII_PHY_DESC(BROADCOM2, BCM5481),
164 MII_PHY_DESC(BROADCOM2, BCM5482), 164 MII_PHY_DESC(BROADCOM2, BCM5482),
165 MII_PHY_DESC(BROADCOM2, BCM5708S), 165 MII_PHY_DESC(BROADCOM2, BCM5708S),
166 MII_PHY_DESC(BROADCOM2, BCM5709C), 166 MII_PHY_DESC(BROADCOM2, BCM5709C),
167 MII_PHY_DESC(BROADCOM2, BCM5709S), 167 MII_PHY_DESC(BROADCOM2, BCM5709S),
168 MII_PHY_DESC(BROADCOM2, BCM5709CAX), 168 MII_PHY_DESC(BROADCOM2, BCM5709CAX),
169 MII_PHY_DESC(BROADCOM2, BCM5722), 169 MII_PHY_DESC(BROADCOM2, BCM5722),
170 MII_PHY_DESC(BROADCOM2, BCM5754), 170 MII_PHY_DESC(BROADCOM2, BCM5754),
171 MII_PHY_DESC(BROADCOM2, BCM5755), 171 MII_PHY_DESC(BROADCOM2, BCM5755),
172 MII_PHY_DESC(BROADCOM2, BCM5756), 172 MII_PHY_DESC(BROADCOM2, BCM5756),
173 MII_PHY_DESC(BROADCOM2, BCM5761), 173 MII_PHY_DESC(BROADCOM2, BCM5761),
174 MII_PHY_DESC(BROADCOM2, BCM5784), 174 MII_PHY_DESC(BROADCOM2, BCM5784),
175 MII_PHY_DESC(BROADCOM2, BCM5785), 175 MII_PHY_DESC(BROADCOM2, BCM5785),
176 MII_PHY_DESC(BROADCOM3, BCM5717C), 176 MII_PHY_DESC(BROADCOM3, BCM5717C),
177 MII_PHY_DESC(BROADCOM3, BCM5719C), 177 MII_PHY_DESC(BROADCOM3, BCM5719C),
178 MII_PHY_DESC(BROADCOM3, BCM5720C), 178 MII_PHY_DESC(BROADCOM3, BCM5720C),
179 MII_PHY_DESC(BROADCOM3, BCM57765), 179 MII_PHY_DESC(BROADCOM3, BCM57765),
180 MII_PHY_DESC(BROADCOM3, BCM57780), 180 MII_PHY_DESC(BROADCOM3, BCM57780),
 181 MII_PHY_DESC(BROADCOM4, BCM54213PE),
181 MII_PHY_DESC(BROADCOM4, BCM5725C), 182 MII_PHY_DESC(BROADCOM4, BCM5725C),
182 MII_PHY_DESC(xxBROADCOM_ALT1, BCM5906), 183 MII_PHY_DESC(xxBROADCOM_ALT1, BCM5906),
183 MII_PHY_END, 184 MII_PHY_END,
184}; 185};
185 186
186static int 187static int
187brgphymatch(device_t parent, cfdata_t match, void *aux) 188brgphymatch(device_t parent, cfdata_t match, void *aux)
188{ 189{
189 struct mii_attach_args *ma = aux; 190 struct mii_attach_args *ma = aux;
190 191
191 if (mii_phy_match(ma, brgphys) != NULL) 192 if (mii_phy_match(ma, brgphys) != NULL)
192 return 10; 193 return 10;
193 194
194 return 0; 195 return 0;
195} 196}
196 197
197static void 198static void
198brgphyattach(device_t parent, device_t self, void *aux) 199brgphyattach(device_t parent, device_t self, void *aux)
199{ 200{
200 struct brgphy_softc *bsc = device_private(self); 201 struct brgphy_softc *bsc = device_private(self);
201 struct mii_softc *sc = &bsc->sc_mii; 202 struct mii_softc *sc = &bsc->sc_mii;
202 struct mii_attach_args *ma = aux; 203 struct mii_attach_args *ma = aux;
203 struct mii_data *mii = ma->mii_data; 204 struct mii_data *mii = ma->mii_data;
204 const struct mii_phydesc *mpd; 205 const struct mii_phydesc *mpd;
205 prop_dictionary_t dict; 206 prop_dictionary_t dict;
206 207
207 mpd = mii_phy_match(ma, brgphys); 208 mpd = mii_phy_match(ma, brgphys);
208 aprint_naive(": Media interface\n"); 209 aprint_naive(": Media interface\n");
209 aprint_normal(": %s, rev. %d\n", mpd->mpd_name, MII_REV(ma->mii_id2)); 210 aprint_normal(": %s, rev. %d\n", mpd->mpd_name, MII_REV(ma->mii_id2));
210 211
211 sc->mii_dev = self; 212 sc->mii_dev = self;
212 sc->mii_inst = mii->mii_instance; 213 sc->mii_inst = mii->mii_instance;
213 sc->mii_phy = ma->mii_phyno; 214 sc->mii_phy = ma->mii_phyno;
214 sc->mii_mpd_oui = MII_OUI(ma->mii_id1, ma->mii_id2); 215 sc->mii_mpd_oui = MII_OUI(ma->mii_id1, ma->mii_id2);
215 sc->mii_mpd_model = MII_MODEL(ma->mii_id2); 216 sc->mii_mpd_model = MII_MODEL(ma->mii_id2);
216 sc->mii_mpd_rev = MII_REV(ma->mii_id2); 217 sc->mii_mpd_rev = MII_REV(ma->mii_id2);
217 sc->mii_pdata = mii; 218 sc->mii_pdata = mii;
218 sc->mii_flags = ma->mii_flags; 219 sc->mii_flags = ma->mii_flags;
219 sc->mii_anegticks = MII_ANEGTICKS; 220 sc->mii_anegticks = MII_ANEGTICKS;
220 221
221 if (device_is_a(parent, "bge")) 222 if (device_is_a(parent, "bge"))
222 bsc->sc_isbge = true; 223 bsc->sc_isbge = true;
223 else if (device_is_a(parent, "bnx")) 224 else if (device_is_a(parent, "bnx"))
224 bsc->sc_isbnx = true; 225 bsc->sc_isbnx = true;
225 226
226 dict = device_properties(parent); 227 dict = device_properties(parent);
227 if (bsc->sc_isbge || bsc->sc_isbnx) { 228 if (bsc->sc_isbge || bsc->sc_isbnx) {
228 if (!prop_dictionary_get_uint32(dict, "phyflags", 229 if (!prop_dictionary_get_uint32(dict, "phyflags",
229 &bsc->sc_phyflags)) 230 &bsc->sc_phyflags))
230 aprint_error_dev(self, "failed to get phyflags\n"); 231 aprint_error_dev(self, "failed to get phyflags\n");
231 if (!prop_dictionary_get_uint32(dict, "chipid", 232 if (!prop_dictionary_get_uint32(dict, "chipid",
232 &bsc->sc_chipid)) 233 &bsc->sc_chipid))
233 aprint_error_dev(self, "failed to get chipid\n"); 234 aprint_error_dev(self, "failed to get chipid\n");
234 } 235 }
235 236
236 if (bsc->sc_isbnx) { 237 if (bsc->sc_isbnx) {
237 /* Currently, only bnx use sc_shared_hwcfg and sc_port_hwcfg */ 238 /* Currently, only bnx use sc_shared_hwcfg and sc_port_hwcfg */
238 if (!prop_dictionary_get_uint32(dict, "shared_hwcfg", 239 if (!prop_dictionary_get_uint32(dict, "shared_hwcfg",
239 &bsc->sc_shared_hwcfg)) 240 &bsc->sc_shared_hwcfg))
240 aprint_error_dev(self, "failed to get shared_hwcfg\n"); 241 aprint_error_dev(self, "failed to get shared_hwcfg\n");
241 if (!prop_dictionary_get_uint32(dict, "port_hwcfg", 242 if (!prop_dictionary_get_uint32(dict, "port_hwcfg",
242 &bsc->sc_port_hwcfg)) 243 &bsc->sc_port_hwcfg))
243 aprint_error_dev(self, "failed to get port_hwcfg\n"); 244 aprint_error_dev(self, "failed to get port_hwcfg\n");
244 } 245 }
245 246
246 if (sc->mii_flags & MIIF_HAVEFIBER) { 247 if (sc->mii_flags & MIIF_HAVEFIBER) {
247 if ((sc->mii_mpd_oui == MII_OUI_BROADCOM2) 248 if ((sc->mii_mpd_oui == MII_OUI_BROADCOM2)
248 && sc->mii_mpd_model == MII_MODEL_BROADCOM2_BCM5708S) 249 && sc->mii_mpd_model == MII_MODEL_BROADCOM2_BCM5708S)
249 sc->mii_funcs = &brgphy_5708s_funcs; 250 sc->mii_funcs = &brgphy_5708s_funcs;
250 else if ((sc->mii_mpd_oui == MII_OUI_BROADCOM2) 251 else if ((sc->mii_mpd_oui == MII_OUI_BROADCOM2)
251 && (sc->mii_mpd_model == MII_MODEL_BROADCOM2_BCM5709S)) { 252 && (sc->mii_mpd_model == MII_MODEL_BROADCOM2_BCM5709S)) {
252 if (bsc->sc_isbnx) 253 if (bsc->sc_isbnx)
253 sc->mii_funcs = &brgphy_5709s_funcs; 254 sc->mii_funcs = &brgphy_5709s_funcs;
254 else { 255 else {
255 /* 256 /*
256 * XXX 257 * XXX
257 * 5720S and 5709S shares the same PHY id. 258 * 5720S and 5709S shares the same PHY id.
258 * Assume 5720S PHY if parent device is bge(4). 259 * Assume 5720S PHY if parent device is bge(4).
259 */ 260 */
260 sc->mii_funcs = &brgphy_5708s_funcs; 261 sc->mii_funcs = &brgphy_5708s_funcs;
261 } 262 }
262 } else 263 } else
263 sc->mii_funcs = &brgphy_fiber_funcs; 264 sc->mii_funcs = &brgphy_fiber_funcs;
264 } else 265 } else
265 sc->mii_funcs = &brgphy_copper_funcs; 266 sc->mii_funcs = &brgphy_copper_funcs;
266 267
267 PHY_RESET(sc); 268 PHY_RESET(sc);
268 269
269 PHY_READ(sc, MII_BMSR, &sc->mii_capabilities); 270 PHY_READ(sc, MII_BMSR, &sc->mii_capabilities);
270 sc->mii_capabilities &= ma->mii_capmask; 271 sc->mii_capabilities &= ma->mii_capmask;
271 if (sc->mii_capabilities & BMSR_EXTSTAT) 272 if (sc->mii_capabilities & BMSR_EXTSTAT)
272 PHY_READ(sc, MII_EXTSR, &sc->mii_extcapabilities); 273 PHY_READ(sc, MII_EXTSR, &sc->mii_extcapabilities);
273 274
274 aprint_normal_dev(self, ""); 275 aprint_normal_dev(self, "");
275 if (sc->mii_flags & MIIF_HAVEFIBER) { 276 if (sc->mii_flags & MIIF_HAVEFIBER) {
276 sc->mii_flags |= MIIF_NOISOLATE | MIIF_NOLOOP; 277 sc->mii_flags |= MIIF_NOISOLATE | MIIF_NOLOOP;
277 278
278 /* 279 /*
279 * Set the proper bits for capabilities so that the 280 * Set the proper bits for capabilities so that the
280 * correct media get selected by mii_phy_add_media() 281 * correct media get selected by mii_phy_add_media()
281 */ 282 */
282 sc->mii_capabilities |= BMSR_ANEG; 283 sc->mii_capabilities |= BMSR_ANEG;
283 sc->mii_capabilities &= ~BMSR_100T4; 284 sc->mii_capabilities &= ~BMSR_100T4;
284 sc->mii_extcapabilities |= EXTSR_1000XFDX; 285 sc->mii_extcapabilities |= EXTSR_1000XFDX;
285 286
286 if (bsc->sc_isbnx) { 287 if (bsc->sc_isbnx) {
287 /* 288 /*
288 * 2.5Gb support is a software enabled feature 289 * 2.5Gb support is a software enabled feature
289 * on the BCM5708S and BCM5709S controllers. 290 * on the BCM5708S and BCM5709S controllers.
290 */ 291 */
291#define ADD(m, c) ifmedia_add(&mii->mii_media, (m), (c), NULL) 292#define ADD(m, c) ifmedia_add(&mii->mii_media, (m), (c), NULL)
292 if (bsc->sc_phyflags 293 if (bsc->sc_phyflags
293 & BNX_PHY_2_5G_CAPABLE_FLAG) { 294 & BNX_PHY_2_5G_CAPABLE_FLAG) {
294 ADD(IFM_MAKEWORD(IFM_ETHER, IFM_2500_SX, 295 ADD(IFM_MAKEWORD(IFM_ETHER, IFM_2500_SX,
295 IFM_FDX, sc->mii_inst), 0); 296 IFM_FDX, sc->mii_inst), 0);
296 aprint_normal("2500baseSX-FDX, "); 297 aprint_normal("2500baseSX-FDX, ");
297#undef ADD 298#undef ADD
298 } 299 }
299 } 300 }
300 } 301 }
301 mii_phy_add_media(sc); 302 mii_phy_add_media(sc);
302 303
303 aprint_normal("\n"); 304 aprint_normal("\n");
304} 305}
305 306
306static int 307static int
307brgphy_service(struct mii_softc *sc, struct mii_data *mii, int cmd) 308brgphy_service(struct mii_softc *sc, struct mii_data *mii, int cmd)
308{ 309{
309 struct ifmedia_entry *ife = mii->mii_media.ifm_cur; 310 struct ifmedia_entry *ife = mii->mii_media.ifm_cur;
310 uint16_t reg, speed, gig; 311 uint16_t reg, speed, gig;
311 312
312 switch (cmd) { 313 switch (cmd) {
313 case MII_POLLSTAT: 314 case MII_POLLSTAT:
314 /* If we're not polling our PHY instance, just return. */ 315 /* If we're not polling our PHY instance, just return. */
315 if (IFM_INST(ife->ifm_media) != sc->mii_inst) 316 if (IFM_INST(ife->ifm_media) != sc->mii_inst)
316 return 0; 317 return 0;
317 break; 318 break;
318 319
319 case MII_MEDIACHG: 320 case MII_MEDIACHG:
320 /* 321 /*
321 * If the media indicates a different PHY instance, 322 * If the media indicates a different PHY instance,
322 * isolate ourselves. 323 * isolate ourselves.
323 */ 324 */
324 if (IFM_INST(ife->ifm_media) != sc->mii_inst) { 325 if (IFM_INST(ife->ifm_media) != sc->mii_inst) {
325 PHY_READ(sc, MII_BMCR, &reg); 326 PHY_READ(sc, MII_BMCR, &reg);
326 PHY_WRITE(sc, MII_BMCR, reg | BMCR_ISO); 327 PHY_WRITE(sc, MII_BMCR, reg | BMCR_ISO);
327 return 0; 328 return 0;
328 } 329 }
329 330
330 /* If the interface is not up, don't do anything. */ 331 /* If the interface is not up, don't do anything. */
331 if ((mii->mii_ifp->if_flags & IFF_UP) == 0) 332 if ((mii->mii_ifp->if_flags & IFF_UP) == 0)
332 break; 333 break;
333 334
334 PHY_RESET(sc); /* XXX hardware bug work-around */ 335 PHY_RESET(sc); /* XXX hardware bug work-around */
335 336
336 switch (IFM_SUBTYPE(ife->ifm_media)) { 337 switch (IFM_SUBTYPE(ife->ifm_media)) {
337 case IFM_AUTO: 338 case IFM_AUTO:
338 (void) brgphy_mii_phy_auto(sc); 339 (void) brgphy_mii_phy_auto(sc);
339 break; 340 break;
340 case IFM_2500_SX: 341 case IFM_2500_SX:
341 speed = BRGPHY_5708S_BMCR_2500; 342 speed = BRGPHY_5708S_BMCR_2500;
342 goto setit; 343 goto setit;
343 case IFM_1000_SX: 344 case IFM_1000_SX:
344 case IFM_1000_T: 345 case IFM_1000_T:
345 speed = BMCR_S1000; 346 speed = BMCR_S1000;
346 goto setit; 347 goto setit;
347 case IFM_100_TX: 348 case IFM_100_TX:
348 speed = BMCR_S100; 349 speed = BMCR_S100;
349 goto setit; 350 goto setit;
350 case IFM_10_T: 351 case IFM_10_T:
351 speed = BMCR_S10; 352 speed = BMCR_S10;
352setit: 353setit:
353 brgphy_loop(sc); 354 brgphy_loop(sc);
354 if ((ife->ifm_media & IFM_FDX) != 0) { 355 if ((ife->ifm_media & IFM_FDX) != 0) {
355 speed |= BMCR_FDX; 356 speed |= BMCR_FDX;
356 gig = GTCR_ADV_1000TFDX; 357 gig = GTCR_ADV_1000TFDX;
357 } else 358 } else
358 gig = GTCR_ADV_1000THDX; 359 gig = GTCR_ADV_1000THDX;
359 360
360 PHY_WRITE(sc, MII_100T2CR, 0); 361 PHY_WRITE(sc, MII_100T2CR, 0);
361 PHY_WRITE(sc, MII_ANAR, ANAR_CSMA); 362 PHY_WRITE(sc, MII_ANAR, ANAR_CSMA);
362 PHY_WRITE(sc, MII_BMCR, speed); 363 PHY_WRITE(sc, MII_BMCR, speed);
363 364
364 if ((IFM_SUBTYPE(ife->ifm_media) != IFM_1000_T) && 365 if ((IFM_SUBTYPE(ife->ifm_media) != IFM_1000_T) &&
365 (IFM_SUBTYPE(ife->ifm_media) != IFM_1000_SX) && 366 (IFM_SUBTYPE(ife->ifm_media) != IFM_1000_SX) &&
366 (IFM_SUBTYPE(ife->ifm_media) != IFM_2500_SX)) 367 (IFM_SUBTYPE(ife->ifm_media) != IFM_2500_SX))
367 break; 368 break;
368 369
369 PHY_WRITE(sc, MII_100T2CR, gig); 370 PHY_WRITE(sc, MII_100T2CR, gig);
370 PHY_WRITE(sc, MII_BMCR, 371 PHY_WRITE(sc, MII_BMCR,
371 speed | BMCR_AUTOEN | BMCR_STARTNEG); 372 speed | BMCR_AUTOEN | BMCR_STARTNEG);
372 373
373 if ((sc->mii_mpd_oui != MII_OUI_BROADCOM) 374 if ((sc->mii_mpd_oui != MII_OUI_BROADCOM)
374 || (sc->mii_mpd_model != MII_MODEL_BROADCOM_BCM5701)) 375 || (sc->mii_mpd_model != MII_MODEL_BROADCOM_BCM5701))
375 break; 376 break;
376 377
377 if (mii->mii_media.ifm_media & IFM_ETH_MASTER) 378 if (mii->mii_media.ifm_media & IFM_ETH_MASTER)
378 gig |= GTCR_MAN_MS | GTCR_ADV_MS; 379 gig |= GTCR_MAN_MS | GTCR_ADV_MS;
379 PHY_WRITE(sc, MII_100T2CR, gig); 380 PHY_WRITE(sc, MII_100T2CR, gig);
380 break; 381 break;
381 default: 382 default:
382 return EINVAL; 383 return EINVAL;
383 } 384 }
384 break; 385 break;
385 386
386 case MII_TICK: 387 case MII_TICK:
387 /* If we're not currently selected, just return. */ 388 /* If we're not currently selected, just return. */
388 if (IFM_INST(ife->ifm_media) != sc->mii_inst) 389 if (IFM_INST(ife->ifm_media) != sc->mii_inst)
389 return 0; 390 return 0;
390 391
391 /* Is the interface even up? */ 392 /* Is the interface even up? */
392 if ((mii->mii_ifp->if_flags & IFF_UP) == 0) 393 if ((mii->mii_ifp->if_flags & IFF_UP) == 0)
393 return 0; 394 return 0;
394 395
395 /* Only used for autonegotiation. */ 396 /* Only used for autonegotiation. */
396 if ((IFM_SUBTYPE(ife->ifm_media) != IFM_AUTO) && 397 if ((IFM_SUBTYPE(ife->ifm_media) != IFM_AUTO) &&
397 (IFM_SUBTYPE(ife->ifm_media) != IFM_1000_T)) { 398 (IFM_SUBTYPE(ife->ifm_media) != IFM_1000_T)) {
398 sc->mii_ticks = 0; 399 sc->mii_ticks = 0;
399 break; 400 break;
400 } 401 }
401 402
402 /* 403 /*
403 * Check for link. 404 * Check for link.
404 * Read the status register twice; BMSR_LINK is latch-low. 405 * Read the status register twice; BMSR_LINK is latch-low.
405 */ 406 */
406 PHY_READ(sc, MII_BMSR, &reg); 407 PHY_READ(sc, MII_BMSR, &reg);
407 PHY_READ(sc, MII_BMSR, &reg); 408 PHY_READ(sc, MII_BMSR, &reg);
408 if (reg & BMSR_LINK) { 409 if (reg & BMSR_LINK) {
409 sc->mii_ticks = 0; 410 sc->mii_ticks = 0;
410 break; 411 break;
411 } 412 }
412 413
413 /* 414 /*
414 * mii_ticks == 0 means it's the first tick after changing the 415 * mii_ticks == 0 means it's the first tick after changing the
415 * media or the link became down since the last tick 416 * media or the link became down since the last tick
416 * (see above), so break to update the status. 417 * (see above), so break to update the status.
417 */ 418 */
418 if (sc->mii_ticks++ == 0) 419 if (sc->mii_ticks++ == 0)
419 break; 420 break;
420 421
421 /* Only retry autonegotiation every mii_anegticks seconds. */ 422 /* Only retry autonegotiation every mii_anegticks seconds. */
422 KASSERT(sc->mii_anegticks != 0); 423 KASSERT(sc->mii_anegticks != 0);
423 if (sc->mii_ticks <= sc->mii_anegticks) 424 if (sc->mii_ticks <= sc->mii_anegticks)
424 break; 425 break;
425 426
426 brgphy_mii_phy_auto(sc); 427 brgphy_mii_phy_auto(sc);
427 break; 428 break;
428 429
429 case MII_DOWN: 430 case MII_DOWN:
430 mii_phy_down(sc); 431 mii_phy_down(sc);
431 return 0; 432 return 0;
432 } 433 }
433 434
434 /* Update the media status. */ 435 /* Update the media status. */
435 mii_phy_status(sc); 436 mii_phy_status(sc);
436 437
437 /* 438 /*
438 * Callback if something changed. Note that we need to poke the DSP on 439 * Callback if something changed. Note that we need to poke the DSP on
439 * the Broadcom PHYs if the media changes. 440 * the Broadcom PHYs if the media changes.
440 */ 441 */
441 if (sc->mii_media_active != mii->mii_media_active || 442 if (sc->mii_media_active != mii->mii_media_active ||
442 sc->mii_media_status != mii->mii_media_status || 443 sc->mii_media_status != mii->mii_media_status ||
443 cmd == MII_MEDIACHG) { 444 cmd == MII_MEDIACHG) {
444 switch (sc->mii_mpd_oui) { 445 switch (sc->mii_mpd_oui) {
445 case MII_OUI_BROADCOM: 446 case MII_OUI_BROADCOM:
446 switch (sc->mii_mpd_model) { 447 switch (sc->mii_mpd_model) {
447 case MII_MODEL_BROADCOM_BCM5400: 448 case MII_MODEL_BROADCOM_BCM5400:
448 brgphy_bcm5401_dspcode(sc); 449 brgphy_bcm5401_dspcode(sc);
449 break; 450 break;
450 case MII_MODEL_BROADCOM_BCM5401: 451 case MII_MODEL_BROADCOM_BCM5401:
451 if (sc->mii_mpd_rev == 1 || sc->mii_mpd_rev == 3) 452 if (sc->mii_mpd_rev == 1 || sc->mii_mpd_rev == 3)
452 brgphy_bcm5401_dspcode(sc); 453 brgphy_bcm5401_dspcode(sc);
453 break; 454 break;
454 case MII_MODEL_BROADCOM_BCM5411: 455 case MII_MODEL_BROADCOM_BCM5411:
455 brgphy_bcm5411_dspcode(sc); 456 brgphy_bcm5411_dspcode(sc);
456 break; 457 break;
457 } 458 }
458 break; 459 break;
459 } 460 }
460 } 461 }
461 462
462 /* Callback if something changed. */ 463 /* Callback if something changed. */
463 mii_phy_update(sc, cmd); 464 mii_phy_update(sc, cmd);
464 return 0; 465 return 0;
465} 466}
466 467
467static void 468static void
468brgphy_copper_status(struct mii_softc *sc) 469brgphy_copper_status(struct mii_softc *sc)
469{ 470{
470 struct mii_data *mii = sc->mii_pdata; 471 struct mii_data *mii = sc->mii_pdata;
471 struct ifmedia_entry *ife = mii->mii_media.ifm_cur; 472 struct ifmedia_entry *ife = mii->mii_media.ifm_cur;
472 uint16_t bmcr, bmsr, auxsts, gtsr; 473 uint16_t bmcr, bmsr, auxsts, gtsr;
473 474
474 mii->mii_media_status = IFM_AVALID; 475 mii->mii_media_status = IFM_AVALID;
475 mii->mii_media_active = IFM_ETHER; 476 mii->mii_media_active = IFM_ETHER;
476 477
477 PHY_READ(sc, MII_BMSR, &bmsr); 478 PHY_READ(sc, MII_BMSR, &bmsr);
478 PHY_READ(sc, MII_BMSR, &bmsr); 479 PHY_READ(sc, MII_BMSR, &bmsr);
479 if (bmsr & BMSR_LINK) 480 if (bmsr & BMSR_LINK)
480 mii->mii_media_status |= IFM_ACTIVE; 481 mii->mii_media_status |= IFM_ACTIVE;
481 482
482 PHY_READ(sc, MII_BMCR, &bmcr); 483 PHY_READ(sc, MII_BMCR, &bmcr);
483 if (bmcr & BMCR_ISO) { 484 if (bmcr & BMCR_ISO) {
484 mii->mii_media_active |= IFM_NONE; 485 mii->mii_media_active |= IFM_NONE;
485 mii->mii_media_status = 0; 486 mii->mii_media_status = 0;
486 return; 487 return;
487 } 488 }
488 489
489 if (bmcr & BMCR_LOOP) 490 if (bmcr & BMCR_LOOP)
490 mii->mii_media_active |= IFM_LOOP; 491 mii->mii_media_active |= IFM_LOOP;
491 492
492 if (bmcr & BMCR_AUTOEN) { 493 if (bmcr & BMCR_AUTOEN) {
493 /* 494 /*
494 * The media status bits are only valid of autonegotiation 495 * The media status bits are only valid of autonegotiation
495 * has completed (or it's disabled). 496 * has completed (or it's disabled).
496 */ 497 */
497 if ((bmsr & BMSR_ACOMP) == 0) { 498 if ((bmsr & BMSR_ACOMP) == 0) {
498 /* Erg, still trying, I guess... */ 499 /* Erg, still trying, I guess... */
499 mii->mii_media_active |= IFM_NONE; 500 mii->mii_media_active |= IFM_NONE;
500 return; 501 return;
501 } 502 }
502 503
503 PHY_READ(sc, BRGPHY_MII_AUXSTS, &auxsts); 504 PHY_READ(sc, BRGPHY_MII_AUXSTS, &auxsts);
504 505
505 switch (auxsts & BRGPHY_AUXSTS_AN_RES) { 506 switch (auxsts & BRGPHY_AUXSTS_AN_RES) {
506 case BRGPHY_RES_1000FD: 507 case BRGPHY_RES_1000FD:
507 mii->mii_media_active |= IFM_1000_T | IFM_FDX; 508 mii->mii_media_active |= IFM_1000_T | IFM_FDX;
508 PHY_READ(sc, MII_100T2SR, &gtsr); 509 PHY_READ(sc, MII_100T2SR, &gtsr);
509 if (gtsr & GTSR_MS_RES) 510 if (gtsr & GTSR_MS_RES)
510 mii->mii_media_active |= IFM_ETH_MASTER; 511 mii->mii_media_active |= IFM_ETH_MASTER;
511 break; 512 break;
512 513
513 case BRGPHY_RES_1000HD: 514 case BRGPHY_RES_1000HD:
514 mii->mii_media_active |= IFM_1000_T | IFM_HDX; 515 mii->mii_media_active |= IFM_1000_T | IFM_HDX;
515 PHY_READ(sc, MII_100T2SR, &gtsr); 516 PHY_READ(sc, MII_100T2SR, &gtsr);
516 if (gtsr & GTSR_MS_RES) 517 if (gtsr & GTSR_MS_RES)
517 mii->mii_media_active |= IFM_ETH_MASTER; 518 mii->mii_media_active |= IFM_ETH_MASTER;
518 break; 519 break;
519 520
520 case BRGPHY_RES_100FD: 521 case BRGPHY_RES_100FD:
521 mii->mii_media_active |= IFM_100_TX | IFM_FDX; 522 mii->mii_media_active |= IFM_100_TX | IFM_FDX;
522 break; 523 break;
523 524
524 case BRGPHY_RES_100T4: 525 case BRGPHY_RES_100T4:
525 mii->mii_media_active |= IFM_100_T4 | IFM_HDX; 526 mii->mii_media_active |= IFM_100_T4 | IFM_HDX;
526 break; 527 break;
527 528
528 case BRGPHY_RES_100HD: 529 case BRGPHY_RES_100HD:
529 mii->mii_media_active |= IFM_100_TX | IFM_HDX; 530 mii->mii_media_active |= IFM_100_TX | IFM_HDX;
530 break; 531 break;
531 532
532 case BRGPHY_RES_10FD: 533 case BRGPHY_RES_10FD:
533 mii->mii_media_active |= IFM_10_T | IFM_FDX; 534 mii->mii_media_active |= IFM_10_T | IFM_FDX;
534 break; 535 break;
535 536
536 case BRGPHY_RES_10HD: 537 case BRGPHY_RES_10HD:
537 mii->mii_media_active |= IFM_10_T | IFM_HDX; 538 mii->mii_media_active |= IFM_10_T | IFM_HDX;
538 break; 539 break;
539 540
540 default: 541 default:
541 mii->mii_media_active |= IFM_NONE; 542 mii->mii_media_active |= IFM_NONE;
542 mii->mii_media_status = 0; 543 mii->mii_media_status = 0;
543 } 544 }
544 545
545 if (mii->mii_media_active & IFM_FDX) 546 if (mii->mii_media_active & IFM_FDX)
546 mii->mii_media_active |= mii_phy_flowstatus(sc); 547 mii->mii_media_active |= mii_phy_flowstatus(sc);
547 548
548 } else 549 } else
549 mii->mii_media_active = ife->ifm_media; 550 mii->mii_media_active = ife->ifm_media;
550} 551}
551 552
552void 553void
553brgphy_fiber_status(struct mii_softc *sc) 554brgphy_fiber_status(struct mii_softc *sc)
554{ 555{
555 struct mii_data *mii = sc->mii_pdata; 556 struct mii_data *mii = sc->mii_pdata;
556 struct ifmedia_entry *ife = mii->mii_media.ifm_cur; 557 struct ifmedia_entry *ife = mii->mii_media.ifm_cur;
557 uint16_t bmcr, bmsr, anar, anlpar, result; 558 uint16_t bmcr, bmsr, anar, anlpar, result;
558 559
559 mii->mii_media_status = IFM_AVALID; 560 mii->mii_media_status = IFM_AVALID;
560 mii->mii_media_active = IFM_ETHER; 561 mii->mii_media_active = IFM_ETHER;
561 562
562 PHY_READ(sc, MII_BMSR, &bmsr); 563 PHY_READ(sc, MII_BMSR, &bmsr);
563 PHY_READ(sc, MII_BMSR, &bmsr); 564 PHY_READ(sc, MII_BMSR, &bmsr);
564 if (bmsr & BMSR_LINK) 565 if (bmsr & BMSR_LINK)
565 mii->mii_media_status |= IFM_ACTIVE; 566 mii->mii_media_status |= IFM_ACTIVE;
566 567
567 PHY_READ(sc, MII_BMCR, &bmcr); 568 PHY_READ(sc, MII_BMCR, &bmcr);
568 if (bmcr & BMCR_LOOP) 569 if (bmcr & BMCR_LOOP)
569 mii->mii_media_active |= IFM_LOOP; 570 mii->mii_media_active |= IFM_LOOP;
570 571
571 if (bmcr & BMCR_AUTOEN) { 572 if (bmcr & BMCR_AUTOEN) {
572 if ((bmsr & BMSR_ACOMP) == 0) { 573 if ((bmsr & BMSR_ACOMP) == 0) {
573 /* Erg, still trying, I guess... */ 574 /* Erg, still trying, I guess... */
574 mii->mii_media_active |= IFM_NONE; 575 mii->mii_media_active |= IFM_NONE;
575 return; 576 return;
576 } 577 }
577 578
578 mii->mii_media_active |= IFM_1000_SX; 579 mii->mii_media_active |= IFM_1000_SX;
579 580
580 PHY_READ(sc, MII_ANAR, &anar); 581 PHY_READ(sc, MII_ANAR, &anar);
581 PHY_READ(sc, MII_ANLPAR, &anlpar); 582 PHY_READ(sc, MII_ANLPAR, &anlpar);
582 result = anar & anlpar; 583 result = anar & anlpar;
583 584
584 if (result & ANAR_X_FD) 585 if (result & ANAR_X_FD)
585 mii->mii_media_active |= IFM_FDX; 586 mii->mii_media_active |= IFM_FDX;
586 else 587 else
587 mii->mii_media_active |= IFM_HDX; 588 mii->mii_media_active |= IFM_HDX;
588 589
589 if (mii->mii_media_active & IFM_FDX) 590 if (mii->mii_media_active & IFM_FDX)
590 mii->mii_media_active |= mii_phy_flowstatus(sc); 591 mii->mii_media_active |= mii_phy_flowstatus(sc);
591 } else 592 } else
592 mii->mii_media_active = ife->ifm_media; 593 mii->mii_media_active = ife->ifm_media;
593} 594}
594 595
595void 596void
596brgphy_5708s_status(struct mii_softc *sc) 597brgphy_5708s_status(struct mii_softc *sc)
597{ 598{
598 struct mii_data *mii = sc->mii_pdata; 599 struct mii_data *mii = sc->mii_pdata;
599 struct ifmedia_entry *ife = mii->mii_media.ifm_cur; 600 struct ifmedia_entry *ife = mii->mii_media.ifm_cur;
600 uint16_t bmcr, bmsr; 601 uint16_t bmcr, bmsr;
601 602
602 mii->mii_media_status = IFM_AVALID; 603 mii->mii_media_status = IFM_AVALID;
603 mii->mii_media_active = IFM_ETHER; 604 mii->mii_media_active = IFM_ETHER;
604 605
605 PHY_READ(sc, MII_BMSR, &bmsr); 606 PHY_READ(sc, MII_BMSR, &bmsr);
606 PHY_READ(sc, MII_BMSR, &bmsr); 607 PHY_READ(sc, MII_BMSR, &bmsr);
607 if (bmsr & BMSR_LINK) 608 if (bmsr & BMSR_LINK)
608 mii->mii_media_status |= IFM_ACTIVE; 609 mii->mii_media_status |= IFM_ACTIVE;
609 610
610 PHY_READ(sc, MII_BMCR, &bmcr); 611 PHY_READ(sc, MII_BMCR, &bmcr);
611 if (bmcr & BMCR_LOOP) 612 if (bmcr & BMCR_LOOP)
612 mii->mii_media_active |= IFM_LOOP; 613 mii->mii_media_active |= IFM_LOOP;
613 614
614 if (bmcr & BMCR_AUTOEN) { 615 if (bmcr & BMCR_AUTOEN) {
615 uint16_t xstat; 616 uint16_t xstat;
616 617
617 if ((bmsr & BMSR_ACOMP) == 0) { 618 if ((bmsr & BMSR_ACOMP) == 0) {
618 PHY_WRITE(sc, BRGPHY_5708S_BLOCK_ADDR, 619 PHY_WRITE(sc, BRGPHY_5708S_BLOCK_ADDR,
619 BRGPHY_5708S_DIG_PG0); 620 BRGPHY_5708S_DIG_PG0);
620 PHY_READ(sc, BRGPHY_5708S_PG0_1000X_STAT1, &xstat); 621 PHY_READ(sc, BRGPHY_5708S_PG0_1000X_STAT1, &xstat);
621 if ((xstat & BRGPHY_5708S_PG0_1000X_STAT1_LINK) == 0) { 622 if ((xstat & BRGPHY_5708S_PG0_1000X_STAT1_LINK) == 0) {
622 /* Erg, still trying, I guess... */ 623 /* Erg, still trying, I guess... */
623 mii->mii_media_active |= IFM_NONE; 624 mii->mii_media_active |= IFM_NONE;
624 return; 625 return;
625 } 626 }
626 } 627 }
627 628
628 PHY_WRITE(sc, BRGPHY_5708S_BLOCK_ADDR, 629 PHY_WRITE(sc, BRGPHY_5708S_BLOCK_ADDR,
629 BRGPHY_5708S_DIG_PG0); 630 BRGPHY_5708S_DIG_PG0);
630 PHY_READ(sc, BRGPHY_5708S_PG0_1000X_STAT1, &xstat); 631 PHY_READ(sc, BRGPHY_5708S_PG0_1000X_STAT1, &xstat);
631 632
632 switch (xstat & BRGPHY_5708S_PG0_1000X_STAT1_SPEED_MASK) { 633 switch (xstat & BRGPHY_5708S_PG0_1000X_STAT1_SPEED_MASK) {
633 case BRGPHY_5708S_PG0_1000X_STAT1_SPEED_10: 634 case BRGPHY_5708S_PG0_1000X_STAT1_SPEED_10:
634 mii->mii_media_active |= IFM_10_FL; 635 mii->mii_media_active |= IFM_10_FL;
635 break; 636 break;
636 case BRGPHY_5708S_PG0_1000X_STAT1_SPEED_100: 637 case BRGPHY_5708S_PG0_1000X_STAT1_SPEED_100:
637 mii->mii_media_active |= IFM_100_FX; 638 mii->mii_media_active |= IFM_100_FX;
638 break; 639 break;
639 case BRGPHY_5708S_PG0_1000X_STAT1_SPEED_1G: 640 case BRGPHY_5708S_PG0_1000X_STAT1_SPEED_1G:
640 mii->mii_media_active |= IFM_1000_SX; 641 mii->mii_media_active |= IFM_1000_SX;
641 break; 642 break;
642 case BRGPHY_5708S_PG0_1000X_STAT1_SPEED_25G: 643 case BRGPHY_5708S_PG0_1000X_STAT1_SPEED_25G:
643 mii->mii_media_active |= IFM_2500_SX; 644 mii->mii_media_active |= IFM_2500_SX;
644 break; 645 break;
645 } 646 }
646 647
647 if (xstat & BRGPHY_5708S_PG0_1000X_STAT1_FDX) 648 if (xstat & BRGPHY_5708S_PG0_1000X_STAT1_FDX)
648 mii->mii_media_active |= IFM_FDX; 649 mii->mii_media_active |= IFM_FDX;
649 else 650 else
650 mii->mii_media_active |= IFM_HDX; 651 mii->mii_media_active |= IFM_HDX;
651 652
652 if (mii->mii_media_active & IFM_FDX) { 653 if (mii->mii_media_active & IFM_FDX) {
653 if (xstat & BRGPHY_5708S_PG0_1000X_STAT1_TX_PAUSE) 654 if (xstat & BRGPHY_5708S_PG0_1000X_STAT1_TX_PAUSE)
654 mii->mii_media_active 655 mii->mii_media_active
655 |= IFM_FLOW | IFM_ETH_TXPAUSE; 656 |= IFM_FLOW | IFM_ETH_TXPAUSE;
656 if (xstat & BRGPHY_5708S_PG0_1000X_STAT1_RX_PAUSE) 657 if (xstat & BRGPHY_5708S_PG0_1000X_STAT1_RX_PAUSE)
657 mii->mii_media_active 658 mii->mii_media_active
658 |= IFM_FLOW | IFM_ETH_RXPAUSE; 659 |= IFM_FLOW | IFM_ETH_RXPAUSE;
659 } 660 }
660 } else 661 } else
661 mii->mii_media_active = ife->ifm_media; 662 mii->mii_media_active = ife->ifm_media;
662} 663}
663 664
664static void 665static void
665brgphy_5709s_status(struct mii_softc *sc) 666brgphy_5709s_status(struct mii_softc *sc)
666{ 667{
667 struct mii_data *mii = sc->mii_pdata; 668 struct mii_data *mii = sc->mii_pdata;
668 struct ifmedia_entry *ife = mii->mii_media.ifm_cur; 669 struct ifmedia_entry *ife = mii->mii_media.ifm_cur;
669 uint16_t bmcr, bmsr, auxsts; 670 uint16_t bmcr, bmsr, auxsts;
670 671
671 mii->mii_media_status = IFM_AVALID; 672 mii->mii_media_status = IFM_AVALID;
672 mii->mii_media_active = IFM_ETHER; 673 mii->mii_media_active = IFM_ETHER;
673 674
674 PHY_READ(sc, MII_BMSR, &bmsr); 675 PHY_READ(sc, MII_BMSR, &bmsr);
675 PHY_READ(sc, MII_BMSR, &bmsr); 676 PHY_READ(sc, MII_BMSR, &bmsr);
676 if (bmsr & BMSR_LINK) 677 if (bmsr & BMSR_LINK)
677 mii->mii_media_status |= IFM_ACTIVE; 678 mii->mii_media_status |= IFM_ACTIVE;
678 679
679 PHY_READ(sc, MII_BMCR, &bmcr); 680 PHY_READ(sc, MII_BMCR, &bmcr);
680 if (bmcr & BMCR_ISO) { 681 if (bmcr & BMCR_ISO) {
681 mii->mii_media_active |= IFM_NONE; 682 mii->mii_media_active |= IFM_NONE;
682 mii->mii_media_status = 0; 683 mii->mii_media_status = 0;
683 return; 684 return;
684 } 685 }
685 686
686 if (bmcr & BMCR_LOOP) 687 if (bmcr & BMCR_LOOP)
687 mii->mii_media_active |= IFM_LOOP; 688 mii->mii_media_active |= IFM_LOOP;
688 689
689 if (bmcr & BMCR_AUTOEN) { 690 if (bmcr & BMCR_AUTOEN) {
690 /* 691 /*
691 * The media status bits are only valid of autonegotiation 692 * The media status bits are only valid of autonegotiation
692 * has completed (or it's disabled). 693 * has completed (or it's disabled).
693 */ 694 */
694 if ((bmsr & BMSR_ACOMP) == 0) { 695 if ((bmsr & BMSR_ACOMP) == 0) {
695 /* Erg, still trying, I guess... */ 696 /* Erg, still trying, I guess... */
696 mii->mii_media_active |= IFM_NONE; 697 mii->mii_media_active |= IFM_NONE;
697 return; 698 return;
698 } 699 }
699 700
700 /* 5709S has its own general purpose status registers */ 701 /* 5709S has its own general purpose status registers */
701 PHY_WRITE(sc, BRGPHY_BLOCK_ADDR, BRGPHY_BLOCK_ADDR_GP_STATUS); 702 PHY_WRITE(sc, BRGPHY_BLOCK_ADDR, BRGPHY_BLOCK_ADDR_GP_STATUS);
702 PHY_READ(sc, BRGPHY_GP_STATUS_TOP_ANEG_STATUS, &auxsts); 703 PHY_READ(sc, BRGPHY_GP_STATUS_TOP_ANEG_STATUS, &auxsts);
703 704
704 PHY_WRITE(sc, BRGPHY_BLOCK_ADDR, 705 PHY_WRITE(sc, BRGPHY_BLOCK_ADDR,
705 BRGPHY_BLOCK_ADDR_COMBO_IEEE0); 706 BRGPHY_BLOCK_ADDR_COMBO_IEEE0);
706 707
707 switch (auxsts & BRGPHY_GP_STATUS_TOP_ANEG_SPEED_MASK) { 708 switch (auxsts & BRGPHY_GP_STATUS_TOP_ANEG_SPEED_MASK) {
708 case BRGPHY_GP_STATUS_TOP_ANEG_SPEED_10: 709 case BRGPHY_GP_STATUS_TOP_ANEG_SPEED_10:
709 mii->mii_media_active |= IFM_10_FL; 710 mii->mii_media_active |= IFM_10_FL;
710 break; 711 break;
711 case BRGPHY_GP_STATUS_TOP_ANEG_SPEED_100: 712 case BRGPHY_GP_STATUS_TOP_ANEG_SPEED_100:
712 mii->mii_media_active |= IFM_100_FX; 713 mii->mii_media_active |= IFM_100_FX;
713 break; 714 break;
714 case BRGPHY_GP_STATUS_TOP_ANEG_SPEED_1G: 715 case BRGPHY_GP_STATUS_TOP_ANEG_SPEED_1G:
715 mii->mii_media_active |= IFM_1000_SX; 716 mii->mii_media_active |= IFM_1000_SX;
716 break; 717 break;
717 case BRGPHY_GP_STATUS_TOP_ANEG_SPEED_25G: 718 case BRGPHY_GP_STATUS_TOP_ANEG_SPEED_25G:
718 mii->mii_media_active |= IFM_2500_SX; 719 mii->mii_media_active |= IFM_2500_SX;
719 break; 720 break;
720 default: 721 default:
721 mii->mii_media_active |= IFM_NONE; 722 mii->mii_media_active |= IFM_NONE;
722 mii->mii_media_status = 0; 723 mii->mii_media_status = 0;
723 break; 724 break;
724 } 725 }
725 726
726 if (auxsts & BRGPHY_GP_STATUS_TOP_ANEG_FDX) 727 if (auxsts & BRGPHY_GP_STATUS_TOP_ANEG_FDX)
727 mii->mii_media_active |= IFM_FDX; 728 mii->mii_media_active |= IFM_FDX;
728 else 729 else
729 mii->mii_media_active |= IFM_HDX; 730 mii->mii_media_active |= IFM_HDX;
730 731
731 if (mii->mii_media_active & IFM_FDX) 732 if (mii->mii_media_active & IFM_FDX)
732 mii->mii_media_active |= mii_phy_flowstatus(sc); 733 mii->mii_media_active |= mii_phy_flowstatus(sc);
733 } else 734 } else
734 mii->mii_media_active = ife->ifm_media; 735 mii->mii_media_active = ife->ifm_media;
735} 736}
736 737
737int 738int
738brgphy_mii_phy_auto(struct mii_softc *sc) 739brgphy_mii_phy_auto(struct mii_softc *sc)
739{ 740{
740 uint16_t anar, ktcr = 0; 741 uint16_t anar, ktcr = 0;
741 742
742 sc->mii_ticks = 0; 743 sc->mii_ticks = 0;
743 brgphy_loop(sc); 744 brgphy_loop(sc);
744 PHY_RESET(sc); 745 PHY_RESET(sc);
745 746
746 if (sc->mii_flags & MIIF_HAVEFIBER) { 747 if (sc->mii_flags & MIIF_HAVEFIBER) {
747 anar = ANAR_X_FD | ANAR_X_HD; 748 anar = ANAR_X_FD | ANAR_X_HD;
748 if (sc->mii_flags & MIIF_DOPAUSE) 749 if (sc->mii_flags & MIIF_DOPAUSE)
749 anar |= ANAR_X_PAUSE_TOWARDS; 750 anar |= ANAR_X_PAUSE_TOWARDS;
750 } else { 751 } else {
751 anar = BMSR_MEDIA_TO_ANAR(sc->mii_capabilities) | ANAR_CSMA; 752 anar = BMSR_MEDIA_TO_ANAR(sc->mii_capabilities) | ANAR_CSMA;
752 if (sc->mii_flags & MIIF_DOPAUSE) 753 if (sc->mii_flags & MIIF_DOPAUSE)
753 anar |= ANAR_FC | ANAR_PAUSE_ASYM; 754 anar |= ANAR_FC | ANAR_PAUSE_ASYM;
754 ktcr = GTCR_ADV_1000TFDX | GTCR_ADV_1000THDX; 755 ktcr = GTCR_ADV_1000TFDX | GTCR_ADV_1000THDX;
755 if ((sc->mii_mpd_oui == MII_OUI_BROADCOM) 756 if ((sc->mii_mpd_oui == MII_OUI_BROADCOM)
756 && (sc->mii_mpd_model == MII_MODEL_BROADCOM_BCM5701)) 757 && (sc->mii_mpd_model == MII_MODEL_BROADCOM_BCM5701))
757 ktcr |= GTCR_MAN_MS | GTCR_ADV_MS; 758 ktcr |= GTCR_MAN_MS | GTCR_ADV_MS;
758 PHY_WRITE(sc, MII_100T2CR, ktcr); 759 PHY_WRITE(sc, MII_100T2CR, ktcr);
759 } 760 }
760 PHY_WRITE(sc, MII_ANAR, anar); 761 PHY_WRITE(sc, MII_ANAR, anar);
761 762
762 /* Start autonegotiation */ 763 /* Start autonegotiation */
763 PHY_WRITE(sc, MII_BMCR, BMCR_AUTOEN | BMCR_STARTNEG); 764 PHY_WRITE(sc, MII_BMCR, BMCR_AUTOEN | BMCR_STARTNEG);
764 PHY_WRITE(sc, BRGPHY_MII_IMR, 0xFF00); 765 PHY_WRITE(sc, BRGPHY_MII_IMR, 0xFF00);
765 766
766 return EJUSTRETURN; 767 return EJUSTRETURN;
767} 768}
768 769
769void 770void
770brgphy_loop(struct mii_softc *sc) 771brgphy_loop(struct mii_softc *sc)
771{ 772{
772 uint16_t bmsr; 773 uint16_t bmsr;
773 int i; 774 int i;
774 775
775 PHY_WRITE(sc, MII_BMCR, BMCR_LOOP); 776 PHY_WRITE(sc, MII_BMCR, BMCR_LOOP);
776 for (i = 0; i < 15000; i++) { 777 for (i = 0; i < 15000; i++) {
777 PHY_READ(sc, MII_BMSR, &bmsr); 778 PHY_READ(sc, MII_BMSR, &bmsr);
778 if (!(bmsr & BMSR_LINK)) 779 if (!(bmsr & BMSR_LINK))
779 break; 780 break;
780 DELAY(10); 781 DELAY(10);
781 } 782 }
782} 783}
783 784
784static void 785static void
785brgphy_reset(struct mii_softc *sc) 786brgphy_reset(struct mii_softc *sc)
786{ 787{
787 struct brgphy_softc *bsc = device_private(sc->mii_dev); 788 struct brgphy_softc *bsc = device_private(sc->mii_dev);
788 uint16_t reg; 789 uint16_t reg;
789 790
790 mii_phy_reset(sc); 791 mii_phy_reset(sc);
791 switch (sc->mii_mpd_oui) { 792 switch (sc->mii_mpd_oui) {
792 case MII_OUI_BROADCOM: 793 case MII_OUI_BROADCOM:
793 switch (sc->mii_mpd_model) { 794 switch (sc->mii_mpd_model) {
794 case MII_MODEL_BROADCOM_BCM5400: 795 case MII_MODEL_BROADCOM_BCM5400:
795 brgphy_bcm5401_dspcode(sc); 796 brgphy_bcm5401_dspcode(sc);
796 break; 797 break;
797 case MII_MODEL_BROADCOM_BCM5401: 798 case MII_MODEL_BROADCOM_BCM5401:
798 if (sc->mii_mpd_rev == 1 || sc->mii_mpd_rev == 3) 799 if (sc->mii_mpd_rev == 1 || sc->mii_mpd_rev == 3)
799 brgphy_bcm5401_dspcode(sc); 800 brgphy_bcm5401_dspcode(sc);
800 break; 801 break;
801 case MII_MODEL_BROADCOM_BCM5411: 802 case MII_MODEL_BROADCOM_BCM5411:
802 brgphy_bcm5411_dspcode(sc); 803 brgphy_bcm5411_dspcode(sc);
803 break; 804 break;
804 case MII_MODEL_BROADCOM_BCM5421: 805 case MII_MODEL_BROADCOM_BCM5421:
805 brgphy_bcm5421_dspcode(sc); 806 brgphy_bcm5421_dspcode(sc);
806 break; 807 break;
807 case MII_MODEL_BROADCOM_BCM54K2: 808 case MII_MODEL_BROADCOM_BCM54K2:
808 brgphy_bcm54k2_dspcode(sc); 809 brgphy_bcm54k2_dspcode(sc);
809 break; 810 break;
810 } 811 }
811 break; 812 break;
812 case MII_OUI_BROADCOM3: 813 case MII_OUI_BROADCOM3:
813 switch (sc->mii_mpd_model) { 814 switch (sc->mii_mpd_model) {
814 case MII_MODEL_BROADCOM3_BCM5717C: 815 case MII_MODEL_BROADCOM3_BCM5717C:
815 case MII_MODEL_BROADCOM3_BCM5719C: 816 case MII_MODEL_BROADCOM3_BCM5719C:
816 case MII_MODEL_BROADCOM3_BCM5720C: 817 case MII_MODEL_BROADCOM3_BCM5720C:
817 case MII_MODEL_BROADCOM3_BCM57765: 818 case MII_MODEL_BROADCOM3_BCM57765:
818 return; 819 return;
819 } 820 }
820 break; 821 break;
821 default: 822 default:
822 break; 823 break;
823 } 824 }
824 825
825 /* Handle any bge (NetXtreme/NetLink) workarounds. */ 826 /* Handle any bge (NetXtreme/NetLink) workarounds. */
826 if (bsc->sc_isbge) { 827 if (bsc->sc_isbge) {
827 if (!(sc->mii_flags & MIIF_HAVEFIBER)) { 828 if (!(sc->mii_flags & MIIF_HAVEFIBER)) {
828 829
829 if (bsc->sc_phyflags & BGEPHYF_ADC_BUG) 830 if (bsc->sc_phyflags & BGEPHYF_ADC_BUG)
830 brgphy_adc_bug(sc); 831 brgphy_adc_bug(sc);
831 if (bsc->sc_phyflags & BGEPHYF_5704_A0_BUG) 832 if (bsc->sc_phyflags & BGEPHYF_5704_A0_BUG)
832 brgphy_5704_a0_bug(sc); 833 brgphy_5704_a0_bug(sc);
833 if (bsc->sc_phyflags & BGEPHYF_BER_BUG) 834 if (bsc->sc_phyflags & BGEPHYF_BER_BUG)
834 brgphy_ber_bug(sc); 835 brgphy_ber_bug(sc);
835 else if (bsc->sc_phyflags & BGEPHYF_JITTER_BUG) { 836 else if (bsc->sc_phyflags & BGEPHYF_JITTER_BUG) {
836 PHY_WRITE(sc, BRGPHY_MII_AUXCTL, 0x0c00); 837 PHY_WRITE(sc, BRGPHY_MII_AUXCTL, 0x0c00);
837 PHY_WRITE(sc, BRGPHY_MII_DSP_ADDR_REG, 0x000a); 838 PHY_WRITE(sc, BRGPHY_MII_DSP_ADDR_REG, 0x000a);
838 839
839 if (bsc->sc_phyflags 840 if (bsc->sc_phyflags
840 & BGEPHYF_ADJUST_TRIM) { 841 & BGEPHYF_ADJUST_TRIM) {
841 PHY_WRITE(sc, BRGPHY_MII_DSP_RW_PORT, 842 PHY_WRITE(sc, BRGPHY_MII_DSP_RW_PORT,
842 0x110b); 843 0x110b);
843 PHY_WRITE(sc, BRGPHY_TEST1, 844 PHY_WRITE(sc, BRGPHY_TEST1,
844 BRGPHY_TEST1_TRIM_EN | 0x4); 845 BRGPHY_TEST1_TRIM_EN | 0x4);
845 } else { 846 } else {
846 PHY_WRITE(sc, BRGPHY_MII_DSP_RW_PORT, 847 PHY_WRITE(sc, BRGPHY_MII_DSP_RW_PORT,
847 0x010b); 848 0x010b);
848 } 849 }
849 850
850 PHY_WRITE(sc, BRGPHY_MII_AUXCTL, 0x0400); 851 PHY_WRITE(sc, BRGPHY_MII_AUXCTL, 0x0400);
851 } 852 }
852 if (bsc->sc_phyflags & BGEPHYF_CRC_BUG) 853 if (bsc->sc_phyflags & BGEPHYF_CRC_BUG)
853 brgphy_crc_bug(sc); 854 brgphy_crc_bug(sc);
854 855
855 /* Set Jumbo frame settings in the PHY. */ 856 /* Set Jumbo frame settings in the PHY. */
856 if (bsc->sc_phyflags & BGEPHYF_JUMBO_CAPABLE) 857 if (bsc->sc_phyflags & BGEPHYF_JUMBO_CAPABLE)
857 brgphy_jumbo_settings(sc); 858 brgphy_jumbo_settings(sc);
858 859
859 /* Adjust output voltage */ 860 /* Adjust output voltage */
860 if ((sc->mii_mpd_oui == MII_OUI_BROADCOM2) 861 if ((sc->mii_mpd_oui == MII_OUI_BROADCOM2)
861 && (sc->mii_mpd_model == MII_MODEL_BROADCOM2_BCM5906)) 862 && (sc->mii_mpd_model == MII_MODEL_BROADCOM2_BCM5906))
862 PHY_WRITE(sc, BRGPHY_MII_EPHY_PTEST, 0x12); 863 PHY_WRITE(sc, BRGPHY_MII_EPHY_PTEST, 0x12);
863 864
864 /* Enable Ethernet@Wirespeed */ 865 /* Enable Ethernet@Wirespeed */
865 if (!(bsc->sc_phyflags & BGEPHYF_NO_WIRESPEED)) 866 if (!(bsc->sc_phyflags & BGEPHYF_NO_WIRESPEED))
866 brgphy_eth_wirespeed(sc); 867 brgphy_eth_wirespeed(sc);
867 868
868#if 0 869#if 0
869 /* Enable Link LED on Dell boxes */ 870 /* Enable Link LED on Dell boxes */
870 if (bsc->sc_phyflags & BGEPHYF_NO_3LED) { 871 if (bsc->sc_phyflags & BGEPHYF_NO_3LED) {
871 PHY_READ(sc, BRGPHY_MII_PHY_EXTCTL, &reg); 872 PHY_READ(sc, BRGPHY_MII_PHY_EXTCTL, &reg);
872 PHY_WRITE(sc, BRGPHY_MII_PHY_EXTCTL, 873 PHY_WRITE(sc, BRGPHY_MII_PHY_EXTCTL,
873 reg & ~BRGPHY_PHY_EXTCTL_3_LED); 874 reg & ~BRGPHY_PHY_EXTCTL_3_LED);
874 } 875 }
875#endif 876#endif
876 } 877 }
877 /* Handle any bnx (NetXtreme II) workarounds. */ 878 /* Handle any bnx (NetXtreme II) workarounds. */
878 } else if (bsc->sc_isbnx) { 879 } else if (bsc->sc_isbnx) {
879 uint32_t chip_num = _BNX_CHIP_NUM(bsc->sc_chipid); 880 uint32_t chip_num = _BNX_CHIP_NUM(bsc->sc_chipid);
880 uint32_t chip_id = _BNX_CHIP_ID(bsc->sc_chipid); 881 uint32_t chip_id = _BNX_CHIP_ID(bsc->sc_chipid);
881 uint32_t chip_rev = _BNX_CHIP_REV(bsc->sc_chipid); 882 uint32_t chip_rev = _BNX_CHIP_REV(bsc->sc_chipid);
882 883
883 if ((sc->mii_mpd_oui == MII_OUI_BROADCOM2) 884 if ((sc->mii_mpd_oui == MII_OUI_BROADCOM2)
884 && sc->mii_mpd_model == MII_MODEL_BROADCOM2_BCM5708S) { 885 && sc->mii_mpd_model == MII_MODEL_BROADCOM2_BCM5708S) {
885 /* 886 /*
886 * Store autoneg capabilities/results in digital block 887 * Store autoneg capabilities/results in digital block
887 * (Page 0) 888 * (Page 0)
888 */ 889 */
889 PHY_WRITE(sc, BRGPHY_5708S_BLOCK_ADDR, 890 PHY_WRITE(sc, BRGPHY_5708S_BLOCK_ADDR,
890 BRGPHY_5708S_DIG3_PG2); 891 BRGPHY_5708S_DIG3_PG2);
891 PHY_WRITE(sc, BRGPHY_5708S_PG2_DIGCTL_3_0, 892 PHY_WRITE(sc, BRGPHY_5708S_PG2_DIGCTL_3_0,
892 BRGPHY_5708S_PG2_DIGCTL_3_0_USE_IEEE); 893 BRGPHY_5708S_PG2_DIGCTL_3_0_USE_IEEE);
893 PHY_WRITE(sc, BRGPHY_5708S_BLOCK_ADDR, 894 PHY_WRITE(sc, BRGPHY_5708S_BLOCK_ADDR,
894 BRGPHY_5708S_DIG_PG0); 895 BRGPHY_5708S_DIG_PG0);
895 896
896 /* Enable fiber mode and autodetection */ 897 /* Enable fiber mode and autodetection */
897 PHY_READ(sc, BRGPHY_5708S_PG0_1000X_CTL1, &reg); 898 PHY_READ(sc, BRGPHY_5708S_PG0_1000X_CTL1, &reg);
898 PHY_WRITE(sc, BRGPHY_5708S_PG0_1000X_CTL1, reg | 899 PHY_WRITE(sc, BRGPHY_5708S_PG0_1000X_CTL1, reg |
899 BRGPHY_5708S_PG0_1000X_CTL1_AUTODET_EN | 900 BRGPHY_5708S_PG0_1000X_CTL1_AUTODET_EN |
900 BRGPHY_5708S_PG0_1000X_CTL1_FIBER_MODE); 901 BRGPHY_5708S_PG0_1000X_CTL1_FIBER_MODE);
901 902
902 /* Enable parallel detection */ 903 /* Enable parallel detection */
903 PHY_READ(sc, BRGPHY_5708S_PG0_1000X_CTL2, &reg); 904 PHY_READ(sc, BRGPHY_5708S_PG0_1000X_CTL2, &reg);
904 PHY_WRITE(sc, BRGPHY_5708S_PG0_1000X_CTL2, 905 PHY_WRITE(sc, BRGPHY_5708S_PG0_1000X_CTL2,
905 reg | BRGPHY_5708S_PG0_1000X_CTL2_PAR_DET_EN); 906 reg | BRGPHY_5708S_PG0_1000X_CTL2_PAR_DET_EN);
906 907
907 /* 908 /*
908 * Advertise 2.5G support through next page during 909 * Advertise 2.5G support through next page during
909 * autoneg 910 * autoneg
910 */ 911 */
911 if (bsc->sc_phyflags & BNX_PHY_2_5G_CAPABLE_FLAG) { 912 if (bsc->sc_phyflags & BNX_PHY_2_5G_CAPABLE_FLAG) {
912 PHY_READ(sc, BRGPHY_5708S_ANEG_NXT_PG_XMIT1, 913 PHY_READ(sc, BRGPHY_5708S_ANEG_NXT_PG_XMIT1,
913 &reg); 914 &reg);
914 PHY_WRITE(sc, BRGPHY_5708S_ANEG_NXT_PG_XMIT1, 915 PHY_WRITE(sc, BRGPHY_5708S_ANEG_NXT_PG_XMIT1,
915 reg | BRGPHY_5708S_ANEG_NXT_PG_XMIT1_25G); 916 reg | BRGPHY_5708S_ANEG_NXT_PG_XMIT1_25G);
916 } 917 }
917 918
918 /* Increase TX signal amplitude */ 919 /* Increase TX signal amplitude */
919 if ((chip_id == BNX_CHIP_ID_5708_A0) || 920 if ((chip_id == BNX_CHIP_ID_5708_A0) ||
920 (chip_id == BNX_CHIP_ID_5708_B0) || 921 (chip_id == BNX_CHIP_ID_5708_B0) ||
921 (chip_id == BNX_CHIP_ID_5708_B1)) { 922 (chip_id == BNX_CHIP_ID_5708_B1)) {
922 PHY_WRITE(sc, BRGPHY_5708S_BLOCK_ADDR, 923 PHY_WRITE(sc, BRGPHY_5708S_BLOCK_ADDR,
923 BRGPHY_5708S_TX_MISC_PG5); 924 BRGPHY_5708S_TX_MISC_PG5);
924 PHY_READ(sc, BRGPHY_5708S_PG5_TXACTL1, &reg); 925 PHY_READ(sc, BRGPHY_5708S_PG5_TXACTL1, &reg);
925 PHY_WRITE(sc, BRGPHY_5708S_PG5_TXACTL1, 926 PHY_WRITE(sc, BRGPHY_5708S_PG5_TXACTL1,
926 reg & ~BRGPHY_5708S_PG5_TXACTL1_VCM); 927 reg & ~BRGPHY_5708S_PG5_TXACTL1_VCM);
927 PHY_WRITE(sc, BRGPHY_5708S_BLOCK_ADDR, 928 PHY_WRITE(sc, BRGPHY_5708S_BLOCK_ADDR,
928 BRGPHY_5708S_DIG_PG0); 929 BRGPHY_5708S_DIG_PG0);
929 } 930 }
930 931
931 /* 932 /*
932 * Backplanes use special 933 * Backplanes use special
933 * driver/pre-driver/pre-emphasis values. 934 * driver/pre-driver/pre-emphasis values.
934 */ 935 */
935 if ((bsc->sc_shared_hwcfg & BNX_SHARED_HW_CFG_PHY_BACKPLANE) && 936 if ((bsc->sc_shared_hwcfg & BNX_SHARED_HW_CFG_PHY_BACKPLANE) &&
936 (bsc->sc_port_hwcfg & BNX_PORT_HW_CFG_CFG_TXCTL3_MASK)) { 937 (bsc->sc_port_hwcfg & BNX_PORT_HW_CFG_CFG_TXCTL3_MASK)) {
937 PHY_WRITE(sc, BRGPHY_5708S_BLOCK_ADDR, 938 PHY_WRITE(sc, BRGPHY_5708S_BLOCK_ADDR,
938 BRGPHY_5708S_TX_MISC_PG5); 939 BRGPHY_5708S_TX_MISC_PG5);
939 PHY_WRITE(sc, BRGPHY_5708S_PG5_TXACTL3, 940 PHY_WRITE(sc, BRGPHY_5708S_PG5_TXACTL3,
940 bsc->sc_port_hwcfg & 941 bsc->sc_port_hwcfg &
941 BNX_PORT_HW_CFG_CFG_TXCTL3_MASK); 942 BNX_PORT_HW_CFG_CFG_TXCTL3_MASK);
942 PHY_WRITE(sc, BRGPHY_5708S_BLOCK_ADDR, 943 PHY_WRITE(sc, BRGPHY_5708S_BLOCK_ADDR,
943 BRGPHY_5708S_DIG_PG0); 944 BRGPHY_5708S_DIG_PG0);
944 } 945 }
945 } else if ((sc->mii_mpd_oui == MII_OUI_BROADCOM2) 946 } else if ((sc->mii_mpd_oui == MII_OUI_BROADCOM2)
946 && (sc->mii_mpd_model == MII_MODEL_BROADCOM2_BCM5709S)) { 947 && (sc->mii_mpd_model == MII_MODEL_BROADCOM2_BCM5709S)) {
947 /* Select the SerDes Digital block of the AN MMD. */ 948 /* Select the SerDes Digital block of the AN MMD. */
948 PHY_WRITE(sc, BRGPHY_BLOCK_ADDR, 949 PHY_WRITE(sc, BRGPHY_BLOCK_ADDR,
949 BRGPHY_BLOCK_ADDR_SERDES_DIG); 950 BRGPHY_BLOCK_ADDR_SERDES_DIG);
950 951
951 PHY_READ(sc, BRGPHY_SERDES_DIG_1000X_CTL1, &reg); 952 PHY_READ(sc, BRGPHY_SERDES_DIG_1000X_CTL1, &reg);
952 PHY_WRITE(sc, BRGPHY_SERDES_DIG_1000X_CTL1, 953 PHY_WRITE(sc, BRGPHY_SERDES_DIG_1000X_CTL1,
953 (reg & ~BRGPHY_SD_DIG_1000X_CTL1_AUTODET) | 954 (reg & ~BRGPHY_SD_DIG_1000X_CTL1_AUTODET) |
954 BRGPHY_SD_DIG_1000X_CTL1_FIBER); 955 BRGPHY_SD_DIG_1000X_CTL1_FIBER);
955 956
956 if (bsc->sc_phyflags & BNX_PHY_2_5G_CAPABLE_FLAG) { 957 if (bsc->sc_phyflags & BNX_PHY_2_5G_CAPABLE_FLAG) {
957 /* Select the Over 1G block of the AN MMD. */ 958 /* Select the Over 1G block of the AN MMD. */
958 PHY_WRITE(sc, BRGPHY_BLOCK_ADDR, 959 PHY_WRITE(sc, BRGPHY_BLOCK_ADDR,
959 BRGPHY_BLOCK_ADDR_OVER_1G); 960 BRGPHY_BLOCK_ADDR_OVER_1G);
960 961
961 /* 962 /*
962 * Enable autoneg "Next Page" to advertise 963 * Enable autoneg "Next Page" to advertise
963 * 2.5G support. 964 * 2.5G support.
964 */ 965 */
965 PHY_READ(sc, BRGPHY_OVER_1G_UNFORMAT_PG1, 966 PHY_READ(sc, BRGPHY_OVER_1G_UNFORMAT_PG1,
966 &reg); 967 &reg);
967 PHY_WRITE(sc, BRGPHY_OVER_1G_UNFORMAT_PG1, 968 PHY_WRITE(sc, BRGPHY_OVER_1G_UNFORMAT_PG1,
968 reg | BRGPHY_5708S_ANEG_NXT_PG_XMIT1_25G); 969 reg | BRGPHY_5708S_ANEG_NXT_PG_XMIT1_25G);
969 } 970 }
970 971
971 /* 972 /*
972 * Select the Multi-Rate Backplane Ethernet block of 973 * Select the Multi-Rate Backplane Ethernet block of
973 * the AN MMD. 974 * the AN MMD.
974 */ 975 */
975 PHY_WRITE(sc, BRGPHY_BLOCK_ADDR, 976 PHY_WRITE(sc, BRGPHY_BLOCK_ADDR,
976 BRGPHY_BLOCK_ADDR_MRBE); 977 BRGPHY_BLOCK_ADDR_MRBE);
977 978
978 /* Enable MRBE speed autoneg. */ 979 /* Enable MRBE speed autoneg. */
979 PHY_READ(sc, BRGPHY_MRBE_MSG_PG5_NP, &reg); 980 PHY_READ(sc, BRGPHY_MRBE_MSG_PG5_NP, &reg);
980 PHY_WRITE(sc, BRGPHY_MRBE_MSG_PG5_NP, 981 PHY_WRITE(sc, BRGPHY_MRBE_MSG_PG5_NP,
981 reg | BRGPHY_MRBE_MSG_PG5_NP_MBRE | 982 reg | BRGPHY_MRBE_MSG_PG5_NP_MBRE |
982 BRGPHY_MRBE_MSG_PG5_NP_T2); 983 BRGPHY_MRBE_MSG_PG5_NP_T2);
983 984
984 /* Select the Clause 73 User B0 block of the AN MMD. */ 985 /* Select the Clause 73 User B0 block of the AN MMD. */
985 PHY_WRITE(sc, BRGPHY_BLOCK_ADDR, 986 PHY_WRITE(sc, BRGPHY_BLOCK_ADDR,
986 BRGPHY_BLOCK_ADDR_CL73_USER_B0); 987 BRGPHY_BLOCK_ADDR_CL73_USER_B0);
987 988
988 /* Enable MRBE speed autoneg. */ 989 /* Enable MRBE speed autoneg. */
989 PHY_WRITE(sc, BRGPHY_CL73_USER_B0_MBRE_CTL1, 990 PHY_WRITE(sc, BRGPHY_CL73_USER_B0_MBRE_CTL1,
990 BRGPHY_CL73_USER_B0_MBRE_CTL1_NP_AFT_BP | 991 BRGPHY_CL73_USER_B0_MBRE_CTL1_NP_AFT_BP |
991 BRGPHY_CL73_USER_B0_MBRE_CTL1_STA_MGR | 992 BRGPHY_CL73_USER_B0_MBRE_CTL1_STA_MGR |
992 BRGPHY_CL73_USER_B0_MBRE_CTL1_ANEG); 993 BRGPHY_CL73_USER_B0_MBRE_CTL1_ANEG);
993 994
994 PHY_WRITE(sc, BRGPHY_BLOCK_ADDR, 995 PHY_WRITE(sc, BRGPHY_BLOCK_ADDR,
995 BRGPHY_BLOCK_ADDR_COMBO_IEEE0); 996 BRGPHY_BLOCK_ADDR_COMBO_IEEE0);
996 997
997 } else if (chip_num == BNX_CHIP_NUM_5709) { 998 } else if (chip_num == BNX_CHIP_NUM_5709) {
998 if ((chip_rev == BNX_CHIP_REV_Ax) || 999 if ((chip_rev == BNX_CHIP_REV_Ax) ||
999 (chip_rev == BNX_CHIP_REV_Bx)) 1000 (chip_rev == BNX_CHIP_REV_Bx))
1000 brgphy_disable_early_dac(sc); 1001 brgphy_disable_early_dac(sc);
1001 1002
1002 /* Set Jumbo frame settings in the PHY. */ 1003 /* Set Jumbo frame settings in the PHY. */
1003 brgphy_jumbo_settings(sc); 1004 brgphy_jumbo_settings(sc);
1004 1005
1005 /* Enable Ethernet@Wirespeed */ 1006 /* Enable Ethernet@Wirespeed */
1006 brgphy_eth_wirespeed(sc); 1007 brgphy_eth_wirespeed(sc);
1007 } else { 1008 } else {
1008 if (!(sc->mii_flags & MIIF_HAVEFIBER)) { 1009 if (!(sc->mii_flags & MIIF_HAVEFIBER)) {
1009 brgphy_ber_bug(sc); 1010 brgphy_ber_bug(sc);
1010 1011
1011 /* Set Jumbo frame settings in the PHY. */ 1012 /* Set Jumbo frame settings in the PHY. */
1012 brgphy_jumbo_settings(sc); 1013 brgphy_jumbo_settings(sc);
1013 1014
1014 /* Enable Ethernet@Wirespeed */ 1015 /* Enable Ethernet@Wirespeed */
1015 brgphy_eth_wirespeed(sc); 1016 brgphy_eth_wirespeed(sc);
1016 } 1017 }
1017 } 1018 }
1018 } 1019 }
1019} 1020}
1020 1021
1021/* Turn off tap power management on 5401. */ 1022/* Turn off tap power management on 5401. */
1022static void 1023static void
1023brgphy_bcm5401_dspcode(struct mii_softc *sc) 1024brgphy_bcm5401_dspcode(struct mii_softc *sc)
1024{ 1025{
1025 static const struct { 1026 static const struct {
1026 int reg; 1027 int reg;
1027 uint16_t val; 1028 uint16_t val;
1028 } dspcode[] = { 1029 } dspcode[] = {
1029 { BRGPHY_MII_AUXCTL, 0x0c20 }, 1030 { BRGPHY_MII_AUXCTL, 0x0c20 },
1030 { BRGPHY_MII_DSP_ADDR_REG, 0x0012 }, 1031 { BRGPHY_MII_DSP_ADDR_REG, 0x0012 },
1031 { BRGPHY_MII_DSP_RW_PORT, 0x1804 }, 1032 { BRGPHY_MII_DSP_RW_PORT, 0x1804 },
1032 { BRGPHY_MII_DSP_ADDR_REG, 0x0013 }, 1033 { BRGPHY_MII_DSP_ADDR_REG, 0x0013 },
1033 { BRGPHY_MII_DSP_RW_PORT, 0x1204 }, 1034 { BRGPHY_MII_DSP_RW_PORT, 0x1204 },
1034 { BRGPHY_MII_DSP_ADDR_REG, 0x8006 }, 1035 { BRGPHY_MII_DSP_ADDR_REG, 0x8006 },
1035 { BRGPHY_MII_DSP_RW_PORT, 0x0132 }, 1036 { BRGPHY_MII_DSP_RW_PORT, 0x0132 },
1036 { BRGPHY_MII_DSP_ADDR_REG, 0x8006 }, 1037 { BRGPHY_MII_DSP_ADDR_REG, 0x8006 },
1037 { BRGPHY_MII_DSP_RW_PORT, 0x0232 }, 1038 { BRGPHY_MII_DSP_RW_PORT, 0x0232 },
1038 { BRGPHY_MII_DSP_ADDR_REG, 0x201f }, 1039 { BRGPHY_MII_DSP_ADDR_REG, 0x201f },
1039 { BRGPHY_MII_DSP_RW_PORT, 0x0a20 }, 1040 { BRGPHY_MII_DSP_RW_PORT, 0x0a20 },
1040 { 0, 0 }, 1041 { 0, 0 },
1041 }; 1042 };
1042 int i; 1043 int i;
1043 1044
1044 for (i = 0; dspcode[i].reg != 0; i++) 1045 for (i = 0; dspcode[i].reg != 0; i++)
1045 PHY_WRITE(sc, dspcode[i].reg, dspcode[i].val); 1046 PHY_WRITE(sc, dspcode[i].reg, dspcode[i].val);
1046 delay(40); 1047 delay(40);
1047} 1048}
1048 1049
1049static void 1050static void
1050brgphy_bcm5411_dspcode(struct mii_softc *sc) 1051brgphy_bcm5411_dspcode(struct mii_softc *sc)
1051{ 1052{
1052 static const struct { 1053 static const struct {
1053 int reg; 1054 int reg;
1054 uint16_t val; 1055 uint16_t val;
1055 } dspcode[] = { 1056 } dspcode[] = {
1056 { 0x1c, 0x8c23 }, 1057 { 0x1c, 0x8c23 },
1057 { 0x1c, 0x8ca3 }, 1058 { 0x1c, 0x8ca3 },
1058 { 0x1c, 0x8c23 }, 1059 { 0x1c, 0x8c23 },
1059 { 0, 0 }, 1060 { 0, 0 },
1060 }; 1061 };
1061 int i; 1062 int i;
1062 1063
1063 for (i = 0; dspcode[i].reg != 0; i++) 1064 for (i = 0; dspcode[i].reg != 0; i++)
1064 PHY_WRITE(sc, dspcode[i].reg, dspcode[i].val); 1065 PHY_WRITE(sc, dspcode[i].reg, dspcode[i].val);
1065} 1066}
1066 1067
1067void 1068void
1068brgphy_bcm5421_dspcode(struct mii_softc *sc) 1069brgphy_bcm5421_dspcode(struct mii_softc *sc)
1069{ 1070{
1070 uint16_t data; 1071 uint16_t data;
1071 1072
1072 /* Set Class A mode */ 1073 /* Set Class A mode */
1073 PHY_WRITE(sc, BRGPHY_MII_AUXCTL, 0x1007); 1074 PHY_WRITE(sc, BRGPHY_MII_AUXCTL, 0x1007);
1074 PHY_READ(sc, BRGPHY_MII_AUXCTL, &data); 1075 PHY_READ(sc, BRGPHY_MII_AUXCTL, &data);
1075 PHY_WRITE(sc, BRGPHY_MII_AUXCTL, data | 0x0400); 1076 PHY_WRITE(sc, BRGPHY_MII_AUXCTL, data | 0x0400);
1076 1077
1077 /* Set FFE gamma override to -0.125 */ 1078 /* Set FFE gamma override to -0.125 */
1078 PHY_WRITE(sc, BRGPHY_MII_AUXCTL, 0x0007); 1079 PHY_WRITE(sc, BRGPHY_MII_AUXCTL, 0x0007);
1079 PHY_READ(sc, BRGPHY_MII_AUXCTL, &data); 1080 PHY_READ(sc, BRGPHY_MII_AUXCTL, &data);
1080 PHY_WRITE(sc, BRGPHY_MII_AUXCTL, data | 0x0800); 1081 PHY_WRITE(sc, BRGPHY_MII_AUXCTL, data | 0x0800);
1081 PHY_WRITE(sc, BRGPHY_MII_DSP_ADDR_REG, 0x000a); 1082 PHY_WRITE(sc, BRGPHY_MII_DSP_ADDR_REG, 0x000a);
1082 PHY_READ(sc, BRGPHY_MII_DSP_RW_PORT, &data); 1083 PHY_READ(sc, BRGPHY_MII_DSP_RW_PORT, &data);
1083 PHY_WRITE(sc, BRGPHY_MII_DSP_RW_PORT, data | 0x0200); 1084 PHY_WRITE(sc, BRGPHY_MII_DSP_RW_PORT, data | 0x0200);
1084} 1085}
1085 1086
1086void 1087void
1087brgphy_bcm54k2_dspcode(struct mii_softc *sc) 1088brgphy_bcm54k2_dspcode(struct mii_softc *sc)
1088{ 1089{
1089 static const struct { 1090 static const struct {
1090 int reg; 1091 int reg;
1091 uint16_t val; 1092 uint16_t val;
1092 } dspcode[] = { 1093 } dspcode[] = {
1093 { 4, 0x01e1 }, 1094 { 4, 0x01e1 },
1094 { 9, 0x0300 }, 1095 { 9, 0x0300 },
1095 { 0, 0 }, 1096 { 0, 0 },
1096 }; 1097 };
1097 int i; 1098 int i;
1098 1099
1099 for (i = 0; dspcode[i].reg != 0; i++) 1100 for (i = 0; dspcode[i].reg != 0; i++)
1100 PHY_WRITE(sc, dspcode[i].reg, dspcode[i].val); 1101 PHY_WRITE(sc, dspcode[i].reg, dspcode[i].val);
1101} 1102}
1102 1103
1103static void 1104static void
1104brgphy_adc_bug(struct mii_softc *sc) 1105brgphy_adc_bug(struct mii_softc *sc)
1105{ 1106{
1106 static const struct { 1107 static const struct {
1107 int reg; 1108 int reg;
1108 uint16_t val; 1109 uint16_t val;
1109 } dspcode[] = { 1110 } dspcode[] = {
1110 { BRGPHY_MII_AUXCTL, 0x0c00 }, 1111 { BRGPHY_MII_AUXCTL, 0x0c00 },
1111 { BRGPHY_MII_DSP_ADDR_REG, 0x201f }, 1112 { BRGPHY_MII_DSP_ADDR_REG, 0x201f },
1112 { BRGPHY_MII_DSP_RW_PORT, 0x2aaa }, 1113 { BRGPHY_MII_DSP_RW_PORT, 0x2aaa },
1113 { BRGPHY_MII_DSP_ADDR_REG, 0x000a }, 1114 { BRGPHY_MII_DSP_ADDR_REG, 0x000a },
1114 { BRGPHY_MII_DSP_RW_PORT, 0x0323 }, 1115 { BRGPHY_MII_DSP_RW_PORT, 0x0323 },
1115 { BRGPHY_MII_AUXCTL, 0x0400 }, 1116 { BRGPHY_MII_AUXCTL, 0x0400 },
1116 { 0, 0 }, 1117 { 0, 0 },
1117 }; 1118 };
1118 int i; 1119 int i;
1119 1120
1120 for (i = 0; dspcode[i].reg != 0; i++) 1121 for (i = 0; dspcode[i].reg != 0; i++)
1121 PHY_WRITE(sc, dspcode[i].reg, dspcode[i].val); 1122 PHY_WRITE(sc, dspcode[i].reg, dspcode[i].val);
1122} 1123}
1123 1124
1124static void 1125static void
1125brgphy_5704_a0_bug(struct mii_softc *sc) 1126brgphy_5704_a0_bug(struct mii_softc *sc)
1126{ 1127{
1127 static const struct { 1128 static const struct {
1128 int reg; 1129 int reg;
1129 uint16_t val; 1130 uint16_t val;
1130 } dspcode[] = { 1131 } dspcode[] = {
1131 { 0x1c, 0x8d68 }, 1132 { 0x1c, 0x8d68 },
1132 { 0x1c, 0x8d68 }, 1133 { 0x1c, 0x8d68 },
1133 { 0, 0 }, 1134 { 0, 0 },
1134 }; 1135 };
1135 int i; 1136 int i;
1136 1137
1137 for (i = 0; dspcode[i].reg != 0; i++) 1138 for (i = 0; dspcode[i].reg != 0; i++)
1138 PHY_WRITE(sc, dspcode[i].reg, dspcode[i].val); 1139 PHY_WRITE(sc, dspcode[i].reg, dspcode[i].val);
1139} 1140}
1140 1141
1141static void 1142static void
1142brgphy_ber_bug(struct mii_softc *sc) 1143brgphy_ber_bug(struct mii_softc *sc)
1143{ 1144{
1144 static const struct { 1145 static const struct {
1145 int reg; 1146 int reg;
1146 uint16_t val; 1147 uint16_t val;
1147 } dspcode[] = { 1148 } dspcode[] = {
1148 { BRGPHY_MII_AUXCTL, 0x0c00 }, 1149 { BRGPHY_MII_AUXCTL, 0x0c00 },
1149 { BRGPHY_MII_DSP_ADDR_REG, 0x000a }, 1150 { BRGPHY_MII_DSP_ADDR_REG, 0x000a },
1150 { BRGPHY_MII_DSP_RW_PORT, 0x310b }, 1151 { BRGPHY_MII_DSP_RW_PORT, 0x310b },
1151 { BRGPHY_MII_DSP_ADDR_REG, 0x201f }, 1152 { BRGPHY_MII_DSP_ADDR_REG, 0x201f },
1152 { BRGPHY_MII_DSP_RW_PORT, 0x9506 }, 1153 { BRGPHY_MII_DSP_RW_PORT, 0x9506 },
1153 { BRGPHY_MII_DSP_ADDR_REG, 0x401f }, 1154 { BRGPHY_MII_DSP_ADDR_REG, 0x401f },
1154 { BRGPHY_MII_DSP_RW_PORT, 0x14e2 }, 1155 { BRGPHY_MII_DSP_RW_PORT, 0x14e2 },
1155 { BRGPHY_MII_AUXCTL, 0x0400 }, 1156 { BRGPHY_MII_AUXCTL, 0x0400 },
1156 { 0, 0 }, 1157 { 0, 0 },
1157 }; 1158 };
1158 int i; 1159 int i;
1159 1160
1160 for (i = 0; dspcode[i].reg != 0; i++) 1161 for (i = 0; dspcode[i].reg != 0; i++)
1161 PHY_WRITE(sc, dspcode[i].reg, dspcode[i].val); 1162 PHY_WRITE(sc, dspcode[i].reg, dspcode[i].val);
1162} 1163}
1163 1164
1164/* BCM5701 A0/B0 CRC bug workaround */ 1165/* BCM5701 A0/B0 CRC bug workaround */
1165void 1166void
1166brgphy_crc_bug(struct mii_softc *sc) 1167brgphy_crc_bug(struct mii_softc *sc)
1167{ 1168{
1168 static const struct { 1169 static const struct {
1169 int reg; 1170 int reg;
1170 uint16_t val; 1171 uint16_t val;
1171 } dspcode[] = { 1172 } dspcode[] = {
1172 { BRGPHY_MII_DSP_ADDR_REG, 0x0a75 }, 1173 { BRGPHY_MII_DSP_ADDR_REG, 0x0a75 },
1173 { 0x1c, 0x8c68 }, 1174 { 0x1c, 0x8c68 },
1174 { 0x1c, 0x8d68 }, 1175 { 0x1c, 0x8d68 },
1175 { 0x1c, 0x8c68 }, 1176 { 0x1c, 0x8c68 },
1176 { 0, 0 }, 1177 { 0, 0 },
1177 }; 1178 };
1178 int i; 1179 int i;
1179 1180
cvs diff -r1.153.2.5 -r1.153.2.6 src/sys/dev/mii/miidevs (switch to unified diff)

--- src/sys/dev/mii/miidevs 2020/03/19 19:21:37 1.153.2.5
+++ src/sys/dev/mii/miidevs 2020/04/14 16:43:12 1.153.2.6
@@ -1,405 +1,413 @@ @@ -1,405 +1,413 @@
1$NetBSD: miidevs,v 1.153.2.5 2020/03/19 19:21:37 martin Exp $ 1$NetBSD: miidevs,v 1.153.2.6 2020/04/14 16:43:12 martin Exp $
2 2
3/*- 3/*-
4 * Copyright (c) 1998, 1999 The NetBSD Foundation, Inc. 4 * Copyright (c) 1998, 1999 The NetBSD Foundation, Inc.
5 * All rights reserved. 5 * All rights reserved.
6 * 6 *
7 * This code is derived from software contributed to The NetBSD Foundation 7 * This code is derived from software contributed to The NetBSD Foundation
8 * by Jason R. Thorpe of the Numerical Aerospace Simulation Facility, 8 * by Jason R. Thorpe of the Numerical Aerospace Simulation Facility,
9 * NASA Ames Research Center. 9 * NASA Ames Research Center.
10 * 10 *
11 * Redistribution and use in source and binary forms, with or without 11 * Redistribution and use in source and binary forms, with or without
12 * modification, are permitted provided that the following conditions 12 * modification, are permitted provided that the following conditions
13 * are met: 13 * are met:
14 * 1. Redistributions of source code must retain the above copyright 14 * 1. Redistributions of source code must retain the above copyright
15 * notice, this list of conditions and the following disclaimer. 15 * notice, this list of conditions and the following disclaimer.
16 * 2. Redistributions in binary form must reproduce the above copyright 16 * 2. Redistributions in binary form must reproduce the above copyright
17 * notice, this list of conditions and the following disclaimer in the 17 * notice, this list of conditions and the following disclaimer in the
18 * documentation and/or other materials provided with the distribution. 18 * documentation and/or other materials provided with the distribution.
19 * 19 *
20 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 20 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
21 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 21 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
22 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 22 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
23 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 23 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
24 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 24 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
25 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 25 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
26 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 26 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
27 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 27 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
28 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 28 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
29 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 29 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
30 * POSSIBILITY OF SUCH DAMAGE. 30 * POSSIBILITY OF SUCH DAMAGE.
31 */ 31 */
32 32
33/* 33/*
34 * List of known MII OUIs. 34 * List of known MII OUIs.
35 * For a complete list see http://standards.ieee.org/regauth/oui/ 35 * For a complete list see http://standards.ieee.org/regauth/oui/
36 * 36 *
37 * XXX Vendors do obviously not agree how OUIs (24 bit) are mapped 37 * XXX Vendors do obviously not agree how OUIs (24 bit) are mapped
38 * to the 22 bits available in the id registers. 38 * to the 22 bits available in the id registers.
39 * IEEE 802.3u-1995, subclause 22.2.4.3.1, figure 22-12, depicts the right 39 * IEEE 802.3u-1995, subclause 22.2.4.3.1, figure 22-12, depicts the right
40 * mapping; the bit positions are defined in IEEE 802-1990, figure 5.2. 40 * mapping; the bit positions are defined in IEEE 802-1990, figure 5.2.
41 * (There is a formal 802.3 interpretation, number 1-07/98 of July 09 1998, 41 * (There is a formal 802.3 interpretation, number 1-07/98 of July 09 1998,
42 * about this.) 42 * about this.)
43 * The MII_OUI() macro in "miivar.h" reflects this. 43 * The MII_OUI() macro in "miivar.h" reflects this.
44 * If a vendor uses a different mapping, an "xx" prefixed OUI is defined here 44 * If a vendor uses a different mapping, an "xx" prefixed OUI is defined here
45 * which is mangled accordingly to compensate. 45 * which is mangled accordingly to compensate.
46 */ 46 */
47 47
48/* 48/*
49 * Use "make -f Makefile.miidevs" to regenerate miidevs.h and miidevs_data.h 49 * Use "make -f Makefile.miidevs" to regenerate miidevs.h and miidevs_data.h
50 */ 50 */
51 51
52oui AMD 0x00001a Advanced Micro Devices 52oui AMD 0x00001a Advanced Micro Devices
53oui TRIDIUM 0x0001f0 Tridium 53oui TRIDIUM 0x0001f0 Tridium
54oui DATATRACK 0x0002c6 Data Track Technology 54oui DATATRACK 0x0002c6 Data Track Technology
55oui AGERE 0x00053d Agere 55oui AGERE 0x00053d Agere
 56oui QUAKE 0x000897 Quake Technologies
56oui BANKSPEED 0x0006b8 Bankspeed Pty 57oui BANKSPEED 0x0006b8 Bankspeed Pty
57oui NETEXCELL 0x0008bb NetExcell 58oui NETEXCELL 0x0008bb NetExcell
58oui NETAS 0x0009c3 Netas 59oui NETAS 0x0009c3 Netas
59oui BROADCOM2 0x000af7 Broadcom Corporation 60oui BROADCOM2 0x000af7 Broadcom Corporation
 61oui AELUROS 0x000b25 Aeluros
60oui RALINK 0x000c43 Ralink Technology 62oui RALINK 0x000c43 Ralink Technology
61oui ASIX 0x000ec6 ASIX 63oui ASIX 0x000ec6 ASIX
62oui BROADCOM 0x001018 Broadcom Corporation 64oui BROADCOM 0x001018 Broadcom Corporation
63oui MICREL 0x0010a1 Micrel 65oui MICREL 0x0010a1 Micrel
64oui ALTIMA 0x0010a9 Altima Communications 66oui ALTIMA 0x0010a9 Altima Communications
65oui ENABLESEMI 0x0010dd Enable Semiconductor 67oui ENABLESEMI 0x0010dd Enable Semiconductor
66oui SUNPLUS 0x001105 Sunplus Technology 68oui SUNPLUS 0x001105 Sunplus Technology
67oui TERANETICS 0x0014a6 Teranetics 69oui TERANETICS 0x0014a6 Teranetics
68oui RALINK2 0x0017a5 Ralink Technology 70oui RALINK2 0x0017a5 Ralink Technology
69oui AQUANTIA 0x0017b6 Aquantia Corporation 71oui AQUANTIA 0x0017b6 Aquantia Corporation
70oui BROADCOM3 0x001be9 Broadcom Corporation 72oui BROADCOM3 0x001be9 Broadcom Corporation
71oui LEVEL1 0x00207b Level 1 73oui LEVEL1 0x00207b Level 1
72oui VIA 0x004063 VIA Technologies 
73oui MARVELL 0x005043 Marvell Semiconductor 74oui MARVELL 0x005043 Marvell Semiconductor
74oui QUALSEMI 0x006051 Quality Semiconductor 75oui QUALSEMI 0x006051 Quality Semiconductor
75oui AMLOGIC 0x006051 Amlogic 76oui AMLOGIC 0x006051 Amlogic
76oui DAVICOM 0x00606e Davicom Semiconductor 77oui DAVICOM 0x00606e Davicom Semiconductor
77oui SMSC 0x00800f SMSC 78oui SMSC 0x00800f SMSC
78oui SEEQ 0x00a07d Seeq 79oui SEEQ 0x00a07d Seeq
79oui ICS 0x00a0be Integrated Circuit Systems 80oui ICS 0x00a0be Integrated Circuit Systems
80oui INTEL 0x00aa00 Intel 81oui INTEL 0x00aa00 Intel
81oui TSC 0x00c039 TDK Semiconductor 82oui TSC 0x00c039 TDK Semiconductor
82oui MYSON 0x00c0b4 Myson Technology 83oui MYSON 0x00c0b4 Myson Technology
83oui ATTANSIC 0x00c82e Attansic Technology 84oui ATTANSIC 0x00c82e Attansic Technology
84oui RDC 0x00d02d RDC Semiconductor 
85oui JMICRON 0x00d831 JMicron 85oui JMICRON 0x00d831 JMicron
86oui PMCSIERRA 0x00e004 PMC-Sierra 86oui PMCSIERRA 0x00e004 PMC-Sierra
87oui SIS 0x00e006 Silicon Integrated Systems 87oui SIS 0x00e006 Silicon Integrated Systems
88oui REALTEK 0x00e04c RealTek 88oui REALTEK 0x00e04c RealTek
89oui ADMTEK 0x00e092 ADMtek 89oui ADMTEK 0x00e092 ADMtek
90oui XAQTI 0x00e0ae XaQti Corp. 90oui XAQTI 0x00e0ae XaQti Corp.
91oui NATSEMI 0x080017 National Semiconductor 91oui NATSEMI 0x080017 National Semiconductor
92oui TI 0x080028 Texas Instruments 92oui TI 0x080028 Texas Instruments
93oui BROADCOM4 0x18c086 Broadcom Corporation 93oui BROADCOM4 0x18c086 Broadcom Corporation
94oui RENESAS 0x749050 Renesas 94oui RENESAS 0x749050 Renesas
95 95
96/* Unregistered or wrong OUI */ 96/* Unregistered or wrong OUI */
97oui yyREALTEK 0x000004 Realtek 97oui yyREALTEK 0x000004 Realtek
98oui yyAMD 0x000058 Advanced Micro Devices 98oui yyAMD 0x000058 Advanced Micro Devices
 99oui xxVIA 0x0002c6 VIA Technologies
99oui xxMYSON 0x00032d Myson Technology 100oui xxMYSON 0x00032d Myson Technology
100oui xxTSC 0x00039c TDK Semiconductor 101oui xxTSC 0x00039c TDK Semiconductor
101oui xxASIX 0x000674 Asix Semiconductor 102oui xxASIX 0x000674 Asix Semiconductor
102oui xxDAVICOM 0x000676 Davicom Semiconductor 103oui xxDAVICOM 0x000676 Davicom Semiconductor
103oui xxAMLOGIC 0x00068a Amlogic 104oui xxAMLOGIC 0x00068a Amlogic
104oui xxQUALSEMI 0x00068a Quality Semiconductor 105oui xxQUALSEMI 0x00068a Quality Semiconductor
105oui xxREALTEK 0x000732 Realtek 106oui xxREALTEK 0x000732 Realtek
106oui xxBROADCOM 0x000818 Broadcom Corporation 107oui xxBROADCOM 0x000818 Broadcom Corporation
107oui xxPMCSIERRA 0x0009c0 PMC-Sierra 108oui xxPMCSIERRA 0x0009c0 PMC-Sierra
108oui xxICPLUS 0x0009c3 IC Plus Corp. 109oui xxICPLUS 0x0009c3 IC Plus Corp.
109oui xxMARVELL 0x000ac2 Marvell Semiconductor 110oui xxMARVELL 0x000ac2 Marvell Semiconductor
110oui xxINTEL 0x001f00 Intel 111oui xxINTEL 0x001f00 Intel
111oui xxBROADCOM_ALT1 0x0050ef Broadcom Corporation 112oui xxBROADCOM_ALT1 0x0050ef Broadcom Corporation
112oui yyINTEL 0x005500 Intel 113oui yyINTEL 0x005500 Intel
113oui yyASIX 0x007063 Asix Semiconductor 114oui yyASIX 0x007063 Asix Semiconductor
114oui xxVITESSE 0x008083 Vitesse Semiconductor 115oui xxVITESSE 0x008083 Vitesse Semiconductor
115oui xxPMCSIERRA2 0x009057 PMC-Sierra 116oui xxPMCSIERRA2 0x009057 PMC-Sierra
116oui xxCICADA 0x00c08f Cicada Semiconductor 117oui xxCICADA 0x00c08f Cicada Semiconductor
 118oui xxRDC 0x00d02d RDC Semiconductor
117oui xxNATSEMI 0x1000e8 National Semiconductor 119oui xxNATSEMI 0x1000e8 National Semiconductor
118oui xxLEVEL1 0x782000 Level 1 120oui xxLEVEL1 0x782000 Level 1
119oui xxXAQTI 0xace000 XaQti Corp. 121oui xxXAQTI 0xace000 XaQti Corp.
120 122
121/* 123/*
122 * List of known models. Grouped by oui. 124 * List of known models. Grouped by oui.
123 */ 125 */
124 126
125/* 127/*
126 * Agere PHYs 128 * Agere PHYs
127 */ 129 */
128model AGERE ET1011 0x0001 ET1011 10/100/1000baseT PHY 130model AGERE ET1011 0x0001 ET1011 10/100/1000baseT PHY
129model AGERE ET1011C 0x0004 ET1011C 10/100/1000baseT PHY 131model AGERE ET1011C 0x0004 ET1011C 10/100/1000baseT PHY
130 132
131/* Asix semiconductor PHYs */ 133/* Asix semiconductor PHYs */
132model xxASIX AX88X9X 0x0031 Ax88x9x internal PHY 134model xxASIX AX88X9X 0x0031 Ax88x9x internal PHY
133model yyASIX AX88772 0x0001 AX88772 internal PHY 135model yyASIX AX88772 0x0001 AX88772 internal PHY
134model yyASIX AX88772A 0x0006 AX88772A internal PHY 136model yyASIX AX88772A 0x0006 AX88772A internal PHY
135model yyASIX AX88772B 0x0008 AX88772B internal PHY 137model yyASIX AX88772B 0x0008 AX88772B internal PHY
136 138
137/* Altima Communications PHYs */ 139/* Altima Communications PHYs */
138/* Don't know the model for ACXXX */ 140/* Don't know the model for ACXXX */
139model ALTIMA ACXXX 0x0001 ACXXX 10/100 media interface 141model ALTIMA ACXXX 0x0001 ACXXX 10/100 media interface
140model ALTIMA AC101L 0x0012 AC101L 10/100 media interface 142model ALTIMA AC101L 0x0012 AC101L 10/100 media interface
141model ALTIMA AC101 0x0021 AC101 10/100 media interface 143model ALTIMA AC101 0x0021 AC101 10/100 media interface
142/* AMD Am79C87[45] have ALTIMA OUI */ 144/* AMD Am79C87[45] have ALTIMA OUI */
143model ALTIMA Am79C875 0x0014 Am79C875 10/100 media interface 145model ALTIMA Am79C875 0x0014 Am79C875 10/100 media interface
144model ALTIMA Am79C874 0x0021 Am79C874 10/100 media interface 146model ALTIMA Am79C874 0x0021 Am79C874 10/100 media interface
145 147
146/* Amlogic PHYs */ 148/* Amlogic PHYs */
147model AMLOGIC GXL 0x0000 Meson GXL internal PHY 149model AMLOGIC GXL 0x0000 Meson GXL internal PHY
148model xxAMLOGIC GXL 0x0000 Meson GXL internal PHY 150model xxAMLOGIC GXL 0x0000 Meson GXL internal PHY
149 151
150/* Attansic/Atheros PHYs */ 152/* Attansic/Atheros PHYs */
151model ATTANSIC L1 0x0001 L1 10/100/1000 PHY 153model ATTANSIC L1 0x0001 L1 10/100/1000 PHY
152model ATTANSIC L2 0x0002 L2 10/100 PHY 154model ATTANSIC L2 0x0002 L2 10/100 PHY
153model ATTANSIC AR8021 0x0004 Atheros AR8021 10/100/1000 PHY 155model ATTANSIC AR8021 0x0004 Atheros AR8021 10/100/1000 PHY
154model ATTANSIC AR8035 0x0007 Atheros AR8035 10/100/1000 PHY 156model ATTANSIC AR8035 0x0007 Atheros AR8035 10/100/1000 PHY
155 157
156/* Advanced Micro Devices PHYs */ 158/* Advanced Micro Devices PHYs */
157/* see Davicom DM9101 for Am79C873 */ 159/* see Davicom DM9101 for Am79C873 */
158model yyAMD 79C972_10T 0x0001 Am79C972 internal 10BASE-T interface 160model yyAMD 79C972_10T 0x0001 Am79C972 internal 10BASE-T interface
159model yyAMD 79c973phy 0x0036 Am79C973 internal 10/100 media interface 161model yyAMD 79c973phy 0x0036 Am79C973 internal 10/100 media interface
160model yyAMD 79c901 0x0037 Am79C901 10BASE-T interface 162model yyAMD 79c901 0x0037 Am79C901 10BASE-T interface
161model yyAMD 79c901home 0x0039 Am79C901 HomePNA 1.0 interface 163model yyAMD 79c901home 0x0039 Am79C901 HomePNA 1.0 interface
162 164
163/* Broadcom Corp. PHYs */ 165/* Broadcom Corp. PHYs */
164model xxBROADCOM 3C905B 0x0012 Broadcom 3c905B internal PHY 166model xxBROADCOM 3C905B 0x0012 Broadcom 3c905B internal PHY
165model xxBROADCOM 3C905C 0x0017 Broadcom 3c905C internal PHY 167model xxBROADCOM 3C905C 0x0017 Broadcom 3c905C internal PHY
166model xxBROADCOM BCM5221 0x001e BCM5221 10/100 media interface 168model xxBROADCOM BCM5221 0x001e BCM5221 10/100 media interface
167model xxBROADCOM BCM5201 0x0021 BCM5201 10/100 media interface 169model xxBROADCOM BCM5201 0x0021 BCM5201 10/100 media interface
168model xxBROADCOM BCM5214 0x0028 BCM5214 Quad 10/100 media interface 170model xxBROADCOM BCM5214 0x0028 BCM5214 Quad 10/100 media interface
169model xxBROADCOM BCM5222 0x0032 BCM5222 Dual 10/100 media interface 171model xxBROADCOM BCM5222 0x0032 BCM5222 Dual 10/100 media interface
170model xxBROADCOM BCM4401 0x0036 BCM4401 10/100 media interface 172model xxBROADCOM BCM4401 0x0036 BCM4401 10/100 media interface
171model xxBROADCOM BCM5365 0x0037 BCM5365 10/100 5-port PHY switch 173model xxBROADCOM BCM5365 0x0037 BCM5365 10/100 5-port PHY switch
172model BROADCOM BCM5400 0x0004 BCM5400 1000BASE-T media interface 174model BROADCOM BCM5400 0x0004 BCM5400 1000BASE-T media interface
173model BROADCOM BCM5401 0x0005 BCM5401 1000BASE-T media interface 175model BROADCOM BCM5401 0x0005 BCM5401 1000BASE-T media interface
174model BROADCOM BCM5402 0x0006 BCM5402 1000BASE-T media interface 176model BROADCOM BCM5402 0x0006 BCM5402 1000BASE-T media interface
175model BROADCOM BCM5411 0x0007 BCM5411 1000BASE-T media interface 177model BROADCOM BCM5411 0x0007 BCM5411 1000BASE-T media interface
176model BROADCOM BCM5404 0x0008 BCM5404 1000BASE-T media interface 178model BROADCOM BCM5404 0x0008 BCM5404 1000BASE-T media interface
177model BROADCOM BCM5424 0x000a BCM5424/BCM5234 1000BASE-T media interface 179model BROADCOM BCM5424 0x000a BCM5424/BCM5234 1000BASE-T media interface
178model BROADCOM BCM5464 0x000b BCM5464 1000BASE-T media interface 180model BROADCOM BCM5464 0x000b BCM5464 1000BASE-T media interface
179model BROADCOM BCM5461 0x000c BCM5461 1000BASE-T media interface 181model BROADCOM BCM5461 0x000c BCM5461 1000BASE-T media interface
180model BROADCOM BCM5462 0x000d BCM5462 1000BASE-T media interface 182model BROADCOM BCM5462 0x000d BCM5462 1000BASE-T media interface
181model BROADCOM BCM5421 0x000e BCM5421 1000BASE-T media interface 183model BROADCOM BCM5421 0x000e BCM5421 1000BASE-T media interface
182model BROADCOM BCM5752 0x0010 BCM5752 1000BASE-T media interface 184model BROADCOM BCM5752 0x0010 BCM5752 1000BASE-T media interface
183model BROADCOM BCM5701 0x0011 BCM5701 1000BASE-T media interface 185model BROADCOM BCM5701 0x0011 BCM5701 1000BASE-T media interface
184model BROADCOM BCM5706 0x0015 BCM5706 1000BASE-T/SX media interface 186model BROADCOM BCM5706 0x0015 BCM5706 1000BASE-T/SX media interface
185model BROADCOM BCM5703 0x0016 BCM5703 1000BASE-T media interface 187model BROADCOM BCM5703 0x0016 BCM5703 1000BASE-T media interface
186model BROADCOM BCM5750 0x0018 BCM5750 1000BASE-T media interface 188model BROADCOM BCM5750 0x0018 BCM5750 1000BASE-T media interface
187model BROADCOM BCM5704 0x0019 BCM5704 1000BASE-T media interface 189model BROADCOM BCM5704 0x0019 BCM5704 1000BASE-T media interface
188model BROADCOM BCM5705 0x001a BCM5705 1000BASE-T media interface 190model BROADCOM BCM5705 0x001a BCM5705 1000BASE-T media interface
189model BROADCOM BCM54K2 0x002e BCM54K2 1000BASE-T media interface 191model BROADCOM BCM54K2 0x002e BCM54K2 1000BASE-T media interface
190model BROADCOM BCM5714 0x0034 BCM5714 1000BASE-T/X media interface 192model BROADCOM BCM5714 0x0034 BCM5714 1000BASE-T/X media interface
191model BROADCOM BCM5780 0x0035 BCM5780 1000BASE-T/X media interface 193model BROADCOM BCM5780 0x0035 BCM5780 1000BASE-T/X media interface
192model BROADCOM BCM5708C 0x0036 BCM5708C 1000BASE-T media interface 194model BROADCOM BCM5708C 0x0036 BCM5708C 1000BASE-T media interface
193model BROADCOM BCM5466 0x003b BCM5466 1000BASE-T media interface 195model BROADCOM BCM5466 0x003b BCM5466 1000BASE-T media interface
194model BROADCOM2 BCM5325 0x0003 BCM5325 10/100 5-port PHY switch 196model BROADCOM2 BCM5325 0x0003 BCM5325 10/100 5-port PHY switch
195model BROADCOM2 BCM5906 0x0004 BCM5906 10/100baseTX media interface 197model BROADCOM2 BCM5906 0x0004 BCM5906 10/100baseTX media interface
196model BROADCOM2 BCM5478 0x0008 BCM5478 1000BASE-T media interface 198model BROADCOM2 BCM5478 0x0008 BCM5478 1000BASE-T media interface
197model BROADCOM2 BCM5488 0x0009 BCM5488 1000BASE-T media interface 199model BROADCOM2 BCM5488 0x0009 BCM5488 1000BASE-T media interface
198model BROADCOM2 BCM5481 0x000a BCM5481 1000BASE-T media interface 200model BROADCOM2 BCM5481 0x000a BCM5481 1000BASE-T media interface
199model BROADCOM2 BCM5482 0x000b BCM5482 1000BASE-T media interface 201model BROADCOM2 BCM5482 0x000b BCM5482 1000BASE-T media interface
200model BROADCOM2 BCM5755 0x000c BCM5755 1000BASE-T media interface 202model BROADCOM2 BCM5755 0x000c BCM5755 1000BASE-T media interface
201model BROADCOM2 BCM5756 0x000d BCM5756 1000BASE-T media interface XXX 203model BROADCOM2 BCM5756 0x000d BCM5756 1000BASE-T media interface XXX
202model BROADCOM2 BCM5754 0x000e BCM5754/5787 1000BASE-T media interface 204model BROADCOM2 BCM5754 0x000e BCM5754/5787 1000BASE-T media interface
203model BROADCOM2 BCM5708S 0x0015 BCM5708S 1000/2500baseSX PHY 205model BROADCOM2 BCM5708S 0x0015 BCM5708S 1000/2500baseSX PHY
204model BROADCOM2 BCM5785 0x0016 BCM5785 1000BASE-T media interface 206model BROADCOM2 BCM5785 0x0016 BCM5785 1000BASE-T media interface
205model BROADCOM2 BCM5709CAX 0x002c BCM5709CAX 10/100/1000baseT PHY 207model BROADCOM2 BCM5709CAX 0x002c BCM5709CAX 10/100/1000baseT PHY
206model BROADCOM2 BCM5722 0x002d BCM5722 1000BASE-T media interface 208model BROADCOM2 BCM5722 0x002d BCM5722 1000BASE-T media interface
207model BROADCOM2 BCM5784 0x003a BCM5784 10/100/1000baseT PHY 209model BROADCOM2 BCM5784 0x003a BCM5784 10/100/1000baseT PHY
208model BROADCOM2 BCM5709C 0x003c BCM5709 10/100/1000baseT PHY 210model BROADCOM2 BCM5709C 0x003c BCM5709 10/100/1000baseT PHY
209model BROADCOM2 BCM5761 0x003d BCM5761 10/100/1000baseT PHY 211model BROADCOM2 BCM5761 0x003d BCM5761 10/100/1000baseT PHY
210model BROADCOM2 BCM5709S 0x003f BCM5709S 1000/2500baseSX PHY 212model BROADCOM2 BCM5709S 0x003f BCM5709S 1000/2500baseSX PHY
211model BROADCOM3 BCM57780 0x0019 BCM57780 1000BASE-T media interface 213model BROADCOM3 BCM57780 0x0019 BCM57780 1000BASE-T media interface
212model BROADCOM3 BCM5717C 0x0020 BCM5717C 1000BASE-T media interface 214model BROADCOM3 BCM5717C 0x0020 BCM5717C 1000BASE-T media interface
213model BROADCOM3 BCM5719C 0x0022 BCM5719C 1000BASE-T media interface 215model BROADCOM3 BCM5719C 0x0022 BCM5719C 1000BASE-T media interface
214model BROADCOM3 BCM57765 0x0024 BCM57765 1000BASE-T media interface 216model BROADCOM3 BCM57765 0x0024 BCM57765 1000BASE-T media interface
215model BROADCOM3 BCM53125 0x0032 BCM53125 1000BASE-T switch 217model BROADCOM3 BCM53125 0x0032 BCM53125 1000BASE-T switch
216model BROADCOM3 BCM5720C 0x0036 BCM5720C 1000BASE-T media interface 218model BROADCOM3 BCM5720C 0x0036 BCM5720C 1000BASE-T media interface
 219model BROADCOM4 BCM54213PE 0x000a BCM54213PE 1000BASE-T media interface
217model BROADCOM4 BCM5725C 0x0038 BCM5725C 1000BASE-T media interface 220model BROADCOM4 BCM5725C 0x0038 BCM5725C 1000BASE-T media interface
218model xxBROADCOM_ALT1 BCM5906 0x0004 BCM5906 10/100baseTX media interface 221model xxBROADCOM_ALT1 BCM5906 0x0004 BCM5906 10/100baseTX media interface
219 222
220/* Cicada Semiconductor PHYs (-> Vitesse -> Microsemi) */ 223/* Cicada Semiconductor PHYs (-> Vitesse -> Microsemi) */
221 224
222model xxCICADA CIS8201 0x0001 Cicada CIS8201 10/100/1000TX PHY 225model xxCICADA CIS8201 0x0001 Cicada CIS8201 10/100/1000TX PHY
223model xxCICADA CIS8204 0x0004 Cicada CIS8204 10/100/1000TX PHY 226model xxCICADA CIS8204 0x0004 Cicada CIS8204 10/100/1000TX PHY
224model xxCICADA VSC8211 0x000b Cicada VSC8211 10/100/1000TX PHY 227model xxCICADA VSC8211 0x000b Cicada VSC8211 10/100/1000TX PHY
225model xxCICADA VSC8221 0x0015 Vitesse VSC8221 10/100/1000BASE-T PHY 228model xxCICADA VSC8221 0x0015 Vitesse VSC8221 10/100/1000BASE-T PHY
226model xxCICADA VSC8224 0x0018 Vitesse VSC8224 10/100/1000BASE-T PHY 229model xxCICADA VSC8224 0x0018 Vitesse VSC8224 10/100/1000BASE-T PHY
227model xxCICADA CIS8201A 0x0020 Cicada CIS8201 10/100/1000TX PHY 230model xxCICADA CIS8201A 0x0020 Cicada CIS8201 10/100/1000TX PHY
228model xxCICADA CIS8201B 0x0021 Cicada CIS8201 10/100/1000TX PHY 231model xxCICADA CIS8201B 0x0021 Cicada CIS8201 10/100/1000TX PHY
229model xxCICADA VSC8234 0x0022 Vitesse VSC8234 10/100/1000TX PHY 232model xxCICADA VSC8234 0x0022 Vitesse VSC8234 10/100/1000TX PHY
230model xxCICADA VSC8244 0x002c Vitesse VSC8244 Quad 10/100/1000BASE-T PHY 233model xxCICADA VSC8244 0x002c Vitesse VSC8244 Quad 10/100/1000BASE-T PHY
231 234
232/* Davicom Semiconductor PHYs */ 235/* Davicom Semiconductor PHYs */
233/* AMD Am79C873 seems to be a relabeled DM9101 */ 236/* AMD Am79C873 seems to be a relabeled DM9101 */
234model DAVICOM DM9101 0x0000 DM9101 (AMD Am79C873) 10/100 media interface 237model DAVICOM DM9101 0x0000 DM9101 (AMD Am79C873) 10/100 media interface
235model xxDAVICOM DM9101 0x0000 DM9101 (AMD Am79C873) 10/100 media interface 238model xxDAVICOM DM9101 0x0000 DM9101 (AMD Am79C873) 10/100 media interface
236model xxDAVICOM DM9102 0x0004 DM9102 10/100 media interface 239model xxDAVICOM DM9102 0x0004 DM9102 10/100 media interface
237model xxDAVICOM DM9161 0x0008 DM9161 10/100 media interface 240model xxDAVICOM DM9161 0x0008 DM9161 10/100 media interface
238model xxDAVICOM DM9161A 0x000a DM9161A 10/100 media interface 241model xxDAVICOM DM9161A 0x000a DM9161A 10/100 media interface
239model xxDAVICOM DM9161B 0x000b DM9161[BC] 10/100 media interface 242model xxDAVICOM DM9161B 0x000b DM9161[BC] 10/100 media interface
240model xxDAVICOM DM9601 0x000c DM9601 internal 10/100 media interface 243model xxDAVICOM DM9601 0x000c DM9601 internal 10/100 media interface
241 244
242/* IC Plus Corp. PHYs */ 245/* IC Plus Corp. PHYs */
243model xxICPLUS IP100 0x0004 IP100 10/100 PHY 246model xxICPLUS IP100 0x0004 IP100 10/100 PHY
244model xxICPLUS IP101 0x0005 IP101 10/100 PHY 247model xxICPLUS IP101 0x0005 IP101 10/100 PHY
245model xxICPLUS IP1000A 0x0008 IP1000A 10/100/1000 PHY 248model xxICPLUS IP1000A 0x0008 IP1000A 10/100/1000 PHY
246model xxICPLUS IP1001 0x0019 IP1001 10/100/1000 PHY 249model xxICPLUS IP1001 0x0019 IP1001 10/100/1000 PHY
247 250
248/* Integrated Circuit Systems PHYs */ 251/* Integrated Circuit Systems PHYs */
249model ICS 1889 0x0001 ICS1889 10/100 media interface 252model ICS 1889 0x0001 ICS1889 10/100 media interface
250model ICS 1890 0x0002 ICS1890 10/100 media interface 253model ICS 1890 0x0002 ICS1890 10/100 media interface
251model ICS 1892 0x0003 ICS1892 10/100 media interface 254model ICS 1892 0x0003 ICS1892 10/100 media interface
252model ICS 1893 0x0004 ICS1893 10/100 media interface 255model ICS 1893 0x0004 ICS1893 10/100 media interface
253model ICS 1893C 0x0005 ICS1893C 10/100 media interface 256model ICS 1893C 0x0005 ICS1893C 10/100 media interface
254 257
255/* Intel PHYs */ 258/* Intel PHYs */
256model xxINTEL I82553 0x0000 i82553 10/100 media interface 259model xxINTEL I82553 0x0000 i82553 10/100 media interface
257model yyINTEL I82555 0x0015 i82555 10/100 media interface 260model yyINTEL I82555 0x0015 i82555 10/100 media interface
258model yyINTEL I82562EH 0x0017 i82562EH HomePNA interface 261model yyINTEL I82562EH 0x0017 i82562EH HomePNA interface
259model yyINTEL I82562G 0x0031 i82562G 10/100 media interface 262model yyINTEL I82562G 0x0031 i82562G 10/100 media interface
260model yyINTEL I82562EM 0x0032 i82562EM 10/100 media interface 263model yyINTEL I82562EM 0x0032 i82562EM 10/100 media interface
261model yyINTEL I82562ET 0x0033 i82562ET 10/100 media interface 264model yyINTEL I82562ET 0x0033 i82562ET 10/100 media interface
262model yyINTEL I82553 0x0035 i82553 10/100 media interface 265model yyINTEL I82553 0x0035 i82553 10/100 media interface
263model yyINTEL IGP01E1000 0x0038 Intel IGP01E1000 Gigabit PHY 266model yyINTEL IGP01E1000 0x0038 Intel IGP01E1000 Gigabit PHY
264model yyINTEL I82566 0x0039 i82566 10/100/1000 media interface 267model yyINTEL I82566 0x0039 i82566 10/100/1000 media interface
265model INTEL I82577 0x0005 i82577 10/100/1000 media interface 268model INTEL I82577 0x0005 i82577 10/100/1000 media interface
266model INTEL I82579 0x0009 i82579 10/100/1000 media interface 269model INTEL I82579 0x0009 i82579 10/100/1000 media interface
267model INTEL I217 0x000a i217 10/100/1000 media interface 270model INTEL I217 0x000a i217 10/100/1000 media interface
268model INTEL X540 0x0020 X540 100M/1G/10G media interface 271model INTEL X540 0x0020 X540 100M/1G/10G media interface
269model INTEL X550 0x0022 X550 100M/1G/10G media interface 272model INTEL X550 0x0022 X550 100M/1G/10G media interface
270model INTEL X557 0x0024 X557 100M/1G/10G media interface 273model INTEL X557 0x0024 X557 100M/1G/10G media interface
271model INTEL I82580 0x003a 82580 10/100/1000 media interface 274model INTEL I82580 0x003a 82580 10/100/1000 media interface
272model INTEL I350 0x003b I350 10/100/1000 media interface 275model INTEL I350 0x003b I350 10/100/1000 media interface
273model xxMARVELL I210 0x0000 I210 10/100/1000 media interface 276model xxMARVELL I210 0x0000 I210 10/100/1000 media interface
274model xxMARVELL I82563 0x000a i82563 10/100/1000 media interface 277model xxMARVELL I82563 0x000a i82563 10/100/1000 media interface
275model ATTANSIC I82578 0x0004 Intel 82578 10/100/1000 media interface 278model ATTANSIC I82578 0x0004 Intel 82578 10/100/1000 media interface
276 279
277 280
278/* JMicron PHYs */ 281/* JMicron PHYs */
279model JMICRON JMP211 0x0021 JMP211 10/100/1000 media interface 282model JMICRON JMP211 0x0021 JMP211 10/100/1000 media interface
280model JMICRON JMP202 0x0022 JMP202 10/100 media interface 283model JMICRON JMP202 0x0022 JMP202 10/100 media interface
281 284
282/* Level 1 PHYs */ 285/* Level 1 PHYs */
283model xxLEVEL1 LXT970 0x0000 LXT970 10/100 media interface 286model xxLEVEL1 LXT970 0x0000 LXT970 10/100 media interface
284model LEVEL1 LXT1000_OLD 0x0003 LXT1000 1000BASE-T media interface 287model LEVEL1 LXT1000_OLD 0x0003 LXT1000 1000BASE-T media interface
285model LEVEL1 LXT974 0x0004 LXT974 10/100 Quad PHY 288model LEVEL1 LXT974 0x0004 LXT974 10/100 Quad PHY
286model LEVEL1 LXT975 0x0005 LXT975 10/100 Quad PHY 289model LEVEL1 LXT975 0x0005 LXT975 10/100 Quad PHY
287model LEVEL1 LXT1000 0x000c LXT1000 1000BASE-T media interface 290model LEVEL1 LXT1000 0x000c LXT1000 1000BASE-T media interface
288model LEVEL1 LXT971 0x000e LXT971/2 10/100 media interface 291model LEVEL1 LXT971 0x000e LXT971/2 10/100 media interface
289model LEVEL1 LXT973 0x0021 LXT973 10/100 Dual PHY 292model LEVEL1 LXT973 0x0021 LXT973 10/100 Dual PHY
290 293
291/* Marvell Semiconductor PHYs */ 294/* Marvell Semiconductor PHYs */
292model xxMARVELL E1000 0x0000 Marvell 88E1000 Gigabit PHY 295model xxMARVELL E1000 0x0000 Marvell 88E1000 Gigabit PHY
293model xxMARVELL E1011 0x0002 Marvell 88E1011 Gigabit PHY 296model xxMARVELL E1011 0x0002 Marvell 88E1011 Gigabit PHY
294model xxMARVELL E1000_3 0x0003 Marvell 88E1000 Gigabit PHY 297model xxMARVELL E1000_3 0x0003 Marvell 88E1000 Gigabit PHY
295model xxMARVELL E1000S 0x0004 Marvell 88E1000S Gigabit PHY 298model xxMARVELL E1000S 0x0004 Marvell 88E1000S Gigabit PHY
296model xxMARVELL E1000_5 0x0005 Marvell 88E1000 Gigabit PHY 299model xxMARVELL E1000_5 0x0005 Marvell 88E1000 Gigabit PHY
297model xxMARVELL E1101 0x0006 Marvell 88E1101 Gigabit PHY 300model xxMARVELL E1101 0x0006 Marvell 88E1101 Gigabit PHY
298model xxMARVELL E3082 0x0008 Marvell 88E3082 10/100 Fast Ethernet PHY 301model xxMARVELL E3082 0x0008 Marvell 88E3082 10/100 Fast Ethernet PHY
299model xxMARVELL E1112 0x0009 Marvell 88E1112 Gigabit PHY 302model xxMARVELL E1112 0x0009 Marvell 88E1112 Gigabit PHY
300model xxMARVELL E1149 0x000b Marvell 88E1149 Gigabit PHY 303model xxMARVELL E1149 0x000b Marvell 88E1149 Gigabit PHY
301model xxMARVELL E1111 0x000c Marvell 88E1111 Gigabit PHY 304model xxMARVELL E1111 0x000c Marvell 88E1111 Gigabit PHY
302model xxMARVELL E1145 0x000d Marvell 88E1145 Quad Gigabit PHY 305model xxMARVELL E1145 0x000d Marvell 88E1145 Quad Gigabit PHY
303model xxMARVELL E6060 0x0010 Marvell 88E6060 6-Port 10/100 Fast Ethernet Switch 306model xxMARVELL E6060 0x0010 Marvell 88E6060 6-Port 10/100 Fast Ethernet Switch
304model xxMARVELL I347 0x001c Intel I347-AT4 Gigabit PHY 307model xxMARVELL I347 0x001c Intel I347-AT4 Gigabit PHY
305model xxMARVELL E1512 0x001d Marvell 88E151[0248] Gigabit PHY 308model xxMARVELL E1512 0x001d Marvell 88E151[0248] Gigabit PHY
306model xxMARVELL E1340M 0x001f Marvell 88E1340 Gigabit PHY 309model xxMARVELL E1340M 0x001f Marvell 88E1340 Gigabit PHY
307model xxMARVELL E1116 0x0021 Marvell 88E1116 Gigabit PHY 310model xxMARVELL E1116 0x0021 Marvell 88E1116 Gigabit PHY
308model xxMARVELL E1118 0x0022 Marvell 88E1118 Gigabit PHY 311model xxMARVELL E1118 0x0022 Marvell 88E1118 Gigabit PHY
309model xxMARVELL E1240 0x0023 Marvell 88E1240 Gigabit PHY 312model xxMARVELL E1240 0x0023 Marvell 88E1240 Gigabit PHY
310model xxMARVELL E1116R 0x0024 Marvell 88E1116R Gigabit PHY 313model xxMARVELL E1116R 0x0024 Marvell 88E1116R Gigabit PHY
311model xxMARVELL E1149R 0x0025 Marvell 88E1149R Quad Gigabit PHY 314model xxMARVELL E1149R 0x0025 Marvell 88E1149R Quad Gigabit PHY
312model xxMARVELL E3016 0x0026 Marvell 88E3016 10/100 Fast Ethernet PHY 315model xxMARVELL E3016 0x0026 Marvell 88E3016 10/100 Fast Ethernet PHY
313model xxMARVELL PHYG65G 0x0027 Marvell PHYG65G Gigabit PHY 316model xxMARVELL PHYG65G 0x0027 Marvell PHYG65G Gigabit PHY
314model xxMARVELL E1318S 0x0029 Marvell 88E1318S Gigabit PHY 317model xxMARVELL E1318S 0x0029 Marvell 88E1318S Gigabit PHY
315model xxMARVELL E1543 0x002a Marvell 88E154[358] Alaska Quad Port Gb PHY 318model xxMARVELL E1543 0x002a Marvell 88E154[358] Alaska Quad Port Gb PHY
316model MARVELL E1000_0 0x0000 Marvell 88E1000 Gigabit PHY 319model MARVELL E1000_0 0x0000 Marvell 88E1000 Gigabit PHY
317model MARVELL E1011 0x0002 Marvell 88E1011 Gigabit PHY 320model MARVELL E1011 0x0002 Marvell 88E1011 Gigabit PHY
318model MARVELL E1000_3 0x0003 Marvell 88E1000 Gigabit PHY 321model MARVELL E1000_3 0x0003 Marvell 88E1000 Gigabit PHY
319model MARVELL E1000_5 0x0005 Marvell 88E1000 Gigabit PHY 322model MARVELL E1000_5 0x0005 Marvell 88E1000 Gigabit PHY
320model MARVELL E1000_6 0x0006 Marvell 88E1000 Gigabit PHY 323model MARVELL E1000_6 0x0006 Marvell 88E1000 Gigabit PHY
321model MARVELL E1111 0x000c Marvell 88E1111 Gigabit PHY 324model MARVELL E1111 0x000c Marvell 88E1111 Gigabit PHY
322 325
323/* Micrel PHYs (Kendin and Microchip) */ 326/* Micrel PHYs (Kendin and Microchip) */
324model MICREL KSZ8041 0x0011 Micrel KSZ8041TL/FTL/MLL 10/100 PHY 327model MICREL KSZ8041 0x0011 Micrel KSZ8041TL/FTL/MLL 10/100 PHY
325model MICREL KSZ8041RNLI 0x0013 Micrel KSZ8041RNLI 10/100 PHY 328model MICREL KSZ8041RNLI 0x0013 Micrel KSZ8041RNLI 10/100 PHY
326model MICREL KSZ8051 0x0015 Micrel KSZ80[235]1 10/100 PHY 329model MICREL KSZ8051 0x0015 Micrel KSZ80[235]1 10/100 PHY
327model MICREL KSZ8081 0x0016 Micrel KSZ80[89]1 10/100 PHY 330model MICREL KSZ8081 0x0016 Micrel KSZ80[89]1 10/100 PHY
328model MICREL KSZ8061 0x0017 Micrel KSZ8061 10/100 PHY 331model MICREL KSZ8061 0x0017 Micrel KSZ8061 10/100 PHY
329model MICREL KSZ9021_8001_8721 0x0021 Micrel KSZ9021 Gb & KSZ8001/8721 10/100 PHY 332model MICREL KSZ9021_8001_8721 0x0021 Micrel KSZ9021 Gb & KSZ8001/8721 10/100 PHY
330model MICREL KSZ9031 0x0022 Micrel KSZ9031 10/100/1000 PHY 333model MICREL KSZ9031 0x0022 Micrel KSZ9031 10/100/1000 PHY
331model MICREL KSZ9477 0x0023 Micrel KSZ9477 10/100/1000 PHY 334model MICREL KSZ9477 0x0023 Micrel KSZ9477 10/100/1000 PHY
332model MICREL KSZ9131 0x0024 Micrel KSZ9131 10/100/1000 PHY 335model MICREL KSZ9131 0x0024 Micrel KSZ9131 10/100/1000 PHY
333model MICREL KS8737 0x0032 Micrel KS8737 10/100 PHY 336model MICREL KS8737 0x0032 Micrel KS8737 10/100 PHY
334 337
335/* Myson Technology PHYs */ 338/* Myson Technology PHYs */
336model xxMYSON MTD972 0x0000 MTD972 10/100 media interface 339model xxMYSON MTD972 0x0000 MTD972 10/100 media interface
337model MYSON MTD803 0x0000 MTD803 3-in-1 media interface 340model MYSON MTD803 0x0000 MTD803 3-in-1 media interface
338 341
339/* National Semiconductor PHYs */ 342/* National Semiconductor PHYs */
340model xxNATSEMI DP83840 0x0000 DP83840 10/100 media interface 343model xxNATSEMI DP83840 0x0000 DP83840 10/100 media interface
341model xxNATSEMI DP83843 0x0001 DP83843 10/100 media interface 344model xxNATSEMI DP83843 0x0001 DP83843 10/100 media interface
342model xxNATSEMI DP83815 0x0002 DP83815/DP83846A 10/100 media interface 345model xxNATSEMI DP83815 0x0002 DP83815/DP83846A 10/100 media interface
343model xxNATSEMI DP83847 0x0003 DP83847 10/100 media interface 346model xxNATSEMI DP83847 0x0003 DP83847 10/100 media interface
344model xxNATSEMI DP83891 0x0005 DP83891 1000BASE-T media interface 347model xxNATSEMI DP83891 0x0005 DP83891 1000BASE-T media interface
345model xxNATSEMI DP83861 0x0006 DP83861 1000BASE-T media interface 348model xxNATSEMI DP83861 0x0006 DP83861 1000BASE-T media interface
346model xxNATSEMI DP83865 0x0007 DP83865 1000BASE-T media interface 349model xxNATSEMI DP83865 0x0007 DP83865 1000BASE-T media interface
347model xxNATSEMI DP83849 0x000a DP83849 10/100 media interface 350model xxNATSEMI DP83849 0x000a DP83849 10/100 media interface
348 351
349/* PMC Sierra PHYs */ 352/* PMC Sierra PHYs */
350model xxPMCSIERRA PM8351 0x0000 PM8351 OctalPHY Gigabit interface 353model xxPMCSIERRA PM8351 0x0000 PM8351 OctalPHY Gigabit interface
351model xxPMCSIERRA2 PM8352 0x0002 PM8352 OctalPHY Gigabit interface 354model xxPMCSIERRA2 PM8352 0x0002 PM8352 OctalPHY Gigabit interface
352model xxPMCSIERRA2 PM8353 0x0003 PM8353 QuadPHY Gigabit interface 355model xxPMCSIERRA2 PM8353 0x0003 PM8353 QuadPHY Gigabit interface
353model PMCSIERRA PM8354 0x0004 PM8354 QuadPHY Gigabit interface 356model PMCSIERRA PM8354 0x0004 PM8354 QuadPHY Gigabit interface
354 357
355/* Quality Semiconductor PHYs */ 358/* Quality Semiconductor PHYs */
356model xxQUALSEMI QS6612 0x0000 QS6612 10/100 media interface 359model xxQUALSEMI QS6612 0x0000 QS6612 10/100 media interface
357 360
358/* RDC Semiconductor PHYs */ 361/* RDC Semiconductor PHYs */
359model RDC R6040 0x0003 R6040 10/100 media interface 362model xxRDC R6040 0x0003 R6040 10/100 media interface
 363model xxRDC R6040_2 0x0005 R6040 10/100 media interface
 364model xxRDC R6040_3 0x0006 R6040 10/100 media interface
360 365
361/* RealTek PHYs */ 366/* RealTek PHYs */
362model xxREALTEK RTL8169S 0x0011 RTL8169S/8110S/8211 1000BASE-T media interface 367model xxREALTEK RTL8169S 0x0011 RTL8169S/8110S/8211 1000BASE-T media interface
363model yyREALTEK RTL8201L 0x0020 RTL8201L 10/100 media interface 368model yyREALTEK RTL8201L 0x0020 RTL8201L 10/100 media interface
364model REALTEK RTL8251 0x0000 RTL8251 1000BASE-T media interface 369model REALTEK RTL8251 0x0000 RTL8251 1000BASE-T media interface
365model REALTEK RTL8201E 0x0008 RTL8201E 10/100 media interface 370model REALTEK RTL8201E 0x0008 RTL8201E 10/100 media interface
366model REALTEK RTL8169S 0x0011 RTL8169S/8110S/8211 1000BASE-T media interface 371model REALTEK RTL8169S 0x0011 RTL8169S/8110S/8211 1000BASE-T media interface
367 372
368/* Seeq PHYs */ 373/* Seeq PHYs */
369model SEEQ 80220 0x0003 Seeq 80220 10/100 media interface 374model SEEQ 80220 0x0003 Seeq 80220 10/100 media interface
370model SEEQ 84220 0x0004 Seeq 84220 10/100 media interface 375model SEEQ 84220 0x0004 Seeq 84220 10/100 media interface
371model SEEQ 80225 0x0008 Seeq 80225 10/100 media interface 376model SEEQ 80225 0x0008 Seeq 80225 10/100 media interface
372 377
373/* Silicon Integrated Systems PHYs */ 378/* Silicon Integrated Systems PHYs */
374model SIS 900 0x0000 SiS 900 10/100 media interface 379model SIS 900 0x0000 SiS 900 10/100 media interface
375 380
376/* SMSC PHYs */ 381/* SMSC PHYs */
377model SMSC LAN83C185 0x000a SMSC LAN83C185 10/100 PHY 382model SMSC LAN83C185 0x000a SMSC LAN83C185 10/100 PHY
378model SMSC LAN8700 0x000c SMSC LAN8700 10/100 Ethernet Transceiver 383model SMSC LAN8700 0x000c SMSC LAN8700 10/100 Ethernet Transceiver
379model SMSC LAN911X 0x000d SMSC LAN911X internal 10/100 PHY 384model SMSC LAN911X 0x000d SMSC LAN911X internal 10/100 PHY
380model SMSC LAN75XX 0x000e SMSC LAN75XX internal 10/100 PHY 385model SMSC LAN75XX 0x000e SMSC LAN75XX internal 10/100 PHY
381model SMSC LAN8710_LAN8720 0x000f SMSC LAN8710/LAN8720 10/100 Ethernet Transceiver 386model SMSC LAN8710_LAN8720 0x000f SMSC LAN8710/LAN8720 10/100 Ethernet Transceiver
382model SMSC LAN8740 0x0011 SMSC LAN8740 10/100 media interface 387model SMSC LAN8740 0x0011 SMSC LAN8740 10/100 media interface
383model SMSC LAN8741A 0x0012 SMSC LAN8741A 10/100 media interface 388model SMSC LAN8741A 0x0012 SMSC LAN8741A 10/100 media interface
384model SMSC LAN8742 0x0013 SMSC LAN8742 10/100 media interface 389model SMSC LAN8742 0x0013 SMSC LAN8742 10/100 media interface
385 390
 391/* Teranetics PHY */
 392model TERANETICS TN1010 0x0001 Teranetics TN1010 10GBase-T PHY
 393
386/* Texas Instruments PHYs */ 394/* Texas Instruments PHYs */
387model TI TLAN10T 0x0001 ThunderLAN 10BASE-T media interface 395model TI TLAN10T 0x0001 ThunderLAN 10BASE-T media interface
388model TI 100VGPMI 0x0002 ThunderLAN 100VG-AnyLan media interface 396model TI 100VGPMI 0x0002 ThunderLAN 100VG-AnyLan media interface
389model TI TNETE2101 0x0003 TNETE2101 media interface 397model TI TNETE2101 0x0003 TNETE2101 media interface
390 398
391/* TDK Semiconductor PHYs */ 399/* TDK Semiconductor PHYs */
392model xxTSC 78Q2120 0x0014 78Q2120 10/100 media interface 400model xxTSC 78Q2120 0x0014 78Q2120 10/100 media interface
393model xxTSC 78Q2121 0x0015 78Q2121 100BASE-TX media interface 401model xxTSC 78Q2121 0x0015 78Q2121 100BASE-TX media interface
394 402
395/* VIA Technologies PHYs */ 403/* VIA Technologies PHYs */
396model VIA VT6103 0x0032 VT6103 10/100 PHY 404model xxVIA VT6103 0x0032 VT6103 10/100 PHY
397model VIA VT6103_2 0x0034 VT6103 10/100 PHY 405model xxVIA VT6103_2 0x0034 VT6103 10/100 PHY
398 406
399/* Vitesse PHYs (Now Microsemi) */ 407/* Vitesse PHYs (Now Microsemi) */
400model xxVITESSE VSC8601 0x0002 VSC8601 10/100/1000 PHY 408model xxVITESSE VSC8601 0x0002 VSC8601 10/100/1000 PHY
401model xxVITESSE VSC8641 0x0003 Vitesse VSC8641 10/100/1000TX PHY 409model xxVITESSE VSC8641 0x0003 Vitesse VSC8641 10/100/1000TX PHY
402model xxVITESSE VSC8501 0x0013 Vitesse VSC8501 10/100/1000TX PHY 410model xxVITESSE VSC8501 0x0013 Vitesse VSC8501 10/100/1000TX PHY
403 411
404/* XaQti Corp. PHYs */ 412/* XaQti Corp. PHYs */
405model xxXAQTI XMACII 0x0000 XaQti Corp. XMAC II gigabit interface 413model xxXAQTI XMACII 0x0000 XaQti Corp. XMAC II gigabit interface
cvs diff -r1.4 -r1.4.4.1 src/sys/dev/mii/rdcphy.c (switch to unified diff)

--- src/sys/dev/mii/rdcphy.c 2019/03/25 09:20:46 1.4
+++ src/sys/dev/mii/rdcphy.c 2020/04/14 16:43:12 1.4.4.1
@@ -1,249 +1,251 @@ @@ -1,249 +1,251 @@
1/* $NetBSD: rdcphy.c,v 1.4 2019/03/25 09:20:46 msaitoh Exp $ */ 1/* $NetBSD: rdcphy.c,v 1.4.4.1 2020/04/14 16:43:12 martin Exp $ */
2 2
3/*- 3/*-
4 * Copyright (c) 2010, Pyun YongHyeon <yongari@FreeBSD.org> 4 * Copyright (c) 2010, Pyun YongHyeon <yongari@FreeBSD.org>
5 * All rights reserved. 5 * All rights reserved.
6 * 6 *
7 * Redistribution and use in source and binary forms, with or without 7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions 8 * modification, are permitted provided that the following conditions
9 * are met: 9 * are met:
10 * 1. Redistributions of source code must retain the above copyright 10 * 1. Redistributions of source code must retain the above copyright
11 * notice unmodified, this list of conditions, and the following 11 * notice unmodified, this list of conditions, and the following
12 * disclaimer. 12 * disclaimer.
13 * 2. Redistributions in binary form must reproduce the above copyright 13 * 2. Redistributions in binary form must reproduce the above copyright
14 * notice, this list of conditions and the following disclaimer in the 14 * notice, this list of conditions and the following disclaimer in the
15 * documentation and/or other materials provided with the distribution. 15 * documentation and/or other materials provided with the distribution.
16 * 16 *
17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
18 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 18 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
19 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 19 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
20 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 20 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
21 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 21 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
22 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 22 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
23 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 23 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
24 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 24 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
25 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 25 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
26 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 26 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
27 * SUCH DAMAGE. 27 * SUCH DAMAGE.
28 */ 28 */
29 29
30/* FreeBSD: src/sys/dev/mii/rdcphy.c,v 1.1 2010/12/30 23:50:25 yongari Exp */ 30/* FreeBSD: src/sys/dev/mii/rdcphy.c,v 1.1 2010/12/30 23:50:25 yongari Exp */
31 31
32/* 32/*
33 * Driver for the RDC Semiconductor R6040 10/100 PHY. 33 * Driver for the RDC Semiconductor R6040 10/100 PHY.
34 */ 34 */
35#include <sys/cdefs.h> 35#include <sys/cdefs.h>
36__KERNEL_RCSID(0, "$NetBSD: rdcphy.c,v 1.4 2019/03/25 09:20:46 msaitoh Exp $"); 36__KERNEL_RCSID(0, "$NetBSD: rdcphy.c,v 1.4.4.1 2020/04/14 16:43:12 martin Exp $");
37 37
38#include <sys/param.h> 38#include <sys/param.h>
39#include <sys/systm.h> 39#include <sys/systm.h>
40#include <sys/kernel.h> 40#include <sys/kernel.h>
41#include <sys/device.h> 41#include <sys/device.h>
42#include <sys/socket.h> 42#include <sys/socket.h>
43#include <sys/errno.h> 43#include <sys/errno.h>
44 44
45#include <sys/bus.h> 45#include <sys/bus.h>
46 46
47#include <net/if.h> 47#include <net/if.h>
48#include <net/if_media.h> 48#include <net/if_media.h>
49 49
50#include <dev/mii/mii.h> 50#include <dev/mii/mii.h>
51#include <dev/mii/miivar.h> 51#include <dev/mii/miivar.h>
52#include <dev/mii/miidevs.h> 52#include <dev/mii/miidevs.h>
53 53
54#include <dev/mii/rdcphyreg.h> 54#include <dev/mii/rdcphyreg.h>
55 55
56struct rdcphy_softc { 56struct rdcphy_softc {
57 struct mii_softc sc_mii; 57 struct mii_softc sc_mii;
58 int sc_mii_link_tick; 58 int sc_mii_link_tick;
59#define RDCPHY_MANNEG_TICK 3 59#define RDCPHY_MANNEG_TICK 3
60}; 60};
61 61
62static int rdcphymatch(device_t, cfdata_t, void *); 62static int rdcphymatch(device_t, cfdata_t, void *);
63static void rdcphyattach(device_t, device_t, void *); 63static void rdcphyattach(device_t, device_t, void *);
64 64
65CFATTACH_DECL_NEW(rdcphy, sizeof(struct rdcphy_softc), 65CFATTACH_DECL_NEW(rdcphy, sizeof(struct rdcphy_softc),
66 rdcphymatch, rdcphyattach, mii_phy_detach, mii_phy_activate); 66 rdcphymatch, rdcphyattach, mii_phy_detach, mii_phy_activate);
67 67
68 68
69static int rdcphy_service(struct mii_softc *, struct mii_data *, int); 69static int rdcphy_service(struct mii_softc *, struct mii_data *, int);
70static void rdcphy_status(struct mii_softc *); 70static void rdcphy_status(struct mii_softc *);
71 71
72static const struct mii_phy_funcs rdcphy_funcs = { 72static const struct mii_phy_funcs rdcphy_funcs = {
73 rdcphy_service, rdcphy_status, mii_phy_reset, 73 rdcphy_service, rdcphy_status, mii_phy_reset,
74}; 74};
75 75
76static const struct mii_phydesc rdcphys[] = { 76static const struct mii_phydesc rdcphys[] = {
77 MII_PHY_DESC(RDC, R6040), 77 MII_PHY_DESC(xxRDC, R6040),
 78 MII_PHY_DESC(xxRDC, R6040_2),
 79 MII_PHY_DESC(xxRDC, R6040_3),
78 MII_PHY_END, 80 MII_PHY_END,
79}; 81};
80 82
81static int 83static int
82rdcphymatch(device_t parent, cfdata_t match, void *aux) 84rdcphymatch(device_t parent, cfdata_t match, void *aux)
83{ 85{
84 struct mii_attach_args *ma = aux; 86 struct mii_attach_args *ma = aux;
85 87
86 if (mii_phy_match(ma, rdcphys) != NULL) 88 if (mii_phy_match(ma, rdcphys) != NULL)
87 return 10; 89 return 10;
88 90
89 return 0; 91 return 0;
90} 92}
91 93
92static void 94static void
93rdcphyattach(device_t parent, device_t self, void *aux) 95rdcphyattach(device_t parent, device_t self, void *aux)
94{ 96{
95 struct rdcphy_softc *rsc = device_private(self); 97 struct rdcphy_softc *rsc = device_private(self);
96 struct mii_softc *sc = &rsc->sc_mii; 98 struct mii_softc *sc = &rsc->sc_mii;
97 struct mii_attach_args *ma = aux; 99 struct mii_attach_args *ma = aux;
98 struct mii_data *mii = ma->mii_data; 100 struct mii_data *mii = ma->mii_data;
99 101
100 const struct mii_phydesc *mpd; 102 const struct mii_phydesc *mpd;
101 103
102 mpd = mii_phy_match(ma, rdcphys); 104 mpd = mii_phy_match(ma, rdcphys);
103 aprint_naive(": Media interface\n"); 105 aprint_naive(": Media interface\n");
104 aprint_normal(": %s, rev. %d\n", mpd->mpd_name, MII_REV(ma->mii_id2)); 106 aprint_normal(": %s, rev. %d\n", mpd->mpd_name, MII_REV(ma->mii_id2));
105 107
106 sc->mii_dev = self; 108 sc->mii_dev = self;
107 sc->mii_inst = mii->mii_instance; 109 sc->mii_inst = mii->mii_instance;
108 sc->mii_phy = ma->mii_phyno; 110 sc->mii_phy = ma->mii_phyno;
109 sc->mii_funcs = &rdcphy_funcs; 111 sc->mii_funcs = &rdcphy_funcs;
110 sc->mii_pdata = mii; 112 sc->mii_pdata = mii;
111 sc->mii_flags = ma->mii_flags; 113 sc->mii_flags = ma->mii_flags;
112 sc->mii_anegticks = MII_ANEGTICKS; 114 sc->mii_anegticks = MII_ANEGTICKS;
113 115
114 PHY_RESET(sc); 116 PHY_RESET(sc);
115 117
116 PHY_READ(sc, MII_BMSR, &sc->mii_capabilities); 118 PHY_READ(sc, MII_BMSR, &sc->mii_capabilities);
117 sc->mii_capabilities &= ma->mii_capmask; 119 sc->mii_capabilities &= ma->mii_capmask;
118 if (sc->mii_capabilities & BMSR_EXTSTAT) 120 if (sc->mii_capabilities & BMSR_EXTSTAT)
119 PHY_READ(sc, MII_EXTSR, &sc->mii_extcapabilities); 121 PHY_READ(sc, MII_EXTSR, &sc->mii_extcapabilities);
120 aprint_normal_dev(self, ""); 122 aprint_normal_dev(self, "");
121 mii_phy_add_media(sc); 123 mii_phy_add_media(sc);
122 aprint_normal("\n"); 124 aprint_normal("\n");
123 125
124 if (!pmf_device_register(self, NULL, mii_phy_resume)) 126 if (!pmf_device_register(self, NULL, mii_phy_resume))
125 aprint_error_dev(self, "couldn't establish power handler\n"); 127 aprint_error_dev(self, "couldn't establish power handler\n");
126 128
127} 129}
128 130
129static int 131static int
130rdcphy_service(struct mii_softc *sc, struct mii_data *mii, int cmd) 132rdcphy_service(struct mii_softc *sc, struct mii_data *mii, int cmd)
131{ 133{
132 struct rdcphy_softc *rsc = (struct rdcphy_softc *)sc; 134 struct rdcphy_softc *rsc = (struct rdcphy_softc *)sc;
133 struct ifmedia_entry *ife = mii->mii_media.ifm_cur; 135 struct ifmedia_entry *ife = mii->mii_media.ifm_cur;
134 136
135 switch (cmd) { 137 switch (cmd) {
136 case MII_POLLSTAT: 138 case MII_POLLSTAT:
137 break; 139 break;
138 140
139 case MII_MEDIACHG: 141 case MII_MEDIACHG:
140 /* If the interface is not up, don't do anything. */ 142 /* If the interface is not up, don't do anything. */
141 if ((mii->mii_ifp->if_flags & IFF_UP) == 0) 143 if ((mii->mii_ifp->if_flags & IFF_UP) == 0)
142 break; 144 break;
143 145
144 mii_phy_setmedia(sc); 146 mii_phy_setmedia(sc);
145 switch (IFM_SUBTYPE(ife->ifm_media)) { 147 switch (IFM_SUBTYPE(ife->ifm_media)) {
146 case IFM_100_TX: 148 case IFM_100_TX:
147 case IFM_10_T: 149 case IFM_10_T:
148 /* 150 /*
149 * Report fake lost link event to parent driver. This 151 * Report fake lost link event to parent driver. This
150 * will stop MAC of parent driver and make it possible 152 * will stop MAC of parent driver and make it possible
151 * to reconfigure MAC after completion of link 153 * to reconfigure MAC after completion of link
152 * establishment. 154 * establishment.
153 * Note, the parent MAC seems to require restarting MAC 155 * Note, the parent MAC seems to require restarting MAC
154 * when underlying any PHY configuration was changed 156 * when underlying any PHY configuration was changed
155 * even if the resolved speed/duplex was not changed at 157 * even if the resolved speed/duplex was not changed at
156 * all. 158 * all.
157 */ 159 */
158 mii->mii_media_status = 0; 160 mii->mii_media_status = 0;
159 mii->mii_media_active = IFM_ETHER | IFM_NONE; 161 mii->mii_media_active = IFM_ETHER | IFM_NONE;
160 rsc->sc_mii_link_tick = RDCPHY_MANNEG_TICK; 162 rsc->sc_mii_link_tick = RDCPHY_MANNEG_TICK;
161 /* Immediately report link down. */ 163 /* Immediately report link down. */
162 mii_phy_update(sc, MII_MEDIACHG); 164 mii_phy_update(sc, MII_MEDIACHG);
163 return 0; 165 return 0;
164 default: 166 default:
165 break; 167 break;
166 } 168 }
167 break; 169 break;
168 170
169 case MII_TICK: 171 case MII_TICK:
170 if (mii_phy_tick(sc) == EJUSTRETURN) 172 if (mii_phy_tick(sc) == EJUSTRETURN)
171 return 0; 173 return 0;
172 if (IFM_SUBTYPE(ife->ifm_media) != IFM_AUTO) { 174 if (IFM_SUBTYPE(ife->ifm_media) != IFM_AUTO) {
173 /* 175 /*
174 * It seems the PHY hardware does not correctly report 176 * It seems the PHY hardware does not correctly report
175 * link status changes when manual link configuration 177 * link status changes when manual link configuration
176 * is in progress. It is also possible for the PHY to 178 * is in progress. It is also possible for the PHY to
177 * complete establishing a link within one second such 179 * complete establishing a link within one second such
178 * that mii(4) did not notice the link change. 180 * that mii(4) did not notice the link change.
179 * To workaround the issue, emulate lost link event and 181 * To workaround the issue, emulate lost link event and
180 * wait for 3 seconds when manual link configuration 182 * wait for 3 seconds when manual link configuration
181 * is in progress. 3 seconds would be long enough to 183 * is in progress. 3 seconds would be long enough to
182 * absorb transient link flips. 184 * absorb transient link flips.
183 */ 185 */
184 if (rsc->sc_mii_link_tick > 0) { 186 if (rsc->sc_mii_link_tick > 0) {
185 rsc->sc_mii_link_tick--; 187 rsc->sc_mii_link_tick--;
186 return 0; 188 return 0;
187 } 189 }
188 } 190 }
189 break; 191 break;
190 } 192 }
191 193
192 /* Update the media status. */ 194 /* Update the media status. */
193 rdcphy_status(sc); 195 rdcphy_status(sc);
194 196
195 /* Callback if something changed. */ 197 /* Callback if something changed. */
196 mii_phy_update(sc, cmd); 198 mii_phy_update(sc, cmd);
197 return 0; 199 return 0;
198} 200}
199 201
200static void 202static void
201rdcphy_status(struct mii_softc *sc) 203rdcphy_status(struct mii_softc *sc)
202{ 204{
203 struct mii_data *mii = sc->mii_pdata; 205 struct mii_data *mii = sc->mii_pdata;
204 uint16_t bmsr, bmcr, physts; 206 uint16_t bmsr, bmcr, physts;
205 207
206 mii->mii_media_status = IFM_AVALID; 208 mii->mii_media_status = IFM_AVALID;
207 mii->mii_media_active = IFM_ETHER; 209 mii->mii_media_active = IFM_ETHER;
208 210
209 PHY_READ(sc, MII_BMSR, &bmsr); 211 PHY_READ(sc, MII_BMSR, &bmsr);
210 PHY_READ(sc, MII_BMSR, &bmsr); 212 PHY_READ(sc, MII_BMSR, &bmsr);
211 PHY_READ(sc, MII_RDCPHY_STATUS, &physts); 213 PHY_READ(sc, MII_RDCPHY_STATUS, &physts);
212 214
213 if ((physts & STATUS_LINK_UP) != 0) 215 if ((physts & STATUS_LINK_UP) != 0)
214 mii->mii_media_status |= IFM_ACTIVE; 216 mii->mii_media_status |= IFM_ACTIVE;
215 217
216 PHY_READ(sc, MII_BMCR, &bmcr); 218 PHY_READ(sc, MII_BMCR, &bmcr);
217 if ((bmcr & BMCR_ISO) != 0) { 219 if ((bmcr & BMCR_ISO) != 0) {
218 mii->mii_media_active |= IFM_NONE; 220 mii->mii_media_active |= IFM_NONE;
219 mii->mii_media_status = 0; 221 mii->mii_media_status = 0;
220 return; 222 return;
221 } 223 }
222 224
223 if ((bmcr & BMCR_LOOP) != 0) 225 if ((bmcr & BMCR_LOOP) != 0)
224 mii->mii_media_active |= IFM_LOOP; 226 mii->mii_media_active |= IFM_LOOP;
225 227
226 if ((bmcr & BMCR_AUTOEN) != 0) { 228 if ((bmcr & BMCR_AUTOEN) != 0) {
227 if ((bmsr & BMSR_ACOMP) == 0) { 229 if ((bmsr & BMSR_ACOMP) == 0) {
228 /* Erg, still trying, I guess... */ 230 /* Erg, still trying, I guess... */
229 mii->mii_media_active |= IFM_NONE; 231 mii->mii_media_active |= IFM_NONE;
230 return; 232 return;
231 } 233 }
232 } 234 }
233 235
234 switch (physts & STATUS_SPEED_MASK) { 236 switch (physts & STATUS_SPEED_MASK) {
235 case STATUS_SPEED_100: 237 case STATUS_SPEED_100:
236 mii->mii_media_active |= IFM_100_TX; 238 mii->mii_media_active |= IFM_100_TX;
237 break; 239 break;
238 case STATUS_SPEED_10: 240 case STATUS_SPEED_10:
239 mii->mii_media_active |= IFM_10_T; 241 mii->mii_media_active |= IFM_10_T;
240 break; 242 break;
241 default: 243 default:
242 mii->mii_media_active |= IFM_NONE; 244 mii->mii_media_active |= IFM_NONE;
243 return; 245 return;
244 } 246 }
245 if ((physts & STATUS_FULL_DUPLEX) != 0) 247 if ((physts & STATUS_FULL_DUPLEX) != 0)
246 mii->mii_media_active |= IFM_FDX | mii_phy_flowstatus(sc); 248 mii->mii_media_active |= IFM_FDX | mii_phy_flowstatus(sc);
247 else 249 else
248 mii->mii_media_active |= IFM_HDX; 250 mii->mii_media_active |= IFM_HDX;
249} 251}