 @@ -1,1156 +1,1162 @@
-/*	$NetBSD: specialreg.h,v 1.150.2.5 2019/11/19 13:15:57 martin Exp $	*/
+/*	$NetBSD: specialreg.h,v 1.150.2.6 2020/04/14 17:15:02 martin Exp $	*/
 /*
  * Copyright (c) 2014-2019 The NetBSD Foundation, Inc.
  * All rights reserved.
+ *
  * Redistribution and use in source and binary forms, with or without
  * modification, are permitted provided that the following conditions
  * are met:
  * 1. Redistributions of source code must retain the above copyright
  *    notice, this list of conditions and the following disclaimer.
  * 2. Redistributions in binary form must reproduce the above copyright
  *    notice, this list of conditions and the following disclaimer in the
  *    documentation and/or other materials provided with the distribution.
+ *
  * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
  * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
  * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
  * PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
  * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
  * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
  * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
  * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
  * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
  * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
  * POSSIBILITY OF SUCH DAMAGE.
  */
 /*
  * Copyright (c) 1991 The Regents of the University of California.
  * All rights reserved.
+ *
  * Redistribution and use in source and binary forms, with or without
  * modification, are permitted provided that the following conditions
  * are met:
  * 1. Redistributions of source code must retain the above copyright
  *    notice, this list of conditions and the following disclaimer.
  * 2. Redistributions in binary form must reproduce the above copyright
  *    notice, this list of conditions and the following disclaimer in the
  *    documentation and/or other materials provided with the distribution.
  * 3. Neither the name of the University nor the names of its contributors
  *    may be used to endorse or promote products derived from this software
  *    without specific prior written permission.
+ *
  * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
  * ARE DISCLAIMED.  IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
  * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
  * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
  * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
  * SUCH DAMAGE.
+ *
  *	@(#)specialreg.h	7.1 (Berkeley) 5/9/91
  */
 /*
  * CR0
  */
 #define CR0_PE	0x00000001	/* Protected mode Enable */
 #define CR0_MP	0x00000002	/* "Math" Present (NPX or NPX emulator) */
 #define CR0_EM	0x00000004	/* EMulate non-NPX coproc. (trap ESC only) */
 #define CR0_TS	0x00000008	/* Task Switched (if MP, trap ESC and WAIT) */
 #define CR0_ET	0x00000010	/* Extension Type (387 (if set) vs 287) */
 #define CR0_NE	0x00000020	/* Numeric Error enable (EX16 vs IRQ13) */
 #define CR0_WP	0x00010000	/* Write Protect (honor PTE_W in all modes) */
 #define CR0_AM	0x00040000	/* Alignment Mask (set to enable AC flag) */
 #define CR0_NW	0x20000000	/* Not Write-through */
 #define CR0_CD	0x40000000	/* Cache Disable */
 #define CR0_PG	0x80000000	/* PaGing enable */
 /*
  * Cyrix 486 DLC special registers, accessible as IO ports
  */
 #define CCR0		0xc0	/* configuration control register 0 */
 #define CCR0_NC0	0x01	/* first 64K of each 1M memory region is non-cacheable */
 #define CCR0_NC1	0x02	/* 640K-1M region is non-cacheable */
 #define CCR0_A20M	0x04	/* enables A20M# input pin */
 #define CCR0_KEN	0x08	/* enables KEN# input pin */
 #define CCR0_FLUSH	0x10	/* enables FLUSH# input pin */
 #define CCR0_BARB	0x20	/* flushes internal cache when entering hold state */
 #define CCR0_CO		0x40	/* cache org: 1=direct mapped, 0=2x set assoc */
 #define CCR0_SUSPEND	0x80	/* enables SUSP# and SUSPA# pins */
 #define CCR1		0xc1	/* configuration control register 1 */
 #define CCR1_RPL	0x01	/* enables RPLSET and RPLVAL# pins */
 /*
  * CR3
  */
 #define CR3_PCID		__BITS(11,0)
 #define CR3_PA			__BITS(62,12)
 #define CR3_NO_TLB_FLUSH	__BIT(63)
 /*
  * CR4
  */
 #define CR4_VME		0x00000001 /* virtual 8086 mode extension enable */
 #define CR4_PVI		0x00000002 /* protected mode virtual interrupt enable */
 #define CR4_TSD		0x00000004 /* restrict RDTSC instruction to cpl 0 */
 #define CR4_DE		0x00000008 /* debugging extension */
 #define CR4_PSE		0x00000010 /* large (4MB) page size enable */
 #define CR4_PAE		0x00000020 /* physical address extension enable */
 #define CR4_MCE		0x00000040 /* machine check enable */
 #define CR4_PGE		0x00000080 /* page global enable */
 #define CR4_PCE		0x00000100 /* enable RDPMC instruction for all cpls */
 #define CR4_OSFXSR	0x00000200 /* enable fxsave/fxrestor and SSE */
 #define CR4_OSXMMEXCPT	0x00000400 /* enable unmasked SSE exceptions */
 #define CR4_UMIP	0x00000800 /* user-mode instruction prevention */
 #define CR4_VMXE	0x00002000 /* enable VMX operations */
 #define CR4_SMXE	0x00004000 /* enable SMX operations */
 #define CR4_FSGSBASE	0x00010000 /* enable *FSBASE and *GSBASE instructions */
 #define CR4_PCIDE	0x00020000 /* enable Process Context IDentifiers */
 #define CR4_OSXSAVE	0x00040000 /* enable xsave and xrestore */
 #define CR4_SMEP	0x00100000 /* enable SMEP support */
 #define CR4_SMAP	0x00200000 /* enable SMAP support */
 #define CR4_PKE		0x00400000 /* protection key enable */
 /*
  * Extended Control Register XCR0
  */
 #define XCR0_X87	0x00000001	/* x87 FPU/MMX state */
 #define XCR0_SSE	0x00000002	/* SSE state */
 #define XCR0_YMM_Hi128	0x00000004	/* AVX-256 (ymmn registers) */
 #define XCR0_BNDREGS	0x00000008	/* Memory protection ext bounds */
 #define XCR0_BNDCSR	0x00000010	/* Memory protection ext state */
 #define XCR0_Opmask	0x00000020	/* AVX-512 Opmask */
 #define XCR0_ZMM_Hi256	0x00000040	/* AVX-512 upper 256 bits low regs */
 #define XCR0_Hi16_ZMM	0x00000080	/* AVX-512 512 bits upper registers */
 #define XCR0_PT		0x00000100	/* Processor Trace state */
 #define XCR0_PKRU	0x00000200	/* Protection Key state */
 #define XCR0_HDC	0x00002000	/* Hardware Duty Cycle state */
 #define XCR0_FLAGS1	"\20" \
 	"\1" "x87"		"\2" "SSE"		"\3" "AVX"	\
 	"\4" "BNDREGS"		"\5" "BNDCSR"		"\6" "Opmask"	\
 	"\7" "ZMM_Hi256"	"\10" "Hi16_ZMM"	"\11" "PT"	\
 	"\12" "PKRU"		"\16" "HDC"
 /*
  * Known FPU bits, only these get enabled. The save area is sized for all the
  * fields below.
  */
 #define XCR0_FPU	(XCR0_X87 | XCR0_SSE | XCR0_YMM_Hi128 | \
 			 XCR0_Opmask | XCR0_ZMM_Hi256 | XCR0_Hi16_ZMM)
 /*
  * XSAVE component indices.
  */
 #define XSAVE_X87	0
 #define XSAVE_SSE	1
 #define XSAVE_YMM_Hi128	2
 #define XSAVE_BNDREGS	3
 #define XSAVE_BNDCSR	4
 #define XSAVE_Opmask	5
 #define XSAVE_ZMM_Hi256	6
 #define XSAVE_Hi16_ZMM	7
 #define XSAVE_PT	8
 #define XSAVE_PKRU	9
 #define XSAVE_HDC	10
 /*
  * Highest XSAVE component enabled by XCR0_FPU.
  */
 #define XSAVE_MAX_COMPONENT XSAVE_Hi16_ZMM
 /*
  * CPUID "features" bits
  */
 /* Fn00000001 %edx features */
 #define CPUID_FPU	0x00000001	/* processor has an FPU? */
 #define CPUID_VME	0x00000002	/* has virtual mode (%cr4's VME/PVI) */
 #define CPUID_DE	0x00000004	/* has debugging extension */
 #define CPUID_PSE	0x00000008	/* has 4MB page size extension */
 #define CPUID_TSC	0x00000010	/* has time stamp counter */
 #define CPUID_MSR	0x00000020	/* has model specific registers */
 #define CPUID_PAE	0x00000040	/* has phys address extension */
 #define CPUID_MCE	0x00000080	/* has machine check exception */
 #define CPUID_CX8	0x00000100	/* has CMPXCHG8B instruction */
 #define CPUID_APIC	0x00000200	/* has enabled APIC */
 #define CPUID_B10	0x00000400	/* reserved, MTRR */
 #define CPUID_SEP	0x00000800	/* has SYSENTER/SYSEXIT extension */
 #define CPUID_MTRR	0x00001000	/* has memory type range register */
 #define CPUID_PGE	0x00002000	/* has page global extension */
 #define CPUID_MCA	0x00004000	/* has machine check architecture */
 #define CPUID_CMOV	0x00008000	/* has CMOVcc instruction */
 #define CPUID_PAT	0x00010000	/* Page Attribute Table */
 #define CPUID_PSE36	0x00020000	/* 36-bit PSE */
 #define CPUID_PN	0x00040000	/* processor serial number */
 #define CPUID_CFLUSH	0x00080000	/* CLFLUSH insn supported */
 #define CPUID_B20	0x00100000	/* reserved */
 #define CPUID_DS	0x00200000	/* Debug Store */
 #define CPUID_ACPI	0x00400000	/* ACPI performance modulation regs */
 #define CPUID_MMX	0x00800000	/* MMX supported */
 #define CPUID_FXSR	0x01000000	/* fast FP/MMX save/restore */
 #define CPUID_SSE	0x02000000	/* streaming SIMD extensions */
 #define CPUID_SSE2	0x04000000	/* streaming SIMD extensions #2 */
 #define CPUID_SS	0x08000000	/* self-snoop */
 #define CPUID_HTT	0x10000000	/* Hyper-Threading Technology */
 #define CPUID_TM	0x20000000	/* thermal monitor (TCC) */
 #define CPUID_IA64	0x40000000	/* IA-64 architecture */
 #define CPUID_SBF	0x80000000	/* signal break on FERR */
 #define CPUID_FLAGS1	"\20" \
 	"\1" "FPU"	"\2" "VME"	"\3" "DE"	"\4" "PSE" \
 	"\5" "TSC"	"\6" "MSR"	"\7" "PAE"	"\10" "MCE" \
 	"\11" "CX8"	"\12" "APIC"	"\13" "B10"	"\14" "SEP" \
 	"\15" "MTRR"	"\16" "PGE"	"\17" "MCA"	"\20" "CMOV" \
 	"\21" "PAT"	"\22" "PSE36"	"\23" "PN"	"\24" "CLFLUSH" \
 	"\25" "B20"	"\26" "DS"	"\27" "ACPI"	"\30" "MMX" \
 	"\31" "FXSR"	"\32" "SSE"	"\33" "SSE2"	"\34" "SS" \
 	"\35" "HTT"	"\36" "TM"	"\37" "IA64"	"\40" "SBF"
 /* Blacklists of CPUID flags - used to mask certain features */
 #ifdef XENPV
 #define CPUID_FEAT_BLACKLIST	 (CPUID_PGE|CPUID_PSE|CPUID_MTRR)
 #else
 #define CPUID_FEAT_BLACKLIST	 0
 #endif
 /*
  * CPUID "features" bits in Fn00000001 %ecx
  */
 #define CPUID2_SSE3	0x00000001	/* Streaming SIMD Extensions 3 */
 #define CPUID2_PCLMUL	0x00000002	/* PCLMULQDQ instructions */
 #define CPUID2_DTES64	0x00000004	/* 64-bit Debug Trace */
 #define CPUID2_MONITOR	0x00000008	/* MONITOR/MWAIT instructions */
 #define CPUID2_DS_CPL	0x00000010	/* CPL Qualified Debug Store */
 #define CPUID2_VMX	0x00000020	/* Virtual Machine Extensions */
 #define CPUID2_SMX	0x00000040	/* Safer Mode Extensions */
 #define CPUID2_EST	0x00000080	/* Enhanced SpeedStep Technology */
 #define CPUID2_TM2	0x00000100	/* Thermal Monitor 2 */
 #define CPUID2_SSSE3	0x00000200	/* Supplemental SSE3 */
 #define CPUID2_CID	0x00000400	/* Context ID */
 #define CPUID2_SDBG	0x00000800	/* Silicon Debug */
 #define CPUID2_FMA	0x00001000	/* has Fused Multiply Add */
 #define CPUID2_CX16	0x00002000	/* has CMPXCHG16B instruction */
 #define CPUID2_xTPR	0x00004000	/* Task Priority Messages disabled? */
 #define CPUID2_PDCM	0x00008000	/* Perf/Debug Capability MSR */
 /* bit 16 unused	0x00010000 */
 #define CPUID2_PCID	0x00020000	/* Process Context ID */
 #define CPUID2_DCA	0x00040000	/* Direct Cache Access */
 #define CPUID2_SSE41	0x00080000	/* Streaming SIMD Extensions 4.1 */
 #define CPUID2_SSE42	0x00100000	/* Streaming SIMD Extensions 4.2 */
 #define CPUID2_X2APIC	0x00200000	/* xAPIC Extensions */
 #define CPUID2_MOVBE	0x00400000	/* MOVBE (move after byteswap) */
 #define CPUID2_POPCNT	0x00800000	/* popcount instruction available */
 #define CPUID2_DEADLINE	0x01000000	/* APIC Timer supports TSC Deadline */
 #define CPUID2_AES	0x02000000	/* AES instructions */
 #define CPUID2_XSAVE	0x04000000	/* XSAVE instructions */
 #define CPUID2_OSXSAVE	0x08000000	/* XGETBV/XSETBV instructions */
 #define CPUID2_AVX	0x10000000	/* AVX instructions */
 #define CPUID2_F16C	0x20000000	/* half precision conversion */
 #define CPUID2_RDRAND	0x40000000	/* RDRAND (hardware random number) */
 #define CPUID2_RAZ	0x80000000	/* RAZ. Indicates guest state. */
 #define CPUID2_FLAGS1	"\20" \
 	"\1" "SSE3"	"\2" "PCLMULQDQ" "\3" "DTES64"	"\4" "MONITOR" \
 	"\5" "DS-CPL"	"\6" "VMX"	"\7" "SMX"	"\10" "EST" \
 	"\11" "TM2"	"\12" "SSSE3"	"\13" "CID"	"\14" "SDBG" \
 	"\15" "FMA"	"\16" "CX16"	"\17" "xTPR"	"\20" "PDCM" \
 	"\21" "B16"	"\22" "PCID"	"\23" "DCA"	"\24" "SSE41" \
 	"\25" "SSE42"	"\26" "X2APIC"	"\27" "MOVBE"	"\30" "POPCNT" \
 	"\31" "DEADLINE" "\32" "AES"	"\33" "XSAVE"	"\34" "OSXSAVE" \
 	"\35" "AVX"	"\36" "F16C"	"\37" "RDRAND"	"\40" "RAZ"
 /* CPUID Fn00000001 %eax */
 #define CPUID_TO_BASEFAMILY(cpuid)	(((cpuid) >> 8) & 0xf)
 #define CPUID_TO_BASEMODEL(cpuid)	(((cpuid) >> 4) & 0xf)
 #define CPUID_TO_STEPPING(cpuid)	((cpuid) & 0xf)
 /*
  * The Extended family bits should only be inspected when CPUID_TO_BASEFAMILY()
  * returns 15. They are use to encode family value 16 to 270 (add 15).
  * The Extended model bits are the high 4 bits of the model.
  * They are only valid for family >= 15 or family 6 (intel, but all amd
  * family 6 are documented to return zero bits for them).
  */
 #define CPUID_TO_EXTFAMILY(cpuid)	(((cpuid) >> 20) & 0xff)
 #define CPUID_TO_EXTMODEL(cpuid)	(((cpuid) >> 16) & 0xf)
 /* The macros for the Display Family and the Display Model */
 #define CPUID_TO_FAMILY(cpuid)	(CPUID_TO_BASEFAMILY(cpuid)	\
 	    + ((CPUID_TO_BASEFAMILY(cpuid) != 0x0f)		\
 		? 0 : CPUID_TO_EXTFAMILY(cpuid)))
 #define CPUID_TO_MODEL(cpuid)	(CPUID_TO_BASEMODEL(cpuid)	\
 	    | ((CPUID_TO_BASEFAMILY(cpuid) != 0x0f)		\
 		&& (CPUID_TO_BASEFAMILY(cpuid) != 0x06)		\
 		? 0 : (CPUID_TO_EXTMODEL(cpuid) << 4)))
 /* CPUID Fn00000001 %ebx */
 #define	CPUID_BRAND_INDEX	__BITS(7,0)
 #define	CPUID_CLFLUSH_SIZE	__BITS(15,8)
 #define	CPUID_HTT_CORES		__BITS(23,16)
 #define	CPUID_LOCAL_APIC_ID	__BITS(31,24)
 /*
  * Intel Deterministic Cache Parameter Leaf
  * Fn0000_0004
  */
 /* %eax */
 #define CPUID_DCP_CACHETYPE	__BITS(4, 0)	/* Cache type */
 #define CPUID_DCP_CACHETYPE_N	0		/*   NULL */
 #define CPUID_DCP_CACHETYPE_D	1		/*   Data cache */
 #define CPUID_DCP_CACHETYPE_I	2		/*   Instruction cache */
 #define CPUID_DCP_CACHETYPE_U	3		/*   Unified cache */
 #define CPUID_DCP_CACHELEVEL	__BITS(7, 5)	/* Cache level (start at 1) */
 #define CPUID_DCP_SELFINITCL	__BIT(8)	/* Self initializing cachelvl*/
 #define CPUID_DCP_FULLASSOC	__BIT(9)	/* Full associative */
 #define CPUID_DCP_SHAREING	__BITS(25, 14)	/* shareing */
 #define CPUID_DCP_CORE_P_PKG	__BITS(31, 26)	/* Cores/package */
 /* %ebx */
 #define CPUID_DCP_LINESIZE	__BITS(11, 0)	/* System coherency linesize */
 #define CPUID_DCP_PARTITIONS	__BITS(21, 12)	/* Physical line partitions */
 #define CPUID_DCP_WAYS		__BITS(31, 22)	/* Ways of associativity */
 /* Number of sets: %ecx */
 /* %edx */
 #define CPUID_DCP_INVALIDATE	__BIT(0)	/* WB invalidate/invalidate */
 #define CPUID_DCP_INCLUSIVE	__BIT(1)	/* Cache inclusiveness */
 #define CPUID_DCP_COMPLEX	__BIT(2)	/* Complex cache indexing */
 /*
  * Intel/AMD MONITOR/MWAIT
  * Fn0000_0005
  */
 /* %eax */
 #define CPUID_MON_MINSIZE	__BITS(15, 0)  /* Smallest monitor-line size */
 /* %ebx */
 #define CPUID_MON_MAXSIZE	__BITS(15, 0)  /* Largest monitor-line size */
 /* %ecx */
 #define CPUID_MON_EMX		__BIT(0)       /* MONITOR/MWAIT Extensions */
 #define CPUID_MON_IBE		__BIT(1)       /* Interrupt as Break Event */
 #define CPUID_MON_FLAGS	"\20" \
 	"\1" "EMX"	"\2" "IBE"
 /* %edx: number of substates for specific C-state */
 #define CPUID_MON_SUBSTATE(edx, cstate) (((edx) >> (cstate * 4)) & 0x0000000f)
 /*
  * Intel/AMD Digital Thermal Sensor and
  * Power Management, Fn0000_0006 - %eax.
  */
 #define CPUID_DSPM_DTS	__BIT(0)	/* Digital Thermal Sensor */
 #define CPUID_DSPM_IDA	__BIT(1)	/* Intel Dynamic Acceleration */
 #define CPUID_DSPM_ARAT	__BIT(2)	/* Always Running APIC Timer */
 #define CPUID_DSPM_PLN	__BIT(4)	/* Power Limit Notification */
 #define CPUID_DSPM_ECMD	__BIT(5)	/* Clock Modulation Extension */
 #define CPUID_DSPM_PTM	__BIT(6)	/* Package Level Thermal Management */
 #define CPUID_DSPM_HWP	__BIT(7)	/* HWP */
 #define CPUID_DSPM_HWP_NOTIFY __BIT(8)	/* HWP Notification */
 #define CPUID_DSPM_HWP_ACTWIN  __BIT(9)	/* HWP Activity Window */
 #define CPUID_DSPM_HWP_EPP __BIT(10)	/* HWP Energy Performance Preference */
 #define CPUID_DSPM_HWP_PLR __BIT(11)	/* HWP Package Level Request */
 #define CPUID_DSPM_HDC	__BIT(13)	/* Hardware Duty Cycling */
 #define CPUID_DSPM_TBMT3 __BIT(14)	/* Turbo Boost Max Technology 3.0 */
 #define CPUID_DSPM_HWP_CAP    __BIT(15)	/* HWP Capabilities */
 #define CPUID_DSPM_HWP_PECI   __BIT(16)	/* HWP PECI override */
 #define CPUID_DSPM_HWP_FLEX   __BIT(17)	/* Flexible HWP */
 #define CPUID_DSPM_HWP_FAST   __BIT(18)	/* Fast access for IA32_HWP_REQUEST */
 #define CPUID_DSPM_HWP_IGNIDL __BIT(20)	/* Ignore Idle Logical Processor HWP */
 #define CPUID_DSPM_FLAGS	"\20" \
 	"\1" "DTS"	"\2" "IDA"	"\3" "ARAT" 			\
 	"\5" "PLN"	"\6" "ECMD"	"\7" "PTM"	"\10" "HWP"	\
 	"\11" "HWP_NOTIFY" "\12" "HWP_ACTWIN" "\13" "HWP_EPP" "\14" "HWP_PLR" \
 			"\16" "HDC"	"\17" "TBM3"	"\20" "HWP_CAP" \
 	"\21" "HWP_PECI" "\22" "HWP_FLEX" "\23" "HWP_FAST"		\
 	"25" "HWP_IGNIDL"
 /*
  * Intel/AMD Digital Thermal Sensor and
  * Power Management, Fn0000_0006 - %ecx.
  */
 #define CPUID_DSPM_HWF	0x00000001	/* MSR_APERF/MSR_MPERF available */
 #define CPUID_DSPM_EPB	0x00000008	/* Energy Performance Bias */
 #define CPUID_DSPM_FLAGS1	"\20" "\1" "HWF" "\4" "EPB"
 /*
  * Intel/AMD Structured Extended Feature leaf Fn0000_0007
  * %eax == 0: Subleaf 0
  *	%eax: The Maximum input value for supported subleaf.
  *	%ebx: Feature bits.
  *	%ecx: Feature bits.
  *	%edx: Feature bits.
  */
 /* %ebx */
 #define CPUID_SEF_FSGSBASE	__BIT(0)  /* {RD,WR}{FS,GS}BASE */
 #define CPUID_SEF_TSC_ADJUST	__BIT(1)  /* IA32_TSC_ADJUST MSR support */
 #define CPUID_SEF_SGX		__BIT(2)  /* Software Guard Extensions */
 #define CPUID_SEF_BMI1		__BIT(3)  /* advanced bit manipulation ext. 1st grp */
 #define CPUID_SEF_HLE		__BIT(4)  /* Hardware Lock Elision */
 #define CPUID_SEF_AVX2		__BIT(5)  /* Advanced Vector Extensions 2 */
 #define CPUID_SEF_FDPEXONLY	__BIT(6)  /* x87FPU Data ptr updated only on x87exp */
 #define CPUID_SEF_SMEP		__BIT(7)  /* Supervisor-Mode Execution Prevention */
 #define CPUID_SEF_BMI2		__BIT(8)  /* advanced bit manipulation ext. 2nd grp */
 #define CPUID_SEF_ERMS		__BIT(9)  /* Enhanced REP MOVSB/STOSB */
 #define CPUID_SEF_INVPCID	__BIT(10) /* INVPCID instruction */
 #define CPUID_SEF_RTM		__BIT(11) /* Restricted Transactional Memory */
 #define CPUID_SEF_QM		__BIT(12) /* Resource Director Technology Monitoring */
 #define CPUID_SEF_FPUCSDS	__BIT(13) /* Deprecate FPU CS and FPU DS values */
 #define CPUID_SEF_MPX		__BIT(14) /* Memory Protection Extensions */
 #define CPUID_SEF_PQE		__BIT(15) /* Resource Director Technology Allocation */
 #define CPUID_SEF_AVX512F	__BIT(16) /* AVX-512 Foundation */
 #define CPUID_SEF_AVX512DQ	__BIT(17) /* AVX-512 Double/Quadword */
 #define CPUID_SEF_RDSEED	__BIT(18) /* RDSEED instruction */
 #define CPUID_SEF_ADX		__BIT(19) /* ADCX/ADOX instructions */
 #define CPUID_SEF_SMAP		__BIT(20) /* Supervisor-Mode Access Prevention */
 #define CPUID_SEF_AVX512_IFMA	__BIT(21) /* AVX-512 Integer Fused Multiply Add */
 /* Bit 22 was PCOMMIT */
 #define CPUID_SEF_CLFLUSHOPT	__BIT(23) /* Cache Line FLUSH OPTimized */
 #define CPUID_SEF_CLWB		__BIT(24) /* Cache Line Write Back */
 #define CPUID_SEF_PT		__BIT(25) /* Processor Trace */
 #define CPUID_SEF_AVX512PF	__BIT(26) /* AVX-512 PreFetch */
 #define CPUID_SEF_AVX512ER	__BIT(27) /* AVX-512 Exponential and Reciprocal */
 #define CPUID_SEF_AVX512CD	__BIT(28) /* AVX-512 Conflict Detection */
 #define CPUID_SEF_SHA		__BIT(29) /* SHA Extensions */
 #define CPUID_SEF_AVX512BW	__BIT(30) /* AVX-512 Byte and Word */
 #define CPUID_SEF_AVX512VL	__BIT(31) /* AVX-512 Vector Length */
 #define CPUID_SEF_FLAGS	"\20" \
 	"\1" "FSGSBASE"	"\2" "TSCADJUST" "\3" "SGX"	"\4" "BMI1"	\
 	"\5" "HLE"	"\6" "AVX2"	"\7" "FDPEXONLY" "\10" "SMEP"	\
 	"\11" "BMI2"	"\12" "ERMS"	"\13" "INVPCID"	"\14" "RTM"	\
 	"\15" "QM"	"\16" "FPUCSDS"	"\17" "MPX"    	"\20" "PQE"	\
 	"\21" "AVX512F"	"\22" "AVX512DQ" "\23" "RDSEED"	"\24" "ADX"	\
 	"\25" "SMAP"	"\26" "AVX512_IFMA"		"\30" "CLFLUSHOPT" \
 	"\31" "CLWB"	"\32" "PT"	"\33" "AVX512PF" "\34" "AVX512ER" \
 	"\35" "AVX512CD""\36" "SHA"	"\37" "AVX512BW" "\40" "AVX512VL"
 /* %ecx */
 #define CPUID_SEF_PREFETCHWT1	__BIT(0)  /* PREFETCHWT1 instruction */
 #define CPUID_SEF_AVX512_VBMI	__BIT(1)  /* AVX-512 Vector Byte Manipulation */
 #define CPUID_SEF_UMIP		__BIT(2)  /* User-Mode Instruction prevention */
 #define CPUID_SEF_PKU		__BIT(3)  /* Protection Keys for User-mode pages */
 #define CPUID_SEF_OSPKE		__BIT(4)  /* OS has set CR4.PKE to ena. protec. keys */
 #define CPUID_SEF_WAITPKG	__BIT(5)  /* TPAUSE,UMONITOR,UMWAIT */
 #define CPUID_SEF_AVX512_VBMI2	__BIT(6)  /* AVX-512 Vector Byte Manipulation 2 */
 #define CPUID_SEF_CET_SS	__BIT(7)  /* CET shadow stack */
 #define CPUID_SEF_GFNI		__BIT(8)
 #define CPUID_SEF_VAES		__BIT(9)
 #define CPUID_SEF_VPCLMULQDQ	__BIT(10)
 #define CPUID_SEF_AVX512_VNNI	__BIT(11) /* Vector neural Network Instruction */
 #define CPUID_SEF_AVX512_BITALG	__BIT(12)
 #define CPUID_SEF_AVX512_VPOPCNTDQ __BIT(14)
 #define CPUID_SEF_MAWAU		__BITS(21, 17) /* MAWAU for BND{LD,ST}X */
 #define CPUID_SEF_RDPID		__BIT(22) /* RDPID and IA32_TSC_AUX */
 #define CPUID_SEF_CLDEMOTE	__BIT(25) /* Cache line demote */
 #define CPUID_SEF_MOVDIRI	__BIT(27) /* MOVDIRI instruction */
 #define CPUID_SEF_MOVDIR64B	__BIT(28) /* MOVDIR64B instruction */
 #define CPUID_SEF_SGXLC		__BIT(30) /* SGX Launch Configuration */
 #define CPUID_SEF_FLAGS1	"\177\20" \
 	"b\0PREFETCHWT1\0" "b\1AVX512_VBMI\0" "b\2UMIP\0" "b\3PKU\0"	\
 	"b\4OSPKE\0"	"b\5WAITPKG\0"	"b\6AVX512_VBMI2\0" "b\7CET_SS\0" \
 	"b\10GFNI\0"	"b\11VAES\0"	"b\12VPCLMULQDQ\0" "b\13AVX512_VNNI\0"\
 	"b\14AVX512_BITALG\0"		"b\16AVX512_VPOPCNTDQ\0"	\
 	"f\21\5MAWAU\0"							\
 					"b\26RDPID\0"			\
 			"b\31CLDEMOTE\0"		"b\33MOVDIRI\0"	\
 	"b\34MOVDIR64B\0"		"b\36SGXLC\0"
 /* %edx */
 #define CPUID_SEF_AVX512_4VNNIW	__BIT(2)
 #define CPUID_SEF_AVX512_4FMAPS	__BIT(3)
 #define CPUID_SEF_FSREP_MOV	__BIT(4)  /* Fast Short REP MOV */
 #define CPUID_SEF_AVX512_VP2INTERSECT __BIT(8)
 #define CPUID_SEF_MD_CLEAR	__BIT(10)
 #define CPUID_SEF_TSX_FORCE_ABORT __BIT(13) /* MSR_TSX_FORCE_ABORT bit 0 */
 #define CPUID_SEF_SERIALIZE	__BIT(14)
 #define CPUID_SEF_HYBRID	__BIT(15) /* Hybrid part */
 #define CPUID_SEF_TSXLDTRK	__BIT(16) /* TSX suspend load addr tracking */
 #define CPUID_SEF_CET_IBT	__BIT(20) /* CET Indirect Branch Tracking */
 #define CPUID_SEF_IBRS		__BIT(26) /* IBRS / IBPB Speculation Control */
 #define CPUID_SEF_STIBP		__BIT(27) /* STIBP Speculation Control */
 #define CPUID_SEF_L1D_FLUSH	__BIT(28) /* IA32_FLUSH_CMD MSR */
 #define CPUID_SEF_ARCH_CAP	__BIT(29) /* IA32_ARCH_CAPABILITIES */
 #define CPUID_SEF_CORE_CAP	__BIT(30) /* IA32_CORE_CAPABILITIES */
 #define CPUID_SEF_SSBD		__BIT(31) /* Speculative Store Bypass Disable */
 #define CPUID_SEF_FLAGS2	"\20" \
 				"\3" "AVX512_4VNNIW" "\4" "AVX512_4FMAPS" \
 	"\5" "FSREP_MOV"						\
-				"\13" "MD_CLEAR"			\
+	"\11" "VP2INTERSECT"	"\13" "MD_CLEAR"			\
-			"\16" "TSX_FORCE_ABORT"		"\20" "HYBRID"	\
+			"\16TSX_FORCE_ABORT" "\17SERIALIZE" "\20HYBRID"	\
 	"\21" "TSXLDTRK"						\
 	"\25" "CET_IBT"							\
 	"\33" "IBRS"	"\34" "STIBP"					\
 	"\35" "L1D_FLUSH" "\36" "ARCH_CAP" "\37CORE_CAP"	"\40" "SSBD"
 /*
  * Intel CPUID Architectural Performance Monitoring Fn0000000a
+ *
  * See also src/usr.sbin/tprof/arch/tprof_x86.c
  */
 /* %eax */
 #define CPUID_PERF_VERSION	__BITS(7, 0)   /* Version ID */
 #define CPUID_PERF_NGPPC	__BITS(15, 8)  /* Num of G.P. perf counter */
 #define CPUID_PERF_NBWGPPC	__BITS(23, 16) /* Bit width of G.P. perfcnt */
 #define CPUID_PERF_BVECLEN	__BITS(31, 24) /* Length of EBX bit vector */
 #define CPUID_PERF_FLAGS0	"\177\20"	\
 	"f\0\10VERSION\0" "f\10\10GPCounter\0"	\
 	"f\20\10GPBitwidth\0" "f\30\10Vectorlen\0"
 /* %ebx */
 #define CPUID_PERF_CORECYCL	__BIT(0)       /* No core cycle */
 #define CPUID_PERF_INSTRETRY	__BIT(1)       /* No instruction retried */
 #define CPUID_PERF_REFCYCL	__BIT(2)       /* No reference cycles */
 #define CPUID_PERF_LLCREF	__BIT(3)       /* No LLCache reference */
 #define CPUID_PERF_LLCMISS	__BIT(4)       /* No LLCache miss */
 #define CPUID_PERF_BRINSRETR	__BIT(5)       /* No branch inst. retried */
 #define CPUID_PERF_BRMISPRRETR	__BIT(6)       /* No branch mispredict retry */
 #define CPUID_PERF_FLAGS1	"\177\20"				      \
 	"b\0CORECYCL\0" "b\1INSTRETRY\0" "b\2REFCYCL\0" "b\3LLCREF\0" \
 	"b\4LLCMISS\0" "b\5BRINSRETR\0" "b\6BRMISPRRETR\0"
 /* %edx */
 #define CPUID_PERF_NFFPC	__BITS(4, 0)   /* Num of fixed-funct perfcnt */
 #define CPUID_PERF_NBWFFPC	__BITS(12, 5)  /* Bit width of fixed-func pc */
 #define CPUID_PERF_ANYTHREADDEPR __BIT(15)      /* Any Thread deprecation */
 #define CPUID_PERF_FLAGS3	"\177\20"				\
 	"f\0\5FixedFunc\0" "f\5\10FFBitwidth\0" "b\17ANYTHREADDEPR\0"
 /*
  * Intel CPUID Extended Topology Enumeration Fn0000000b
  * %ecx == level number
  *	%eax: See below.
  *	%ebx: Number of logical processors at this level.
  *	%ecx: See below.
  *	%edx: x2APIC ID of the current logical processor.
  */
 /* %eax */
 #define CPUID_TOP_SHIFTNUM	__BITS(4, 0) /* Topology ID shift value */
 /* %ecx */
 #define CPUID_TOP_LVLNUM	__BITS(7, 0) /* Level number */
 #define CPUID_TOP_LVLTYPE	__BITS(15, 8) /* Level type */
 #define CPUID_TOP_LVLTYPE_INVAL	0	 	/* Invalid */
 #define CPUID_TOP_LVLTYPE_SMT	1	 	/* SMT */
 #define CPUID_TOP_LVLTYPE_CORE	2	 	/* Core */
 /*
  * Intel/AMD CPUID Processor extended state Enumeration Fn0000000d
+ *
  * %ecx == 0: supported features info:
  *	%eax: Valid bits of lower 32bits of XCR0
  *	%ebx: Maximum save area size for features enabled in XCR0
  *	%ecx: Maximum save area size for all cpu features
  *	%edx: Valid bits of upper 32bits of XCR0
+ *
  * %ecx == 1:
  *	%eax: Bit 0 => xsaveopt instruction available (sandy bridge onwards)
  *	%ebx: Save area size for features enabled by XCR0 | IA32_XSS
  *	%ecx: Valid bits of lower 32bits of IA32_XSS
  *	%edx: Valid bits of upper 32bits of IA32_XSS
+ *
  * %ecx >= 2: Save area details for XCR0 bit n
  *	%eax: size of save area for this feature
  *	%ebx: offset of save area for this feature
  *	%ecx, %edx: reserved
  *	All of %eax, %ebx, %ecx and %edx are zero for unsupported features.
  */
 /* %ecx=1 %eax */
 #define CPUID_PES1_XSAVEOPT	0x00000001	/* xsaveopt instruction */
 #define CPUID_PES1_XSAVEC	0x00000002	/* xsavec & compacted XRSTOR */
 #define CPUID_PES1_XGETBV	0x00000004	/* xgetbv with ECX = 1 */
 #define CPUID_PES1_XSAVES	0x00000008	/* xsaves/xrstors, IA32_XSS */
 #define CPUID_PES1_FLAGS	"\20" \
 	"\1" "XSAVEOPT"	"\2" "XSAVEC"	"\3" "XGETBV"	"\4" "XSAVES"
 /*
  * Intel Deterministic Address Translation Parameter Leaf
  * Fn0000_0018
  */
 /* %ecx=0 %eax __BITS(31, 0): the maximum input value of supported sub-leaf */
 /* %ebx */
 #define CPUID_DATP_PGSIZE	__BITS(3, 0)	/* page size */
 #define CPUID_DATP_PGSIZE_4KB	__BIT(0)	/* 4KB page support */
 #define CPUID_DATP_PGSIZE_2MB	__BIT(1)	/* 2MB page support */
 #define CPUID_DATP_PGSIZE_4MB	__BIT(2)	/* 4MB page support */
 #define CPUID_DATP_PGSIZE_1GB	__BIT(3)	/* 1GB page support */
 #define CPUID_DATP_PARTITIONING	__BITS(10, 8)	/* Partitioning */
 #define CPUID_DATP_WAYS		__BITS(31, 16)	/* Ways of associativity */
 /* Number of sets: %ecx */
 /* %edx */
 #define CPUID_DATP_TCTYPE	__BITS(4, 0)	/* Translation Cache type */
 #define CPUID_DATP_TCTYPE_N	0		/*   NULL (not valid) */
 #define CPUID_DATP_TCTYPE_D	1		/*   Data TLB */
 #define CPUID_DATP_TCTYPE_I	2		/*   Instruction TLB */
 #define CPUID_DATP_TCTYPE_U	3		/*   Unified TLB */
 #define CPUID_DATP_TCLEVEL	__BITS(7, 5)	/* TLB level (start at 1) */
 #define CPUID_DATP_FULLASSOC	__BIT(8)	/* Full associative */
 #define CPUID_DATP_SHAREING	__BITS(25, 14)	/* shareing */
 /* Intel Fn80000001 extended features - %edx */
 #define CPUID_SYSCALL	0x00000800	/* SYSCALL/SYSRET */
 #define CPUID_XD	0x00100000	/* Execute Disable (like CPUID_NOX) */
 #define CPUID_P1GB	0x04000000	/* 1GB Large Page Support */
 #define CPUID_RDTSCP	0x08000000	/* Read TSC Pair Instruction */
 #define CPUID_EM64T	0x20000000	/* Intel EM64T */
 #define CPUID_INTEL_EXT_FLAGS	"\20" \
 	"\14" "SYSCALL/SYSRET"	"\25" "XD"	"\33" "P1GB" \
 	"\34" "RDTSCP"	"\36" "EM64T"
 /* Intel Fn80000001 extended features - %ecx */
 #define CPUID_LAHF	0x00000001	/* LAHF/SAHF in IA-32e mode, 64bit sub*/
 		/*	0x00000020 */	/* LZCNT. Same as AMD's CPUID_LZCNT */
 #define CPUID_PREFETCHW	0x00000100	/* PREFETCHW */
 #define CPUID_INTEL_FLAGS4	"\20"				\
 	"\1" "LAHF"	"\02" "B01"	"\03" "B02"		\
 			"\06" "LZCNT"				\
 	"\11" "PREFETCHW"
 /* AMD/VIA Fn80000001 extended features - %edx */
 /*	CPUID_SYSCALL			   SYSCALL/SYSRET */
 #define CPUID_MPC	0x00080000	/* Multiprocessing Capable */
 #define CPUID_NOX	0x00100000	/* No Execute Page Protection */
 #define CPUID_MMXX	0x00400000	/* AMD MMX Extensions */
 /*	CPUID_MMX			   MMX supported */
 /*	CPUID_FXSR			   fast FP/MMX save/restore */
 #define CPUID_FFXSR	0x02000000	/* FXSAVE/FXSTOR Extensions */
 /*	CPUID_P1GB			   1GB Large Page Support */
 /*	CPUID_RDTSCP			   Read TSC Pair Instruction */
 /*	CPUID_EM64T			   Long mode */
 #define CPUID_3DNOW2	0x40000000	/* 3DNow! Instruction Extension */
 #define CPUID_3DNOW	0x80000000	/* 3DNow! Instructions */
 #define CPUID_EXT_FLAGS	"\20" \
 						"\14" "SYSCALL/SYSRET"	\
 							"\24" "MPC"	\
 	"\25" "NOX"			"\27" "MMXX"	"\30" "MMX"	\
 	"\31" "FXSR"	"\32" "FFXSR"	"\33" "P1GB"	"\34" "RDTSCP"	\
 			"\36" "LONG"	"\37" "3DNOW2"	"\40" "3DNOW"
 /* AMD Fn8000_0001 extended features - %ecx */
 /* 	CPUID_LAHF			   LAHF/SAHF instruction */
 #define CPUID_CMPLEGACY	0x00000002	/* Compare Legacy */
 #define CPUID_SVM	0x00000004	/* Secure Virtual Machine */
 #define CPUID_EAPIC	0x00000008	/* Extended APIC space */
 #define CPUID_ALTMOVCR0	0x00000010	/* Lock Mov Cr0 */
 #define CPUID_LZCNT	0x00000020	/* LZCNT instruction */
 #define CPUID_SSE4A	0x00000040	/* SSE4A instruction set */
 #define CPUID_MISALIGNSSE 0x00000080	/* Misaligned SSE */
 #define CPUID_3DNOWPF	0x00000100	/* 3DNow Prefetch */
 #define CPUID_OSVW	0x00000200	/* OS visible workarounds */
 #define CPUID_IBS	0x00000400	/* Instruction Based Sampling */
 #define CPUID_XOP	0x00000800	/* XOP instruction set */
 #define CPUID_SKINIT	0x00001000	/* SKINIT */
 #define CPUID_WDT	0x00002000	/* watchdog timer support */
 #define CPUID_LWP	0x00008000	/* Light Weight Profiling */
 #define CPUID_FMA4	0x00010000	/* FMA4 instructions */
 #define CPUID_TCE	0x00020000	/* Translation cache Extension */
 #define CPUID_NODEID	0x00080000	/* NodeID MSR available*/
 #define CPUID_TBM	0x00200000	/* TBM instructions */
 #define CPUID_TOPOEXT	0x00400000	/* cpuid Topology Extension */
 #define CPUID_PCEC	0x00800000	/* Perf Ctr Ext Core */
 #define CPUID_PCENB	0x01000000	/* Perf Ctr Ext NB */
 #define CPUID_SPM	0x02000000	/* Stream Perf Mon */
 #define CPUID_DBE	0x04000000	/* Data Breakpoint Extension */
 #define CPUID_PTSC	0x08000000	/* PerfTsc */
 #define CPUID_L2IPERFC	0x10000000	/* L2I performance counter Extension */
 #define CPUID_MWAITX	0x20000000	/* MWAITX/MONITORX support */
 #define CPUID_AMD_FLAGS4	"\20" \
 	"\1" "LAHF"	"\2" "CMPLEGACY" "\3" "SVM"	"\4" "EAPIC" \
 	"\5" "ALTMOVCR0" "\6" "LZCNT"	"\7" "SSE4A"	"\10" "MISALIGNSSE" \
 	"\11" "3DNOWPREFETCH" \
 			"\12" "OSVW"	"\13" "IBS"	"\14" "XOP" \
 	"\15" "SKINIT"	"\16" "WDT"	"\17" "B14"	"\20" "LWP" \
 	"\21" "FMA4"	"\22" "TCE"	"\23" "B18"	"\24" "NodeID" \
 	"\25" "B20"	"\26" "TBM"	"\27" "TopoExt"	"\30" "PCExtC" \
 	"\31" "PCExtNB"	"\32" "StrmPM"	"\33" "DBExt"	"\34" "PerfTsc" \
 	"\35" "L2IPERFC" "\36" "MWAITX"	"\37" "B30"	"\40" "B31"
 /*
- * AMD Advanced Power Management
+ * Advanced Power Management
  * CPUID Fn8000_0007 %edx
+ *
  * Only ITSC is for both Intel and AMD. Others are only for AMD.
  */
 #define CPUID_APM_TS	0x00000001	/* Temperature Sensor */
 #define CPUID_APM_FID	0x00000002	/* Frequency ID control */
 #define CPUID_APM_VID	0x00000004	/* Voltage ID control */
 #define CPUID_APM_TTP	0x00000008	/* THERMTRIP (PCI F3xE4 register) */
 #define CPUID_APM_HTC	0x00000010	/* Hardware thermal control (HTC) */
 #define CPUID_APM_STC	0x00000020	/* Software thermal control (STC) */
 #define CPUID_APM_100	0x00000040	/* 100MHz multiplier control */
 #define CPUID_APM_HWP	0x00000080	/* HW P-State control */
-#define CPUID_APM_TSC	0x00000100	/* TSC invariant */
+#define CPUID_APM_ITSC	0x00000100	/* invariant TSC */
 #define CPUID_APM_CPB	0x00000200	/* Core performance boost */
 #define CPUID_APM_EFF	0x00000400	/* Effective Frequency (read-only) */
 #define CPUID_APM_PROCFI 0x00000800	/* Proc Feedback Interface */
 #define CPUID_APM_PROCPR 0x00001000	/* Proc Power Reporting  */
 #define CPUID_APM_CONNSTBY 0x00002000	/* Connected Standby */
 #define CPUID_APM_RAPL	0x00004000	/* Running Average Power Limit */
 #define CPUID_APM_FLAGS		"\20"					      \
 	"\1" "TS"	"\2" "FID"	"\3" "VID"	"\4" "TTP"	      \
 	"\5" "HTC"	"\6" "STC"	"\7" "100"	"\10" "HWP"	      \
-	"\11" "TSC"	"\12" "CPB"	"\13" "EffFreq"	"\14" "PROCFI"	      \
+	"\11" "ITSC"	"\12" "CPB"	"\13" "EffFreq"	"\14" "PROCFI"	      \
 	"\15" "PROCPR"	"\16" "CONNSTBY" "\17" "RAPL"
 /*
  * AMD Processor Capacity Parameters and Extended Features
  * CPUID Fn8000_0008
  * %eax: Long Mode Size Identifiers
  * %ebx: Extended Feature Identifiers
  * %ecx: Size Identifiers
  */
 /* %ebx */
 #define CPUID_CAPEX_CLZERO	__BIT(0)	/* CLZERO instruction */
 #define CPUID_CAPEX_IRPERF	__BIT(1)	/* InstRetCntMsr */
 #define CPUID_CAPEX_XSAVEERPTR	__BIT(2)	/* RstrFpErrPtrs by XRSTOR */
 #define CPUID_CAPEX_RDPRU	__BIT(4)	/* RDPRU instruction */
 #define CPUID_CAPEX_MCOMMIT	__BIT(8)	/* MCOMMIT instruction */
 #define CPUID_CAPEX_WBNOINVD	__BIT(9)	/* WBNOINVD instruction */
 #define CPUID_CAPEX_IBPB	__BIT(12)	/* Speculation Control IBPB */
 #define CPUID_CAPEX_IBRS	__BIT(14)	/* Speculation Control IBRS */
 #define CPUID_CAPEX_STIBP	__BIT(15)	/* Speculation Control STIBP */
 #define CPUID_CAPEX_IBRS_ALWAYSON __BIT(16)	/* IBRS always on mode */
 #define CPUID_CAPEX_STIBP_ALWAYSON __BIT(17)	/* STIBP always on mode */
 #define CPUID_CAPEX_PREFER_IBRS	__BIT(18)	/* IBRS preferred */
 #define CPUID_CAPEX_SSBD	__BIT(24)	/* Speculation Control SSBD */
 #define CPUID_CAPEX_VIRT_SSBD	__BIT(25)	/* Virt Spec Control SSBD */
 #define CPUID_CAPEX_SSB_NO	__BIT(26)	/* SSBD not required */
 #define CPUID_CAPEX_FLAGS	"\20"					 \
 	"\1CLZERO"	"\2IRPERF"	"\3XSAVEERPTR"			 \
 	"\5RDPRU"			"\7B6"				 \
 	"\11MCOMMIT"	"\12WBNOINVD"	"\13B10"			 \
 	"\15IBPB"	"\16B13"	"\17IBRS"	"\20STIBP"	 \
 	"\21IBRS_ALWAYSON" "\22STIBP_ALWAYSON" "\23PREFER_IBRS"	"\24B19" \
 	"\31SSBD"	"\32VIRT_SSBD"	"\33SSB_NO"
 /* AMD Fn8000_000a %edx features (SVM features) */
 #define CPUID_AMD_SVM_NP		0x00000001
 #define CPUID_AMD_SVM_LbrVirt		0x00000002
 #define CPUID_AMD_SVM_SVML		0x00000004
 #define CPUID_AMD_SVM_NRIPS		0x00000008
 #define CPUID_AMD_SVM_TSCRateCtrl	0x00000010
 #define CPUID_AMD_SVM_VMCBCleanBits	0x00000020
 #define CPUID_AMD_SVM_FlushByASID	0x00000040
 #define CPUID_AMD_SVM_DecodeAssist	0x00000080
 #define CPUID_AMD_SVM_PauseFilter	0x00000400
 #define CPUID_AMD_SVM_PFThreshold	0x00001000 /* PAUSE filter threshold */
 #define CPUID_AMD_SVM_AVIC		0x00002000 /* AMD Virtual intr. ctrl */
 #define CPUID_AMD_SVM_V_VMSAVE_VMLOAD	0x00008000 /* Virtual VM{SAVE/LOAD} */
 #define CPUID_AMD_SVM_vGIF		0x00010000 /* Virtualized GIF */
 #define CPUID_AMD_SVM_GMET		0x00020000
 #define CPUID_AMD_SVM_FLAGS	 "\20" \
 	"\1" "NP"	"\2" "LbrVirt"	"\3" "SVML"	"\4" "NRIPS"	\
 	"\5" "TSCRate"	"\6" "VMCBCleanBits" 				\
 			        "\7" "FlushByASID" "\10" "DecodeAssist"	\
 	"\11" "B08"	"\12" "B09"	"\13" "PauseFilter" "\14" "B11"	\
 	"\15" "PFThreshold" "\16" "AVIC" "\17" "B14"			\
 						"\20" "V_VMSAVE_VMLOAD"	\
 	"\21" "VGIF"	"\22" "GMET"					\
 	"\25" "B20"
 /*
  * AMD Fn8000_0001d Cache Topology Information.
  * It's almost the same as Intel Deterministic Cache Parameter Leaf(0x04)
  * except the following:
  *	No Cores/package (%eax bit 31..26)
  *	No Complex cache indexing (%edx bit 2)
  */
 /*
  * AMD Fn8000_0001f Encrypted Memory Capabilities.
  * %eax: flags
  * %ebx:  5-0: Cbit Position
  *       11-6: PhysAddrReduction
  * %ecx: 31-0: NumEncryptedGuests
  * %edx: 31-0: MinSevNoEsAsid
  */
 #define CPUID_AMD_ENCMEM_SME	__BIT(0)   /* Secure Memory Encryption */
 #define CPUID_AMD_ENCMEM_SEV	__BIT(1)   /* Secure Encrypted Virtualiz. */
 #define CPUID_AMD_ENCMEM_PGFLMSR __BIT(2)  /* Page Flush MSR */
 #define CPUID_AMD_ENCMEM_SEVES	__BIT(3)   /* SEV Encrypted State */
 #define CPUID_AMD_ENCMEM_VTE	__BIT(16)  /* Virtual Transparent Encryption */
 #define CPUID_AMD_ENCMEM_FLAGS	 "\20"					      \
 	"\1" "SME"	"\2" "SEV"	"\3" "PageFlushMsr"	"\4" "SEV-ES" \
 	"\21" "VTE"
 /*
  * Centaur Extended Feature flags
  */
 #define CPUID_VIA_HAS_RNG	0x00000004	/* Random number generator */
 #define CPUID_VIA_DO_RNG	0x00000008
 #define CPUID_VIA_HAS_ACE	0x00000040	/* AES Encryption */
 #define CPUID_VIA_DO_ACE	0x00000080
 #define CPUID_VIA_HAS_ACE2	0x00000100	/* AES+CTR instructions */
 #define CPUID_VIA_DO_ACE2	0x00000200
 #define CPUID_VIA_HAS_PHE	0x00000400	/* SHA1+SHA256 HMAC */
 #define CPUID_VIA_DO_PHE	0x00000800
 #define CPUID_VIA_HAS_PMM	0x00001000	/* RSA Instructions */
 #define CPUID_VIA_DO_PMM	0x00002000
 #define CPUID_FLAGS_PADLOCK	"\20" \
 	"\3" "RNG"	"\7" "AES"	"\11" "AES/CTR"	"\13" "SHA1/SHA256" \
 	"\15" "RSA"
 /*
  * Model-Specific Registers
  */
 #define MSR_TSC			0x010
 #define MSR_IA32_PLATFORM_ID	0x017
 #define MSR_APICBASE		0x01b
 #define 	APICBASE_BSP		0x00000100	/* boot processor */
 #define 	APICBASE_EXTD		0x00000400	/* x2APIC mode */
 #define 	APICBASE_EN		0x00000800	/* software enable */
 /*
  * APICBASE_PHYSADDR is actually variable-sized on some CPUs. But we're
  * only interested in the initial value, which is guaranteed to fit the
  * first 32 bits. So this macro is fine.
  */
 #define 	APICBASE_PHYSADDR	0xfffff000	/* physical address */
 #define MSR_EBL_CR_POWERON	0x02a
 #define MSR_EBC_FREQUENCY_ID	0x02c	/* PIV only */
 #define MSR_IA32_SPEC_CTRL	0x048
 #define 	IA32_SPEC_CTRL_IBRS	0x01
 #define 	IA32_SPEC_CTRL_STIBP	0x02
 #define 	IA32_SPEC_CTRL_SSBD	0x04
 #define MSR_IA32_PRED_CMD	0x049
 #define 	IA32_PRED_CMD_IBPB	0x01
 #define MSR_BIOS_UPDT_TRIG	0x079
 #define MSR_BIOS_SIGN		0x08b
 #define MSR_PERFCTR0		0x0c1
 #define MSR_PERFCTR1		0x0c2
 #define MSR_FSB_FREQ		0x0cd	/* Core Duo/Solo only */
 #define MSR_MPERF		0x0e7
 #define MSR_APERF		0x0e8
 #define MSR_IA32_EXT_CONFIG	0x0ee	/* Undocumented. Core Solo/Duo only */
 #define MSR_MTRRcap		0x0fe
 #define MSR_IA32_ARCH_CAPABILITIES 0x10a
 #define 	IA32_ARCH_RDCL_NO	0x01
 #define 	IA32_ARCH_IBRS_ALL	0x02
 #define 	IA32_ARCH_RSBA		0x04
 #define 	IA32_ARCH_SKIP_L1DFL_VMENTRY 0x08
 #define 	IA32_ARCH_SSB_NO	0x10
 #define 	IA32_ARCH_MDS_NO	0x20
 #define 	IA32_ARCH_TSX_CTRL	0x80
 #define 	IA32_ARCH_TAA_NO	0x100
 #define MSR_IA32_FLUSH_CMD	0x10b
 #define 	IA32_FLUSH_CMD_L1D_FLUSH 0x01
 #define MSR_TSX_FORCE_ABORT	0x10f
 #define MSR_IA32_TSX_CTRL	0x122
 #define 	IA32_TSX_CTRL_RTM_DISABLE	__BIT(0)
 #define 	IA32_TSX_CTRL_TSX_CPUID_CLEAR	__BIT(1)
 #define MSR_SYSENTER_CS		0x174	/* PII+ only */
 #define MSR_SYSENTER_ESP	0x175	/* PII+ only */
 #define MSR_SYSENTER_EIP	0x176	/* PII+ only */
 #define MSR_MCG_CAP		0x179
 #define MSR_MCG_STATUS		0x17a
 #define MSR_MCG_CTL		0x17b
 #define MSR_EVNTSEL0		0x186
 #define MSR_EVNTSEL1		0x187
 #define MSR_PERF_STATUS		0x198	/* Pentium M */
 #define MSR_PERF_CTL		0x199	/* Pentium M */
 #define MSR_THERM_CONTROL	0x19a
 #define MSR_THERM_INTERRUPT	0x19b
 #define MSR_THERM_STATUS	0x19c
 #define MSR_THERM2_CTL		0x19d	/* Pentium M */
 #define MSR_MISC_ENABLE		0x1a0
 #define 	IA32_MISC_FAST_STR_EN	__BIT(0)
 #define 	IA32_MISC_ATCC_EN	__BIT(3)
 #define 	IA32_MISC_PERFMON_EN	__BIT(7)
 #define 	IA32_MISC_BTS_UNAVAIL	__BIT(11)
 #define 	IA32_MISC_PEBS_UNAVAIL	__BIT(12)
 #define 	IA32_MISC_EISST_EN	__BIT(16)
 #define 	IA32_MISC_MWAIT_EN	__BIT(18)
 #define 	IA32_MISC_LIMIT_CPUID	__BIT(22)
 #define 	IA32_MISC_XTPR_DIS	__BIT(23)
 #define 	IA32_MISC_XD_DIS	__BIT(34)
 #define MSR_TEMPERATURE_TARGET	0x1a2
 #define MSR_DEBUGCTLMSR		0x1d9
 #define MSR_LASTBRANCHFROMIP	0x1db
 #define MSR_LASTBRANCHTOIP	0x1dc
 #define MSR_LASTINTFROMIP	0x1dd
 #define MSR_LASTINTTOIP		0x1de
 #define MSR_ROB_CR_BKUPTMPDR6	0x1e0
 #define MSR_MTRRphysBase0	0x200
 #define MSR_MTRRphysMask0	0x201
 #define MSR_MTRRphysBase1	0x202
 #define MSR_MTRRphysMask1	0x203
 #define MSR_MTRRphysBase2	0x204
 #define MSR_MTRRphysMask2	0x205
 #define MSR_MTRRphysBase3	0x206
 #define MSR_MTRRphysMask3	0x207
 #define MSR_MTRRphysBase4	0x208
 #define MSR_MTRRphysMask4	0x209
 #define MSR_MTRRphysBase5	0x20a
 #define MSR_MTRRphysMask5	0x20b
 #define MSR_MTRRphysBase6	0x20c
 #define MSR_MTRRphysMask6	0x20d
 #define MSR_MTRRphysBase7	0x20e
 #define MSR_MTRRphysMask7	0x20f
 #define MSR_MTRRphysBase8	0x210
 #define MSR_MTRRphysMask8	0x211
 #define MSR_MTRRphysBase9	0x212
 #define MSR_MTRRphysMask9	0x213
 #define MSR_MTRRphysBase10	0x214
 #define MSR_MTRRphysMask10	0x215
 #define MSR_MTRRphysBase11	0x216
 #define MSR_MTRRphysMask11	0x217
 #define MSR_MTRRphysBase12	0x218
 #define MSR_MTRRphysMask12	0x219
 #define MSR_MTRRphysBase13	0x21a
 #define MSR_MTRRphysMask13	0x21b
 #define MSR_MTRRphysBase14	0x21c
 #define MSR_MTRRphysMask14	0x21d
 #define MSR_MTRRphysBase15	0x21e
 #define MSR_MTRRphysMask15	0x21f
 #define MSR_MTRRfix64K_00000	0x250
 #define MSR_MTRRfix16K_80000	0x258
 #define MSR_MTRRfix16K_A0000	0x259
 #define MSR_MTRRfix4K_C0000	0x268
 #define MSR_MTRRfix4K_C8000	0x269
 #define MSR_MTRRfix4K_D0000	0x26a
 #define MSR_MTRRfix4K_D8000	0x26b
 #define MSR_MTRRfix4K_E0000	0x26c
 #define MSR_MTRRfix4K_E8000	0x26d
 #define MSR_MTRRfix4K_F0000	0x26e
 #define MSR_MTRRfix4K_F8000	0x26f
 #define MSR_CR_PAT		0x277
 #define MSR_MTRRdefType		0x2ff
 #define MSR_MC0_CTL		0x400
 #define MSR_MC0_STATUS		0x401
 #define MSR_MC0_ADDR		0x402
 #define MSR_MC0_MISC		0x403
 #define MSR_MC1_CTL		0x404
 #define MSR_MC1_STATUS		0x405
 #define MSR_MC1_ADDR		0x406
 #define MSR_MC1_MISC		0x407
 #define MSR_MC2_CTL		0x408
 #define MSR_MC2_STATUS		0x409
 #define MSR_MC2_ADDR		0x40a
 #define MSR_MC2_MISC		0x40b
 #define MSR_MC3_CTL		0x40c
 #define MSR_MC3_STATUS		0x40d
 #define MSR_MC3_ADDR		0x40e
 #define MSR_MC3_MISC		0x40f
 #define MSR_MC4_CTL		0x410
 #define MSR_MC4_STATUS		0x411
 #define MSR_MC4_ADDR		0x412
 #define MSR_MC4_MISC		0x413
 				/* 0x480 - 0x490 VMX */
 #define MSR_X2APIC_BASE		0x800	/* 0x800 - 0xBFF */
 #define  MSR_X2APIC_ID			0x002	/* x2APIC ID. (RO) */
 #define  MSR_X2APIC_VERS		0x003	/* Version. (RO) */
 #define  MSR_X2APIC_TPRI		0x008	/* Task Prio. (RW) */
 #define  MSR_X2APIC_PPRI		0x00a	/* Processor prio. (RO) */
 #define  MSR_X2APIC_EOI			0x00b	/* End Int. (W) */
 #define  MSR_X2APIC_LDR			0x00d	/* Logical dest. (RO) */
 #define  MSR_X2APIC_SVR			0x00f	/* Spurious intvec (RW) */
 #define  MSR_X2APIC_ISR			0x010	/* In-Service Status (RO) */
 #define  MSR_X2APIC_TMR			0x018	/* Trigger Mode (RO) */
 #define  MSR_X2APIC_IRR			0x020	/* Interrupt Req (RO) */
 #define  MSR_X2APIC_ESR			0x028	/* Err status. (RW) */
 #define  MSR_X2APIC_LVT_CMCI		0x02f	/* LVT CMCI (RW) */
 #define  MSR_X2APIC_ICRLO		0x030	/* Int. cmd. (RW64) */
 #define  MSR_X2APIC_LVTT		0x032	/* Loc.vec.(timer) (RW) */
 #define  MSR_X2APIC_TMINT		0x033	/* Loc.vec (Thermal) (RW) */
 #define  MSR_X2APIC_PCINT		0x034	/* Loc.vec (Perf Mon) (RW) */
 #define  MSR_X2APIC_LVINT0		0x035	/* Loc.vec (LINT0) (RW) */
 #define  MSR_X2APIC_LVINT1		0x036	/* Loc.vec (LINT1) (RW) */
 #define  MSR_X2APIC_LVERR		0x037	/* Loc.vec (ERROR) (RW) */
 #define  MSR_X2APIC_ICR_TIMER		0x038	/* Initial count (RW) */
 #define  MSR_X2APIC_CCR_TIMER		0x039	/* Current count (RO) */
 #define  MSR_X2APIC_DCR_TIMER		0x03e	/* Divisor config (RW) */
 #define  MSR_X2APIC_SELF_IPI		0x03f	/* SELF IPI (W) */
 /*
  * VIA "Nehemiah" MSRs
  */
 #define MSR_VIA_RNG		0x0000110b
 #define MSR_VIA_RNG_ENABLE	0x00000040
 #define MSR_VIA_RNG_NOISE_MASK	0x00000300
 #define MSR_VIA_RNG_NOISE_A	0x00000000
 #define MSR_VIA_RNG_NOISE_B	0x00000100
 #define MSR_VIA_RNG_2NOISE	0x00000300
 #define MSR_VIA_ACE		0x00001107
 #define 	VIA_ACE_ALTINST	0x00000001
 #define 	VIA_ACE_ECX8	0x00000002
 #define 	VIA_ACE_ENABLE	0x10000000
 /*
  * VIA "Eden" MSRs
  */
 #define MSR_VIA_FCR		MSR_VIA_ACE
 /*
  * AMD K6/K7 MSRs.
  */
 #define MSR_K6_UWCCR		0xc0000085
 #define MSR_K7_EVNTSEL0		0xc0010000
 #define MSR_K7_EVNTSEL1		0xc0010001
 #define MSR_K7_EVNTSEL2		0xc0010002
 #define MSR_K7_EVNTSEL3		0xc0010003
 #define MSR_K7_PERFCTR0		0xc0010004
 #define MSR_K7_PERFCTR1		0xc0010005
 #define MSR_K7_PERFCTR2		0xc0010006
 #define MSR_K7_PERFCTR3		0xc0010007
 /*
  * AMD K8 (Opteron) MSRs.
  */
 #define MSR_SYSCFG	0xc0010010
 #define MSR_EFER	0xc0000080		/* Extended feature enable */
 #define 	EFER_SCE	0x00000001	/* SYSCALL extension */
 #define 	EFER_LME	0x00000100	/* Long Mode Enable */
 #define 	EFER_LMA	0x00000400	/* Long Mode Active */
 #define 	EFER_NXE	0x00000800	/* No-Execute Enabled */
 #define 	EFER_SVME	0x00001000	/* Secure Virtual Machine En. */
 #define 	EFER_LMSLE	0x00002000	/* Long Mode Segment Limit E. */
 #define 	EFER_FFXSR	0x00004000	/* Fast FXSAVE/FXRSTOR En. */
 #define 	EFER_TCE	0x00008000	/* Translation Cache Ext. */
 #define MSR_STAR	0xc0000081		/* 32 bit syscall gate addr */
 #define MSR_LSTAR	0xc0000082		/* 64 bit syscall gate addr */
 #define MSR_CSTAR	0xc0000083		/* compat syscall gate addr */
 #define MSR_SFMASK	0xc0000084		/* flags to clear on syscall */
 #define MSR_FSBASE	0xc0000100		/* 64bit offset for fs: */
 #define MSR_GSBASE	0xc0000101		/* 64bit offset for gs: */
 #define MSR_KERNELGSBASE 0xc0000102		/* storage for swapgs ins */
 #define MSR_VMCR	0xc0010114	/* Virtual Machine Control Register */
 #define 	VMCR_DPD	0x00000001	/* Debug port disable */
 #define 	VMCR_RINIT	0x00000002	/* intercept init */
 #define 	VMCR_DISA20	0x00000004	/* Disable A20 masking */
 #define 	VMCR_LOCK	0x00000008	/* SVM Lock */
 #define 	VMCR_SVMED	0x00000010	/* SVME Disable */
 #define MSR_SVMLOCK	0xc0010118	/* SVM Lock key */
 /*
  * These require a 'passcode' for access.  See cpufunc.h.
  */
 #define MSR_HWCR	0xc0010015
 #define 	HWCR_TLBCACHEDIS	0x00000008
 #define 	HWCR_FFDIS		0x00000040
 #define MSR_NB_CFG	0xc001001f
 #define 	NB_CFG_DISIOREQLOCK	0x0000000000000008ULL
 #define 	NB_CFG_DISDATMSK	0x0000001000000000ULL
 #define 	NB_CFG_INITAPICCPUIDLO	(1ULL << 54)
 #define MSR_LS_CFG	0xc0011020
 #define 	LS_CFG_ERRATA_1033	__BIT(4)
 #define 	LS_CFG_ERRATA_793	__BIT(15)
 #define 	LS_CFG_ERRATA_1095	__BIT(57)
 #define 	LS_CFG_DIS_LS2_SQUISH	0x02000000
 #define 	LS_CFG_DIS_SSB_F15H	0x0040000000000000ULL
 #define 	LS_CFG_DIS_SSB_F16H	0x0000000200000000ULL
 #define 	LS_CFG_DIS_SSB_F17H	0x0000000000000400ULL
 #define MSR_IC_CFG	0xc0011021
 #define 	IC_CFG_DIS_SEQ_PREFETCH	0x00000800
 #define 	IC_CFG_DIS_IND		0x00004000
 #define 	IC_CFG_ERRATA_776	__BIT(26)
 #define MSR_DC_CFG	0xc0011022
 #define 	DC_CFG_DIS_CNV_WC_SSO	0x00000008
 #define 	DC_CFG_DIS_SMC_CHK_BUF	0x00000400
 #define 	DC_CFG_ERRATA_261	0x01000000
 #define MSR_BU_CFG	0xc0011023
 #define 	BU_CFG_ERRATA_298	0x0000000000000002ULL
 #define 	BU_CFG_ERRATA_254	0x0000000000200000ULL
 #define 	BU_CFG_ERRATA_309	0x0000000000800000ULL
 #define 	BU_CFG_THRL2IDXCMPDIS	0x0000080000000000ULL
 #define 	BU_CFG_WBPFSMCCHKDIS	0x0000200000000000ULL
 #define 	BU_CFG_WBENHWSBDIS	0x0001000000000000ULL
 #define MSR_FP_CFG	0xc0011028
 #define 	FP_CFG_ERRATA_1049	__BIT(4)
 #define MSR_DE_CFG	0xc0011029
 #define 	DE_CFG_ERRATA_721	0x00000001
 #define 	DE_CFG_ERRATA_1021	__BIT(13)
 #define MSR_BU_CFG2	0xc001102a
 #define 	BU_CFG2_CWPLUS_DIS	__BIT(24)
 #define MSR_LS_CFG2	0xc001102d
 #define 	LS_CFG2_ERRATA_1091	__BIT(34)
 /* AMD Family10h MSRs */
 #define MSR_OSVW_ID_LENGTH		0xc0010140
 #define MSR_OSVW_STATUS			0xc0010141
 #define MSR_UCODE_AMD_PATCHLEVEL	0x0000008b
 #define MSR_UCODE_AMD_PATCHLOADER	0xc0010020
 /* X86 MSRs */
 #define MSR_RDTSCP_AUX			0xc0000103
 /*
  * Constants related to MTRRs
  */
 #define MTRR_N64K		8	/* numbers of fixed-size entries */
 #define MTRR_N16K		16
 #define MTRR_N4K		64
 /*
  * the following four 3-byte registers control the non-cacheable regions.
  * These registers must be written as three separate bytes.
+ *
  * NCRx+0: A31-A24 of starting address
  * NCRx+1: A23-A16 of starting address
  * NCRx+2: A15-A12 of starting address | NCR_SIZE_xx.
+ *
  * The non-cacheable region's starting address must be aligned to the
  * size indicated by the NCR_SIZE_xx field.
  */
 #define NCR1	0xc4
 #define NCR2	0xc7
 #define NCR3	0xca
 #define NCR4	0xcd
 #define NCR_SIZE_0K	0
 #define NCR_SIZE_4K	1
 #define NCR_SIZE_8K	2
 #define NCR_SIZE_16K	3
 #define NCR_SIZE_32K	4
 #define NCR_SIZE_64K	5
 #define NCR_SIZE_128K	6
 #define NCR_SIZE_256K	7
 #define NCR_SIZE_512K	8
 #define NCR_SIZE_1M	9
 #define NCR_SIZE_2M	10
 #define NCR_SIZE_4M	11
 #define NCR_SIZE_8M	12
 #define NCR_SIZE_16M	13
 #define NCR_SIZE_32M	14
 #define NCR_SIZE_4G	15

 @@ -1,524 +1,524 @@
-/*	$NetBSD: procfs_machdep.c,v 1.33.2.1 2019/10/17 18:56:25 martin Exp $ */
+/*	$NetBSD: procfs_machdep.c,v 1.33.2.2 2020/04/14 17:15:02 martin Exp $ */
 /*
  * Copyright (c) 2001 Wasabi Systems, Inc.
  * All rights reserved.
+ *
  * Written by Frank van der Linden and Jason R. Thorpe for
  * Wasabi Systems, Inc.
+ *
  * Redistribution and use in source and binary forms, with or without
  * modification, are permitted provided that the following conditions
  * are met:
  * 1. Redistributions of source code must retain the above copyright
  *    notice, this list of conditions and the following disclaimer.
  * 2. Redistributions in binary form must reproduce the above copyright
  *    notice, this list of conditions and the following disclaimer in the
  *    documentation and/or other materials provided with the distribution.
  * 3. All advertising materials mentioning features or use of this software
  *    must display the following acknowledgement:
  *      This product includes software developed for the NetBSD Project by
  *      Wasabi Systems, Inc.
  * 4. The name of Wasabi Systems, Inc. may not be used to endorse
  *    or promote products derived from this software without specific prior
  *    written permission.
+ *
  * THIS SOFTWARE IS PROVIDED BY WASABI SYSTEMS, INC. ``AS IS'' AND
  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
  * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
  * PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL WASABI SYSTEMS, INC
  * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
  * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
  * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
  * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
  * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
  * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
  * POSSIBILITY OF SUCH DAMAGE.
  */
 /*
  * NOTE: We simply use the primary CPU's cpuid_level and tsc_freq
  * here.  Might want to change this later.
  */
 #include <sys/cdefs.h>
-__KERNEL_RCSID(0, "$NetBSD: procfs_machdep.c,v 1.33.2.1 2019/10/17 18:56:25 martin Exp $");
+__KERNEL_RCSID(0, "$NetBSD: procfs_machdep.c,v 1.33.2.2 2020/04/14 17:15:02 martin Exp $");
 #include <sys/param.h>
 #include <sys/systm.h>
 #include <sys/mount.h>
 #include <sys/stat.h>
 #include <sys/vnode.h>
 #include <miscfs/procfs/procfs.h>
 #include <machine/cpu.h>
 #include <machine/reg.h>
 #include <machine/specialreg.h>
 #include <x86/cputypes.h>
 #include <x86/cpuvar.h>
 /*
  *  The feature table. The order is the same as Linux's
  *  x86/include/asm/cpufeatures.h.
  */
 static const char * const x86_features[][32] = {
 	{ /* (0) Common: 0x0000001 edx */
 	"fpu", "vme", "de", "pse", "tsc", "msr", "pae", "mce",
 	"cx8", "apic", NULL, "sep", "mtrr", "pge", "mca", "cmov",
 	"pat", "pse36", "pn", "clflush", NULL, "dts", "acpi", "mmx",
 	"fxsr", "sse", "sse2", "ss", "ht", "tm", "ia64", "pbe"},
 	{ /* (1) AMD-defined: 0x80000001 edx */
 	NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL,
 	NULL, NULL, NULL, "syscall", NULL, NULL, NULL, NULL,
 	NULL, NULL, NULL, "mp", "nx", NULL, "mmxext", NULL,
 	NULL, "fxsr_opt", "pdpe1gb", "rdtscp", NULL, "lm", "3dnowext","3dnow"},
 	{ /* (2) Transmeta-defined */
 	"recovery", "longrun", NULL, "lrti", NULL, NULL, NULL, NULL,
 	NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL,
 	NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL,
 	NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL},
 	{ /* (3) Linux mapping */
 	"cxmmx", NULL, "cyrix_arr", "centaur_mcr", NULL,
 	"constant_tsc", NULL, NULL,
 	NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL,
 	NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL,
 	NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL},
 	{ /* (4) Intel-defined: 0x00000001 ecx */
 	"pni", "pclmulqdq", "dtes64", "monitor", "ds_cpl", "vmx", "smx", "est",
 	"tm2", "ssse3", "cid", "sdbg", "fma", "cx16", "xtpr", "pdcm",
 	NULL, "pcid", "dca", "sse4_1", "sse4_2", "x2apic", "movbe", "popcnt",
 	"tsc_deadline_timer", "aes", "xsave", NULL,
 	"avx", "f16c", "rdrand", "hypervisor"},
 	{ /* (5) VIA/Cyrix/Centaur-defined */
 	NULL, NULL, "rng", "rng_en", NULL, NULL, "ace", "ace_en",
 	"ace2", "ace2_en", "phe", "phe_en", "pmm", "pmm_en", NULL, NULL,
 	NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL,
 	NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL},
 	{ /* (6) AMD defined 80000001 ecx */
 	"lahf_lm", "cmp_legacy", "svm", "extapic",
 	"cr8_legacy", "abm", "sse4a", "misalignsse",
 	"3dnowprefetch", "osvw", "ibs", "xop", "skinit", "wdt", NULL, "lwp",
 	"fma4", "tce", NULL, "nodeid_msr",
 	NULL, "tbm", "topoext", "perfctr_core",
 	"perfctr_nb", NULL, "bpext", "ptsc",
 	"perfctr_llc", "mwaitx", NULL, NULL},
 	{ /* (7) Linux mapping */
 	NULL, NULL, "cpb", "ebp", NULL, "pln", "pts", "dtherm",
 	"hw_pstate", "proc_feedback", "sme", NULL,
 	NULL, NULL, NULL, NULL,
 	NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL,
 	NULL, "ibrs", "ibpb", "stibp", NULL, NULL, NULL, NULL},
 	{ /* (8) Linux mapping */
 	"tpr_shadow", "vnmi", "flexpriority", "ept",
 	"vpid", "npt", "lbrv", "svm_lock",
 	"nrip_save", "tsc_scale", "vmcb_clean", "flushbyasid",
 	"decodeassists", "pausefilter", "pfthreshold", "vmmcall",
 	NULL, "ept_ad", NULL, NULL, NULL, NULL, NULL, NULL,
 	NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL},
 	{ /* (9) Intel-defined: 00000007 ebx */
 	"fsgsbase", "tsc_adjust", NULL, "bmi1", "hle", "avx2", NULL, "smep",
 	"bmi2", "erms", "invpcid", "rtm", "cqm", NULL, "mpx", "rdt_a",
 	"avx512f", "avx512dq", "rdseed", "adx",
 	"smap", "avx512ifma", NULL, "clflushopt",
 	"clwb", "intel_pt", "avx512pf", "avx512er",
 	"avx512cd", "sha_ni", "avx512bw", "avx512vl"},
 	{ /* (10) 0x0000000d:1 eax */
 	"xsaveopt", "xsavec", "xgetbv1", "xsaves", NULL, NULL, NULL, NULL,
 	NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL,
 	NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL,
 	NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL},
 	{ /* (11) 0x0000000f:0 edx */
 	NULL, "cqm_llc", NULL, NULL, NULL, NULL, NULL, NULL,
 	NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL,
 	NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL,
 	NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL},
 	{ /* (12) 0x0000000f:1 edx */
 	"cqm_occup_llc", "cqm_mbm_total", "cqm_mbm_local", NULL,
 	NULL, NULL, NULL, NULL,
 	NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL,
 	NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL,
 	NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL},
 	{ /* (13) AMD 0x80000008 ebx */
 	"clzero", "irperf", "xsaveerptr", NULL, "rdpru", NULL, NULL, NULL,
 	NULL, "wbnoinvd", NULL, NULL, NULL, NULL, NULL, NULL,
 	NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL,
 	NULL, "virt_ssbd", NULL, NULL, NULL, NULL, NULL, NULL},
 	{ /* (14) 0x00000006 eax */
 	"dtherm", "ida", "arat", NULL, "pln", NULL, "pts", "hwp",
 	"hwp_notify", "hwp_act_window", "hwp_epp","hwp_pkg_req",
 	NULL, NULL, NULL, NULL,
 	NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL,
 	NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL},
 	{ /* (15) 0x8000000a edx */
 	"npt", "lbrv", "svm_lock", "nrip_save",
 	"tsc_scale", "vmcb_clean", "flushbyasid", "decodeassists",
 	NULL, NULL, "pausefilter", NULL, "pfthreshold", "avic", NULL,
 	"v_vmsave_vmload",
 	"vgif", NULL, NULL, NULL, NULL, NULL, NULL, NULL,
 	NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL},
 	{ /* (16) 0x00000007:0 ecx */
 	NULL, "avx512vbmi", "umip", "pku",
 	"ospke", "waitpkg", "avx512_vbmi2", NULL,
 	"gfni", "vaes", "vpclmulqdq", "avx512_vnni",
 	"avx512_bitalg", "tme", "avx512_vpopcntdq", NULL,
 	"la57", NULL, NULL, NULL, NULL, NULL, "rdpid", NULL,
 	NULL, "cldemote", NULL, "movdiri", "movdir64b", NULL, NULL, NULL},
 	{ /* (17) 0x80000007 ebx */
 	"overflow_recov", "succor", NULL, "smca", NULL, NULL, NULL, NULL,
 	NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL,
 	NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL,
 	NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL},
 	{ /* (18) Intel 0x00000007 edx */
-	NULL, NULL, "avx512_4vnniw", "avx512_4fmaps", NULL, NULL, NULL, NULL,
+	NULL, NULL, "avx512_4vnniw", "avx512_4fmaps", "fsrm", NULL, NULL, NULL,
-	NULL, NULL, "md_clear", NULL, NULL, NULL, NULL, NULL,
+	"vp2intersect", NULL, "md_clear", NULL, NULL, NULL, NULL, NULL,
 	NULL, NULL, "pconfig", NULL, NULL, NULL, NULL, NULL,
 	NULL, NULL, NULL, NULL,
 	"flush_l1d", "arch_capabilities", NULL, "ssbd"},
 };
 static int	procfs_getonecpu(int, struct cpu_info *, char *, size_t *);
 /*
  * Linux-style /proc/cpuinfo.
  * Only used when procfs is mounted with -o linux.
+ *
  * In the multiprocessor case, this should be a loop over all CPUs.
  */
 int
 procfs_getcpuinfstr(char *bf, size_t *len)
+{
 	struct cpu_info *ci;
 	CPU_INFO_ITERATOR cii;
 	size_t i, total, size, used;
 	i = total = 0;
 	used = size = *len;
 	for (CPU_INFO_FOREACH(cii, ci)) {
 		procfs_getonecpu(i++, ci, bf, &used);
 		total += used + 1;
 		if (used + 1 <= size) {
 			bf += used;
 			*bf++ = '\n';
 			size -= used + 1;
 			used = size;
 		} else
 			used = 0;
+	}
 	size = *len;
 	*len = total;
 	return size < *len ? -1 : 0;
+}
 static int
 procfs_getonefeatreg(uint32_t reg, const char * const *table, char *p,
     size_t *left)
+{
 	size_t l;
 	for (size_t i = 0; i < 32; i++) {
 		if ((reg & (1U << i)) && table[i]) {
 			l = snprintf(p, *left, "%s ", table[i]);
 			if (l < *left) {
 				*left -= l;
 				p += l;
 			} else
 				break;
+		}
+	}
 	return 0; /* XXX */
+}
 /*
  * Print feature bits. The code assume that unused entry of x86_features[]
  * is zero-cleared.
+ *
  * XXX This function will be rewritten when all of linux entries are
  * decoded.
  */
 static int
 procfs_getonecpufeatures(struct cpu_info *ci, char *p, size_t *left)
+{
 	size_t last = *left;
 	size_t diff;
 	u_int descs[4];
 	procfs_getonefeatreg(ci->ci_feat_val[0], x86_features[0], p, left);
 	diff = last - *left;
 	procfs_getonefeatreg(ci->ci_feat_val[2], x86_features[1], p + diff,
 	    left);
 	diff = last - *left;
 	/* x86_features[2] is for Transmeta */
 	/* x86_features[3] is Linux defined mapping */
 	procfs_getonefeatreg(ci->ci_feat_val[1], x86_features[4], p + diff,
 	    left);
 	diff = last - *left;
 	procfs_getonefeatreg(ci->ci_feat_val[4], x86_features[5], p + diff,
 	    left);
 	diff = last - *left;
 	procfs_getonefeatreg(ci->ci_feat_val[3], x86_features[6], p + diff,
 	    left);
 	diff = last - *left;
 	/* x86_features[7] is Linux defined mapping */
 	/* x86_features[8] is Linux defined mapping */
 	procfs_getonefeatreg(ci->ci_feat_val[5], x86_features[9], p + diff,
 	    left);
 	diff = last - *left;
 	if (ci->ci_max_cpuid >= 0x0d) {
 		x86_cpuid2(0x0d, 1, descs);
 		procfs_getonefeatreg(descs[0], x86_features[10], p + diff,
 		    left);
 		diff = last - *left;
+	}
 	if (ci->ci_max_cpuid >= 0x0f) {
 		x86_cpuid2(0x0f, 0, descs);
 		procfs_getonefeatreg(descs[3], x86_features[11], p + diff,
 		    left);
 		diff = last - *left;
 		x86_cpuid2(0x0f, 1, descs);
 		procfs_getonefeatreg(descs[3], x86_features[12], p + diff,
 		    left);
 		diff = last - *left;
+	}
 	if ((cpu_vendor == CPUVENDOR_AMD)
 	    && (ci->ci_max_ext_cpuid >= 0x80000008)) {
 		x86_cpuid(0x80000008, descs);
 		procfs_getonefeatreg(descs[1], x86_features[13], p + diff,
 		    left);
 		diff = last - *left;
+	}
 	if (ci->ci_max_cpuid >= 0x06) {
 		x86_cpuid(0x06, descs);
 		procfs_getonefeatreg(descs[0], x86_features[14], p + diff,
 		    left);
 		diff = last - *left;
+	}
 	if ((cpu_vendor == CPUVENDOR_AMD)
 	    && (ci->ci_max_ext_cpuid >= 0x8000000a)) {
 		x86_cpuid(0x8000000a, descs);
 		procfs_getonefeatreg(descs[3], x86_features[15], p + diff,
 		    left);
 		diff = last - *left;
+	}
 	procfs_getonefeatreg(ci->ci_feat_val[6], x86_features[16], p + diff,
 	    left);
 	diff = last - *left;
 	if ((cpu_vendor == CPUVENDOR_AMD)
 	    && (ci->ci_max_ext_cpuid >= 0x80000007)) {
 		x86_cpuid(0x80000007, descs);
 		procfs_getonefeatreg(descs[1], x86_features[17], p + diff,
 		    left);
 		diff = last - *left;
+	}
 	if ((cpu_vendor == CPUVENDOR_INTEL)
 	    && (ci->ci_max_cpuid >= 0x00000007)) {
 		x86_cpuid(0x00000007, descs);
 		procfs_getonefeatreg(descs[3], x86_features[18], p + diff,
 		    left);
 		diff = last - *left;
+	}
 	return 0; /* XXX */
+}
 static int
 procfs_getonecpu(int xcpu, struct cpu_info *ci, char *bf, size_t *len)
+{
 	size_t left, l, size;
 	char featurebuf[1024], *p;
 	p = featurebuf;
 	left = sizeof(featurebuf);
 	size = *len;
 	procfs_getonecpufeatures(ci, p, &left);
 	p = bf;
 	left = *len;
 	size = 0;
 	l = snprintf(p, left,
 	    "processor\t: %d\n"
 	    "vendor_id\t: %s\n"
 	    "cpu family\t: %d\n"
 	    "model\t\t: %d\n"
 	    "model name\t: %s\n"
 	    "stepping\t: ",
 	    xcpu,
 	    (char *)ci->ci_vendor,
 	    CPUID_TO_FAMILY(ci->ci_signature),
 	    CPUID_TO_MODEL(ci->ci_signature),
 	    cpu_brand_string
 	);
 	size += l;
 	if (l < left) {
 		left -= l;
 		p += l;
 	} else
 		left = 0;
 	if (cpuid_level >= 0)
 		l = snprintf(p, left, "%d\n",
 		    CPUID_TO_STEPPING(ci->ci_signature));
 	else
 		l = snprintf(p, left, "unknown\n");
 	size += l;
 	if (l < left) {
 		left -= l;
 		p += l;
 	} else
 		left = 0;
 	if (ci->ci_data.cpu_cc_freq != 0) {
 		uint64_t freq, fraq;
 		freq = (ci->ci_data.cpu_cc_freq + 4999) / 1000000;
 		fraq = ((ci->ci_data.cpu_cc_freq + 4999) / 10000) % 100;
 		l = snprintf(p, left, "cpu MHz\t\t: %" PRIu64 ".%02" PRIu64
 		    "\n", freq, fraq);
 	} else
 		l = snprintf(p, left, "cpu MHz\t\t: unknown\n");
 	size += l;
 	if (l < left) {
 		left -= l;
 		p += l;
 	} else
 		left = 0;
 	l = snprintf(p, left,
 	    "apicid\t\t: %lu\n"
 	    "initial apicid\t: %u\n",
 	    ci->ci_cpuid,
 	    ci->ci_initapicid
 	);
 	size += l;
 	if (l < left) {
 		left -= l;
 		p += l;
 	} else
 		left = 0;
 	l = snprintf(p, left,
 #ifdef __i386__
 	    "fdiv_bug\t: %s\n"
 #endif
 	    "fpu\t\t: yes\n"
 	    "fpu_exception\t: yes\n"
 	    "cpuid level\t: %d\n"
 	    "wp\t\t: %s\n"
 	    "flags\t\t: %s\n"
 	    "clflush size\t: %d\n",
 #ifdef __i386__
 	    i386_fpu_fdivbug ? "yes" : "no",	/* an old pentium */
 #endif
 	    ci->ci_max_cpuid,
 	    (rcr0() & CR0_WP) ? "yes" : "no",
 	    featurebuf,
 	    ci->ci_cflush_lsize
 	);
 	size += l;
 	left = *len;
 	*len = size;
 	return left < *len ? -1 : 0;
+}
 #if defined(__HAVE_PROCFS_MACHDEP) && !defined(__x86_64__)
 void
 procfs_machdep_allocvp(struct vnode *vp)
+{
 	struct pfsnode *pfs = vp->v_data;
 	switch (pfs->pfs_type) {
 	case Pmachdep_xmmregs:
 		/* /proc/N/xmmregs = -rw------- */
 		pfs->pfs_mode = S_IRUSR|S_IWUSR;
 		vp->v_type = VREG;
 		break;
 	default:
 		KASSERT(false);
+	}
+}
 int
 procfs_machdep_rw(struct lwp *curl, struct lwp *l, struct pfsnode *pfs,
     struct uio *uio)
+{
 	switch (pfs->pfs_type) {
 	case Pmachdep_xmmregs:
 		return (procfs_machdep_doxmmregs(curl, l, pfs, uio));
 	default:
 		KASSERT(false);
+	}
 	return EINVAL;
+}
 int
 procfs_machdep_getattr(struct vnode *vp, struct vattr *vap, struct proc *procp)
+{
 	struct pfsnode *pfs = VTOPFS(vp);
 	switch (pfs->pfs_type) {
 	case Pmachdep_xmmregs:
 		vap->va_bytes = vap->va_size = sizeof(struct xmmregs);
 		break;
 	default:
 		KASSERT(false);
+	}
 	return 0;
+}
 int
 procfs_machdep_doxmmregs(struct lwp *curl, struct lwp *l,
     struct pfsnode *pfs, struct uio *uio)
+{
 	return process_machdep_doxmmregs(curl, l, uio);
+}
 int
 procfs_machdep_validxmmregs(struct lwp *l, struct mount *mp)
+{
 	return process_machdep_validxmmregs(l->l_proc);
+}
 #endif

 @@ -1,2628 +1,2622 @@
-/*	$NetBSD: i386.c,v 1.104.2.4 2019/11/19 13:15:57 martin Exp $	*/
+/*	$NetBSD: i386.c,v 1.104.2.5 2020/04/14 17:15:02 martin Exp $	*/
 /*-
  * Copyright (c) 1999, 2000, 2001, 2006, 2007, 2008 The NetBSD Foundation, Inc.
  * All rights reserved.
+ *
  * This code is derived from software contributed to The NetBSD Foundation
  * by Frank van der Linden,  and by Jason R. Thorpe.
+ *
  * Redistribution and use in source and binary forms, with or without
  * modification, are permitted provided that the following conditions
  * are met:
  * 1. Redistributions of source code must retain the above copyright
  *    notice, this list of conditions and the following disclaimer.
  * 2. Redistributions in binary form must reproduce the above copyright
  *    notice, this list of conditions and the following disclaimer in the
  *    documentation and/or other materials provided with the distribution.
+ *
  * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
  * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
  * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
  * PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
  * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
  * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
  * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
  * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
  * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
  * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
  * POSSIBILITY OF SUCH DAMAGE.
  */
 /*-
  * Copyright (c)2008 YAMAMOTO Takashi,
  * All rights reserved.
+ *
  * Redistribution and use in source and binary forms, with or without
  * modification, are permitted provided that the following conditions
  * are met:
  * 1. Redistributions of source code must retain the above copyright
  *    notice, this list of conditions and the following disclaimer.
  * 2. Redistributions in binary form must reproduce the above copyright
  *    notice, this list of conditions and the following disclaimer in the
  *    documentation and/or other materials provided with the distribution.
+ *
  * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
  * ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
  * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
  * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
  * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
  * SUCH DAMAGE.
  */
 #include <sys/cdefs.h>
 #ifndef lint
-__RCSID("$NetBSD: i386.c,v 1.104.2.4 2019/11/19 13:15:57 martin Exp $");
+__RCSID("$NetBSD: i386.c,v 1.104.2.5 2020/04/14 17:15:02 martin Exp $");
 #endif /* not lint */
 #include <sys/types.h>
 #include <sys/param.h>
 #include <sys/bitops.h>
 #include <sys/sysctl.h>
 #include <sys/ioctl.h>
 #include <sys/cpuio.h>
 #include <errno.h>
 #include <string.h>
 #include <stdio.h>
 #include <stdlib.h>
 #include <err.h>
 #include <assert.h>
 #include <math.h>
 #include <util.h>
 #include <machine/specialreg.h>
 #include <machine/cpu.h>
 #include <x86/cpuvar.h>
 #include <x86/cputypes.h>
 #include <x86/cacheinfo.h>
 #include <x86/cpu_ucode.h>
 #include "../cpuctl.h"
 #include "cpuctl_i386.h"
 /* Size of buffer for printing humanized numbers */
 #define HUMAN_BUFSIZE sizeof("999KB")
 struct cpu_info {
 	const char	*ci_dev;
 	int32_t		ci_cpu_type;	 /* for cpu's without cpuid */
 	int32_t		ci_cpuid_level;	 /* highest cpuid supported */
 	uint32_t	ci_cpuid_extlevel; /* highest cpuid extended func lv */
 	uint32_t	ci_signature;	 /* X86 cpuid type */
 	uint32_t	ci_family;	 /* from ci_signature */
 	uint32_t	ci_model;	 /* from ci_signature */
 	uint32_t	ci_feat_val[10]; /* X86 CPUID feature bits
 					  *	[0] basic features %edx
 					  *	[1] basic features %ecx
 					  *	[2] extended features %edx
 					  *	[3] extended features %ecx
 					  *	[4] VIA padlock features
 					  *	[5] structure ext. feat. %ebx
 					  *	[6] structure ext. feat. %ecx
 					  *     [7] structure ext. feat. %edx
 					  *	[8] XCR0 bits (d:0 %eax)
 					  *	[9] xsave flags (d:1 %eax)
 					  */
 	uint32_t	ci_cpu_class;	 /* CPU class */
 	uint32_t	ci_brand_id;	 /* Intel brand id */
 	uint32_t	ci_vendor[4];	 /* vendor string */
 	uint32_t	ci_cpu_serial[3]; /* PIII serial number */
 	uint64_t	ci_tsc_freq;	 /* cpu cycles/second */
 	uint8_t		ci_packageid;
 	uint8_t		ci_coreid;
 	uint8_t		ci_smtid;
 	uint32_t	ci_initapicid;
 	uint32_t	ci_max_ext_cpuid;
 	uint32_t	ci_cur_xsave;
 	uint32_t	ci_max_xsave;
 	struct x86_cache_info ci_cinfo[CAI_COUNT];
 	void		(*ci_info)(struct cpu_info *);
 };
 struct cpu_nocpuid_nameclass {
 	int cpu_vendor;
 	const char *cpu_vendorname;
 	const char *cpu_name;
 	int cpu_class;
 	void (*cpu_setup)(struct cpu_info *);
 	void (*cpu_cacheinfo)(struct cpu_info *);
 	void (*cpu_info)(struct cpu_info *);
 };
 struct cpu_cpuid_nameclass {
 	const char *cpu_id;
 	int cpu_vendor;
 	const char *cpu_vendorname;
 	struct cpu_cpuid_family {
 		int cpu_class;
 		const char *cpu_models[256];
 		const char *cpu_model_default;
 		void (*cpu_setup)(struct cpu_info *);
 		void (*cpu_probe)(struct cpu_info *);
 		void (*cpu_info)(struct cpu_info *);
 	} cpu_family[CPU_MAXFAMILY - CPU_MINFAMILY + 1];
 };
 static const struct x86_cache_info intel_cpuid_cache_info[] = INTEL_CACHE_INFO;
 /*
  * Map Brand ID from cpuid instruction to brand name.
  * Source: Table 3-24, Mapping of Brand Indices; and Intel 64 and IA-32
  * Processor Brand Strings, Chapter 3 in "Intel (R) 64 and IA-32
  * Architectures Software Developer's Manual, Volume 2A".
  */
 static const char * const i386_intel_brand[] = {
 	"",		    /* Unsupported */
 	"Celeron",	    /* Intel (R) Celeron (TM) processor */
 	"Pentium III",	    /* Intel (R) Pentium (R) III processor */
 	"Pentium III Xeon", /* Intel (R) Pentium (R) III Xeon (TM) processor */
 	"Pentium III",	    /* Intel (R) Pentium (R) III processor */
 	"",		    /* 0x05: Reserved */
 	"Mobile Pentium III",/* Mobile Intel (R) Pentium (R) III processor-M */
 	"Mobile Celeron",   /* Mobile Intel (R) Celeron (R) processor */
 	"Pentium 4",	    /* Intel (R) Pentium (R) 4 processor */
 	"Pentium 4",	    /* Intel (R) Pentium (R) 4 processor */
 	"Celeron",	    /* Intel (R) Celeron (TM) processor */
 	"Xeon",		    /* Intel (R) Xeon (TM) processor */
 	"Xeon MP",	    /* Intel (R) Xeon (TM) processor MP */
 	"",		    /* 0x0d: Reserved */
 	"Mobile Pentium 4", /* Mobile Intel (R) Pentium (R) 4 processor-M */
 	"Mobile Celeron",   /* Mobile Intel (R) Celeron (R) processor */
 	"",		    /* 0x10: Reserved */
 	"Mobile Genuine",   /* Moblie Genuine Intel (R) processor */
 	"Celeron M",	    /* Intel (R) Celeron (R) M processor */
 	"Mobile Celeron",   /* Mobile Intel (R) Celeron (R) processor */
 	"Celeron",	    /* Intel (R) Celeron (R) processor */
 	"Mobile Genuine",   /* Moblie Genuine Intel (R) processor */
 	"Pentium M",	    /* Intel (R) Pentium (R) M processor */
 	"Mobile Celeron",   /* Mobile Intel (R) Celeron (R) processor */
 };
 /*
  * AMD processors don't have Brand IDs, so we need these names for probe.
  */
 static const char * const amd_brand[] = {
 	"",
 	"Duron",	/* AMD Duron(tm) */
 	"MP",		/* AMD Athlon(tm) MP */
 	"XP",		/* AMD Athlon(tm) XP */
 	"4"		/* AMD Athlon(tm) 4 */
 };
 static int cpu_vendor;
 static char cpu_brand_string[49];
 static char amd_brand_name[48];
 static int use_pae, largepagesize;
 /* Setup functions */
 static void	disable_tsc(struct cpu_info *);
 static void	amd_family5_setup(struct cpu_info *);
 static void	cyrix6x86_cpu_setup(struct cpu_info *);
 static void	winchip_cpu_setup(struct cpu_info *);
 /* Brand/Model name functions */
 static const char *intel_family6_name(struct cpu_info *);
 static const char *amd_amd64_name(struct cpu_info *);
 /* Probe functions */
 static void	amd_family6_probe(struct cpu_info *);
 static void	powernow_probe(struct cpu_info *);
 static void	intel_family_new_probe(struct cpu_info *);
 static void	via_cpu_probe(struct cpu_info *);
 /* (Cache) Info functions */
 static void	cpu_dcp_cacheinfo(struct cpu_info *, uint32_t);
 static void	intel_cpu_cacheinfo(struct cpu_info *);
 static void	amd_cpu_cacheinfo(struct cpu_info *);
 static void	via_cpu_cacheinfo(struct cpu_info *);
 static void	tmx86_get_longrun_status(u_int *, u_int *, u_int *);
 static void	transmeta_cpu_info(struct cpu_info *);
 /* Common functions */
 static void	cpu_probe_base_features(struct cpu_info *, const char *);
 static void	cpu_probe_hv_features(struct cpu_info *, const char *);
 static void	cpu_probe_features(struct cpu_info *);
 static void	print_bits(const char *, const char *, const char *, uint32_t);
 static void	identifycpu_cpuids(struct cpu_info *);
 static const struct x86_cache_info *cache_info_lookup(
     const struct x86_cache_info *, uint8_t);
 static const char *print_cache_config(struct cpu_info *, int, const char *,
     const char *);
 static const char *print_tlb_config(struct cpu_info *, int, const char *,
     const char *);
 static void	x86_print_cache_and_tlb_info(struct cpu_info *);
 /*
  * Note: these are just the ones that may not have a cpuid instruction.
  * We deal with the rest in a different way.
  */
 const struct cpu_nocpuid_nameclass i386_nocpuid_cpus[] = {
 	{ CPUVENDOR_INTEL, "Intel", "386SX",	CPUCLASS_386,
 	  NULL, NULL, NULL },			/* CPU_386SX */
 	{ CPUVENDOR_INTEL, "Intel", "386DX",	CPUCLASS_386,
 	  NULL, NULL, NULL },			/* CPU_386   */
 	{ CPUVENDOR_INTEL, "Intel", "486SX",	CPUCLASS_486,
 	  NULL, NULL, NULL },			/* CPU_486SX */
 	{ CPUVENDOR_INTEL, "Intel", "486DX",	CPUCLASS_486,
 	  NULL, NULL, NULL },			/* CPU_486   */
 	{ CPUVENDOR_CYRIX, "Cyrix", "486DLC",	CPUCLASS_486,
 	  NULL, NULL, NULL },			/* CPU_486DLC */
 	{ CPUVENDOR_CYRIX, "Cyrix", "6x86",	CPUCLASS_486,
 	  NULL, NULL, NULL },		/* CPU_6x86 */
 	{ CPUVENDOR_NEXGEN,"NexGen","586",	CPUCLASS_386,
 	  NULL, NULL, NULL },			/* CPU_NX586 */
 };
 const char *classnames[] = {
 	"386",
 	"486",
 	"586",
 	"686"
 };
 const char *modifiers[] = {
 	"",
 	"OverDrive",
 	"Dual",
 	""
 };
 const struct cpu_cpuid_nameclass i386_cpuid_cpus[] = {
+	{
 		/*
 		 * For Intel processors, check Chapter 35Model-specific
 		 * registers (MSRS), in "Intel (R) 64 and IA-32 Architectures
 		 * Software Developer's Manual, Volume 3C".
 		 */
 		"GenuineIntel",
 		CPUVENDOR_INTEL,
 		"Intel",
 		/* Family 4 */
 		{ {
 			CPUCLASS_486,
+			{
 				"486DX", "486DX", "486SX", "486DX2", "486SL",
 				"486SX2", 0, "486DX2 W/B Enhanced",
 				"486DX4", 0, 0, 0, 0, 0, 0, 0,
 			},
 			"486",		/* Default */
 			NULL,
 			NULL,
 			intel_cpu_cacheinfo,
 		},
 		/* Family 5 */
+		{
 			CPUCLASS_586,
+			{
 				"Pentium (P5 A-step)", "Pentium (P5)",
 				"Pentium (P54C)", "Pentium (P24T)",
 				"Pentium/MMX", "Pentium", 0,
 				"Pentium (P54C)", "Pentium/MMX (Tillamook)",
 				"Quark X1000", 0, 0, 0, 0, 0, 0,
 			},
 			"Pentium",	/* Default */
 			NULL,
 			NULL,
 			intel_cpu_cacheinfo,
 		},
 		/* Family 6 */
+		{
 			CPUCLASS_686,
+			{
 				[0x00] = "Pentium Pro (A-step)",
 				[0x01] = "Pentium Pro",
 				[0x03] = "Pentium II (Klamath)",
 				[0x04] = "Pentium Pro",
 				[0x05] = "Pentium II/Celeron (Deschutes)",
 				[0x06] = "Celeron (Mendocino)",
 				[0x07] = "Pentium III (Katmai)",
 				[0x08] = "Pentium III (Coppermine)",
 				[0x09] = "Pentium M (Banias)",
 				[0x0a] = "Pentium III Xeon (Cascades)",
 				[0x0b] = "Pentium III (Tualatin)",
 				[0x0d] = "Pentium M (Dothan)",
 				[0x0e] = "Pentium Core Duo, Core solo",
 				[0x0f] = "Xeon 30xx, 32xx, 51xx, 53xx, 73xx, "
 					 "Core 2 Quad 6xxx, "
 					 "Core 2 Extreme 6xxx, "
 					 "Core 2 Duo 4xxx, 5xxx, 6xxx, 7xxx "
 					 "and Pentium DC",
 				[0x15] = "EP80579 Integrated Processor",
 				[0x16] = "Celeron (45nm)",
 				[0x17] = "Xeon 31xx, 33xx, 52xx, 54xx, "
 					 "Core 2 Quad 8xxx and 9xxx",
 				[0x1a] = "Core i7, Xeon 34xx, 35xx and 55xx "
 					 "(Nehalem)",
 				[0x1c] = "45nm Atom Family",
 				[0x1d] = "XeonMP 74xx (Nehalem)",
 				[0x1e] = "Core i7 and i5",
 				[0x1f] = "Core i7 and i5",
 				[0x25] = "Xeon 36xx & 56xx, i7, i5 and i3",
 				[0x26] = "Atom Family",
 				[0x27] = "Atom Family",
 				[0x2a] = "Xeon E3-12xx, 2nd gen i7, i5, "
 					 "i3 2xxx",
 				[0x2c] = "Xeon 36xx & 56xx, i7, i5 and i3",
 				[0x2d] = "Xeon E5 Sandy Bridge family, "
 					 "Core i7-39xx Extreme",
 				[0x2e] = "Xeon 75xx & 65xx",
 				[0x2f] = "Xeon E7 family",
 				[0x35] = "Atom Family",
 				[0x36] = "Atom S1000",
 				[0x37] = "Atom E3000, Z3[67]00",
 				[0x3a] = "Xeon E3-1200v2 and 3rd gen core, "
 					 "Ivy Bridge",
 				[0x3c] = "4th gen Core, Xeon E3-12xx v3 "
 					 "(Haswell)",
 				[0x3d] = "Core M-5xxx, 5th gen Core (Broadwell)",
 				[0x3e] = "Xeon E5/E7 v2 (Ivy Bridge-E), "
 					 "Core i7-49xx Extreme",
 				[0x3f] = "Xeon E5-4600/2600/1600 v3, Xeon E7 v3 (Haswell-E), "
 					 "Core i7-59xx Extreme",
 				[0x45] = "4th gen Core, Xeon E3-12xx v3 "
 					 "(Haswell)",
 				[0x46] = "4th gen Core, Xeon E3-12xx v3 "
 					 "(Haswell)",
 				[0x47] = "5th gen Core, Xeon E3-1200 v4 (Broadwell)",
 				[0x4a] = "Atom Z3400",
 				[0x4c] = "Atom X[57]-Z8000 (Airmont)",
 				[0x4d] = "Atom C2000",
 				[0x4e] = "6th gen Core, Xeon E3-1[25]00 v5 (Skylake)",
 				[0x4f] = "Xeon E[57] v4 (Broadwell), Core i7-69xx Extreme",
 				[0x55] = "Xeon Scalable (Skylake, Cascade Lake, Copper Lake)",
 				[0x56] = "Xeon D-1500 (Broadwell)",
 				[0x57] = "Xeon Phi [357]200 (Knights Landing)",
 				[0x5a] = "Atom E3500",
 				[0x5c] = "Atom (Goldmont)",
 				[0x5d] = "Atom X3-C3000 (Silvermont)",
 				[0x5e] = "6th gen Core, Xeon E3-1[25]00 v5 (Skylake)",
 				[0x5f] = "Atom (Goldmont, Denverton)",
 				[0x66] = "8th gen Core i3 (Cannon Lake)",
 				[0x6a] = "Future Xeon (Ice Lake)",
 				[0x6c] = "Future Xeon (Ice Lake)",
 				[0x7a] = "Atom (Goldmont Plus)",
 				[0x7d] = "10th gen Core (Ice Lake)",
 				[0x7e] = "10th gen Core (Ice Lake)",
 				[0x85] = "Xeon Phi 7215, 7285, 7295 (Knights Mill)",
 				[0x86] = "Atom (Tremont)",
 				[0x8e] = "7th or 8th gen Core (Kaby Lake, Coffee Lake) or Xeon E (Coffee Lake)",
 				[0x9e] = "7th or 8th gen Core (Kaby Lake, Coffee Lake) or Xeon E (Coffee Lake)",
 			},
 			"Pentium Pro, II or III",	/* Default */
 			NULL,
 			intel_family_new_probe,
 			intel_cpu_cacheinfo,
 		},
 		/* Family > 6 */
+		{
 			CPUCLASS_686,
+			{
 , 0, 0, 0, 0, 0, 0, 0,
 , 0, 0, 0, 0, 0, 0, 0,
 			},
 			"Pentium 4",	/* Default */
 			NULL,
 			intel_family_new_probe,
 			intel_cpu_cacheinfo,
 		} }
 	},
+	{
 		"AuthenticAMD",
 		CPUVENDOR_AMD,
 		"AMD",
 		/* Family 4 */
 		{ {
 			CPUCLASS_486,
+			{
 , 0, 0, "Am486DX2 W/T",
 , 0, 0, "Am486DX2 W/B",
 				"Am486DX4 W/T or Am5x86 W/T 150",
 				"Am486DX4 W/B or Am5x86 W/B 150", 0, 0,
 , 0, "Am5x86 W/T 133/160",
 				"Am5x86 W/B 133/160",
 			},
 			"Am486 or Am5x86",	/* Default */
 			NULL,
 			NULL,
 			NULL,
 		},
 		/* Family 5 */
+		{
 			CPUCLASS_586,
+			{
 				"K5", "K5", "K5", "K5", 0, 0, "K6",
 				"K6", "K6-2", "K6-III", "Geode LX", 0, 0,
 				"K6-2+/III+", 0, 0,
 			},
 			"K5 or K6",		/* Default */
 			amd_family5_setup,
 			NULL,
 			amd_cpu_cacheinfo,
 		},
 		/* Family 6 */
+		{
 			CPUCLASS_686,
+			{
 , "Athlon Model 1", "Athlon Model 2",
 				"Duron", "Athlon Model 4 (Thunderbird)",
 , "Athlon", "Duron", "Athlon", 0,
 				"Athlon", 0, 0, 0, 0, 0,
 			},
 			"K7 (Athlon)",	/* Default */
 			NULL,
 			amd_family6_probe,
 			amd_cpu_cacheinfo,
 		},
 		/* Family > 6 */
+		{
 			CPUCLASS_686,
+			{
 , 0, 0, 0, 0, 0, 0, 0,
 , 0, 0, 0, 0, 0, 0, 0,
 			},
 			"Unknown K8 (Athlon)",	/* Default */
 			NULL,
 			amd_family6_probe,
 			amd_cpu_cacheinfo,
 		} }
 	},
+	{
 		"CyrixInstead",
 		CPUVENDOR_CYRIX,
 		"Cyrix",
 		/* Family 4 */
 		{ {
 			CPUCLASS_486,
+			{
 , 0, 0,
 				"MediaGX",
 , 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
 			},
 			"486",		/* Default */
 			cyrix6x86_cpu_setup, /* XXX ?? */
 			NULL,
 			NULL,
 		},
 		/* Family 5 */
+		{
 			CPUCLASS_586,
+			{
 , 0, "6x86", 0,
 				"MMX-enhanced MediaGX (GXm)", /* or Geode? */
 , 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
 			},
 			"6x86",		/* Default */
 			cyrix6x86_cpu_setup,
 			NULL,
 			NULL,
 		},
 		/* Family 6 */
+		{
 			CPUCLASS_686,
+			{
 				"6x86MX", 0, 0, 0, 0, 0, 0, 0,
 , 0, 0, 0, 0, 0, 0, 0,
 			},
 			"6x86MX",		/* Default */
 			cyrix6x86_cpu_setup,
 			NULL,
 			NULL,
 		},
 		/* Family > 6 */
+		{
 			CPUCLASS_686,
+			{
 , 0, 0, 0, 0, 0, 0, 0,
 , 0, 0, 0, 0, 0, 0, 0,
 			},
 			"Unknown 6x86MX",		/* Default */
 			NULL,
 			NULL,
 			NULL,
 		} }
 	},
 	{	/* MediaGX is now owned by National Semiconductor */
 		"Geode by NSC",
 		CPUVENDOR_CYRIX, /* XXX */
 		"National Semiconductor",
 		/* Family 4, NSC never had any of these */
 		{ {
 			CPUCLASS_486,
+			{
 , 0, 0, 0, 0, 0, 0, 0,
 , 0, 0, 0, 0, 0, 0, 0,
 			},
 			"486 compatible",	/* Default */
 			NULL,
 			NULL,
 			NULL,
 		},
 		/* Family 5: Geode family, formerly MediaGX */
+		{
 			CPUCLASS_586,
+			{
 , 0, 0, 0,
 				"Geode GX1",
 , 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
 			},
 			"Geode",		/* Default */
 			cyrix6x86_cpu_setup,
 			NULL,
 			amd_cpu_cacheinfo,
 		},
 		/* Family 6, not yet available from NSC */
+		{
 			CPUCLASS_686,
+			{
 , 0, 0, 0, 0, 0, 0, 0,
 , 0, 0, 0, 0, 0, 0, 0,
 			},
 			"Pentium Pro compatible", /* Default */
 			NULL,
 			NULL,
 			NULL,
 		},
 		/* Family > 6, not yet available from NSC */
+		{
 			CPUCLASS_686,
+			{
 , 0, 0, 0, 0, 0, 0, 0,
 , 0, 0, 0, 0, 0, 0, 0,
 			},
 			"Pentium Pro compatible",	/* Default */
 			NULL,
 			NULL,
 			NULL,
 		} }
 	},
+	{
 		"CentaurHauls",
 		CPUVENDOR_IDT,
 		"IDT",
 		/* Family 4, IDT never had any of these */
 		{ {
 			CPUCLASS_486,
+			{
 , 0, 0, 0, 0, 0, 0, 0,
 , 0, 0, 0, 0, 0, 0, 0,
 			},
 			"486 compatible",	/* Default */
 			NULL,
 			NULL,
 			NULL,
 		},
 		/* Family 5 */
+		{
 			CPUCLASS_586,
+			{
 , 0, 0, 0, "WinChip C6", 0, 0, 0,
 				"WinChip 2", "WinChip 3", 0, 0, 0, 0, 0, 0,
 			},
 			"WinChip",		/* Default */
 			winchip_cpu_setup,
 			NULL,
 			NULL,
 		},
 		/* Family 6, VIA acquired IDT Centaur design subsidiary */
+		{
 			CPUCLASS_686,
+			{
 , 0, 0, 0, 0, 0, "C3 Samuel",
 				"C3 Samuel 2/Ezra", "C3 Ezra-T",
 				"C3 Nehemiah", "C7 Esther", 0, 0, "C7 Esther",
 , "VIA Nano",
 			},
 			"Unknown VIA/IDT",	/* Default */
 			NULL,
 			via_cpu_probe,
 			via_cpu_cacheinfo,
 		},
 		/* Family > 6, not yet available from VIA */
+		{
 			CPUCLASS_686,
+			{
 , 0, 0, 0, 0, 0, 0, 0,
 , 0, 0, 0, 0, 0, 0, 0,
 			},
 			"Pentium Pro compatible",	/* Default */
 			NULL,
 			NULL,
 			NULL,
 		} }
 	},
+	{
 		"GenuineTMx86",
 		CPUVENDOR_TRANSMETA,
 		"Transmeta",
 		/* Family 4, Transmeta never had any of these */
 		{ {
 			CPUCLASS_486,
+			{
 , 0, 0, 0, 0, 0, 0, 0,
 , 0, 0, 0, 0, 0, 0, 0,
 			},
 			"486 compatible",	/* Default */
 			NULL,
 			NULL,
 			NULL,
 		},
 		/* Family 5 */
+		{
 			CPUCLASS_586,
+			{
 , 0, 0, 0, 0, 0, 0, 0,
 , 0, 0, 0, 0, 0, 0, 0,
 			},
 			"Crusoe",		/* Default */
 			NULL,
 			NULL,
 			transmeta_cpu_info,
 		},
 		/* Family 6, not yet available from Transmeta */
+		{
 			CPUCLASS_686,
+			{
 , 0, 0, 0, 0, 0, 0, 0,
 , 0, 0, 0, 0, 0, 0, 0,
 			},
 			"Pentium Pro compatible",	/* Default */
 			NULL,
 			NULL,
 			NULL,
 		},
 		/* Family > 6, not yet available from Transmeta */
+		{
 			CPUCLASS_686,
+			{
 , 0, 0, 0, 0, 0, 0, 0,
 , 0, 0, 0, 0, 0, 0, 0,
 			},
 			"Pentium Pro compatible",	/* Default */
 			NULL,
 			NULL,
 			NULL,
 		} }
+	}
 };
 /*
  * disable the TSC such that we don't use the TSC in microtime(9)
  * because some CPUs got the implementation wrong.
  */
 static void
 disable_tsc(struct cpu_info *ci)
+{
 	if (ci->ci_feat_val[0] & CPUID_TSC) {
 		ci->ci_feat_val[0] &= ~CPUID_TSC;
 		aprint_error("WARNING: broken TSC disabled\n");
+	}
+}
 static void
 amd_family5_setup(struct cpu_info *ci)
+{
 	switch (ci->ci_model) {
 	case 0:		/* AMD-K5 Model 0 */
 		/*
 		 * According to the AMD Processor Recognition App Note,
 		 * the AMD-K5 Model 0 uses the wrong bit to indicate
 		 * support for global PTEs, instead using bit 9 (APIC)
 		 * rather than bit 13 (i.e. "0x200" vs. 0x2000".  Oops!).
 		 */
 		if (ci->ci_feat_val[0] & CPUID_APIC)
 			ci->ci_feat_val[0] =
 			    (ci->ci_feat_val[0] & ~CPUID_APIC) | CPUID_PGE;
 		/*
 		 * XXX But pmap_pg_g is already initialized -- need to kick
 		 * XXX the pmap somehow.  How does the MP branch do this?
 		 */
 		break;
+	}
+}
 static void
 cyrix6x86_cpu_setup(struct cpu_info *ci)
+{
 	/*
 	 * Do not disable the TSC on the Geode GX, it's reported to
 	 * work fine.
 	 */
 	if (ci->ci_signature != 0x552)
 		disable_tsc(ci);
+}
 static void
 winchip_cpu_setup(struct cpu_info *ci)
+{
 	switch (ci->ci_model) {
 	case 4:	/* WinChip C6 */
 		disable_tsc(ci);
+	}
+}
 static const char *
 intel_family6_name(struct cpu_info *ci)
+{
 	const char *ret = NULL;
 	u_int l2cache = ci->ci_cinfo[CAI_L2CACHE].cai_totalsize;
 	if (ci->ci_model == 5) {
 		switch (l2cache) {
 		case 0:
 		case 128 * 1024:
 			ret = "Celeron (Covington)";
 			break;
 		case 256 * 1024:
 			ret = "Mobile Pentium II (Dixon)";
 			break;
 		case 512 * 1024:
 			ret = "Pentium II";
 			break;
 		case 1 * 1024 * 1024:
 		case 2 * 1024 * 1024:
 			ret = "Pentium II Xeon";
 			break;
+		}
 	} else if (ci->ci_model == 6) {
 		switch (l2cache) {
 		case 256 * 1024:
 		case 512 * 1024:
 			ret = "Mobile Pentium II";
 			break;
+		}
 	} else if (ci->ci_model == 7) {
 		switch (l2cache) {
 		case 512 * 1024:
 			ret = "Pentium III";
 			break;
 		case 1 * 1024 * 1024:
 		case 2 * 1024 * 1024:
 			ret = "Pentium III Xeon";
 			break;
+		}
 	} else if (ci->ci_model >= 8) {
 		if (ci->ci_brand_id && ci->ci_brand_id < 0x10) {
 			switch (ci->ci_brand_id) {
 			case 0x3:
 				if (ci->ci_signature == 0x6B1)
 					ret = "Celeron";
 				break;
 			case 0x8:
 				if (ci->ci_signature >= 0xF13)
 					ret = "genuine processor";
 				break;
 			case 0xB:
 				if (ci->ci_signature >= 0xF13)
 					ret = "Xeon MP";
 				break;
 			case 0xE:
 				if (ci->ci_signature < 0xF13)
 					ret = "Xeon";
 				break;
+			}
 			if (ret == NULL)
 				ret = i386_intel_brand[ci->ci_brand_id];
+		}
+	}
 	return ret;
+}
 /*
  * Identify AMD64 CPU names from cpuid.
+ *
  * Based on:
  * "Revision Guide for AMD Athlon 64 and AMD Opteron Processors"
  * http://www.amd.com/us-en/assets/content_type/white_papers_and_tech_docs/25759.pdf
  * "Revision Guide for AMD NPT Family 0Fh Processors"
  * http://www.amd.com/us-en/assets/content_type/white_papers_and_tech_docs/33610.pdf
  * and other miscellaneous reports.
+ *
  * This is all rather pointless, these are cross 'brand' since the raw
  * silicon is shared.
  */
 static const char *
 amd_amd64_name(struct cpu_info *ci)
+{
 	static char family_str[32];
 	/* Only called if family >= 15 */
 	switch (ci->ci_family) {
 	case 15:
 		switch (ci->ci_model) {
 		case 0x21:	/* rev JH-E1/E6 */
 		case 0x41:	/* rev JH-F2 */
 			return "Dual-Core Opteron";
 		case 0x23:	/* rev JH-E6 (Toledo) */
 			return "Dual-Core Opteron or Athlon 64 X2";
 		case 0x43:	/* rev JH-F2 (Windsor) */
 			return "Athlon 64 FX or Athlon 64 X2";
 		case 0x24:	/* rev SH-E5 (Lancaster?) */
 			return "Mobile Athlon 64 or Turion 64";
 		case 0x05:	/* rev SH-B0/B3/C0/CG (SledgeHammer?) */
 			return "Opteron or Athlon 64 FX";
 		case 0x15:	/* rev SH-D0 */
 		case 0x25:	/* rev SH-E4 */
 			return "Opteron";
 		case 0x27:	/* rev DH-E4, SH-E4 */
 			return "Athlon 64 or Athlon 64 FX or Opteron";
 		case 0x48:	/* rev BH-F2 */
 			return "Turion 64 X2";
 		case 0x04:	/* rev SH-B0/C0/CG (ClawHammer) */
 		case 0x07:	/* rev SH-CG (ClawHammer) */
 		case 0x0b:	/* rev CH-CG */
 		case 0x14:	/* rev SH-D0 */
 		case 0x17:	/* rev SH-D0 */
 		case 0x1b:	/* rev CH-D0 */
 			return "Athlon 64";
 		case 0x2b:	/* rev BH-E4 (Manchester) */
 		case 0x4b:	/* rev BH-F2 (Windsor) */
 			return "Athlon 64 X2";
 		case 0x6b:	/* rev BH-G1 (Brisbane) */
 			return "Athlon X2 or Athlon 64 X2";
 		case 0x08:	/* rev CH-CG */
 		case 0x0c:	/* rev DH-CG (Newcastle) */
 		case 0x0e:	/* rev DH-CG (Newcastle?) */
 		case 0x0f:	/* rev DH-CG (Newcastle/Paris) */
 		case 0x18:	/* rev CH-D0 */
 		case 0x1c:	/* rev DH-D0 (Winchester) */
 		case 0x1f:	/* rev DH-D0 (Winchester/Victoria) */
 		case 0x2c:	/* rev DH-E3/E6 */
 		case 0x2f:	/* rev DH-E3/E6 (Venice/Palermo) */
 		case 0x4f:	/* rev DH-F2 (Orleans/Manila) */
 		case 0x5f:	/* rev DH-F2 (Orleans/Manila) */
 		case 0x6f:	/* rev DH-G1 */
 			return "Athlon 64 or Sempron";
 		default:
 			break;
+		}
 		return "Unknown AMD64 CPU";
 #if 0
 	case 16:
 		return "Family 10h";
 	case 17:
 		return "Family 11h";
 	case 18:
 		return "Family 12h";
 	case 19:
 		return "Family 14h";
 	case 20:
 		return "Family 15h";
 #endif
 	default:
 		break;
+	}
 	snprintf(family_str, sizeof family_str, "Family %xh", ci->ci_family);
 	return family_str;
+}
 static void
 intel_family_new_probe(struct cpu_info *ci)
+{
 	uint32_t descs[4];
 	x86_cpuid(0x80000000, descs);
 	/*
 	 * Determine extended feature flags.
 	 */
 	if (descs[0] >= 0x80000001) {
 		x86_cpuid(0x80000001, descs);
 		ci->ci_feat_val[2] |= descs[3];
 		ci->ci_feat_val[3] |= descs[2];
+	}
+}
 static void
 via_cpu_probe(struct cpu_info *ci)
+{
 	u_int stepping = CPUID_TO_STEPPING(ci->ci_signature);
 	u_int descs[4];
 	u_int lfunc;
 	/*
 	 * Determine the largest extended function value.
 	 */
 	x86_cpuid(0x80000000, descs);
 	lfunc = descs[0];
 	/*
 	 * Determine the extended feature flags.
 	 */
 	if (lfunc >= 0x80000001) {
 		x86_cpuid(0x80000001, descs);
 		ci->ci_feat_val[2] |= descs[3];
+	}
 	if (ci->ci_model < 0x9 || (ci->ci_model == 0x9 && stepping < 3))
 		return;
 	/* Nehemiah or Esther */
 	x86_cpuid(0xc0000000, descs);
 	lfunc = descs[0];
 	if (lfunc < 0xc0000001)	/* no ACE, no RNG */
 		return;
 	x86_cpuid(0xc0000001, descs);
 	lfunc = descs[3];
 	ci->ci_feat_val[4] = lfunc;
+}
 static void
 amd_family6_probe(struct cpu_info *ci)
+{
 	uint32_t descs[4];
 	char *p;
 	size_t i;
 	x86_cpuid(0x80000000, descs);
 	/*
 	 * Determine the extended feature flags.
 	 */
 	if (descs[0] >= 0x80000001) {
 		x86_cpuid(0x80000001, descs);
 		ci->ci_feat_val[2] |= descs[3]; /* %edx */
 		ci->ci_feat_val[3] = descs[2]; /* %ecx */
+	}
 	if (*cpu_brand_string == '\0')
 		return;
 	for (i = 1; i < __arraycount(amd_brand); i++)
 		if ((p = strstr(cpu_brand_string, amd_brand[i])) != NULL) {
 			ci->ci_brand_id = i;
 			strlcpy(amd_brand_name, p, sizeof(amd_brand_name));
 			break;
+		}
+}
 /*
  * Get cache info from one of the following:
  *	Intel Deterministic Cache Parameter Leaf (0x04)
  *	AMD Cache Topology Information Leaf (0x8000001d)
  */
 static void
 cpu_dcp_cacheinfo(struct cpu_info *ci, uint32_t leaf)
+{
 	u_int descs[4];
 	int type, level, ways, partitions, linesize, sets, totalsize;
 	int caitype = -1;
 	int i;
 	for (i = 0; ; i++) {
 		x86_cpuid2(leaf, i, descs);
 		type = __SHIFTOUT(descs[0], CPUID_DCP_CACHETYPE);
 		if (type == CPUID_DCP_CACHETYPE_N)
 			break;
 		level = __SHIFTOUT(descs[0], CPUID_DCP_CACHELEVEL);
 		switch (level) {
 		case 1:
 			if (type == CPUID_DCP_CACHETYPE_I)
 				caitype = CAI_ICACHE;
 			else if (type == CPUID_DCP_CACHETYPE_D)
 				caitype = CAI_DCACHE;
 			else
 				caitype = -1;
 			break;
 		case 2:
 			if (type == CPUID_DCP_CACHETYPE_U)
 				caitype = CAI_L2CACHE;
 			else
 				caitype = -1;
 			break;
 		case 3:
 			if (type == CPUID_DCP_CACHETYPE_U)
 				caitype = CAI_L3CACHE;
 			else
 				caitype = -1;
 			break;
 		default:
 			caitype = -1;
 			break;
+		}
 		if (caitype == -1) {
 			aprint_error_dev(ci->ci_dev,
 			    "error: unknown cache level&type (%d & %d)\n",
 			    level, type);
 			continue;
+		}
 		ways = __SHIFTOUT(descs[1], CPUID_DCP_WAYS) + 1;
 		partitions =__SHIFTOUT(descs[1], CPUID_DCP_PARTITIONS)
 		    + 1;
 		linesize = __SHIFTOUT(descs[1], CPUID_DCP_LINESIZE)
 		    + 1;
 		sets = descs[2] + 1;
 		totalsize = ways * partitions * linesize * sets;
 		ci->ci_cinfo[caitype].cai_totalsize = totalsize;
 		ci->ci_cinfo[caitype].cai_associativity = ways;
 		ci->ci_cinfo[caitype].cai_linesize = linesize;
+	}
+}
 static void
 intel_cpu_cacheinfo(struct cpu_info *ci)
+{
 	const struct x86_cache_info *cai;
 	u_int descs[4];
 	int iterations, i, j;
 	int type, level, ways, linesize, sets;
 	int caitype = -1;
 	uint8_t desc;
 	/* Return if the cpu is old pre-cpuid instruction cpu */
 	if (ci->ci_cpu_type >= 0)
 		return;
 	if (ci->ci_cpuid_level < 2)
 		return;
 	/*
 	 * Parse the cache info from `cpuid leaf 2', if we have it.
 	 * XXX This is kinda ugly, but hey, so is the architecture...
 	 */
 	x86_cpuid(2, descs);
 	iterations = descs[0] & 0xff;
 	while (iterations-- > 0) {
 		for (i = 0; i < 4; i++) {
 			if (descs[i] & 0x80000000)
 				continue;
 			for (j = 0; j < 4; j++) {
 				/*
 				 * The least significant byte in EAX
 				 * ((desc[0] >> 0) & 0xff) is always 0x01 and
 				 * it should be ignored.
 				 */
 				if (i == 0 && j == 0)
 					continue;
 				desc = (descs[i] >> (j * 8)) & 0xff;
 				if (desc == 0)
 					continue;
 				cai = cache_info_lookup(intel_cpuid_cache_info,
 				    desc);
 				if (cai != NULL)
 					ci->ci_cinfo[cai->cai_index] = *cai;
 				else if ((verbose != 0) && (desc != 0xff)
 				    && (desc != 0xfe))
 					aprint_error_dev(ci->ci_dev, "error:"
 					    " Unknown cacheinfo desc %02x\n",
 					    desc);
+			}
+		}
 		x86_cpuid(2, descs);
+	}
 	if (ci->ci_cpuid_level < 4)
 		return;
 	/* Parse the cache info from `cpuid leaf 4', if we have it. */
 	cpu_dcp_cacheinfo(ci, 4);
 	if (ci->ci_cpuid_level < 0x18)
 		return;
 	/* Parse the TLB info from `cpuid leaf 18H', if we have it. */
 	x86_cpuid(0x18, descs);
 	iterations = descs[0];
 	for (i = 0; i <= iterations; i++) {
 		uint32_t pgsize;
 		bool full;
 		x86_cpuid2(0x18, i, descs);
 		type = __SHIFTOUT(descs[3], CPUID_DATP_TCTYPE);
 		if (type == CPUID_DATP_TCTYPE_N)
 			continue;
 		level = __SHIFTOUT(descs[3], CPUID_DATP_TCLEVEL);
 		pgsize = __SHIFTOUT(descs[1], CPUID_DATP_PGSIZE);
 		switch (level) {
 		case 1:
 			if (type == CPUID_DATP_TCTYPE_I) {
 				switch (pgsize) {
 				case CPUID_DATP_PGSIZE_4KB:
 					caitype = CAI_ITLB;
 					break;
 				case CPUID_DATP_PGSIZE_2MB
 				    | CPUID_DATP_PGSIZE_4MB:
 					caitype = CAI_ITLB2;
 					break;
 				case CPUID_DATP_PGSIZE_1GB:
 					caitype = CAI_L1_1GBITLB;
 					break;
 				default:
 					aprint_error_dev(ci->ci_dev,
 					    "error: unknown ITLB size (%d)\n",
 					    pgsize);
 					caitype = CAI_ITLB;
 					break;
+				}
 			} else if (type == CPUID_DATP_TCTYPE_D) {
 				switch (pgsize) {
 				case CPUID_DATP_PGSIZE_4KB:
 					caitype = CAI_DTLB;
 					break;
 				case CPUID_DATP_PGSIZE_2MB
 				    | CPUID_DATP_PGSIZE_4MB:
 					caitype = CAI_DTLB2;
 					break;
 				case CPUID_DATP_PGSIZE_1GB:
 					caitype = CAI_L1_1GBDTLB;
 					break;
 				default:
 					aprint_error_dev(ci->ci_dev,
 					    "error: unknown DTLB size (%d)\n",
 					    pgsize);
 					caitype = CAI_DTLB;
 					break;
+				}
 			} else
 				caitype = -1;
 			break;
 		case 2:
 			if (type == CPUID_DATP_TCTYPE_I)
 				caitype = CAI_L2_ITLB;
 			else if (type == CPUID_DATP_TCTYPE_D)
 				caitype = CAI_L2_DTLB;
 			else if (type == CPUID_DATP_TCTYPE_U) {
 				switch (pgsize) {
 				case CPUID_DATP_PGSIZE_4KB:
 					caitype = CAI_L2_STLB;
 					break;
 				case CPUID_DATP_PGSIZE_4KB
 				    | CPUID_DATP_PGSIZE_2MB:
 					caitype = CAI_L2_STLB2;
 					break;
 				case CPUID_DATP_PGSIZE_2MB
 				    | CPUID_DATP_PGSIZE_4MB:
 					caitype = CAI_L2_STLB3;
 					break;
 				default:
 					aprint_error_dev(ci->ci_dev,
 					    "error: unknown L2 STLB size (%d)\n",
 					    pgsize);
 					caitype = CAI_DTLB;
 					break;
+				}
 			} else
 				caitype = -1;
 			break;
 		case 3:
 			/* XXX need work for L3 TLB */
 			caitype = CAI_L3CACHE;
 			break;
 		default:
 			caitype = -1;
 			break;
+		}
 		if (caitype == -1) {
 			aprint_error_dev(ci->ci_dev,
 			    "error: unknown TLB level&type (%d & %d)\n",
 			    level, type);
 			continue;
+		}
 		switch (pgsize) {
 		case CPUID_DATP_PGSIZE_4KB:
 			linesize = 4 * 1024;
 			break;
 		case CPUID_DATP_PGSIZE_2MB:
 			linesize = 2 * 1024 * 1024;
 			break;
 		case CPUID_DATP_PGSIZE_4MB:
 			linesize = 4 * 1024 * 1024;
 			break;
 		case CPUID_DATP_PGSIZE_1GB:
 			linesize = 1024 * 1024 * 1024;
 			break;
 		case CPUID_DATP_PGSIZE_2MB | CPUID_DATP_PGSIZE_4MB:
 			aprint_error_dev(ci->ci_dev,
 			    "WARINING: Currently 2M/4M info can't print correctly\n");
 			linesize = 4 * 1024 * 1024;
 			break;
 		default:
 			aprint_error_dev(ci->ci_dev,
 			    "error: Unknown size combination\n");
 			linesize = 4 * 1024;
 			break;
+		}
 		ways = __SHIFTOUT(descs[1], CPUID_DATP_WAYS);
 		sets = descs[2];
 		full = descs[3] & CPUID_DATP_FULLASSOC;
 		ci->ci_cinfo[caitype].cai_totalsize
 		    = ways * sets; /* entries */
 		ci->ci_cinfo[caitype].cai_associativity
 		    = full ? 0xff : ways;
 		ci->ci_cinfo[caitype].cai_linesize = linesize; /* pg size */
+	}
+}
 static const struct x86_cache_info amd_cpuid_l2l3cache_assoc_info[] =
     AMD_L2L3CACHE_INFO;
 static void
 amd_cpu_cacheinfo(struct cpu_info *ci)
+{
 	const struct x86_cache_info *cp;
 	struct x86_cache_info *cai;
 	u_int descs[4];
 	u_int lfunc;
 	/* K5 model 0 has none of this info. */
 	if (ci->ci_family == 5 && ci->ci_model == 0)
 		return;
 	/* Determine the largest extended function value. */
 	x86_cpuid(0x80000000, descs);
 	lfunc = descs[0];
 	if (lfunc < 0x80000005)
 		return;
 	/* Determine L1 cache/TLB info. */
 	x86_cpuid(0x80000005, descs);
 	/* K6-III and higher have large page TLBs. */
 	if ((ci->ci_family == 5 && ci->ci_model >= 9) || ci->ci_family >= 6) {
 		cai = &ci->ci_cinfo[CAI_ITLB2];
 		cai->cai_totalsize = AMD_L1_EAX_ITLB_ENTRIES(descs[0]);
 		cai->cai_associativity = AMD_L1_EAX_ITLB_ASSOC(descs[0]);
 		cai->cai_linesize = largepagesize;
 		cai = &ci->ci_cinfo[CAI_DTLB2];
 		cai->cai_totalsize = AMD_L1_EAX_DTLB_ENTRIES(descs[0]);
 		cai->cai_associativity = AMD_L1_EAX_DTLB_ASSOC(descs[0]);
 		cai->cai_linesize = largepagesize;
+	}
 	cai = &ci->ci_cinfo[CAI_ITLB];
 	cai->cai_totalsize = AMD_L1_EBX_ITLB_ENTRIES(descs[1]);
 	cai->cai_associativity = AMD_L1_EBX_ITLB_ASSOC(descs[1]);
 	cai->cai_linesize = (4 * 1024);
 	cai = &ci->ci_cinfo[CAI_DTLB];
 	cai->cai_totalsize = AMD_L1_EBX_DTLB_ENTRIES(descs[1]);
 	cai->cai_associativity = AMD_L1_EBX_DTLB_ASSOC(descs[1]);
 	cai->cai_linesize = (4 * 1024);
 	cai = &ci->ci_cinfo[CAI_DCACHE];
 	cai->cai_totalsize = AMD_L1_ECX_DC_SIZE(descs[2]);
 	cai->cai_associativity = AMD_L1_ECX_DC_ASSOC(descs[2]);
 	cai->cai_linesize = AMD_L1_ECX_DC_LS(descs[2]);
 	cai = &ci->ci_cinfo[CAI_ICACHE];
 	cai->cai_totalsize = AMD_L1_EDX_IC_SIZE(descs[3]);
 	cai->cai_associativity = AMD_L1_EDX_IC_ASSOC(descs[3]);
 	cai->cai_linesize = AMD_L1_EDX_IC_LS(descs[3]);
 	if (lfunc < 0x80000006)
 		return;
 	/* Determine L2 cache/TLB info. */
 	x86_cpuid(0x80000006, descs);
 	cai = &ci->ci_cinfo[CAI_L2_ITLB];
 	cai->cai_totalsize = AMD_L2_EBX_IUTLB_ENTRIES(descs[1]);
 	cai->cai_associativity = AMD_L2_EBX_IUTLB_ASSOC(descs[1]);
 	cai->cai_linesize = (4 * 1024);
 	cp = cache_info_lookup(amd_cpuid_l2l3cache_assoc_info,
 	    cai->cai_associativity);
 	if (cp != NULL)
 		cai->cai_associativity = cp->cai_associativity;
 	else
 		cai->cai_associativity = 0;	/* XXX Unknown/reserved */
 	cai = &ci->ci_cinfo[CAI_L2_ITLB2];
 	cai->cai_totalsize = AMD_L2_EAX_IUTLB_ENTRIES(descs[0]);
 	cai->cai_associativity = AMD_L2_EAX_IUTLB_ASSOC(descs[0]);
 	cai->cai_linesize = largepagesize;
 	cp = cache_info_lookup(amd_cpuid_l2l3cache_assoc_info,
 	    cai->cai_associativity);
 	if (cp != NULL)
 		cai->cai_associativity = cp->cai_associativity;
 	else
 		cai->cai_associativity = 0;	/* XXX Unknown/reserved */
 	cai = &ci->ci_cinfo[CAI_L2_DTLB];
 	cai->cai_totalsize = AMD_L2_EBX_DTLB_ENTRIES(descs[1]);
 	cai->cai_associativity = AMD_L2_EBX_DTLB_ASSOC(descs[1]);
 	cai->cai_linesize = (4 * 1024);
 	cp = cache_info_lookup(amd_cpuid_l2l3cache_assoc_info,
 	    cai->cai_associativity);
 	if (cp != NULL)
 		cai->cai_associativity = cp->cai_associativity;
 	else
 		cai->cai_associativity = 0;	/* XXX Unknown/reserved */
 	cai = &ci->ci_cinfo[CAI_L2_DTLB2];
 	cai->cai_totalsize = AMD_L2_EAX_DTLB_ENTRIES(descs[0]);
 	cai->cai_associativity = AMD_L2_EAX_DTLB_ASSOC(descs[0]);
 	cai->cai_linesize = largepagesize;
 	cp = cache_info_lookup(amd_cpuid_l2l3cache_assoc_info,
 	    cai->cai_associativity);
 	if (cp != NULL)
 		cai->cai_associativity = cp->cai_associativity;
 	else
 		cai->cai_associativity = 0;	/* XXX Unknown/reserved */
 	cai = &ci->ci_cinfo[CAI_L2CACHE];
 	cai->cai_totalsize = AMD_L2_ECX_C_SIZE(descs[2]);
 	cai->cai_associativity = AMD_L2_ECX_C_ASSOC(descs[2]);
 	cai->cai_linesize = AMD_L2_ECX_C_LS(descs[2]);
 	cp = cache_info_lookup(amd_cpuid_l2l3cache_assoc_info,
 	    cai->cai_associativity);
 	if (cp != NULL)
 		cai->cai_associativity = cp->cai_associativity;
 	else
 		cai->cai_associativity = 0;	/* XXX Unknown/reserved */
 	/* Determine L3 cache info on AMD Family 10h and newer processors */
 	if (ci->ci_family >= 0x10) {
 		cai = &ci->ci_cinfo[CAI_L3CACHE];
 		cai->cai_totalsize = AMD_L3_EDX_C_SIZE(descs[3]);
 		cai->cai_associativity = AMD_L3_EDX_C_ASSOC(descs[3]);
 		cai->cai_linesize = AMD_L3_EDX_C_LS(descs[3]);
 		cp = cache_info_lookup(amd_cpuid_l2l3cache_assoc_info,
 		    cai->cai_associativity);
 		if (cp != NULL)
 			cai->cai_associativity = cp->cai_associativity;
 		else
 			cai->cai_associativity = 0;	/* XXX Unkn/Rsvd */
+	}
 	if (lfunc < 0x80000019)
 		return;
 	/* Determine 1GB TLB info. */
 	x86_cpuid(0x80000019, descs);
 	cai = &ci->ci_cinfo[CAI_L1_1GBITLB];
 	cai->cai_totalsize = AMD_L1_1GB_EAX_IUTLB_ENTRIES(descs[0]);
 	cai->cai_associativity = AMD_L1_1GB_EAX_IUTLB_ASSOC(descs[0]);
 	cai->cai_linesize = (1024 * 1024 * 1024);
 	cp = cache_info_lookup(amd_cpuid_l2l3cache_assoc_info,
 	    cai->cai_associativity);
 	if (cp != NULL)
 		cai->cai_associativity = cp->cai_associativity;
 	else
 		cai->cai_associativity = 0;	/* XXX Unknown/reserved */
 	cai = &ci->ci_cinfo[CAI_L1_1GBDTLB];
 	cai->cai_totalsize = AMD_L1_1GB_EAX_DTLB_ENTRIES(descs[0]);
 	cai->cai_associativity = AMD_L1_1GB_EAX_DTLB_ASSOC(descs[0]);
 	cai->cai_linesize = (1024 * 1024 * 1024);
 	cp = cache_info_lookup(amd_cpuid_l2l3cache_assoc_info,
 	    cai->cai_associativity);
 	if (cp != NULL)
 		cai->cai_associativity = cp->cai_associativity;
 	else
 		cai->cai_associativity = 0;	/* XXX Unknown/reserved */
 	cai = &ci->ci_cinfo[CAI_L2_1GBITLB];
 	cai->cai_totalsize = AMD_L2_1GB_EBX_IUTLB_ENTRIES(descs[1]);
 	cai->cai_associativity = AMD_L2_1GB_EBX_IUTLB_ASSOC(descs[1]);
 	cai->cai_linesize = (1024 * 1024 * 1024);
 	cp = cache_info_lookup(amd_cpuid_l2l3cache_assoc_info,
 	    cai->cai_associativity);
 	if (cp != NULL)
 		cai->cai_associativity = cp->cai_associativity;
 	else
 		cai->cai_associativity = 0;	/* XXX Unknown/reserved */
 	cai = &ci->ci_cinfo[CAI_L2_1GBDTLB];
 	cai->cai_totalsize = AMD_L2_1GB_EBX_DUTLB_ENTRIES(descs[1]);
 	cai->cai_associativity = AMD_L2_1GB_EBX_DUTLB_ASSOC(descs[1]);
 	cai->cai_linesize = (1024 * 1024 * 1024);
 	cp = cache_info_lookup(amd_cpuid_l2l3cache_assoc_info,
 	    cai->cai_associativity);
 	if (cp != NULL)
 		cai->cai_associativity = cp->cai_associativity;
 	else
 		cai->cai_associativity = 0;	/* XXX Unknown/reserved */
 	if (lfunc < 0x8000001d)
 		return;
 	if (ci->ci_feat_val[3] & CPUID_TOPOEXT)
 		cpu_dcp_cacheinfo(ci, 0x8000001d);
+}
 static void
 via_cpu_cacheinfo(struct cpu_info *ci)
+{
 	struct x86_cache_info *cai;
 	int stepping;
 	u_int descs[4];
 	u_int lfunc;
 	stepping = CPUID_TO_STEPPING(ci->ci_signature);
 	/*
 	 * Determine the largest extended function value.
 	 */
 	x86_cpuid(0x80000000, descs);
 	lfunc = descs[0];
 	/*
 	 * Determine L1 cache/TLB info.
 	 */
 	if (lfunc < 0x80000005) {
 		/* No L1 cache info available. */
 		return;
+	}
 	x86_cpuid(0x80000005, descs);
 	cai = &ci->ci_cinfo[CAI_ITLB];
 	cai->cai_totalsize = VIA_L1_EBX_ITLB_ENTRIES(descs[1]);
 	cai->cai_associativity = VIA_L1_EBX_ITLB_ASSOC(descs[1]);
 	cai->cai_linesize = (4 * 1024);
 	cai = &ci->ci_cinfo[CAI_DTLB];
 	cai->cai_totalsize = VIA_L1_EBX_DTLB_ENTRIES(descs[1]);
 	cai->cai_associativity = VIA_L1_EBX_DTLB_ASSOC(descs[1]);
 	cai->cai_linesize = (4 * 1024);
 	cai = &ci->ci_cinfo[CAI_DCACHE];
 	cai->cai_totalsize = VIA_L1_ECX_DC_SIZE(descs[2]);
 	cai->cai_associativity = VIA_L1_ECX_DC_ASSOC(descs[2]);
 	cai->cai_linesize = VIA_L1_EDX_IC_LS(descs[2]);
 	if (ci->ci_model == 9 && stepping == 8) {
 		/* Erratum: stepping 8 reports 4 when it should be 2 */
 		cai->cai_associativity = 2;
+	}
 	cai = &ci->ci_cinfo[CAI_ICACHE];
 	cai->cai_totalsize = VIA_L1_EDX_IC_SIZE(descs[3]);
 	cai->cai_associativity = VIA_L1_EDX_IC_ASSOC(descs[3]);
 	cai->cai_linesize = VIA_L1_EDX_IC_LS(descs[3]);
 	if (ci->ci_model == 9 && stepping == 8) {
 		/* Erratum: stepping 8 reports 4 when it should be 2 */
 		cai->cai_associativity = 2;
+	}
 	/*
 	 * Determine L2 cache/TLB info.
 	 */
 	if (lfunc < 0x80000006) {
 		/* No L2 cache info available. */
 		return;
+	}
 	x86_cpuid(0x80000006, descs);
 	cai = &ci->ci_cinfo[CAI_L2CACHE];
 	if (ci->ci_model >= 9) {
 		cai->cai_totalsize = VIA_L2N_ECX_C_SIZE(descs[2]);
 		cai->cai_associativity = VIA_L2N_ECX_C_ASSOC(descs[2]);
 		cai->cai_linesize = VIA_L2N_ECX_C_LS(descs[2]);
 	} else {
 		cai->cai_totalsize = VIA_L2_ECX_C_SIZE(descs[2]);
 		cai->cai_associativity = VIA_L2_ECX_C_ASSOC(descs[2]);
 		cai->cai_linesize = VIA_L2_ECX_C_LS(descs[2]);
+	}
+}
 static void
 tmx86_get_longrun_status(u_int *frequency, u_int *voltage, u_int *percentage)
+{
 	u_int descs[4];
 	x86_cpuid(0x80860007, descs);
 	*frequency = descs[0];
 	*voltage = descs[1];
 	*percentage = descs[2];
+}
 static void
 transmeta_cpu_info(struct cpu_info *ci)
+{
 	u_int descs[4], nreg;
 	u_int frequency, voltage, percentage;
 	x86_cpuid(0x80860000, descs);
 	nreg = descs[0];
 	if (nreg >= 0x80860001) {
 		x86_cpuid(0x80860001, descs);
 		aprint_verbose_dev(ci->ci_dev, "Processor revision %u.%u.%u.%u\n",
 		    (descs[1] >> 24) & 0xff,
 		    (descs[1] >> 16) & 0xff,
 		    (descs[1] >> 8) & 0xff,
 		    descs[1] & 0xff);
+	}
 	if (nreg >= 0x80860002) {
 		x86_cpuid(0x80860002, descs);
 		aprint_verbose_dev(ci->ci_dev, "Code Morphing Software Rev: %u.%u.%u-%u-%u\n",
 		    (descs[1] >> 24) & 0xff,
 		    (descs[1] >> 16) & 0xff,
 		    (descs[1] >> 8) & 0xff,
 		    descs[1] & 0xff,
 		    descs[2]);
+	}
 	if (nreg >= 0x80860006) {
 		union {
 			char text[65];
 			u_int descs[4][4];
 		} info;
 		int i;
 		for (i=0; i<4; i++) {
 			x86_cpuid(0x80860003 + i, info.descs[i]);
+		}
 		info.text[64] = '\0';
 		aprint_verbose_dev(ci->ci_dev, "%s\n", info.text);
+	}
 	if (nreg >= 0x80860007) {
 		tmx86_get_longrun_status(&frequency,
 		    &voltage, &percentage);
 		aprint_verbose_dev(ci->ci_dev, "LongRun <%dMHz %dmV %d%%>\n",
 		    frequency, voltage, percentage);
+	}
+}
 static void
 cpu_probe_base_features(struct cpu_info *ci, const char *cpuname)
+{
 	u_int descs[4];
 	int i;
 	uint32_t brand[12];
 	memset(ci, 0, sizeof(*ci));
 	ci->ci_dev = cpuname;
 	ci->ci_cpu_type = x86_identify();
 	if (ci->ci_cpu_type >= 0) {
 		/* Old pre-cpuid instruction cpu */
 		ci->ci_cpuid_level = -1;
 		return;
+	}
 	/*
 	 * This CPU supports cpuid instruction, so we can call x86_cpuid()
 	 * function.
 	 */
 	/*
 	 * Fn0000_0000:
 	 * - Save cpuid max level.
 	 * - Save vendor string.
 	 */
 	x86_cpuid(0, descs);
 	ci->ci_cpuid_level = descs[0];
 	/* Save vendor string */
 	ci->ci_vendor[0] = descs[1];
 	ci->ci_vendor[2] = descs[2];
 	ci->ci_vendor[1] = descs[3];
 	ci->ci_vendor[3] = 0;
 	/*
 	 * Fn8000_0000:
 	 * - Get cpuid extended function's max level.
 	 */
 	x86_cpuid(0x80000000, descs);
 	if (descs[0] >= 0x80000000)
 		ci->ci_cpuid_extlevel = descs[0];
 	else {
 		/* Set lower value than 0x80000000 */
 		ci->ci_cpuid_extlevel = 0;
+	}
 	/*
 	 * Fn8000_000[2-4]:
 	 * - Save brand string.
 	 */
 	if (ci->ci_cpuid_extlevel >= 0x80000004) {
 		x86_cpuid(0x80000002, brand);
 		x86_cpuid(0x80000003, brand + 4);
 		x86_cpuid(0x80000004, brand + 8);
 		for (i = 0; i < 48; i++)
 			if (((char *) brand)[i] != ' ')
 				break;
 		memcpy(cpu_brand_string, ((char *) brand) + i, 48 - i);
+	}
 	if (ci->ci_cpuid_level < 1)
 		return;
 	/*
 	 * Fn0000_0001:
 	 * - Get CPU family, model and stepping (from eax).
 	 * - Initial local APIC ID and brand ID (from ebx)
 	 * - CPUID2 (from ecx)
 	 * - CPUID (from edx)
 	 */
 	x86_cpuid(1, descs);
 	ci->ci_signature = descs[0];
 	/* Extract full family/model values */
 	ci->ci_family = CPUID_TO_FAMILY(ci->ci_signature);
 	ci->ci_model = CPUID_TO_MODEL(ci->ci_signature);
 	/* Brand is low order 8 bits of ebx */
 	ci->ci_brand_id = __SHIFTOUT(descs[1], CPUID_BRAND_INDEX);
 	/* Initial local APIC ID */
 	ci->ci_initapicid = __SHIFTOUT(descs[1], CPUID_LOCAL_APIC_ID);
 	ci->ci_feat_val[1] = descs[2];
 	ci->ci_feat_val[0] = descs[3];
 	if (ci->ci_cpuid_level < 3)
 		return;
 	/*
 	 * If the processor serial number misfeature is present and supported,
 	 * extract it here.
 	 */
 	if ((ci->ci_feat_val[0] & CPUID_PN) != 0) {
 		ci->ci_cpu_serial[0] = ci->ci_signature;
 		x86_cpuid(3, descs);
 		ci->ci_cpu_serial[2] = descs[2];
 		ci->ci_cpu_serial[1] = descs[3];
+	}
 	if (ci->ci_cpuid_level < 0x7)
 		return;
 	x86_cpuid(7, descs);
 	ci->ci_feat_val[5] = descs[1];
 	ci->ci_feat_val[6] = descs[2];
 	ci->ci_feat_val[7] = descs[3];
 	if (ci->ci_cpuid_level < 0xd)
 		return;
 	/* Get support XCR0 bits */
 	x86_cpuid2(0xd, 0, descs);
 	ci->ci_feat_val[8] = descs[0];	/* Actually 64 bits */
 	ci->ci_cur_xsave = descs[1];
 	ci->ci_max_xsave = descs[2];
 	/* Additional flags (eg xsaveopt support) */
 	x86_cpuid2(0xd, 1, descs);
 	ci->ci_feat_val[9] = descs[0];	 /* Actually 64 bits */
+}
 static void
 cpu_probe_hv_features(struct cpu_info *ci, const char *cpuname)
+{
 	uint32_t descs[4];
 	char hv_sig[13];
 	char *p;
 	const char *hv_name;
 	int i;
 	/*
 	 * [RFC] CPUID usage for interaction between Hypervisors and Linux.
 	 * http://lkml.org/lkml/2008/10/1/246
+	 *
 	 * KB1009458: Mechanisms to determine if software is running in
 	 * a VMware virtual machine
 	 * http://kb.vmware.com/kb/1009458
 	 */
 	if ((ci->ci_feat_val[1] & CPUID2_RAZ) != 0) {
 		x86_cpuid(0x40000000, descs);
 		for (i = 1, p = hv_sig; i < 4; i++, p += sizeof(descs) / 4)
 			memcpy(p, &descs[i], sizeof(descs[i]));
 		*p = '\0';
 		/*
 		 * HV vendor	ID string
 		 * ------------+--------------
 		 * HAXM		"HAXMHAXMHAXM"
 		 * KVM		"KVMKVMKVM"
 		 * Microsoft	"Microsoft Hv"
 		 * QEMU(TCG)	"TCGTCGTCGTCG"
 		 * VMware	"VMwareVMware"
 		 * Xen		"XenVMMXenVMM"
 		 * NetBSD	"___ NVMM ___"
 		 */
 		if (strncmp(hv_sig, "HAXMHAXMHAXM", 12) == 0)
 			hv_name = "HAXM";
 		else if (strncmp(hv_sig, "KVMKVMKVM", 9) == 0)
 			hv_name = "KVM";
 		else if (strncmp(hv_sig, "Microsoft Hv", 12) == 0)
 			hv_name = "Hyper-V";
 		else if (strncmp(hv_sig, "TCGTCGTCGTCG", 12) == 0)
 			hv_name = "QEMU(TCG)";
 		else if (strncmp(hv_sig, "VMwareVMware", 12) == 0)
 			hv_name = "VMware";
 		else if (strncmp(hv_sig, "XenVMMXenVMM", 12) == 0)
 			hv_name = "Xen";
 		else if (strncmp(hv_sig, "___ NVMM ___", 12) == 0)
 			hv_name = "NVMM";
 		else
 			hv_name = "unknown";
 		printf("%s: Running on hypervisor: %s\n", cpuname, hv_name);
+	}
+}
 static void
 cpu_probe_features(struct cpu_info *ci)
+{
 	const struct cpu_cpuid_nameclass *cpup = NULL;
 	unsigned int i;
 	if (ci->ci_cpuid_level < 1)
 		return;
 	for (i = 0; i < __arraycount(i386_cpuid_cpus); i++) {
 		if (!strncmp((char *)ci->ci_vendor,
 		    i386_cpuid_cpus[i].cpu_id, 12)) {
 			cpup = &i386_cpuid_cpus[i];
 			break;
+		}
+	}
 	if (cpup == NULL)
 		return;
 	i = ci->ci_family - CPU_MINFAMILY;
 	if (i >= __arraycount(cpup->cpu_family))
 		i = __arraycount(cpup->cpu_family) - 1;
 	if (cpup->cpu_family[i].cpu_probe == NULL)
 		return;
 	(*cpup->cpu_family[i].cpu_probe)(ci);
+}
 static void
 print_bits(const char *cpuname, const char *hdr, const char *fmt, uint32_t val)
+{
 	char buf[32 * 16];
 	char *bp;
 #define	MAX_LINE_LEN	79	/* get from command arg or 'stty cols' ? */
 	if (val == 0 || fmt == NULL)
 		return;
 	snprintb_m(buf, sizeof(buf), fmt, val,
 	    MAX_LINE_LEN - strlen(cpuname) - 2 - strlen(hdr) - 1);
 	bp = buf;
 	while (*bp != '\0') {
 		aprint_verbose("%s: %s %s\n", cpuname, hdr, bp);
 		bp += strlen(bp) + 1;
+	}
+}
 static void
 dump_descs(uint32_t leafstart, uint32_t leafend, const char *cpuname,
     const char *blockname)
+{
 	uint32_t descs[4];
 	uint32_t leaf;
 	aprint_verbose("%s: highest %s info %08x\n", cpuname, blockname,
 	    leafend);
 	if (verbose) {
 		for (leaf = leafstart; leaf <= leafend; leaf++) {
 			x86_cpuid(leaf, descs);
 			printf("%s: %08x: %08x %08x %08x %08x\n", cpuname,
 			    leaf, descs[0], descs[1], descs[2], descs[3]);
+		}
+	}
+}
 static void
 identifycpu_cpuids_intel_0x04(struct cpu_info *ci)
+{
 	u_int lp_max = 1;	/* logical processors per package */
 	u_int smt_max;		/* smt per core */
 	u_int core_max = 1;	/* core per package */
 	u_int smt_bits, core_bits;
 	uint32_t descs[4];
 	/*
 	 * 253668.pdf 7.10.2
 	 */
 	if ((ci->ci_feat_val[0] & CPUID_HTT) != 0) {
 		x86_cpuid(1, descs);
 		lp_max = __SHIFTOUT(descs[1], CPUID_HTT_CORES);
+	}
 	x86_cpuid2(4, 0, descs);
 	core_max = __SHIFTOUT(descs[0], CPUID_DCP_CORE_P_PKG) + 1;
 	assert(lp_max >= core_max);
 	smt_max = lp_max / core_max;
 	smt_bits = ilog2(smt_max - 1) + 1;
 	core_bits = ilog2(core_max - 1) + 1;
 	if (smt_bits + core_bits)
 		ci->ci_packageid = ci->ci_initapicid >> (smt_bits + core_bits);
 	if (core_bits)
 		ci->ci_coreid = __SHIFTOUT(ci->ci_initapicid,
 		    __BITS(smt_bits, smt_bits + core_bits - 1));
 	if (smt_bits)
 		ci->ci_smtid = __SHIFTOUT(ci->ci_initapicid,
 		    __BITS((int)0, (int)(smt_bits - 1)));
+}
 static void
 identifycpu_cpuids_intel_0x0b(struct cpu_info *ci)
+{
 	const char *cpuname = ci->ci_dev;
 	u_int smt_bits, core_bits, core_shift = 0, pkg_shift = 0;
 	uint32_t descs[4];
 	int i;
 	x86_cpuid(0x0b, descs);
 	if (descs[1] == 0) {
 		identifycpu_cpuids_intel_0x04(ci);
 		return;
+	}
 	for (i = 0; ; i++) {
 		unsigned int shiftnum, lvltype;
 		x86_cpuid2(0x0b, i, descs);
 		/* On invalid level, (EAX and) EBX return 0 */
 		if (descs[1] == 0)
 			break;
 		shiftnum = __SHIFTOUT(descs[0], CPUID_TOP_SHIFTNUM);
 		lvltype = __SHIFTOUT(descs[2], CPUID_TOP_LVLTYPE);
 		switch (lvltype) {
 		case CPUID_TOP_LVLTYPE_SMT:
 			core_shift = shiftnum;
 			break;
 		case CPUID_TOP_LVLTYPE_CORE:
 			pkg_shift = shiftnum;
 			break;
 		case CPUID_TOP_LVLTYPE_INVAL:
 			aprint_verbose("%s: Invalid level type\n", cpuname);
 			break;
 		default:
 			aprint_verbose("%s: Unknown level type(%d) \n",
 			    cpuname, lvltype);
 			break;
+		}
+	}
 	assert(pkg_shift >= core_shift);
 	smt_bits = core_shift;
 	core_bits = pkg_shift - core_shift;
 	ci->ci_packageid = ci->ci_initapicid >> pkg_shift;
 	if (core_bits)
 		ci->ci_coreid = __SHIFTOUT(ci->ci_initapicid,
 		    __BITS(core_shift, pkg_shift - 1));
 	if (smt_bits)
 		ci->ci_smtid = __SHIFTOUT(ci->ci_initapicid,
 		    __BITS((int)0, core_shift - 1));
+}
 static void
 identifycpu_cpuids_intel(struct cpu_info *ci)
+{
 	const char *cpuname = ci->ci_dev;
 	if (ci->ci_cpuid_level >= 0x0b)
 		identifycpu_cpuids_intel_0x0b(ci);
 	else if (ci->ci_cpuid_level >= 4)
 		identifycpu_cpuids_intel_0x04(ci);
 	aprint_verbose("%s: Cluster/Package ID %u\n", cpuname,
 	    ci->ci_packageid);
 	aprint_verbose("%s: Core ID %u\n", cpuname, ci->ci_coreid);
 	aprint_verbose("%s: SMT ID %u\n", cpuname, ci->ci_smtid);
+}
 static void
 identifycpu_cpuids_amd(struct cpu_info *ci)
+{
 	const char *cpuname = ci->ci_dev;
 	u_int lp_max, core_max;
 	int n, cpu_family, apic_id, smt_bits, core_bits = 0;
 	uint32_t descs[4];
 	apic_id = ci->ci_initapicid;
 	cpu_family = CPUID_TO_FAMILY(ci->ci_signature);
 	if (cpu_family < 0xf)
 		return;
 	if ((ci->ci_feat_val[0] & CPUID_HTT) != 0) {
 		x86_cpuid(1, descs);
 		lp_max = __SHIFTOUT(descs[1], CPUID_HTT_CORES);
-		if (cpu_family >= 0x10 && ci->ci_max_ext_cpuid >= 0x8000008) {
+		if (cpu_family >= 0x10 && ci->ci_cpuid_extlevel >= 0x8000008) {
 			x86_cpuid(0x8000008, descs);
 			core_max = (descs[2] & 0xff) + 1;
 			n = (descs[2] >> 12) & 0x0f;
 			if (n != 0)
 				core_bits = n;
+		}
 	} else {
 		lp_max = 1;
+	}
 	core_max = lp_max;
 	smt_bits = ilog2((lp_max / core_max) - 1) + 1;
 	if (core_bits == 0)
 		core_bits = ilog2(core_max - 1) + 1;
 #if 0 /* MSRs need kernel mode */
 	if (cpu_family < 0x11) {
 		const uint64_t reg = rdmsr(MSR_NB_CFG);
 		if ((reg & NB_CFG_INITAPICCPUIDLO) == 0) {
 			const u_int node_id = apic_id & __BITS(0, 2);
 			apic_id = (cpu_family == 0xf) ?
 				(apic_id >> core_bits) | (node_id << core_bits) :
 				(apic_id >> 5) | (node_id << 2);
+		}
+	}
 #endif
 	if (cpu_family == 0x17) {
 		x86_cpuid(0x8000001e, descs);
 		const u_int threads = ((descs[1] >> 8) & 0xff) + 1;
 		smt_bits = ilog2(threads);
 		core_bits -= smt_bits;
+	}
 	if (smt_bits + core_bits) {
 		if (smt_bits + core_bits < 32)
 			ci->ci_packageid = 0;
+	}
 	if (core_bits) {
 		u_int core_mask = __BITS(smt_bits, smt_bits + core_bits - 1);
 		ci->ci_coreid = __SHIFTOUT(apic_id, core_mask);
+	}
 	if (smt_bits) {
 		u_int smt_mask = __BITS(0, smt_bits - 1);
 		ci->ci_smtid = __SHIFTOUT(apic_id, smt_mask);
+	}
 	aprint_verbose("%s: Cluster/Package ID %u\n", cpuname,
 	    ci->ci_packageid);
 	aprint_verbose("%s: Core ID %u\n", cpuname, ci->ci_coreid);
 	aprint_verbose("%s: SMT ID %u\n", cpuname, ci->ci_smtid);
+}
 static void
 identifycpu_cpuids(struct cpu_info *ci)
+{
 	const char *cpuname = ci->ci_dev;
 	aprint_verbose("%s: Initial APIC ID %u\n", cpuname, ci->ci_initapicid);
 	ci->ci_packageid = ci->ci_initapicid;
 	ci->ci_coreid = 0;
 	ci->ci_smtid = 0;
 	if (cpu_vendor == CPUVENDOR_INTEL)
 		identifycpu_cpuids_intel(ci);
 	else if (cpu_vendor == CPUVENDOR_AMD)
 		identifycpu_cpuids_amd(ci);
+}
 void
 identifycpu(int fd, const char *cpuname)
+{
 	const char *name = "", *modifier, *vendorname, *brand = "";
 	int class = CPUCLASS_386;
 	unsigned int i;
 	int modif, family;
 	const struct cpu_cpuid_nameclass *cpup = NULL;
 	const struct cpu_cpuid_family *cpufam;
 	struct cpu_info *ci, cistore;
 	u_int descs[4];
 	size_t sz;
 	struct cpu_ucode_version ucode;
 	union {
 		struct cpu_ucode_version_amd amd;
 		struct cpu_ucode_version_intel1 intel1;
 	} ucvers;
 	ci = &cistore;
 	cpu_probe_base_features(ci, cpuname);
 	dump_descs(0x00000000, ci->ci_cpuid_level, cpuname, "basic");
 	if ((ci->ci_feat_val[1] & CPUID2_RAZ) != 0) {
 		x86_cpuid(0x40000000, descs);
 		dump_descs(0x40000000, descs[0], cpuname, "hypervisor");
+	}
 	dump_descs(0x80000000, ci->ci_cpuid_extlevel, cpuname, "extended");
 	cpu_probe_hv_features(ci, cpuname);
 	cpu_probe_features(ci);
 	if (ci->ci_cpu_type >= 0) {
 		/* Old pre-cpuid instruction cpu */
 		if (ci->ci_cpu_type >= (int)__arraycount(i386_nocpuid_cpus))
 			errx(1, "unknown cpu type %d", ci->ci_cpu_type);
 		name = i386_nocpuid_cpus[ci->ci_cpu_type].cpu_name;
 		cpu_vendor = i386_nocpuid_cpus[ci->ci_cpu_type].cpu_vendor;
 		vendorname = i386_nocpuid_cpus[ci->ci_cpu_type].cpu_vendorname;
 		class = i386_nocpuid_cpus[ci->ci_cpu_type].cpu_class;
 		ci->ci_info = i386_nocpuid_cpus[ci->ci_cpu_type].cpu_info;
 		modifier = "";
 	} else {
 		/* CPU which support cpuid instruction */
 		modif = (ci->ci_signature >> 12) & 0x3;
 		family = ci->ci_family;
 		if (family < CPU_MINFAMILY)
 			errx(1, "identifycpu: strange family value");
 		if (family > CPU_MAXFAMILY)
 			family = CPU_MAXFAMILY;
 		for (i = 0; i < __arraycount(i386_cpuid_cpus); i++) {
 			if (!strncmp((char *)ci->ci_vendor,
 			    i386_cpuid_cpus[i].cpu_id, 12)) {
 				cpup = &i386_cpuid_cpus[i];
 				break;
+			}
+		}
 		if (cpup == NULL) {
 			cpu_vendor = CPUVENDOR_UNKNOWN;
 			if (ci->ci_vendor[0] != '\0')
 				vendorname = (char *)&ci->ci_vendor[0];
 			else
 				vendorname = "Unknown";
 			class = family - 3;
 			modifier = "";
 			name = "";
 			ci->ci_info = NULL;
 		} else {
 			cpu_vendor = cpup->cpu_vendor;
 			vendorname = cpup->cpu_vendorname;
 			modifier = modifiers[modif];
 			cpufam = &cpup->cpu_family[family - CPU_MINFAMILY];
 			name = cpufam->cpu_models[ci->ci_model];
 			if (name == NULL || *name == '\0')
 				name = cpufam->cpu_model_default;
 			class = cpufam->cpu_class;
 			ci->ci_info = cpufam->cpu_info;
 			if (cpu_vendor == CPUVENDOR_INTEL) {
 				if (ci->ci_family == 6 && ci->ci_model >= 5) {
 					const char *tmp;
 					tmp = intel_family6_name(ci);
 					if (tmp != NULL)
 						name = tmp;
+				}
 				if (ci->ci_family == 15 &&
 				    ci->ci_brand_id <
 				    __arraycount(i386_intel_brand) &&
 				    i386_intel_brand[ci->ci_brand_id])
 					name =
 					    i386_intel_brand[ci->ci_brand_id];
+			}
 			if (cpu_vendor == CPUVENDOR_AMD) {
 				if (ci->ci_family == 6 && ci->ci_model >= 6) {
 					if (ci->ci_brand_id == 1)
 						/*
 						 * It's Duron. We override the
 						 * name, since it might have
 						 * been misidentified as Athlon.
 						 */
 						name =
 						    amd_brand[ci->ci_brand_id];
 					else
 						brand = amd_brand_name;
+				}
 				if (CPUID_TO_BASEFAMILY(ci->ci_signature)
 				    == 0xf) {
 					/* Identify AMD64 CPU names.  */
 					const char *tmp;
 					tmp = amd_amd64_name(ci);
 					if (tmp != NULL)
 						name = tmp;
+				}
+			}
 			if (cpu_vendor == CPUVENDOR_IDT && ci->ci_family >= 6)
 				vendorname = "VIA";
+		}
+	}
 	ci->ci_cpu_class = class;
 	sz = sizeof(ci->ci_tsc_freq);
 	(void)sysctlbyname("machdep.tsc_freq", &ci->ci_tsc_freq, &sz, NULL, 0);
 	sz = sizeof(use_pae);
 	(void)sysctlbyname("machdep.pae", &use_pae, &sz, NULL, 0);
 	largepagesize = (use_pae ? 2 * 1024 * 1024 : 4 * 1024 * 1024);
 	/*
 	 * The 'cpu_brand_string' is much more useful than the 'cpu_model'
 	 * we try to determine from the family/model values.
 	 */
 	if (*cpu_brand_string != '\0')
 		aprint_normal("%s: \"%s\"\n", cpuname, cpu_brand_string);
 	aprint_normal("%s: %s", cpuname, vendorname);
 	if (*modifier)
 		aprint_normal(" %s", modifier);
 	if (*name)
 		aprint_normal(" %s", name);
 	if (*brand)
 		aprint_normal(" %s", brand);
 	aprint_normal(" (%s-class)", classnames[class]);
 	if (ci->ci_tsc_freq != 0)
 		aprint_normal(", %ju.%02ju MHz",
 		    ((uintmax_t)ci->ci_tsc_freq + 4999) / 1000000,
 		    (((uintmax_t)ci->ci_tsc_freq + 4999) / 10000) % 100);
 	aprint_normal("\n");
 	aprint_normal_dev(ci->ci_dev, "family %#x model %#x stepping %#x",
 	    ci->ci_family, ci->ci_model, CPUID_TO_STEPPING(ci->ci_signature));
 	if (ci->ci_signature != 0)
 		aprint_normal(" (id %#x)", ci->ci_signature);
 	aprint_normal("\n");
 	if (ci->ci_info)
 		(*ci->ci_info)(ci);
 	/*
 	 * display CPU feature flags
 	 */
 	print_bits(cpuname, "features", CPUID_FLAGS1, ci->ci_feat_val[0]);
 	print_bits(cpuname, "features1", CPUID2_FLAGS1, ci->ci_feat_val[1]);
 	/* These next two are actually common definitions! */
 	print_bits(cpuname, "features2",
 	    cpu_vendor == CPUVENDOR_INTEL ? CPUID_INTEL_EXT_FLAGS
 		: CPUID_EXT_FLAGS, ci->ci_feat_val[2]);
 	print_bits(cpuname, "features3",
 	    cpu_vendor == CPUVENDOR_INTEL ? CPUID_INTEL_FLAGS4
 		: CPUID_AMD_FLAGS4, ci->ci_feat_val[3]);
 	print_bits(cpuname, "padloack features", CPUID_FLAGS_PADLOCK,
 	    ci->ci_feat_val[4]);
 	if ((cpu_vendor == CPUVENDOR_INTEL) || (cpu_vendor == CPUVENDOR_AMD))
 		print_bits(cpuname, "features5", CPUID_SEF_FLAGS,
 		    ci->ci_feat_val[5]);
 	if ((cpu_vendor == CPUVENDOR_INTEL) || (cpu_vendor == CPUVENDOR_AMD))
 		print_bits(cpuname, "features6", CPUID_SEF_FLAGS1,
 		    ci->ci_feat_val[6]);
 	if (cpu_vendor == CPUVENDOR_INTEL)
 		print_bits(cpuname, "features7", CPUID_SEF_FLAGS2,
 		    ci->ci_feat_val[7]);
 	print_bits(cpuname, "xsave features", XCR0_FLAGS1, ci->ci_feat_val[8]);
 	print_bits(cpuname, "xsave instructions", CPUID_PES1_FLAGS,
 	    ci->ci_feat_val[9]);
 	if (ci->ci_max_xsave != 0) {
 		aprint_normal("%s: xsave area size: current %d, maximum %d",
 		    cpuname, ci->ci_cur_xsave, ci->ci_max_xsave);
 		aprint_normal(", xgetbv %sabled\n",
 		    ci->ci_feat_val[1] & CPUID2_OSXSAVE ? "en" : "dis");
 		if (ci->ci_feat_val[1] & CPUID2_OSXSAVE)
 			print_bits(cpuname, "enabled xsave", XCR0_FLAGS1,
 			    x86_xgetbv());
+	}
 	x86_print_cache_and_tlb_info(ci);
 	if (ci->ci_cpuid_level >= 3 && (ci->ci_feat_val[0] & CPUID_PN)) {
 		aprint_verbose("%s: serial number %04X-%04X-%04X-%04X-%04X-%04X\n",
 		    cpuname,
 		    ci->ci_cpu_serial[0] / 65536, ci->ci_cpu_serial[0] % 65536,
 		    ci->ci_cpu_serial[1] / 65536, ci->ci_cpu_serial[1] % 65536,
 		    ci->ci_cpu_serial[2] / 65536, ci->ci_cpu_serial[2] % 65536);
+	}
 	if (ci->ci_cpu_class == CPUCLASS_386)
 		errx(1, "NetBSD requires an 80486 or later processor");
 	if (ci->ci_cpu_type == CPU_486DLC) {
 #ifndef CYRIX_CACHE_WORKS
 		aprint_error("WARNING: CYRIX 486DLC CACHE UNCHANGED.\n");
 #else
 #ifndef CYRIX_CACHE_REALLY_WORKS
 		aprint_error("WARNING: CYRIX 486DLC CACHE ENABLED IN HOLD-FLUSH MODE.\n");
 #else
 		aprint_error("WARNING: CYRIX 486DLC CACHE ENABLED.\n");
 #endif
 #endif
+	}
 	/*
 	 * Everything past this point requires a Pentium or later.
 	 */
 	if (ci->ci_cpuid_level < 0)
 		return;
 	identifycpu_cpuids(ci);
 	if ((ci->ci_cpuid_level >= 5)
 	    && ((cpu_vendor == CPUVENDOR_INTEL)
 		|| (cpu_vendor == CPUVENDOR_AMD))) {
 		uint16_t lmin, lmax;
 		x86_cpuid(5, descs);
 		print_bits(cpuname, "MONITOR/MWAIT extensions",
 		    CPUID_MON_FLAGS, descs[2]);
 		lmin = __SHIFTOUT(descs[0], CPUID_MON_MINSIZE);
 		lmax = __SHIFTOUT(descs[1], CPUID_MON_MAXSIZE);
 		aprint_normal("%s: monitor-line size %hu", cpuname, lmin);
 		if (lmin != lmax)
 			aprint_normal("-%hu", lmax);
 		aprint_normal("\n");
 		for (i = 0; i <= 7; i++) {
 			unsigned int num = CPUID_MON_SUBSTATE(descs[3], i);
 			if (num != 0)
 				aprint_normal("%s: C%u substates %u\n",
 				    cpuname, i, num);
+		}
+	}
 	if ((ci->ci_cpuid_level >= 6)
 	    && ((cpu_vendor == CPUVENDOR_INTEL)
 		|| (cpu_vendor == CPUVENDOR_AMD))) {
 		x86_cpuid(6, descs);
 		print_bits(cpuname, "DSPM-eax", CPUID_DSPM_FLAGS, descs[0]);
 		print_bits(cpuname, "DSPM-ecx", CPUID_DSPM_FLAGS1, descs[2]);
+	}
 	if ((ci->ci_cpuid_level >= 7)
 	    && ((cpu_vendor == CPUVENDOR_INTEL)
 		|| (cpu_vendor == CPUVENDOR_AMD))) {
 		x86_cpuid(7, descs);
 		aprint_verbose("%s: SEF highest subleaf %08x\n",
 		    cpuname, descs[0]);
+	}
-	if (cpu_vendor == CPUVENDOR_AMD) {
+	if ((cpu_vendor == CPUVENDOR_INTEL) || (cpu_vendor == CPUVENDOR_AMD))
-		x86_cpuid(0x80000000, descs);
+		if (ci->ci_cpuid_extlevel >= 0x80000007)
 		if (descs[0] >= 0x80000000)
 			ci->ci_max_ext_cpuid = descs[0];
 		else
 			ci->ci_max_ext_cpuid = 0;
 		if (ci->ci_max_ext_cpuid >= 0x80000007)
 			powernow_probe(ci);
-		if (ci->ci_max_ext_cpuid >= 0x80000008) {
+	if (cpu_vendor == CPUVENDOR_AMD) {
 		if (ci->ci_cpuid_extlevel >= 0x80000008) {
 			x86_cpuid(0x80000008, descs);
 			print_bits(cpuname, "AMD Extended features",
 			    CPUID_CAPEX_FLAGS, descs[1]);
+		}
-		if ((ci->ci_max_ext_cpuid >= 0x8000000a)
+		if ((ci->ci_cpuid_extlevel >= 0x8000000a)
 		    && (ci->ci_feat_val[3] & CPUID_SVM) != 0) {
 			x86_cpuid(0x8000000a, descs);
 			aprint_verbose("%s: SVM Rev. %d\n", cpuname,
 			    descs[0] & 0xf);
 			aprint_verbose("%s: SVM NASID %d\n", cpuname,
 			    descs[1]);
 			print_bits(cpuname, "SVM features",
 			    CPUID_AMD_SVM_FLAGS, descs[3]);
+		}
-		if (ci->ci_max_ext_cpuid >= 0x8000001f) {
+		if (ci->ci_cpuid_extlevel >= 0x8000001f) {
 			x86_cpuid(0x8000001f, descs);
 			print_bits(cpuname, "Encrypted Memory features",
 			    CPUID_AMD_ENCMEM_FLAGS, descs[0]);
+		}
 	} else if (cpu_vendor == CPUVENDOR_INTEL) {
 		int32_t bi_index;
 		for (bi_index = 1; bi_index <= ci->ci_cpuid_level; bi_index++) {
 			x86_cpuid(bi_index, descs);
 			switch (bi_index) {
 			case 0x0a:
 				print_bits(cpuname, "Perfmon-eax",
 				    CPUID_PERF_FLAGS0, descs[0]);
 				print_bits(cpuname, "Perfmon-ebx",
 				    CPUID_PERF_FLAGS1, descs[1]);
 				print_bits(cpuname, "Perfmon-edx",
 				    CPUID_PERF_FLAGS3, descs[3]);
 				break;
 			default:
 #if 0
 				aprint_verbose("%s: basic %08x-eax %08x\n",
 				    cpuname, bi_index, descs[0]);
 				aprint_verbose("%s: basic %08x-ebx %08x\n",
 				    cpuname, bi_index, descs[1]);
 				aprint_verbose("%s: basic %08x-ecx %08x\n",
 				    cpuname, bi_index, descs[2]);
 				aprint_verbose("%s: basic %08x-edx %08x\n",
 				    cpuname, bi_index, descs[3]);
 #endif
 				break;
+			}
+		}
+	}
 #ifdef INTEL_ONDEMAND_CLOCKMOD
 	clockmod_init();
 #endif
 	if (cpu_vendor == CPUVENDOR_AMD)
 		ucode.loader_version = CPU_UCODE_LOADER_AMD;
 	else if (cpu_vendor == CPUVENDOR_INTEL)
 		ucode.loader_version = CPU_UCODE_LOADER_INTEL1;
 	else
 		return;
 	ucode.data = &ucvers;
 	if (ioctl(fd, IOC_CPU_UCODE_GET_VERSION, &ucode) < 0) {
 #ifdef __i386__
 		struct cpu_ucode_version_64 ucode_64;
 		if (errno != ENOTTY)
 			return;
 		/* Try the 64 bit ioctl */
 		memset(&ucode_64, 0, sizeof ucode_64);
 		ucode_64.data = &ucvers;
 		ucode_64.loader_version = ucode.loader_version;
 		if (ioctl(fd, IOC_CPU_UCODE_GET_VERSION_64, &ucode_64) < 0)
 			return;
 #else
 		return;
 #endif
+	}
 	if (cpu_vendor == CPUVENDOR_AMD)
 		printf("%s: UCode version: 0x%"PRIx64"\n", cpuname, ucvers.amd.version);
 	else if (cpu_vendor == CPUVENDOR_INTEL)
 		printf("%s: microcode version 0x%x, platform ID %d\n", cpuname,
 		    ucvers.intel1.ucodeversion, ucvers.intel1.platformid);
+}
 static const struct x86_cache_info *
 cache_info_lookup(const struct x86_cache_info *cai, uint8_t desc)
+{
 	int i;
 	for (i = 0; cai[i].cai_desc != 0; i++) {
 		if (cai[i].cai_desc == desc)
 			return (&cai[i]);
+	}
 	return (NULL);
+}
 static const char *
 print_cache_config(struct cpu_info *ci, int cache_tag, const char *name,
     const char *sep)
+{
 	struct x86_cache_info *cai = &ci->ci_cinfo[cache_tag];
 	char human_num[HUMAN_BUFSIZE];
 	if (cai->cai_totalsize == 0)
 		return sep;
 	if (sep == NULL)
 		aprint_verbose_dev(ci->ci_dev, "");
 	else
 		aprint_verbose("%s", sep);
 	if (name != NULL)
 		aprint_verbose("%s ", name);
 	if (cai->cai_string != NULL) {
 		aprint_verbose("%s ", cai->cai_string);
 	} else {
 		(void)humanize_number(human_num, sizeof(human_num),
 		    cai->cai_totalsize, "B", HN_AUTOSCALE, HN_NOSPACE);
 		aprint_verbose("%s %dB/line ", human_num, cai->cai_linesize);
+	}
 	switch (cai->cai_associativity) {
 	case	0:
 		aprint_verbose("disabled");
 		break;
 	case	1:
 		aprint_verbose("direct-mapped");
 		break;
 	case 0xff:
 		aprint_verbose("fully associative");
 		break;
 	default:
 		aprint_verbose("%d-way", cai->cai_associativity);
 		break;
+	}
 	return ", ";
+}
 static const char *
 print_tlb_config(struct cpu_info *ci, int cache_tag, const char *name,
     const char *sep)
+{
 	struct x86_cache_info *cai = &ci->ci_cinfo[cache_tag];
 	char human_num[HUMAN_BUFSIZE];
 	if (cai->cai_totalsize == 0)
 		return sep;
 	if (sep == NULL)
 		aprint_verbose_dev(ci->ci_dev, "");
 	else
 		aprint_verbose("%s", sep);
 	if (name != NULL)
 		aprint_verbose("%s ", name);
 	if (cai->cai_string != NULL) {
 		aprint_verbose("%s", cai->cai_string);
 	} else {
 		(void)humanize_number(human_num, sizeof(human_num),
 		    cai->cai_linesize, "B", HN_AUTOSCALE, HN_NOSPACE);
 		aprint_verbose("%d %s entries ", cai->cai_totalsize,
 		    human_num);
 		switch (cai->cai_associativity) {
 		case 0:
 			aprint_verbose("disabled");
 			break;
 		case 1:
 			aprint_verbose("direct-mapped");
 			break;
 		case 0xff:
 			aprint_verbose("fully associative");
 			break;
 		default:
 			aprint_verbose("%d-way", cai->cai_associativity);
 			break;
+		}
+	}
 	return ", ";
+}
 static void
 x86_print_cache_and_tlb_info(struct cpu_info *ci)
+{
 	const char *sep = NULL;
 	if (ci->ci_cinfo[CAI_ICACHE].cai_totalsize != 0 ||
 	    ci->ci_cinfo[CAI_DCACHE].cai_totalsize != 0) {
 		sep = print_cache_config(ci, CAI_ICACHE, "I-cache", NULL);
 		sep = print_cache_config(ci, CAI_DCACHE, "D-cache", sep);
 		if (sep != NULL)
 			aprint_verbose("\n");
+	}
 	if (ci->ci_cinfo[CAI_L2CACHE].cai_totalsize != 0) {
 		sep = print_cache_config(ci, CAI_L2CACHE, "L2 cache", NULL);
 		if (sep != NULL)
 			aprint_verbose("\n");
+	}
 	if (ci->ci_cinfo[CAI_L3CACHE].cai_totalsize != 0) {
 		sep = print_cache_config(ci, CAI_L3CACHE, "L3 cache", NULL);
 		if (sep != NULL)
 			aprint_verbose("\n");
+	}
 	if (ci->ci_cinfo[CAI_PREFETCH].cai_linesize != 0) {
 		aprint_verbose_dev(ci->ci_dev, "%dB prefetching",
 		    ci->ci_cinfo[CAI_PREFETCH].cai_linesize);
 		if (sep != NULL)
 			aprint_verbose("\n");
+	}
 	if (ci->ci_cinfo[CAI_ITLB].cai_totalsize != 0) {
 		sep = print_tlb_config(ci, CAI_ITLB, "ITLB", NULL);
 		sep = print_tlb_config(ci, CAI_ITLB2, NULL, sep);
 		if (sep != NULL)
 			aprint_verbose("\n");
+	}
 	if (ci->ci_cinfo[CAI_DTLB].cai_totalsize != 0) {
 		sep = print_tlb_config(ci, CAI_DTLB, "DTLB", NULL);
 		sep = print_tlb_config(ci, CAI_DTLB2, NULL, sep);
 		if (sep != NULL)
 			aprint_verbose("\n");
+	}
 	if (ci->ci_cinfo[CAI_L2_ITLB].cai_totalsize != 0) {
 		sep = print_tlb_config(ci, CAI_L2_ITLB, "L2 ITLB", NULL);
 		sep = print_tlb_config(ci, CAI_L2_ITLB2, NULL, sep);
 		if (sep != NULL)
 			aprint_verbose("\n");
+	}
 	if (ci->ci_cinfo[CAI_L2_DTLB].cai_totalsize != 0) {
 		sep = print_tlb_config(ci, CAI_L2_DTLB, "L2 DTLB", NULL);
 		sep = print_tlb_config(ci, CAI_L2_DTLB2, NULL, sep);
 		if (sep != NULL)
 			aprint_verbose("\n");
+	}
 	if (ci->ci_cinfo[CAI_L2_STLB].cai_totalsize != 0) {
 		sep = print_tlb_config(ci, CAI_L2_STLB, "L2 STLB", NULL);
 		sep = print_tlb_config(ci, CAI_L2_STLB2, NULL, sep);
 		sep = print_tlb_config(ci, CAI_L2_STLB3, NULL, sep);
 		if (sep != NULL)
 			aprint_verbose("\n");
+	}
 	if (ci->ci_cinfo[CAI_L1_1GBITLB].cai_totalsize != 0) {
 		sep = print_tlb_config(ci, CAI_L1_1GBITLB, "L1 1GB page ITLB",
 		    NULL);
 		if (sep != NULL)
 			aprint_verbose("\n");
+	}
 	if (ci->ci_cinfo[CAI_L1_1GBDTLB].cai_totalsize != 0) {
 		sep = print_tlb_config(ci, CAI_L1_1GBDTLB, "L1 1GB page DTLB",
 		    NULL);
 		if (sep != NULL)
 			aprint_verbose("\n");
+	}
 	if (ci->ci_cinfo[CAI_L2_1GBITLB].cai_totalsize != 0) {
 		sep = print_tlb_config(ci, CAI_L2_1GBITLB, "L2 1GB page ITLB",
 		    NULL);
 		if (sep != NULL)
 			aprint_verbose("\n");
+	}
 	if (ci->ci_cinfo[CAI_L2_1GBDTLB].cai_totalsize != 0) {
 		sep = print_tlb_config(ci, CAI_L2_1GBDTLB, "L2 1GB page DTLB",
 		    NULL);
 		if (sep != NULL)
 			aprint_verbose("\n");
+	}
+}
 static void
 powernow_probe(struct cpu_info *ci)
+{
 	uint32_t regs[4];
 	char buf[256];
 	x86_cpuid(0x80000007, regs);
 	snprintb(buf, sizeof(buf), CPUID_APM_FLAGS, regs[3]);
-	aprint_normal_dev(ci->ci_dev, "AMD Power Management features: %s\n",
+	aprint_normal_dev(ci->ci_dev, "Power Management features: %s\n", buf);
 	    buf);
+}
 bool
 identifycpu_bind(void)
+{
 	return true;
+}
 int
 ucodeupdate_check(int fd, struct cpu_ucode *uc)
+{
 	struct cpu_info ci;
 	int loader_version, res;
 	struct cpu_ucode_version versreq;
 	cpu_probe_base_features(&ci, "unknown");
 	if (!strcmp((char *)ci.ci_vendor, "AuthenticAMD"))
 		loader_version = CPU_UCODE_LOADER_AMD;
 	else if (!strcmp((char *)ci.ci_vendor, "GenuineIntel"))
 		loader_version = CPU_UCODE_LOADER_INTEL1;
 	else
 		return -1;
 	/* check whether the kernel understands this loader version */
 	versreq.loader_version = loader_version;
 	versreq.data = 0;
 	res = ioctl(fd, IOC_CPU_UCODE_GET_VERSION, &versreq);
 	if (res)
 		return -1;
 	switch (loader_version) {
 	case CPU_UCODE_LOADER_AMD:
 		if (uc->cpu_nr != -1) {
 			/* printf? */
 			return -1;
+		}
 		uc->cpu_nr = CPU_UCODE_ALL_CPUS;
 		break;
 	case CPU_UCODE_LOADER_INTEL1:
 		if (uc->cpu_nr == -1)
 			uc->cpu_nr = CPU_UCODE_ALL_CPUS; /* for Xen */
 		else
 			uc->cpu_nr = CPU_UCODE_CURRENT_CPU;
 		break;
 	default: /* can't happen */
 		return -1;
+	}
 	uc->loader_version = loader_version;
 	return 0;
+}