 @@ -1,14 +1,14 @@
-/* $NetBSD: spdmem.c,v 1.24.6.2 2019/01/03 11:23:54 martin Exp $ */
+/* $NetBSD: spdmem.c,v 1.24.6.3 2020/04/14 17:39:28 martin Exp $ */
 /*
  * Copyright (c) 2007 Nicolas Joly
  * Copyright (c) 2007 Paul Goyette
  * Copyright (c) 2007 Tobias Nygren
  * All rights reserved.
+ *
  * Redistribution and use in source and binary forms, with or without
  * modification, are permitted provided that the following conditions
  * are met:
  * 1. Redistributions of source code must retain the above copyright
  *    notice, this list of conditions and the following disclaimer.
  * 2. Redistributions in binary form must reproduce the above copyright
 @@ -25,27 +25,27 @@
  * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
  * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
  * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
  * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
  * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
  * POSSIBILITY OF SUCH DAMAGE.
  */
 /*
  * Serial Presence Detect (SPD) memory identification
  */
 #include <sys/cdefs.h>
-__KERNEL_RCSID(0, "$NetBSD: spdmem.c,v 1.24.6.2 2019/01/03 11:23:54 martin Exp $");
+__KERNEL_RCSID(0, "$NetBSD: spdmem.c,v 1.24.6.3 2020/04/14 17:39:28 martin Exp $");
 #include <sys/param.h>
 #include <sys/device.h>
 #include <sys/endian.h>
 #include <sys/sysctl.h>
 #include <machine/bswap.h>
 #include <dev/i2c/i2cvar.h>
 #include <dev/ic/spdmemreg.h>
 #include <dev/ic/spdmemvar.h>
 /* Routines for decoding spd data */
 static void decode_edofpm(const struct sysctlnode *, device_t, struct spdmem *);
 @@ -330,32 +330,32 @@ spdmem_common_attach(struct spdmem_softc
 		spd_len = sizeof(struct spdmem);
 	for (i = 3; i < spd_len; i++)
 		(sc->sc_read)(sc, i, &((uint8_t *)s)[i]);
 	/*
 	 * Setup our sysctl subtree, hw.spdmemN
 	 */
 	sc->sc_sysctl_log = NULL;
 	sysctl_createv(&sc->sc_sysctl_log, 0, NULL, &node,
 , CTLTYPE_NODE,
 	    device_xname(self), NULL, NULL, 0, NULL, 0,
 	    CTL_HW, CTL_CREATE, CTL_EOL);
 	if (node != NULL && spd_len != 0)
-                sysctl_createv(&sc->sc_sysctl_log, 0, NULL, NULL,
+		sysctl_createv(&sc->sc_sysctl_log, 0, NULL, NULL,
 ,
-                    CTLTYPE_STRUCT, "spd_data",
+		    CTLTYPE_STRUCT, "spd_data",
 		    SYSCTL_DESCR("raw spd data"), NULL,
 , s, spd_len,
-                    CTL_HW, node->sysctl_num, CTL_CREATE, CTL_EOL);
+		    CTL_HW, node->sysctl_num, CTL_CREATE, CTL_EOL);
 	/*
 	 * Decode and print key SPD contents
 	 */
 	if (IS_RAMBUS_TYPE) {
 		if (s->sm_type == SPDMEM_MEMTYPE_RAMBUS)
 			type = "Rambus";
 		else if (s->sm_type == SPDMEM_MEMTYPE_DIRECTRAMBUS)
 			type = "Direct Rambus";
 		else
 			type = "Rambus (unknown)";
 		switch (s->sm_len) {
 @@ -401,27 +401,27 @@ spdmem_common_attach(struct spdmem_softc
 	strlcpy(sc->sc_type, type, SPDMEM_TYPE_MAXLEN);
 	if (s->sm_type == SPDMEM_MEMTYPE_DDR4SDRAM) {
 		/*
 		 * The latest spec (DDR4 SPD Document Release 3) defines
 		 * NVDIMM Hybrid only.
 		 */
 		if ((s->sm_ddr4.ddr4_hybrid)
 		    && (s->sm_ddr4.ddr4_hybrid_media == 1))
 			strlcat(sc->sc_type, " NVDIMM hybrid",
 			    SPDMEM_TYPE_MAXLEN);
+	}
 	if (node != NULL)
 		sysctl_createv(&sc->sc_sysctl_log, 0, NULL, NULL,
 ,
 		    CTLTYPE_STRING, "mem_type",
 		    SYSCTL_DESCR("memory module type"), NULL,
 , sc->sc_type, 0,
 		    CTL_HW, node->sysctl_num, CTL_CREATE, CTL_EOL);
 	if (IS_RAMBUS_TYPE) {
 		aprint_naive("\n");
 		aprint_normal("\n");
 		aprint_normal_dev(self, "%s, SPD Revision %s", type, rambus_rev);
 		dimm_size = 1 << (s->sm_rdr.rdr_rows + s->sm_rdr.rdr_cols - 13);
 @@ -605,27 +605,27 @@ decode_sdram(const struct sysctlnode *no
 	cycle_time = s->sm_sdr.sdr_cycle_whole * 1000 +
 		     s->sm_sdr.sdr_cycle_tenths * 100;
 	bits = le16toh(s->sm_sdr.sdr_datawidth);
 	if (s->sm_config == 1 || s->sm_config == 2)
 		bits -= 8;
 	/* Calculate speed here - from OpenBSD */
 	if (spd_len >= 128)
 		freq = ((uint8_t *)s)[126];
 	else
 		freq = 0;
 	switch (freq) {
 		/*
 		 * Must check cycle time since some PC-133 DIMMs
 		 * actually report PC-100
 		 */
 	    case 100:
 	    case 133:
 		if (cycle_time < 8000)
 			speed = 133;
 		else
 			speed = 100;
 		break;
 	    case 0x66:		/* Legacy DIMMs use _hex_ 66! */
 	    default:
 		speed = 66;
+	}
 @@ -746,26 +746,50 @@ decode_ddr2(const struct sysctlnode *nod
 	decode_voltage_refresh(self, s);
+}
 static void
 print_part(const char *part, size_t pnsize)
+{
 	const char *p = memchr(part, ' ', pnsize);
 	if (p == NULL)
 		p = part + pnsize;
 	aprint_normal(": %.*s\n", (int)(p - part), part);
+}
 static u_int
 ddr3_value_pico(struct spdmem *s, uint8_t txx_mtb, uint8_t txx_ftb)
+{
 	u_int mtb, ftb; /* in picoseconds */
 	intmax_t signed_txx_ftb;
 	u_int val;
 	mtb = (u_int)s->sm_ddr3.ddr3_mtb_dividend * 1000 /
 	    s->sm_ddr3.ddr3_mtb_divisor;
 	ftb = (u_int)s->sm_ddr3.ddr3_ftb_dividend * 1000 /
 	    s->sm_ddr3.ddr3_ftb_divisor;
 	/* tXX_ftb is signed value */
 	signed_txx_ftb = (int8_t)txx_ftb;
 	val = txx_mtb * mtb +
 	    ((txx_ftb > 127) ? signed_txx_ftb : txx_ftb) * ftb / 1000;
 	return val;
+}
 #define __DDR3_VALUE_PICO(s, field)				\
 	ddr3_value_pico(s, s->sm_ddr3.ddr3_##field##_mtb,	\
 	    s->sm_ddr3.ddr3_##field##_ftb)
 static void
 decode_ddr3(const struct sysctlnode *node, device_t self, struct spdmem *s)
+{
 	int dimm_size, cycle_time, bits;
 	aprint_naive("\n");
 	print_part(s->sm_ddr3.ddr3_part, sizeof(s->sm_ddr3.ddr3_part));
 	aprint_normal_dev(self, "%s", spdmem_basic_types[s->sm_type]);
 	if (s->sm_ddr3.ddr3_mod_type ==
 		SPDMEM_DDR3_TYPE_MINI_RDIMM ||
 	    s->sm_ddr3.ddr3_mod_type == SPDMEM_DDR3_TYPE_RDIMM)
 		aprint_normal(" (registered)");
 @@ -776,48 +800,49 @@ decode_ddr3(const struct sysctlnode *nod
 	/*
 	 * DDR3 size specification is quite different from others
+	 *
 	 * Module capacity is defined as
 	 *	Chip_Capacity_in_bits / 8bits-per-byte *
 	 *	external_bus_width / internal_bus_width
 	 * We further divide by 2**20 to get our answer in MB
 	 */
 	dimm_size = (s->sm_ddr3.ddr3_chipsize + 28 - 20) - 3 +
 		    (s->sm_ddr3.ddr3_datawidth + 3) -
 		    (s->sm_ddr3.ddr3_chipwidth + 2);
 	dimm_size = (1 << dimm_size) * (s->sm_ddr3.ddr3_physbanks + 1);
-	cycle_time = (1000 * s->sm_ddr3.ddr3_mtb_dividend +
+	cycle_time = __DDR3_VALUE_PICO(s, tCKmin);
 			    (s->sm_ddr3.ddr3_mtb_divisor / 2)) /
 		     s->sm_ddr3.ddr3_mtb_divisor;
 	cycle_time *= s->sm_ddr3.ddr3_tCKmin;
 	bits = 1 << (s->sm_ddr3.ddr3_datawidth + 3);
 	decode_size_speed(self, node, dimm_size, cycle_time, 2, bits, FALSE,
 			  "PC3", 0);
 	aprint_verbose_dev(self,
 	    "%d rows, %d cols, %d log. banks, %d phys. banks, "
 	    "%d.%03dns cycle time\n",
-	    s->sm_ddr3.ddr3_rows + 9, s->sm_ddr3.ddr3_cols + 12,
+	    s->sm_ddr3.ddr3_rows + 12, s->sm_ddr3.ddr3_cols + 9,
 << (s->sm_ddr3.ddr3_logbanks + 3),
 	    s->sm_ddr3.ddr3_physbanks + 1,
 	    cycle_time/1000, cycle_time % 1000);
-#define	__DDR3_CYCLES(field) (s->sm_ddr3.field / s->sm_ddr3.ddr3_tCKmin)
+#define	__DDR3_CYCLES(val)						\
 	((val / cycle_time) + ((val % cycle_time) ? 1 : 0))
-	aprint_verbose_dev(self, LATENCY, __DDR3_CYCLES(ddr3_tAAmin),
+	aprint_verbose_dev(self, LATENCY,
-		__DDR3_CYCLES(ddr3_tRCDmin), __DDR3_CYCLES(ddr3_tRPmin),
+	    __DDR3_CYCLES(__DDR3_VALUE_PICO(s, tAAmin)),
-		(s->sm_ddr3.ddr3_tRAS_msb * 256 + s->sm_ddr3.ddr3_tRAS_lsb) /
+	    __DDR3_CYCLES(__DDR3_VALUE_PICO(s, tRCDmin)),
-		    s->sm_ddr3.ddr3_tCKmin);
+	    __DDR3_CYCLES(__DDR3_VALUE_PICO(s, tRPmin)),
 	    __DDR3_CYCLES((s->sm_ddr3.ddr3_tRAS_msb * 256
 		+ s->sm_ddr3.ddr3_tRAS_lsb) * s->sm_ddr3.ddr3_mtb_dividend
 		/ s->sm_ddr3.ddr3_mtb_divisor * 1000));
 #undef	__DDR3_CYCLES
 	/* For DDR3, Voltage is written in another area */
 	if (!s->sm_ddr3.ddr3_NOT15V || s->sm_ddr3.ddr3_135V
 	    || s->sm_ddr3.ddr3_125V) {
 		aprint_verbose("%s:", device_xname(self));
 		if (!s->sm_ddr3.ddr3_NOT15V)
 			aprint_verbose(" 1.5V");
 		if (s->sm_ddr3.ddr3_135V)
 			aprint_verbose(" 1.35V");
 		if (s->sm_ddr3.ddr3_125V)
 			aprint_verbose(" 1.25V");
 @@ -847,47 +872,47 @@ decode_fbdimm(const struct sysctlnode *n
 	bits = 1 << (s->sm_fbd.fbdimm_dev_width + 2);
 	decode_size_speed(self, node, dimm_size, cycle_time, 2, bits, TRUE,
 			  "PC2", 0);
 	aprint_verbose_dev(self,
 	    "%d rows, %d cols, %d banks, %d.%02dns cycle time\n",
 	    s->sm_fbd.fbdimm_rows, s->sm_fbd.fbdimm_cols,
 << (s->sm_fbd.fbdimm_banks + 2),
 	    cycle_time / 1000, (cycle_time % 1000 + 5) /10 );
 #define	__FBDIMM_CYCLES(field) (s->sm_fbd.field / s->sm_fbd.fbdimm_tCKmin)
 	aprint_verbose_dev(self, LATENCY, __FBDIMM_CYCLES(fbdimm_tAAmin),
-		__FBDIMM_CYCLES(fbdimm_tRCDmin), __FBDIMM_CYCLES(fbdimm_tRPmin),
+	    __FBDIMM_CYCLES(fbdimm_tRCDmin), __FBDIMM_CYCLES(fbdimm_tRPmin),
-		(s->sm_fbd.fbdimm_tRAS_msb * 256 + s->sm_fbd.fbdimm_tRAS_lsb) /
+	    (s->sm_fbd.fbdimm_tRAS_msb * 256 + s->sm_fbd.fbdimm_tRAS_lsb) /
-		    s->sm_fbd.fbdimm_tCKmin);
+	    s->sm_fbd.fbdimm_tCKmin);
 #undef	__FBDIMM_CYCLES
 	decode_voltage_refresh(self, s);
+}
 static void
 decode_ddr4(const struct sysctlnode *node, device_t self, struct spdmem *s)
+{
 	int dimm_size, cycle_time, ranks;
-	int tAA_clocks, tRCD_clocks,tRP_clocks, tRAS_clocks;
+	int tAA_clocks, tRCD_clocks, tRP_clocks, tRAS_clocks;
 	aprint_naive("\n");
 	print_part(s->sm_ddr4.ddr4_part_number,
 	    sizeof(s->sm_ddr4.ddr4_part_number));
 	aprint_normal_dev(self, "%s", spdmem_basic_types[s->sm_type]);
 	if (s->sm_ddr4.ddr4_mod_type < __arraycount(spdmem_ddr4_module_types))
 		aprint_normal(" (%s)",
 		    spdmem_ddr4_module_types[s->sm_ddr4.ddr4_mod_type]);
 	aprint_normal(", %sECC, %stemp-sensor, ",
 		(s->sm_ddr4.ddr4_bus_width_extension) ? "" : "no ",
 		(s->sm_ddr4.ddr4_has_therm_sensor) ? "" : "no ");
 	/*
 	 * DDR4 size calculation from JEDEC spec
+	 *
 	 * Module capacity in bytes is defined as
 	 *	Chip_Capacity_in_bits / 8bits-per-byte *
 	 *	primary_bus_width / DRAM_width *
 	 *	logical_ranks_per_DIMM
+	 *
 @@ -902,57 +927,57 @@ decode_ddr4(const struct sysctlnode *nod
 		     + (s->sm_ddr4.ddr4_primary_bus_width + 3); /* bus width */
 	switch (s->sm_ddr4.ddr4_device_width) {		/* DRAM width */
 	case 0:	dimm_size -= 2;
 		break;
 	case 1: dimm_size -= 3;
 		break;
 	case 2:	dimm_size -= 4;
 		break;
 	case 4: dimm_size -= 5;
 		break;
 	default:
 		dimm_size = -1;		/* flag invalid value */
+	}
 	if (dimm_size >= 0) {
 		dimm_size = (1 << dimm_size) *
 		    (s->sm_ddr4.ddr4_package_ranks + 1); /* log.ranks/DIMM */
 		if (s->sm_ddr4.ddr4_signal_loading == 2) {
 			dimm_size *= (s->sm_ddr4.ddr4_diecount + 1);
+		}
+	}
 /*
  * Note that the ddr4_xxx_ftb fields are actually signed offsets from
  * the corresponding mtb value, so we might have to subtract 256!
  */
 #define	__DDR4_VALUE(field) ((s->sm_ddr4.ddr4_##field##_mtb * 125 +	\
 			     s->sm_ddr4.ddr4_##field##_ftb) - 		\
 			    ((s->sm_ddr4.ddr4_##field##_ftb > 127)?256:0))
 	/*
 	 * For now, the only value for mtb is 0 = 125ps, and ftb = 1ps
 	 * so we don't need to figure out the time-base units - just
 	 * hard-code them for now.
 	 */
 	cycle_time = __DDR4_VALUE(tCKAVGmin);
 	decode_size_speed(self, node, dimm_size, cycle_time, 2,
 << (s->sm_ddr4.ddr4_primary_bus_width + 3),
 			  TRUE, "PC4", 0);
 	ranks = s->sm_ddr4.ddr4_package_ranks + 1;
 	aprint_verbose_dev(self,
 	    "%d rows, %d cols, %d ranks%s, %d banks/group, %d bank groups\n",
 	    s->sm_ddr4.ddr4_rows + 12, s->sm_ddr4.ddr4_cols + 9,
 	    ranks, (ranks > 1) ? ((s->sm_ddr4.ddr4_rank_mix == 1)
-		? " (asymmetric)" : " (symmetiric)") : "",
+		? " (asymmetric)" : " (symmetric)") : "",
 << (2 + s->sm_ddr4.ddr4_logbanks),
 << s->sm_ddr4.ddr4_bankgroups);
 	aprint_verbose_dev(self, "%d.%03dns cycle time\n",
 	    cycle_time / 1000, cycle_time % 1000);
 	tAA_clocks =  __DDR4_VALUE(tAAmin)  * 1000 / cycle_time;
 	tRCD_clocks = __DDR4_VALUE(tRCDmin) * 1000 / cycle_time;
 	tRP_clocks =  __DDR4_VALUE(tRPmin)  * 1000 / cycle_time;
 	tRAS_clocks = (s->sm_ddr4.ddr4_tRASmin_msb * 256 +
 		       s->sm_ddr4.ddr4_tRASmin_lsb) * 125 * 1000 / cycle_time;
 /*

 @@ -1,14 +1,14 @@
-/* $NetBSD: spdmemvar.h,v 1.13.6.1 2019/01/03 11:23:54 martin Exp $ */
+/* $NetBSD: spdmemvar.h,v 1.13.6.2 2020/04/14 17:39:28 martin Exp $ */
 /*
  * Copyright (c) 2007 Paul Goyette
  * Copyright (c) 2007 Tobias Nygren
  * All rights reserved.
+ *
  * Redistribution and use in source and binary forms, with or without
  * modification, are permitted provided that the following conditions
  * are met:
  * 1. Redistributions of source code must retain the above copyright
  *    notice, this list of conditions and the following disclaimer.
  * 2. Redistributions in binary form must reproduce the above copyright
  *    notice, this list of conditions and the following disclaimer in the
 @@ -453,66 +453,73 @@ struct spdmem_ddr3 {				/* Dual Data Rat
 	/* datawidth in bits offset by 3: 1 = 16b, 2 = 32b, 3 = 64b */
 	SPD_BITFIELD(				\
 		uint8_t ddr3_datawidth:3,	\
 		uint8_t ddr3_hasECC:2,		\
 		uint8_t ddr3_unused2a:3 ,	\
 	);
 	/* Fine time base, in pico-seconds */
 	SPD_BITFIELD(				\
 		uint8_t ddr3_ftb_divisor:4,	\
 		uint8_t ddr3_ftb_dividend:4, ,	\
 	);
 	uint8_t ddr3_mtb_dividend;	/* 0x0108 = 0.1250ns */
 	uint8_t	ddr3_mtb_divisor;	/* 0x010f = 0.0625ns */
-	uint8_t	ddr3_tCKmin;		/* in terms of mtb */
+	uint8_t	ddr3_tCKmin_mtb;
 	uint8_t	ddr3_unused3;
 	uint16_t ddr3_CAS_sup;		/* Bit 0 ==> CAS 4 cycles */
-	uint8_t	ddr3_tAAmin;		/* in terms of mtb */
+	uint8_t	ddr3_tAAmin_mtb;
 	uint8_t	ddr3_tWRmin;
-	uint8_t	ddr3_tRCDmin;
+	uint8_t	ddr3_tRCDmin_mtb;
 	uint8_t	ddr3_tRRDmin;
-	uint8_t	ddr3_tRPmin;
+	uint8_t	ddr3_tRPmin_mtb;
 	SPD_BITFIELD(				\
 		uint8_t	ddr3_tRAS_msb:4,	\
-		uint8_t	ddr3_tRC_msb:4, ,	\
+		uint8_t	ddr3_tRCmin_mtb_msb:4, , \
 	);
 	uint8_t	ddr3_tRAS_lsb;
-	uint8_t	ddr3_tRC_lsb;
+	uint8_t	ddr3_tRCmin_mtb_lsb;
 	uint8_t	ddr3_tRFCmin_lsb;
 	uint8_t	ddr3_tRFCmin_msb;
 	uint8_t	ddr3_tWTRmin;
 	uint8_t	ddr3_tRTPmin;
 	SPD_BITFIELD(				\
 		uint8_t	ddr3_tFAW_msb:4, , ,	\
 	);
 	uint8_t	ddr3_tFAW_lsb;
 	uint8_t	ddr3_output_drvrs;
 	SPD_BITFIELD(				\
 		uint8_t	ddr3_ext_temp_range:1,	\
 		uint8_t	ddr3_ext_temp_2x_refresh:1, \
 		uint8_t	ddr3_asr_refresh:1,	\
 		/* Bit 4 indicates on-die thermal sensor */
 		/* Bit 7 indicates Partial-Array Self-Refresh (PASR) */
 		uint8_t	ddr3_unused7:5		\
 	);
 	SPD_BITFIELD(				\
 		uint8_t ddr3_therm_sensor_acc:7,\
 		uint8_t ddr3_has_therm_sensor:1, , \
 	);
 	SPD_BITFIELD(				\
 		uint8_t ddr3_non_std_devtype:7,	\
 		uint8_t ddr3_std_device:1, ,	\
 	);
-	uint8_t	ddr3_unused4[26];
+	uint8_t ddr3_tCKmin_ftb;
 	uint8_t ddr3_tAAmin_ftb;
 	uint8_t ddr3_tRCDmin_ftb;
 	uint8_t ddr3_tRPmin_ftb;
 	uint8_t ddr3_tRCmin_ftb;
 	uint8_t	ddr3_unused4[2];
 	uint8_t	ddr3_MAC;
 	uint8_t	ddr3_unused4a[18];
 	uint8_t	ddr3_mod_height;
 	uint8_t	ddr3_mod_thickness;
 	uint8_t	ddr3_ref_card;
 	uint8_t	ddr3_mapping;
 	uint8_t	ddr3_unused5[53];
 	uint8_t	ddr3_mfgID_lsb;
 	uint8_t	ddr3_mfgID_msb;
 	uint8_t	ddr3_mfgloc;
 	uint8_t	ddr3_mfg_year;
 	uint8_t	ddr3_mfg_week;
 	uint8_t	ddr3_serial[4];
 	uint16_t ddr3_crc;
 	uint8_t ddr3_part[18];