Thu Apr 16 08:59:16 2020 UTC ()
Shave off 3 instructions per trap


(skrll)
diff -r1.14 -r1.15 src/sys/arch/aarch64/aarch64/vectors.S
cvs diff -r1.14 -r1.15 src/sys/arch/aarch64/aarch64/vectors.S (expand / switch to unified diff)

--- src/sys/arch/aarch64/aarch64/vectors.S 2020/04/13 05:40:25 1.14
+++ src/sys/arch/aarch64/aarch64/vectors.S 2020/04/16 08:59:16 1.15
@@ -1,41 +1,42 @@ @@ -1,41 +1,42 @@
1/* $NetBSD: vectors.S,v 1.14 2020/04/13 05:40:25 maxv Exp $ */ 1/* $NetBSD: vectors.S,v 1.15 2020/04/16 08:59:16 skrll Exp $ */
2 2
3#include <aarch64/asm.h> 3#include <aarch64/asm.h>
4#include "assym.h" 4#include "assym.h"
5#include "opt_cpuoptions.h" 5#include "opt_cpuoptions.h"
6#include "opt_ddb.h" 6#include "opt_ddb.h"
7#include "opt_dtrace.h" 7#include "opt_dtrace.h"
8 8
9 ARMV8_DEFINE_OPTIONS 9 ARMV8_DEFINE_OPTIONS
10 10
11#ifdef KDTRACE_HOOKS 11#ifdef KDTRACE_HOOKS
12/* 12/*
13 * dtrace needs to emulate stp x29,x30,[sp,#-FRAMESIZE]! where 13 * dtrace needs to emulate stp x29,x30,[sp,#-FRAMESIZE]! where
14 * FRAMESIZE can be as large as 512, so create a 512-byte buffer 14 * FRAMESIZE can be as large as 512, so create a 512-byte buffer
15 * between the interrupted code's frame and our struct trapframe. 15 * between the interrupted code's frame and our struct trapframe.
16 */ 16 */
17#define TRAP_FRAMESIZE (TF_SIZE + 512) 17#define TRAP_FRAMESIZE (TF_SIZE + 512)
18#else 18#else
19#define TRAP_FRAMESIZE TF_SIZE 19#define TRAP_FRAMESIZE TF_SIZE
20#endif 20#endif
21 21
22/* 22/*
23 * Template for the handler functions. 23 * Template for the handler functions.
24 */ 24 */
25.macro vector_func, func, el, label, tpidr 25.macro vector_func, func, el, label, tpidr
26ENTRY_NBTI(\func) 
27 .align 7 /* cacheline-aligned */ 26 .align 7 /* cacheline-aligned */
28 27
 28ENTRY_NBTI(\func)
 29
29 .if \el == 1 30 .if \el == 1
30 /* need to allocate stack on el1 */ 31 /* need to allocate stack on el1 */
31 sub sp, sp, #TRAP_FRAMESIZE 32 sub sp, sp, #TRAP_FRAMESIZE
32 .endif 33 .endif
33 34
34 stp x0, x1, [sp, #TF_X0] 35 stp x0, x1, [sp, #TF_X0]
35 stp x2, x3, [sp, #TF_X2] 36 stp x2, x3, [sp, #TF_X2]
36 stp x4, x5, [sp, #TF_X4] 37 stp x4, x5, [sp, #TF_X4]
37 stp x6, x7, [sp, #TF_X6] 38 stp x6, x7, [sp, #TF_X6]
38 stp x8, x9, [sp, #TF_X8] 39 stp x8, x9, [sp, #TF_X8]
39 stp x10, x11, [sp, #TF_X10] 40 stp x10, x11, [sp, #TF_X10]
40 stp x12, x13, [sp, #TF_X12] 41 stp x12, x13, [sp, #TF_X12]
41 stp x14, x15, [sp, #TF_X14] 42 stp x14, x15, [sp, #TF_X14]