 @@ -1,14 +1,14 @@
-/*	$NetBSD: pmap.c,v 1.405 2020/04/16 21:20:43 ad Exp $	*/
+/*	$NetBSD: pmap.c,v 1.406 2020/04/17 08:17:06 skrll Exp $	*/
 /*
  * Copyright 2003 Wasabi Systems, Inc.
  * All rights reserved.
+ *
  * Written by Steve C. Woodford for Wasabi Systems, Inc.
+ *
  * Redistribution and use in source and binary forms, with or without
  * modification, are permitted provided that the following conditions
  * are met:
  * 1. Redistributions of source code must retain the above copyright
  *    notice, this list of conditions and the following disclaimer.
  * 2. Redistributions in binary form must reproduce the above copyright
 @@ -188,27 +188,27 @@
 #include "opt_arm_debug.h"
 #include "opt_cpuoptions.h"
 #include "opt_pmap_debug.h"
 #include "opt_ddb.h"
 #include "opt_lockdebug.h"
 #include "opt_multiprocessor.h"
 #ifdef MULTIPROCESSOR
 #define _INTR_PRIVATE
 #endif
 #include <sys/cdefs.h>
-__KERNEL_RCSID(0, "$NetBSD: pmap.c,v 1.405 2020/04/16 21:20:43 ad Exp $");
+__KERNEL_RCSID(0, "$NetBSD: pmap.c,v 1.406 2020/04/17 08:17:06 skrll Exp $");
 #include <sys/atomic.h>
 #include <sys/param.h>
 #include <sys/types.h>
 #include <sys/atomic.h>
 #include <sys/bus.h>
 #include <sys/cpu.h>
 #include <sys/intr.h>
 #include <sys/kernel.h>
 #include <sys/kernhist.h>
 #include <sys/kmem.h>
 #include <sys/pool.h>
 #include <sys/proc.h>
 @@ -3123,29 +3123,28 @@ pmap_enter(pmap_t pm, vaddr_t va, paddr_
 	u_int nflags;
 	u_int oflags;
 	const bool kpm_p = (pm == pmap_kernel());
 #ifdef ARM_HAS_VBAR
 	const bool vector_page_p = false;
 #else
 	const bool vector_page_p = (va == vector_page);
 #endif
 	struct pmap_page *pp = pmap_pv_tracked(pa);
 	struct pv_entry *new_pv = NULL;
 	struct pv_entry *old_pv = NULL;
 	int error = 0;
-	UVMHIST_FUNC(__func__); UVMHIST_CALLED(maphist);
+	UVMHIST_FUNC(__func__);
 	UVMHIST_CALLARGS(maphist, "pm %#jx va %#jx pa %#jx prot %#jx",
 	UVMHIST_LOG(maphist, " (pm %#jx va %#jx pa %#jx prot %#jx",
 	    (uintptr_t)pm, va, pa, prot);
 	UVMHIST_LOG(maphist, "  flag %#jx", flags, 0, 0, 0);
 	KDASSERT((flags & PMAP_WIRED) == 0 || (flags & VM_PROT_ALL) != 0);
 	KDASSERT(((va | pa) & PGOFSET) == 0);
 	/*
 	 * Get a pointer to the page.  Later on in this function, we
 	 * test for a managed page by checking pg != NULL.
 	 */
 	pg = pmap_initialized ? PHYS_TO_VM_PAGE(pa) : NULL;
 	/*
 	 * if we may need a new pv entry allocate if now, as we can't do it
 @@ -3493,28 +3492,28 @@ free_pv:
  *     all invalidations until pmap_update(), since pmap_remove_all() has
  *     already flushed the cache.
  *  4. Maybe later fast-case a single page, but I don't think this is
  *     going to make _that_ much difference overall.
  */
 #define	PMAP_REMOVE_CLEAN_LIST_SIZE	3
 void
 pmap_remove(pmap_t pm, vaddr_t sva, vaddr_t eva)
+{
 	SLIST_HEAD(,pv_entry) opv_list;
 	struct pv_entry *pv, *npv;
-	UVMHIST_FUNC(__func__); UVMHIST_CALLED(maphist);
+	UVMHIST_FUNC(__func__);
-	UVMHIST_LOG(maphist, " (pm=%#jx, sva=%#jx, eva=%#jx)",
+	UVMHIST_CALLARGS(maphist, " (pm=%#jx, sva=%#jx, eva=%#jx)",
 	    (uintptr_t)pm, sva, eva, 0);
 #ifdef PMAP_FAULTINFO
 	curpcb->pcb_faultinfo.pfi_faultaddr = 0;
 	curpcb->pcb_faultinfo.pfi_repeats = 0;
 	curpcb->pcb_faultinfo.pfi_faultptep = NULL;
 #endif
 	SLIST_INIT(&opv_list);
 	/*
 	 * we lock in the pmap => pv_head direction
 	 */
 	pmap_acquire_pmap_lock(pm);
 @@ -3741,29 +3740,29 @@ pmap_kenter_pa(vaddr_t va, paddr_t pa, v
 #endif
 #ifdef PMAP_CACHE_VIPT
 	struct vm_page *pg = PHYS_TO_VM_PAGE(pa);
 	struct vm_page *opg;
 #ifndef ARM_MMU_EXTENDED
 	struct pv_entry *pv = NULL;
 #endif
 #endif
 	struct vm_page_md *md = pg != NULL ? VM_PAGE_TO_MD(pg) : NULL;
 	UVMHIST_FUNC(__func__);
 	if (pmap_initialized) {
-		UVMHIST_CALLED(maphist);
+		UVMHIST_CALLARGS(maphist,
-		UVMHIST_LOG(maphist, " (va=%#jx, pa=%#jx, prot=%#jx, flags=%#jx",
+		    "va=%#jx, pa=%#jx, prot=%#jx, flags=%#jx", va, pa, prot,
-		    va, pa, prot, flags);
+		     flags);
+	}
 	pmap_t kpm = pmap_kernel();
 	pmap_acquire_pmap_lock(kpm);
 	struct l2_bucket * const l2b = pmap_get_l2_bucket(kpm, va);
 	const size_t l1slot __diagused = l1pte_index(va);
 	KASSERTMSG(l2b != NULL,
 	    "va %#lx pa %#lx prot %d maxkvaddr %#lx: l2 %p l2b %p kva %p",
 	    va, pa, prot, pmap_curmaxkvaddr, kpm->pm_l2[L2_IDX(l1slot)],
 	    kpm->pm_l2[L2_IDX(l1slot)]
 		? &kpm->pm_l2[L2_IDX(l1slot)]->l2_bucket[L2_BUCKET(l1slot)]
 		: NULL,
 	    kpm->pm_l2[L2_IDX(l1slot)]
 @@ -3898,29 +3897,28 @@ pmap_kenter_pa(vaddr_t va, paddr_t pa, v
+	}
+}
 void
 pmap_kremove(vaddr_t va, vsize_t len)
+{
 #ifdef UVMHIST
 	u_int total_mappings = 0;
 #endif
 	PMAPCOUNT(kenter_unmappings);
-	UVMHIST_FUNC(__func__); UVMHIST_CALLED(maphist);
+	UVMHIST_FUNC(__func__);
 	UVMHIST_CALLARGS(maphist, " (va=%#jx, len=%#jx)", va, len, 0, 0);
 	UVMHIST_LOG(maphist, " (va=%#jx, len=%#jx)", va, len, 0, 0);
 	const vaddr_t eva = va + len;
 	pmap_t kpm = pmap_kernel();
 	pmap_acquire_pmap_lock(kpm);
 	while (va < eva) {
 		vaddr_t next_bucket = L2_NEXT_BUCKET_VA(va);
 		if (next_bucket > eva)
 			next_bucket = eva;
 		struct l2_bucket * const l2b = pmap_get_l2_bucket(kpm, va);
 		KDASSERT(l2b != NULL);
 @@ -4415,34 +4413,34 @@ pmap_prefetchabt_fixup(void *v)
 	return rv;
+}
 #endif
 int
 pmap_fault_fixup(pmap_t pm, vaddr_t va, vm_prot_t ftype, int user)
+{
 	struct l2_dtable *l2;
 	struct l2_bucket *l2b;
 	paddr_t pa;
 	const size_t l1slot = l1pte_index(va);
 	int rv = 0;
-	UVMHIST_FUNC(__func__); UVMHIST_CALLED(maphist);
+	UVMHIST_FUNC(__func__);
 	UVMHIST_CALLARGS(maphist, "pm=%#jx, va=%#jx, ftype=%#jx, user=%jd",
 	    (uintptr_t)pm, va, ftype, user);
 	va = trunc_page(va);
 	KASSERT(!user || (pm != pmap_kernel()));
 	UVMHIST_LOG(maphist, " (pm=%#jx, va=%#jx, ftype=%#jx, user=%jd)",
 	    (uintptr_t)pm, va, ftype, user);
 #ifdef ARM_MMU_EXTENDED
 	UVMHIST_LOG(maphist, " ti=%#jx pai=%#jx asid=%#jx",
 	    (uintptr_t)cpu_tlb_info(curcpu()),
 	    (uintptr_t)PMAP_PAI(pm, cpu_tlb_info(curcpu())),
 	    (uintptr_t)PMAP_PAI(pm, cpu_tlb_info(curcpu()))->pai_asid, 0);
 #endif
 	pmap_acquire_pmap_lock(pm);
 	/*
 	 * If there is no l2_dtable for this address, then the process
 	 * has no business accessing it.
+	 *
 @@ -4887,69 +4885,72 @@ pmap_unwire(pmap_t pm, vaddr_t va)
 		pmap_acquire_page_lock(md);
 		(void) pmap_modify_pv(md, pa, pm, va, PVF_WIRED, 0);
 		pmap_release_page_lock(md);
+	}
 	pmap_release_pmap_lock(pm);
+}
 #ifdef ARM_MMU_EXTENDED
 void
 pmap_md_pdetab_activate(pmap_t pm, struct lwp *l)
+{
-	UVMHIST_FUNC(__func__); UVMHIST_CALLED(maphist);
+	UVMHIST_FUNC(__func__);
 	struct cpu_info * const ci = curcpu();
 	struct pmap_asid_info * const pai = PMAP_PAI(pm, cpu_tlb_info(ci));
 	UVMHIST_CALLARGS(maphist, "pm %#jx (pm->pm_l1_pa %08jx asid %ju)",
 	    (uintptr_t)pm, pm->pm_l1_pa, pai->pai_asid, 0);
 	/*
 	 * Assume that TTBR1 has only global mappings and TTBR0 only
 	 * has non-global mappings.  To prevent speculation from doing
 	 * evil things we disable translation table walks using TTBR0
 	 * before setting the CONTEXTIDR (ASID) or new TTBR0 value.
 	 * Once both are set, table walks are reenabled.
 	 */
 	const uint32_t old_ttbcr = armreg_ttbcr_read();
 	armreg_ttbcr_write(old_ttbcr | TTBCR_S_PD0);
 	arm_isb();
 	pmap_tlb_asid_acquire(pm, l);
 	struct cpu_info * const ci = curcpu();
 	struct pmap_asid_info * const pai = PMAP_PAI(pm, cpu_tlb_info(ci));
 	cpu_setttb(pm->pm_l1_pa, pai->pai_asid);
 	/*
 	 * Now we can reenable tablewalks since the CONTEXTIDR and TTRB0
 	 * have been updated.
 	 */
 	arm_isb();
 	if (pm != pmap_kernel()) {
 		armreg_ttbcr_write(old_ttbcr & ~TTBCR_S_PD0);
+	}
 	cpu_cpwait();
 	UVMHIST_LOG(maphist, " pm %#jx pm->pm_l1_pa %08jx asid %ju... done",
 	    (uintptr_t)pm, pm->pm_l1_pa, pai->pai_asid, 0);
 	KASSERTMSG(ci->ci_pmap_asid_cur == pai->pai_asid, "%u vs %u",
 	    ci->ci_pmap_asid_cur, pai->pai_asid);
 	ci->ci_pmap_cur = pm;
+}
 void
 pmap_md_pdetab_deactivate(pmap_t pm)
+{
-	UVMHIST_FUNC(__func__); UVMHIST_CALLED(maphist);
+	UVMHIST_FUNC(__func__);
 	UVMHIST_CALLARGS(maphist, "pm %#jx", (uintptr_t)pm, 0, 0, 0);
 	kpreempt_disable();
 	struct cpu_info * const ci = curcpu();
 	/*
 	 * Disable translation table walks from TTBR0 while no pmap has been
 	 * activated.
 	 */
 	const uint32_t old_ttbcr = armreg_ttbcr_read();
 	armreg_ttbcr_write(old_ttbcr | TTBCR_S_PD0);
 	arm_isb();
 	pmap_tlb_asid_deactivate(pm);
 	cpu_setttb(pmap_kernel()->pm_l1_pa, KERNEL_PID);
 	arm_isb();
 @@ -4957,30 +4958,29 @@ pmap_md_pdetab_deactivate(pmap_t pm)
 	ci->ci_pmap_cur = pmap_kernel();
 	KASSERTMSG(ci->ci_pmap_asid_cur == KERNEL_PID, "ci_pmap_asid_cur %u",
 	    ci->ci_pmap_asid_cur);
 	kpreempt_enable();
+}
 #endif
 void
 pmap_activate(struct lwp *l)
+{
 	extern int block_userspace_access;
 	pmap_t npm = l->l_proc->p_vmspace->vm_map.pmap;
-	UVMHIST_FUNC(__func__); UVMHIST_CALLED(maphist);
+	UVMHIST_FUNC(__func__);
 	UVMHIST_CALLARGS(maphist, "l=%#jx pm=%#jx", (uintptr_t)l,
-	UVMHIST_LOG(maphist, "(l=%#jx) pm=%#jx", (uintptr_t)l, (uintptr_t)npm,
+	    (uintptr_t)npm, 0, 0);
 , 0);
 	struct cpu_info * const ci = curcpu();
 	/*
 	 * If activating a non-current lwp or the current lwp is
 	 * already active, just return.
 	 */
 	if (false
 	    || l != curlwp
 #ifdef ARM_MMU_EXTENDED
 	    || (ci->ci_pmap_cur == npm &&
 		(npm == pmap_kernel()
 		 /* || PMAP_PAI_ASIDVALID_P(pai, cpu_tlb_info(ci)) */))
 @@ -5115,54 +5115,52 @@ pmap_activate(struct lwp *l)
 		/* But the new one is */
 		npm->pm_activated = true;
+	}
 	ci->ci_pmap_cur = npm;
 #endif
 	UVMHIST_LOG(maphist, " <-- done", 0, 0, 0, 0);
+}
 void
 pmap_deactivate(struct lwp *l)
+{
 	pmap_t pm = l->l_proc->p_vmspace->vm_map.pmap;
-	UVMHIST_FUNC(__func__); UVMHIST_CALLED(maphist);
+	UVMHIST_FUNC(__func__);
 	UVMHIST_CALLARGS(maphist, "l=%#jx (pm=%#jx)", (uintptr_t)l,
-	UVMHIST_LOG(maphist, "(l=%#jx) pm=%#jx", (uintptr_t)l, (uintptr_t)pm,
+		(uintptr_t)pm, 0, 0);
 , 0);
 #ifdef ARM_MMU_EXTENDED
 	pmap_md_pdetab_deactivate(pm);
 #else
 	/*
 	 * If the process is exiting, make sure pmap_activate() does
 	 * a full MMU context-switch and cache flush, which we might
 	 * otherwise skip. See PR port-arm/38950.
 	 */
 	if (l->l_proc->p_sflag & PS_WEXIT)
 		curcpu()->ci_lastlwp = NULL;
 	pm->pm_activated = false;
 #endif
 	UVMHIST_LOG(maphist, "  <-- done", 0, 0, 0, 0);
+}
 void
 pmap_update(pmap_t pm)
+{
-	UVMHIST_FUNC(__func__); UVMHIST_CALLED(maphist);
+	UVMHIST_FUNC(__func__);
 	UVMHIST_CALLARGS(maphist, "pm=%#jx remove_all %jd", (uintptr_t)pm,
 	UVMHIST_LOG(maphist, "pm=%#jx remove_all %jd", (uintptr_t)pm,
 	    pm->pm_remove_all, 0, 0);
 #ifndef ARM_MMU_EXTENDED
 	if (pm->pm_remove_all) {
 		/*
 		 * Finish up the pmap_remove_all() optimisation by flushing
 		 * the TLB.
 		 */
 		pmap_tlb_flushID(pm);
 		pm->pm_remove_all = false;
+	}
 	if (pmap_is_current(pm)) {
 @@ -5253,34 +5251,33 @@ pmap_remove_all(pmap_t pm)
 	pmap_tlb_asid_release_all(pm);
 #endif
 	pm->pm_remove_all = true;
 	return false;
+}
 /*
  * Retire the given physical map from service.
  * Should only be called if the map contains no valid mappings.
  */
 void
 pmap_destroy(pmap_t pm)
+{
-	UVMHIST_FUNC(__func__); UVMHIST_CALLED(maphist);
+	UVMHIST_FUNC(__func__);
 	UVMHIST_CALLARGS(maphist, "pm=%#jx remove_all %jd", (uintptr_t)pm,
 	    pm ? pm->pm_remove_all : 0, 0, 0);
 	if (pm == NULL)
 		return;
 	UVMHIST_LOG(maphist, "pm=%#jx remove_all %jd", (uintptr_t)pm,
 	    pm->pm_remove_all, 0, 0);
 	if (pm->pm_remove_all) {
 #ifdef ARM_MMU_EXTENDED
  		pmap_tlb_asid_release_all(pm);
 #else
 		pmap_tlb_flushID(pm);
 #endif
 		pm->pm_remove_all = false;
+	}
 	/*
 	 * Drop reference count
 	 */
 	if (atomic_dec_uint_nv(&pm->pm_refs) > 0) {