 @@ -1,14 +1,14 @@
-/*	$NetBSD: identcpu.c,v 1.105 2020/04/09 02:07:01 christos Exp $	*/
+/*	$NetBSD: identcpu.c,v 1.106 2020/04/20 04:17:51 msaitoh Exp $	*/
 /*-
  * Copyright (c) 1999, 2000, 2001, 2006, 2007, 2008 The NetBSD Foundation, Inc.
  * All rights reserved.
+ *
  * This code is derived from software contributed to The NetBSD Foundation
  * by Frank van der Linden,  and by Jason R. Thorpe.
+ *
  * Redistribution and use in source and binary forms, with or without
  * modification, are permitted provided that the following conditions
  * are met:
  * 1. Redistributions of source code must retain the above copyright
  *    notice, this list of conditions and the following disclaimer.
 @@ -20,27 +20,27 @@
  * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
  * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
  * PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
  * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
  * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
  * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
  * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
  * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
  * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
  * POSSIBILITY OF SUCH DAMAGE.
  */
 #include <sys/cdefs.h>
-__KERNEL_RCSID(0, "$NetBSD: identcpu.c,v 1.105 2020/04/09 02:07:01 christos Exp $");
+__KERNEL_RCSID(0, "$NetBSD: identcpu.c,v 1.106 2020/04/20 04:17:51 msaitoh Exp $");
 #include "opt_xen.h"
 #include <sys/param.h>
 #include <sys/systm.h>
 #include <sys/device.h>
 #include <sys/cpu.h>
 #include <uvm/uvm_extern.h>
 #include <machine/specialreg.h>
 #include <machine/pio.h>
 #include <machine/cpu.h>
 @@ -52,47 +52,47 @@ __KERNEL_RCSID(0, "$NetBSD: identcpu.c,v
 #include <x86/x86/vmtreg.h>	/* for vmt_hvcall() */
 #include <x86/x86/vmtvar.h>	/* for vmt_hvcall() */
 #ifndef XEN
 #include "hyperv.h"
 #if NHYPERV > 0
 #include <x86/x86/hypervvar.h>
 #endif
 #endif
 static const struct x86_cache_info intel_cpuid_cache_info[] = INTEL_CACHE_INFO;
 static const struct x86_cache_info amd_cpuid_l2l3cache_assoc_info[] =
 	AMD_L2L3CACHE_INFO;
 int cpu_vendor;
 char cpu_brand_string[49];
 int x86_fpu_save __read_mostly;
 unsigned int x86_fpu_save_size __read_mostly = sizeof(struct save87);
 uint64_t x86_xsave_features __read_mostly = 0;
 size_t x86_xsave_offsets[XSAVE_MAX_COMPONENT+1] __read_mostly;
 size_t x86_xsave_sizes[XSAVE_MAX_COMPONENT+1] __read_mostly;
 /*
  * Note: these are just the ones that may not have a cpuid instruction.
  * We deal with the rest in a different way.
  */
 const int i386_nocpuid_cpus[] = {
 	CPUVENDOR_INTEL, CPUCLASS_386,	/* CPU_386SX */
 	CPUVENDOR_INTEL, CPUCLASS_386,	/* CPU_386   */
 	CPUVENDOR_INTEL, CPUCLASS_486,	/* CPU_486SX */
-	CPUVENDOR_INTEL, CPUCLASS_486, 	/* CPU_486   */
+	CPUVENDOR_INTEL, CPUCLASS_486,	/* CPU_486   */
 	CPUVENDOR_CYRIX, CPUCLASS_486,	/* CPU_486DLC */
 	CPUVENDOR_CYRIX, CPUCLASS_486,	/* CPU_6x86 */
 	CPUVENDOR_NEXGEN, CPUCLASS_386,	/* CPU_NX586 */
 };
 static const char cpu_vendor_names[][10] = {
 	"Unknown", "Intel", "NS/Cyrix", "NexGen", "AMD", "IDT/VIA", "Transmeta",
 	"Vortex86"
 };
 static const struct x86_cache_info *
 cache_info_lookup(const struct x86_cache_info *cai, uint8_t desc)
+{
 @@ -164,27 +164,27 @@ cpu_dcp_cacheinfo(struct cpu_info *ci, u
 		ci->ci_cinfo[caitype].cai_associativity = ways;
 		ci->ci_cinfo[caitype].cai_linesize = linesize;
+	}
+}
 static void
 cpu_probe_intel_cache(struct cpu_info *ci)
+{
 	const struct x86_cache_info *cai;
 	u_int descs[4];
 	int iterations, i, j;
 	uint8_t desc;
 	if (cpuid_level >= 2) {
 		/* Parse the cache info from `cpuid leaf 2', if we have it. */
 		x86_cpuid(2, descs);
 		iterations = descs[0] & 0xff;
 		while (iterations-- > 0) {
 			for (i = 0; i < 4; i++) {
 				if (descs[i] & 0x80000000)
 					continue;
 				for (j = 0; j < 4; j++) {
 					if (i == 0 && j == 0)
 						continue;
 					desc = (descs[i] >> (j * 8)) & 0xff;
 					if (desc == 0)
 						continue;
 @@ -478,27 +478,27 @@ cpu_probe_cyrix_cmn(struct cpu_info *ci)
 	 * When powersave mode is enabled, the TSC stops counting
 	 * while the CPU is halted in idle() waiting for an interrupt.
 	 * This means we can't use the TSC for interval time in
 	 * microtime(9), and thus it is disabled here.
+	 *
 	 * It still makes a perfectly good cycle counter
 	 * for program profiling, so long as you remember you're
 	 * counting cycles, and not time. Further, if you don't
 	 * mind not using powersave mode, the TSC works just fine,
 	 * so this should really be optional. XXX
 	 */
 	cyrix_write_reg(0xc2, cyrix_read_reg(0xc2) | 0x08);
 	/*
 	 * Do not disable the TSC on the Geode GX, it's reported to
 	 * work fine.
 	 */
 	if (ci->ci_signature != 0x552)
 		ci->ci_feat_val[0] &= ~CPUID_TSC;
 	/* enable access to ccr4/ccr5 */
 	c3 = cyrix_read_reg(0xC3);
 	cyrix_write_reg(0xC3, c3 | 0x10);
 	/* cyrix's workaround  for the "coma bug" */
 	cyrix_write_reg(0x31, cyrix_read_reg(0x31) | 0xf8);
 	cyrix_write_reg(0x32, cyrix_read_reg(0x32) | 0x7f);
 	cyrix_write_reg(0x33, cyrix_read_reg(0x33) & ~0xff);
 @@ -515,27 +515,27 @@ cpu_probe_cyrix(struct cpu_info *ci)
 	    CPUID_TO_FAMILY(ci->ci_signature) < 4 ||
 	    CPUID_TO_FAMILY(ci->ci_signature) > 6)
 		return;
 	cpu_probe_cyrix_cmn(ci);
+}
 static void
 cpu_probe_winchip(struct cpu_info *ci)
+{
 	if (cpu_vendor != CPUVENDOR_IDT ||
 	    CPUID_TO_FAMILY(ci->ci_signature) != 5)
-	    	return;
+		return;
 	/* WinChip C6 */
 	if (CPUID_TO_MODEL(ci->ci_signature) == 4)
 		ci->ci_feat_val[0] &= ~CPUID_TSC;
+}
 static void
 cpu_probe_c3(struct cpu_info *ci)
+{
 	u_int family, model, stepping, descs[4], lfunc, msr;
 	struct x86_cache_info *cai;
 	if (cpu_vendor != CPUVENDOR_IDT ||
 @@ -546,27 +546,27 @@ cpu_probe_c3(struct cpu_info *ci)
 	model = CPUID_TO_MODEL(ci->ci_signature);
 	stepping = CPUID_TO_STEPPING(ci->ci_signature);
 	/* Determine the largest extended function value. */
 	x86_cpuid(0x80000000, descs);
 	lfunc = descs[0];
 	if (family == 6) {
 		/*
 		 * VIA Eden ESP.
+		 *
 		 * Quoting from page 3-4 of: "VIA Eden ESP Processor Datasheet"
 		 * http://www.via.com.tw/download/mainboards/6/14/Eden20v115.pdf
+		 *
 		 * 1. The CMPXCHG8B instruction is provided and always enabled,
 		 *    however, it appears disabled in the corresponding CPUID
 		 *    function bit 0 to avoid a bug in an early version of
 		 *    Windows NT. However, this default can be changed via a
 		 *    bit in the FCR MSR.
 		 */
 		ci->ci_feat_val[0] |= CPUID_CX8;
 		wrmsr(MSR_VIA_FCR, rdmsr(MSR_VIA_FCR) | VIA_ACE_ECX8);
+	}
 	if (family > 6 || model > 0x9 || (model == 0x9 && stepping >= 3)) {
 		/* VIA Nehemiah or Esther. */
 		x86_cpuid(0xc0000000, descs);
 @@ -636,27 +636,27 @@ cpu_probe_c3(struct cpu_info *ci)
+		    }
 		    if (ace_enable) {
 			msr = rdmsr(MSR_VIA_ACE);
 			wrmsr(MSR_VIA_ACE, msr | VIA_ACE_ENABLE);
+		    }
+		}
+	}
 	/* Explicitly disable unsafe ALTINST mode. */
 	if (ci->ci_feat_val[4] & CPUID_VIA_DO_ACE) {
 		msr = rdmsr(MSR_VIA_ACE);
 		wrmsr(MSR_VIA_ACE, msr & ~VIA_ACE_ALTINST);
+	}
 	/*
 	 * Determine L1 cache/TLB info.
 	 */
 	if (lfunc < 0x80000005) {
 		/* No L1 cache info available. */
 		return;
+	}
 	x86_cpuid(0x80000005, descs);
 	cai = &ci->ci_cinfo[CAI_ITLB];
 	cai->cai_totalsize = VIA_L1_EBX_ITLB_ENTRIES(descs[1]);
 @@ -704,27 +704,27 @@ cpu_probe_c3(struct cpu_info *ci)
 	} else {
 		cai->cai_totalsize = VIA_L2_ECX_C_SIZE(descs[2]);
 		cai->cai_associativity = VIA_L2_ECX_C_ASSOC(descs[2]);
 		cai->cai_linesize = VIA_L2_ECX_C_LS(descs[2]);
+	}
+}
 static void
 cpu_probe_geode(struct cpu_info *ci)
+{
 	if (memcmp("Geode by NSC", ci->ci_vendor, 12) != 0 ||
 	    CPUID_TO_FAMILY(ci->ci_signature) != 5)
-	    	return;
+		return;
 	cpu_probe_cyrix_cmn(ci);
 	cpu_probe_amd_cache(ci);
+}
 static void
 cpu_probe_vortex86(struct cpu_info *ci)
+{
 #define PCI_MODE1_ADDRESS_REG	0x0cf8
 #define PCI_MODE1_DATA_REG	0x0cfc
 #define PCI_MODE1_ENABLE	0x80000000UL
 	uint32_t reg, idx;